2 * wm8955.c -- WM8955 ALSA SoC Audio driver
4 * Copyright 2009 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/wm8955.h>
33 #define WM8955_NUM_SUPPLIES 4
34 static const char *wm8955_supply_names
[WM8955_NUM_SUPPLIES
] = {
41 /* codec private data */
43 enum snd_soc_control_type control_type
;
45 u16 reg_cache
[WM8955_MAX_REGISTER
+ 1];
47 unsigned int mclk_rate
;
52 struct regulator_bulk_data supplies
[WM8955_NUM_SUPPLIES
];
55 static const u16 wm8955_reg
[WM8955_MAX_REGISTER
+ 1] = {
58 0x0079, /* R2 - LOUT1 volume */
59 0x0079, /* R3 - ROUT1 volume */
61 0x0008, /* R5 - DAC Control */
63 0x000A, /* R7 - Audio Interface */
64 0x0000, /* R8 - Sample Rate */
66 0x00FF, /* R10 - Left DAC volume */
67 0x00FF, /* R11 - Right DAC volume */
68 0x000F, /* R12 - Bass control */
69 0x000F, /* R13 - Treble control */
71 0x0000, /* R15 - Reset */
79 0x00C1, /* R23 - Additional control (1) */
80 0x0000, /* R24 - Additional control (2) */
81 0x0000, /* R25 - Power Management (1) */
82 0x0000, /* R26 - Power Management (2) */
83 0x0000, /* R27 - Additional Control (3) */
90 0x0050, /* R34 - Left out Mix (1) */
91 0x0050, /* R35 - Left out Mix (2) */
92 0x0050, /* R36 - Right out Mix (1) */
93 0x0050, /* R37 - Right Out Mix (2) */
94 0x0050, /* R38 - Mono out Mix (1) */
95 0x0050, /* R39 - Mono out Mix (2) */
96 0x0079, /* R40 - LOUT2 volume */
97 0x0079, /* R41 - ROUT2 volume */
98 0x0079, /* R42 - MONOOUT volume */
99 0x0000, /* R43 - Clocking / PLL */
100 0x0103, /* R44 - PLL Control 1 */
101 0x0024, /* R45 - PLL Control 2 */
102 0x01BA, /* R46 - PLL Control 3 */
115 0x0000, /* R59 - PLL Control 4 */
118 static int wm8955_reset(struct snd_soc_codec
*codec
)
120 return snd_soc_write(codec
, WM8955_RESET
, 0);
129 /* The size in bits of the FLL divide multiplied by 10
130 * to allow rounding later */
131 #define FIXED_FLL_SIZE ((1 << 22) * 10)
133 static int wm8995_pll_factors(struct device
*dev
,
134 int Fref
, int Fout
, struct pll_factors
*pll
)
137 unsigned int K
, Ndiv
, Nmod
, target
;
139 dev_dbg(dev
, "Fref=%u Fout=%u\n", Fref
, Fout
);
141 /* The oscilator should run at should be 90-100MHz, and
142 * there's a divide by 4 plus an optional divide by 2 in the
143 * output path to generate the system clock. The clock table
144 * is sortd so we should always generate a suitable target. */
146 if (target
< 90000000) {
153 WARN_ON(target
< 90000000 || target
> 100000000);
155 dev_dbg(dev
, "Fvco=%dHz\n", target
);
157 /* Now, calculate N.K */
158 Ndiv
= target
/ Fref
;
161 Nmod
= target
% Fref
;
162 dev_dbg(dev
, "Nmod=%d\n", Nmod
);
164 /* Calculate fractional part - scale up so we can round. */
165 Kpart
= FIXED_FLL_SIZE
* (long long)Nmod
;
169 K
= Kpart
& 0xFFFFFFFF;
174 /* Move down to proper range now rounding is done */
177 dev_dbg(dev
, "N=%x K=%x OUTDIV=%x\n", pll
->n
, pll
->k
, pll
->outdiv
);
182 /* Lookup table specifiying SRATE (table 25 in datasheet); some of the
183 * output frequencies have been rounded to the standard frequencies
184 * they are intended to match where the error is slight. */
191 { 18432000, 8000, 0, 3, },
192 { 18432000, 12000, 0, 9, },
193 { 18432000, 16000, 0, 11, },
194 { 18432000, 24000, 0, 29, },
195 { 18432000, 32000, 0, 13, },
196 { 18432000, 48000, 0, 1, },
197 { 18432000, 96000, 0, 15, },
199 { 16934400, 8018, 0, 19, },
200 { 16934400, 11025, 0, 25, },
201 { 16934400, 22050, 0, 27, },
202 { 16934400, 44100, 0, 17, },
203 { 16934400, 88200, 0, 31, },
205 { 12000000, 8000, 1, 2, },
206 { 12000000, 11025, 1, 25, },
207 { 12000000, 12000, 1, 8, },
208 { 12000000, 16000, 1, 10, },
209 { 12000000, 22050, 1, 27, },
210 { 12000000, 24000, 1, 28, },
211 { 12000000, 32000, 1, 12, },
212 { 12000000, 44100, 1, 17, },
213 { 12000000, 48000, 1, 0, },
214 { 12000000, 88200, 1, 31, },
215 { 12000000, 96000, 1, 14, },
217 { 12288000, 8000, 0, 2, },
218 { 12288000, 12000, 0, 8, },
219 { 12288000, 16000, 0, 10, },
220 { 12288000, 24000, 0, 28, },
221 { 12288000, 32000, 0, 12, },
222 { 12288000, 48000, 0, 0, },
223 { 12288000, 96000, 0, 14, },
225 { 12289600, 8018, 0, 18, },
226 { 12289600, 11025, 0, 24, },
227 { 12289600, 22050, 0, 26, },
228 { 11289600, 44100, 0, 16, },
229 { 11289600, 88200, 0, 31, },
232 static int wm8955_configure_clocking(struct snd_soc_codec
*codec
)
234 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
239 struct pll_factors pll
;
241 /* If we're not running a sample rate currently just pick one */
245 /* Can we generate an exact output? */
246 for (i
= 0; i
< ARRAY_SIZE(clock_cfgs
); i
++) {
247 if (wm8955
->fs
!= clock_cfgs
[i
].fs
)
251 if (wm8955
->mclk_rate
== clock_cfgs
[i
].mclk
)
255 /* We should never get here with an unsupported sample rate */
257 dev_err(codec
->dev
, "Sample rate %dHz unsupported\n",
263 if (i
== ARRAY_SIZE(clock_cfgs
)) {
264 /* If we can't generate the right clock from MCLK then
265 * we should configure the PLL to supply us with an
268 clocking
|= WM8955_MCLKSEL
;
270 /* Use the last divider configuration we saw for the
272 ret
= wm8995_pll_factors(codec
->dev
, wm8955
->mclk_rate
,
273 clock_cfgs
[sr
].mclk
, &pll
);
276 "Unable to generate %dHz from %dHz MCLK\n",
277 wm8955
->fs
, wm8955
->mclk_rate
);
281 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_1
,
282 WM8955_N_MASK
| WM8955_K_21_18_MASK
,
283 (pll
.n
<< WM8955_N_SHIFT
) |
285 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_2
,
287 (pll
.k
>> 9) & WM8955_K_17_9_MASK
);
288 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_2
,
290 pll
.k
& WM8955_K_8_0_MASK
);
292 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_4
,
293 WM8955_KEN
, WM8955_KEN
);
295 snd_soc_update_bits(codec
, WM8955_PLL_CONTROL_4
,
299 val
= WM8955_PLL_RB
| WM8955_PLLOUTDIV2
;
303 /* Now start the PLL running */
304 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
305 WM8955_PLL_RB
| WM8955_PLLOUTDIV2
, val
);
306 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
307 WM8955_PLLEN
, WM8955_PLLEN
);
310 srate
= clock_cfgs
[sr
].usb
| (clock_cfgs
[sr
].sr
<< WM8955_SR_SHIFT
);
312 snd_soc_update_bits(codec
, WM8955_SAMPLE_RATE
,
313 WM8955_USB
| WM8955_SR_MASK
, srate
);
314 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
315 WM8955_MCLKSEL
, clocking
);
320 static int wm8955_sysclk(struct snd_soc_dapm_widget
*w
,
321 struct snd_kcontrol
*kcontrol
, int event
)
323 struct snd_soc_codec
*codec
= w
->codec
;
326 /* Always disable the clocks - if we're doing reconfiguration this
327 * avoids misclocking.
329 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
331 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
332 WM8955_PLL_RB
| WM8955_PLLEN
, 0);
335 case SND_SOC_DAPM_POST_PMD
:
337 case SND_SOC_DAPM_PRE_PMU
:
338 ret
= wm8955_configure_clocking(codec
);
348 static int deemph_settings
[] = { 0, 32000, 44100, 48000 };
350 static int wm8955_set_deemph(struct snd_soc_codec
*codec
)
352 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
355 /* If we're using deemphasis select the nearest available sample
358 if (wm8955
->deemph
) {
360 for (i
= 2; i
< ARRAY_SIZE(deemph_settings
); i
++) {
361 if (abs(deemph_settings
[i
] - wm8955
->fs
) <
362 abs(deemph_settings
[best
] - wm8955
->fs
))
366 val
= best
<< WM8955_DEEMPH_SHIFT
;
371 dev_dbg(codec
->dev
, "Set deemphasis %d\n", val
);
373 return snd_soc_update_bits(codec
, WM8955_DAC_CONTROL
,
374 WM8955_DEEMPH_MASK
, val
);
377 static int wm8955_get_deemph(struct snd_kcontrol
*kcontrol
,
378 struct snd_ctl_elem_value
*ucontrol
)
380 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
381 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
383 return wm8955
->deemph
;
386 static int wm8955_put_deemph(struct snd_kcontrol
*kcontrol
,
387 struct snd_ctl_elem_value
*ucontrol
)
389 struct snd_soc_codec
*codec
= snd_kcontrol_chip(kcontrol
);
390 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
391 int deemph
= ucontrol
->value
.enumerated
.item
[0];
396 wm8955
->deemph
= deemph
;
398 return wm8955_set_deemph(codec
);
401 static const char *bass_mode_text
[] = {
402 "Linear", "Adaptive",
405 static const struct soc_enum bass_mode
=
406 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL
, 7, 2, bass_mode_text
);
408 static const char *bass_cutoff_text
[] = {
412 static const struct soc_enum bass_cutoff
=
413 SOC_ENUM_SINGLE(WM8955_BASS_CONTROL
, 6, 2, bass_cutoff_text
);
415 static const char *treble_cutoff_text
[] = {
419 static const struct soc_enum treble_cutoff
=
420 SOC_ENUM_SINGLE(WM8955_TREBLE_CONTROL
, 6, 2, treble_cutoff_text
);
422 static const DECLARE_TLV_DB_SCALE(digital_tlv
, -12750, 50, 1);
423 static const DECLARE_TLV_DB_SCALE(atten_tlv
, -600, 600, 0);
424 static const DECLARE_TLV_DB_SCALE(bypass_tlv
, -1500, 300, 0);
425 static const DECLARE_TLV_DB_SCALE(mono_tlv
, -2100, 300, 0);
426 static const DECLARE_TLV_DB_SCALE(out_tlv
, -12100, 100, 1);
427 static const DECLARE_TLV_DB_SCALE(treble_tlv
, -1200, 150, 1);
429 static const struct snd_kcontrol_new wm8955_snd_controls
[] = {
430 SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8955_LEFT_DAC_VOLUME
,
431 WM8955_RIGHT_DAC_VOLUME
, 0, 255, 0, digital_tlv
),
432 SOC_SINGLE_TLV("Playback Attenuation Volume", WM8955_DAC_CONTROL
, 7, 1, 1,
434 SOC_SINGLE_BOOL_EXT("DAC Deemphasis Switch", 0,
435 wm8955_get_deemph
, wm8955_put_deemph
),
437 SOC_ENUM("Bass Mode", bass_mode
),
438 SOC_ENUM("Bass Cutoff", bass_cutoff
),
439 SOC_SINGLE("Bass Volume", WM8955_BASS_CONTROL
, 0, 15, 1),
441 SOC_ENUM("Treble Cutoff", treble_cutoff
),
442 SOC_SINGLE_TLV("Treble Volume", WM8955_TREBLE_CONTROL
, 0, 14, 1, treble_tlv
),
444 SOC_SINGLE_TLV("Left Bypass Volume", WM8955_LEFT_OUT_MIX_1
, 4, 7, 1,
446 SOC_SINGLE_TLV("Left Mono Volume", WM8955_LEFT_OUT_MIX_2
, 4, 7, 1,
449 SOC_SINGLE_TLV("Right Mono Volume", WM8955_RIGHT_OUT_MIX_1
, 4, 7, 1,
451 SOC_SINGLE_TLV("Right Bypass Volume", WM8955_RIGHT_OUT_MIX_2
, 4, 7, 1,
454 /* Not a stereo pair so they line up with the DAPM switches */
455 SOC_SINGLE_TLV("Mono Left Bypass Volume", WM8955_MONO_OUT_MIX_1
, 4, 7, 1,
457 SOC_SINGLE_TLV("Mono Right Bypass Volume", WM8955_MONO_OUT_MIX_2
, 4, 7, 1,
460 SOC_DOUBLE_R_TLV("Headphone Volume", WM8955_LOUT1_VOLUME
,
461 WM8955_ROUT1_VOLUME
, 0, 127, 0, out_tlv
),
462 SOC_DOUBLE_R("Headphone ZC Switch", WM8955_LOUT1_VOLUME
,
463 WM8955_ROUT1_VOLUME
, 7, 1, 0),
465 SOC_DOUBLE_R_TLV("Speaker Volume", WM8955_LOUT2_VOLUME
,
466 WM8955_ROUT2_VOLUME
, 0, 127, 0, out_tlv
),
467 SOC_DOUBLE_R("Speaker ZC Switch", WM8955_LOUT2_VOLUME
,
468 WM8955_ROUT2_VOLUME
, 7, 1, 0),
470 SOC_SINGLE_TLV("Mono Volume", WM8955_MONOOUT_VOLUME
, 0, 127, 0, out_tlv
),
471 SOC_SINGLE("Mono ZC Switch", WM8955_MONOOUT_VOLUME
, 7, 1, 0),
474 static const struct snd_kcontrol_new lmixer
[] = {
475 SOC_DAPM_SINGLE("Playback Switch", WM8955_LEFT_OUT_MIX_1
, 8, 1, 0),
476 SOC_DAPM_SINGLE("Bypass Switch", WM8955_LEFT_OUT_MIX_1
, 7, 1, 0),
477 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_LEFT_OUT_MIX_2
, 8, 1, 0),
478 SOC_DAPM_SINGLE("Mono Switch", WM8955_LEFT_OUT_MIX_2
, 7, 1, 0),
481 static const struct snd_kcontrol_new rmixer
[] = {
482 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_RIGHT_OUT_MIX_1
, 8, 1, 0),
483 SOC_DAPM_SINGLE("Mono Switch", WM8955_RIGHT_OUT_MIX_1
, 7, 1, 0),
484 SOC_DAPM_SINGLE("Playback Switch", WM8955_RIGHT_OUT_MIX_2
, 8, 1, 0),
485 SOC_DAPM_SINGLE("Bypass Switch", WM8955_RIGHT_OUT_MIX_2
, 7, 1, 0),
488 static const struct snd_kcontrol_new mmixer
[] = {
489 SOC_DAPM_SINGLE("Left Playback Switch", WM8955_MONO_OUT_MIX_1
, 8, 1, 0),
490 SOC_DAPM_SINGLE("Left Bypass Switch", WM8955_MONO_OUT_MIX_1
, 7, 1, 0),
491 SOC_DAPM_SINGLE("Right Playback Switch", WM8955_MONO_OUT_MIX_2
, 8, 1, 0),
492 SOC_DAPM_SINGLE("Right Bypass Switch", WM8955_MONO_OUT_MIX_2
, 7, 1, 0),
495 static const struct snd_soc_dapm_widget wm8955_dapm_widgets
[] = {
496 SND_SOC_DAPM_INPUT("MONOIN-"),
497 SND_SOC_DAPM_INPUT("MONOIN+"),
498 SND_SOC_DAPM_INPUT("LINEINR"),
499 SND_SOC_DAPM_INPUT("LINEINL"),
501 SND_SOC_DAPM_PGA("Mono Input", SND_SOC_NOPM
, 0, 0, NULL
, 0),
503 SND_SOC_DAPM_SUPPLY("SYSCLK", WM8955_POWER_MANAGEMENT_1
, 0, 1, wm8955_sysclk
,
504 SND_SOC_DAPM_PRE_PMU
| SND_SOC_DAPM_POST_PMD
),
505 SND_SOC_DAPM_SUPPLY("TSDEN", WM8955_ADDITIONAL_CONTROL_1
, 8, 0, NULL
, 0),
507 SND_SOC_DAPM_DAC("DACL", "Playback", WM8955_POWER_MANAGEMENT_2
, 8, 0),
508 SND_SOC_DAPM_DAC("DACR", "Playback", WM8955_POWER_MANAGEMENT_2
, 7, 0),
510 SND_SOC_DAPM_PGA("LOUT1 PGA", WM8955_POWER_MANAGEMENT_2
, 6, 0, NULL
, 0),
511 SND_SOC_DAPM_PGA("ROUT1 PGA", WM8955_POWER_MANAGEMENT_2
, 5, 0, NULL
, 0),
512 SND_SOC_DAPM_PGA("LOUT2 PGA", WM8955_POWER_MANAGEMENT_2
, 4, 0, NULL
, 0),
513 SND_SOC_DAPM_PGA("ROUT2 PGA", WM8955_POWER_MANAGEMENT_2
, 3, 0, NULL
, 0),
514 SND_SOC_DAPM_PGA("MOUT PGA", WM8955_POWER_MANAGEMENT_2
, 2, 0, NULL
, 0),
515 SND_SOC_DAPM_PGA("OUT3 PGA", WM8955_POWER_MANAGEMENT_2
, 1, 0, NULL
, 0),
517 /* The names are chosen to make the control names nice */
518 SND_SOC_DAPM_MIXER("Left", SND_SOC_NOPM
, 0, 0,
519 lmixer
, ARRAY_SIZE(lmixer
)),
520 SND_SOC_DAPM_MIXER("Right", SND_SOC_NOPM
, 0, 0,
521 rmixer
, ARRAY_SIZE(rmixer
)),
522 SND_SOC_DAPM_MIXER("Mono", SND_SOC_NOPM
, 0, 0,
523 mmixer
, ARRAY_SIZE(mmixer
)),
525 SND_SOC_DAPM_OUTPUT("LOUT1"),
526 SND_SOC_DAPM_OUTPUT("ROUT1"),
527 SND_SOC_DAPM_OUTPUT("LOUT2"),
528 SND_SOC_DAPM_OUTPUT("ROUT2"),
529 SND_SOC_DAPM_OUTPUT("MONOOUT"),
530 SND_SOC_DAPM_OUTPUT("OUT3"),
533 static const struct snd_soc_dapm_route wm8955_intercon
[] = {
534 { "DACL", NULL
, "SYSCLK" },
535 { "DACR", NULL
, "SYSCLK" },
537 { "Mono Input", NULL
, "MONOIN-" },
538 { "Mono Input", NULL
, "MONOIN+" },
540 { "Left", "Playback Switch", "DACL" },
541 { "Left", "Right Playback Switch", "DACR" },
542 { "Left", "Bypass Switch", "LINEINL" },
543 { "Left", "Mono Switch", "Mono Input" },
545 { "Right", "Playback Switch", "DACR" },
546 { "Right", "Left Playback Switch", "DACL" },
547 { "Right", "Bypass Switch", "LINEINR" },
548 { "Right", "Mono Switch", "Mono Input" },
550 { "Mono", "Left Playback Switch", "DACL" },
551 { "Mono", "Right Playback Switch", "DACR" },
552 { "Mono", "Left Bypass Switch", "LINEINL" },
553 { "Mono", "Right Bypass Switch", "LINEINR" },
555 { "LOUT1 PGA", NULL
, "Left" },
556 { "LOUT1", NULL
, "TSDEN" },
557 { "LOUT1", NULL
, "LOUT1 PGA" },
559 { "ROUT1 PGA", NULL
, "Right" },
560 { "ROUT1", NULL
, "TSDEN" },
561 { "ROUT1", NULL
, "ROUT1 PGA" },
563 { "LOUT2 PGA", NULL
, "Left" },
564 { "LOUT2", NULL
, "TSDEN" },
565 { "LOUT2", NULL
, "LOUT2 PGA" },
567 { "ROUT2 PGA", NULL
, "Right" },
568 { "ROUT2", NULL
, "TSDEN" },
569 { "ROUT2", NULL
, "ROUT2 PGA" },
571 { "MOUT PGA", NULL
, "Mono" },
572 { "MONOOUT", NULL
, "MOUT PGA" },
574 /* OUT3 not currently implemented */
575 { "OUT3", NULL
, "OUT3 PGA" },
578 static int wm8955_add_widgets(struct snd_soc_codec
*codec
)
580 snd_soc_add_controls(codec
, wm8955_snd_controls
,
581 ARRAY_SIZE(wm8955_snd_controls
));
583 snd_soc_dapm_new_controls(codec
, wm8955_dapm_widgets
,
584 ARRAY_SIZE(wm8955_dapm_widgets
));
586 snd_soc_dapm_add_routes(codec
, wm8955_intercon
,
587 ARRAY_SIZE(wm8955_intercon
));
592 static int wm8955_hw_params(struct snd_pcm_substream
*substream
,
593 struct snd_pcm_hw_params
*params
,
594 struct snd_soc_dai
*dai
)
596 struct snd_soc_codec
*codec
= dai
->codec
;
597 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
601 switch (params_format(params
)) {
602 case SNDRV_PCM_FORMAT_S16_LE
:
605 case SNDRV_PCM_FORMAT_S20_3LE
:
608 case SNDRV_PCM_FORMAT_S24_LE
:
611 case SNDRV_PCM_FORMAT_S32_LE
:
617 snd_soc_update_bits(codec
, WM8955_AUDIO_INTERFACE
,
620 wm8955
->fs
= params_rate(params
);
621 wm8955_set_deemph(codec
);
623 /* If the chip is clocked then disable the clocks and force a
624 * reconfiguration, otherwise DAPM will power up the
625 * clocks for us later. */
626 ret
= snd_soc_read(codec
, WM8955_POWER_MANAGEMENT_1
);
629 if (ret
& WM8955_DIGENB
) {
630 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
632 snd_soc_update_bits(codec
, WM8955_CLOCKING_PLL
,
633 WM8955_PLL_RB
| WM8955_PLLEN
, 0);
635 wm8955_configure_clocking(codec
);
642 static int wm8955_set_sysclk(struct snd_soc_dai
*dai
, int clk_id
,
643 unsigned int freq
, int dir
)
645 struct snd_soc_codec
*codec
= dai
->codec
;
646 struct wm8955_priv
*priv
= snd_soc_codec_get_drvdata(codec
);
650 case WM8955_CLK_MCLK
:
651 if (freq
> 15000000) {
652 priv
->mclk_rate
= freq
/= 2;
653 div
= WM8955_MCLKDIV2
;
655 priv
->mclk_rate
= freq
;
659 snd_soc_update_bits(codec
, WM8955_SAMPLE_RATE
,
660 WM8955_MCLKDIV2
, div
);
667 dev_dbg(dai
->dev
, "Clock source is %d at %uHz\n", clk_id
, freq
);
672 static int wm8955_set_fmt(struct snd_soc_dai
*dai
, unsigned int fmt
)
674 struct snd_soc_codec
*codec
= dai
->codec
;
677 switch (fmt
& SND_SOC_DAIFMT_MASTER_MASK
) {
678 case SND_SOC_DAIFMT_CBS_CFS
:
680 case SND_SOC_DAIFMT_CBM_CFM
:
687 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
688 case SND_SOC_DAIFMT_DSP_B
:
690 case SND_SOC_DAIFMT_DSP_A
:
693 case SND_SOC_DAIFMT_I2S
:
696 case SND_SOC_DAIFMT_RIGHT_J
:
698 case SND_SOC_DAIFMT_LEFT_J
:
705 switch (fmt
& SND_SOC_DAIFMT_FORMAT_MASK
) {
706 case SND_SOC_DAIFMT_DSP_A
:
707 case SND_SOC_DAIFMT_DSP_B
:
708 /* frame inversion not valid for DSP modes */
709 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
710 case SND_SOC_DAIFMT_NB_NF
:
712 case SND_SOC_DAIFMT_IB_NF
:
713 aif
|= WM8955_BCLKINV
;
720 case SND_SOC_DAIFMT_I2S
:
721 case SND_SOC_DAIFMT_RIGHT_J
:
722 case SND_SOC_DAIFMT_LEFT_J
:
723 switch (fmt
& SND_SOC_DAIFMT_INV_MASK
) {
724 case SND_SOC_DAIFMT_NB_NF
:
726 case SND_SOC_DAIFMT_IB_IF
:
727 aif
|= WM8955_BCLKINV
| WM8955_LRP
;
729 case SND_SOC_DAIFMT_IB_NF
:
730 aif
|= WM8955_BCLKINV
;
732 case SND_SOC_DAIFMT_NB_IF
:
743 snd_soc_update_bits(codec
, WM8955_AUDIO_INTERFACE
,
744 WM8955_MS
| WM8955_FORMAT_MASK
| WM8955_BCLKINV
|
751 static int wm8955_digital_mute(struct snd_soc_dai
*codec_dai
, int mute
)
753 struct snd_soc_codec
*codec
= codec_dai
->codec
;
761 snd_soc_update_bits(codec
, WM8955_DAC_CONTROL
, WM8955_DACMU
, val
);
766 static int wm8955_set_bias_level(struct snd_soc_codec
*codec
,
767 enum snd_soc_bias_level level
)
769 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
773 case SND_SOC_BIAS_ON
:
776 case SND_SOC_BIAS_PREPARE
:
777 /* VMID resistance 2*50k */
778 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
780 0x1 << WM8955_VMIDSEL_SHIFT
);
782 /* Default bias current */
783 snd_soc_update_bits(codec
, WM8955_ADDITIONAL_CONTROL_1
,
785 0x2 << WM8955_VSEL_SHIFT
);
788 case SND_SOC_BIAS_STANDBY
:
789 if (codec
->bias_level
== SND_SOC_BIAS_OFF
) {
790 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8955
->supplies
),
794 "Failed to enable supplies: %d\n",
799 /* Sync back cached values if they're
800 * different from the hardware default.
802 for (i
= 0; i
< ARRAY_SIZE(wm8955
->reg_cache
); i
++) {
803 if (i
== WM8955_RESET
)
806 if (wm8955
->reg_cache
[i
] == wm8955_reg
[i
])
809 snd_soc_write(codec
, i
, wm8955
->reg_cache
[i
]);
812 /* Enable VREF and VMID */
813 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
817 0x3 << WM8955_VREF_SHIFT
);
822 /* High resistance VROI to maintain outputs */
823 snd_soc_update_bits(codec
,
824 WM8955_ADDITIONAL_CONTROL_3
,
825 WM8955_VROI
, WM8955_VROI
);
828 /* Maintain VMID with 2*250k */
829 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
831 0x2 << WM8955_VMIDSEL_SHIFT
);
833 /* Minimum bias current */
834 snd_soc_update_bits(codec
, WM8955_ADDITIONAL_CONTROL_1
,
835 WM8955_VSEL_MASK
, 0);
838 case SND_SOC_BIAS_OFF
:
839 /* Low resistance VROI to help discharge */
840 snd_soc_update_bits(codec
,
841 WM8955_ADDITIONAL_CONTROL_3
,
844 /* Turn off VMID and VREF */
845 snd_soc_update_bits(codec
, WM8955_POWER_MANAGEMENT_1
,
847 WM8955_VMIDSEL_MASK
, 0);
849 regulator_bulk_disable(ARRAY_SIZE(wm8955
->supplies
),
853 codec
->bias_level
= level
;
857 #define WM8955_RATES SNDRV_PCM_RATE_8000_96000
859 #define WM8955_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
860 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
862 static struct snd_soc_dai_ops wm8955_dai_ops
= {
863 .set_sysclk
= wm8955_set_sysclk
,
864 .set_fmt
= wm8955_set_fmt
,
865 .hw_params
= wm8955_hw_params
,
866 .digital_mute
= wm8955_digital_mute
,
869 static struct snd_soc_dai_driver wm8955_dai
= {
870 .name
= "wm8955-hifi",
872 .stream_name
= "Playback",
875 .rates
= WM8955_RATES
,
876 .formats
= WM8955_FORMATS
,
878 .ops
= &wm8955_dai_ops
,
882 static int wm8955_suspend(struct snd_soc_codec
*codec
, pm_message_t state
)
884 wm8955_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
889 static int wm8955_resume(struct snd_soc_codec
*codec
)
891 wm8955_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
896 #define wm8955_suspend NULL
897 #define wm8955_resume NULL
900 static int wm8955_probe(struct snd_soc_codec
*codec
)
902 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
903 struct wm8955_pdata
*pdata
= dev_get_platdata(codec
->dev
);
906 ret
= snd_soc_codec_set_cache_io(codec
, 7, 9, wm8955
->control_type
);
908 dev_err(codec
->dev
, "Failed to set cache I/O: %d\n", ret
);
912 for (i
= 0; i
< ARRAY_SIZE(wm8955
->supplies
); i
++)
913 wm8955
->supplies
[i
].supply
= wm8955_supply_names
[i
];
915 ret
= regulator_bulk_get(codec
->dev
, ARRAY_SIZE(wm8955
->supplies
),
918 dev_err(codec
->dev
, "Failed to request supplies: %d\n", ret
);
922 ret
= regulator_bulk_enable(ARRAY_SIZE(wm8955
->supplies
),
925 dev_err(codec
->dev
, "Failed to enable supplies: %d\n", ret
);
929 ret
= wm8955_reset(codec
);
931 dev_err(codec
->dev
, "Failed to issue reset: %d\n", ret
);
935 /* Change some default settings - latch VU and enable ZC */
936 wm8955
->reg_cache
[WM8955_LEFT_DAC_VOLUME
] |= WM8955_LDVU
;
937 wm8955
->reg_cache
[WM8955_RIGHT_DAC_VOLUME
] |= WM8955_RDVU
;
938 wm8955
->reg_cache
[WM8955_LOUT1_VOLUME
] |= WM8955_LO1VU
| WM8955_LO1ZC
;
939 wm8955
->reg_cache
[WM8955_ROUT1_VOLUME
] |= WM8955_RO1VU
| WM8955_RO1ZC
;
940 wm8955
->reg_cache
[WM8955_LOUT2_VOLUME
] |= WM8955_LO2VU
| WM8955_LO2ZC
;
941 wm8955
->reg_cache
[WM8955_ROUT2_VOLUME
] |= WM8955_RO2VU
| WM8955_RO2ZC
;
942 wm8955
->reg_cache
[WM8955_MONOOUT_VOLUME
] |= WM8955_MOZC
;
944 /* Also enable adaptive bass boost by default */
945 wm8955
->reg_cache
[WM8955_BASS_CONTROL
] |= WM8955_BB
;
947 /* Set platform data values */
949 if (pdata
->out2_speaker
)
950 wm8955
->reg_cache
[WM8955_ADDITIONAL_CONTROL_2
]
953 if (pdata
->monoin_diff
)
954 wm8955
->reg_cache
[WM8955_MONO_OUT_MIX_1
]
958 wm8955_set_bias_level(codec
, SND_SOC_BIAS_STANDBY
);
960 /* Bias level configuration will have done an extra enable */
961 regulator_bulk_disable(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
963 wm8955_add_widgets(codec
);
967 regulator_bulk_disable(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
969 regulator_bulk_free(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
973 static int wm8955_remove(struct snd_soc_codec
*codec
)
975 struct wm8955_priv
*wm8955
= snd_soc_codec_get_drvdata(codec
);
977 wm8955_set_bias_level(codec
, SND_SOC_BIAS_OFF
);
978 regulator_bulk_free(ARRAY_SIZE(wm8955
->supplies
), wm8955
->supplies
);
982 static struct snd_soc_codec_driver soc_codec_dev_wm8955
= {
983 .probe
= wm8955_probe
,
984 .remove
= wm8955_remove
,
985 .suspend
= wm8955_suspend
,
986 .resume
= wm8955_resume
,
987 .set_bias_level
= wm8955_set_bias_level
,
988 .reg_cache_size
= ARRAY_SIZE(wm8955_reg
),
989 .reg_word_size
= sizeof(u16
),
990 .reg_cache_default
= wm8955_reg
,
993 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
994 static __devinit
int wm8955_i2c_probe(struct i2c_client
*i2c
,
995 const struct i2c_device_id
*id
)
997 struct wm8955_priv
*wm8955
;
1000 wm8955
= kzalloc(sizeof(struct wm8955_priv
), GFP_KERNEL
);
1004 i2c_set_clientdata(i2c
, wm8955
);
1006 ret
= snd_soc_register_codec(&i2c
->dev
,
1007 &soc_codec_dev_wm8955
, &wm8955_dai
, 1);
1013 static __devexit
int wm8955_i2c_remove(struct i2c_client
*client
)
1015 snd_soc_unregister_codec(&client
->dev
);
1016 kfree(i2c_get_clientdata(client
));
1020 static const struct i2c_device_id wm8955_i2c_id
[] = {
1024 MODULE_DEVICE_TABLE(i2c
, wm8955_i2c_id
);
1026 static struct i2c_driver wm8955_i2c_driver
= {
1028 .name
= "wm8955-codec",
1029 .owner
= THIS_MODULE
,
1031 .probe
= wm8955_i2c_probe
,
1032 .remove
= __devexit_p(wm8955_i2c_remove
),
1033 .id_table
= wm8955_i2c_id
,
1037 static int __init
wm8955_modinit(void)
1040 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1041 ret
= i2c_add_driver(&wm8955_i2c_driver
);
1043 printk(KERN_ERR
"Failed to register WM8955 I2C driver: %d\n",
1049 module_init(wm8955_modinit
);
1051 static void __exit
wm8955_exit(void)
1053 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1054 i2c_del_driver(&wm8955_i2c_driver
);
1057 module_exit(wm8955_exit
);
1059 MODULE_DESCRIPTION("ASoC WM8955 driver");
1060 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1061 MODULE_LICENSE("GPL");