projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
ASoC: sta32x: Fix wrong enum for limiter2 release rate
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / soc / codecs / sta32x.c
1 /*
2 * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
3 *
4 * Copyright: 2011 Raumfeld GmbH
5 * Author: Johannes Stezenbach <js@sig21.net>
6 *
7 * based on code from:
8 * Wolfson Microelectronics PLC.
9 * Mark Brown <broonie@opensource.wolfsonmicro.com>
10 * Freescale Semiconductor, Inc.
11 * Timur Tabi <timur@freescale.com>
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/pm.h>
26 #include <linux/i2c.h>
27 #include <linux/regmap.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/workqueue.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <sound/soc-dapm.h>
36 #include <sound/initval.h>
37 #include <sound/tlv.h>
38
39 #include <sound/sta32x.h>
40 #include "sta32x.h"
41
42 #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
43 SNDRV_PCM_RATE_44100 | \
44 SNDRV_PCM_RATE_48000 | \
45 SNDRV_PCM_RATE_88200 | \
46 SNDRV_PCM_RATE_96000 | \
47 SNDRV_PCM_RATE_176400 | \
48 SNDRV_PCM_RATE_192000)
49
50 #define STA32X_FORMATS \
51 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | \
52 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S18_3BE | \
53 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S20_3BE | \
54 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | \
55 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE | \
56 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE)
57
58 /* Power-up register defaults */
59 static const struct reg_default sta32x_regs[] = {
60 { 0x0, 0x63 },
61 { 0x1, 0x80 },
62 { 0x2, 0xc2 },
63 { 0x3, 0x40 },
64 { 0x4, 0xc2 },
65 { 0x5, 0x5c },
66 { 0x6, 0x10 },
67 { 0x7, 0xff },
68 { 0x8, 0x60 },
69 { 0x9, 0x60 },
70 { 0xa, 0x60 },
71 { 0xb, 0x80 },
72 { 0xc, 0x00 },
73 { 0xd, 0x00 },
74 { 0xe, 0x00 },
75 { 0xf, 0x40 },
76 { 0x10, 0x80 },
77 { 0x11, 0x77 },
78 { 0x12, 0x6a },
79 { 0x13, 0x69 },
80 { 0x14, 0x6a },
81 { 0x15, 0x69 },
82 { 0x16, 0x00 },
83 { 0x17, 0x00 },
84 { 0x18, 0x00 },
85 { 0x19, 0x00 },
86 { 0x1a, 0x00 },
87 { 0x1b, 0x00 },
88 { 0x1c, 0x00 },
89 { 0x1d, 0x00 },
90 { 0x1e, 0x00 },
91 { 0x1f, 0x00 },
92 { 0x20, 0x00 },
93 { 0x21, 0x00 },
94 { 0x22, 0x00 },
95 { 0x23, 0x00 },
96 { 0x24, 0x00 },
97 { 0x25, 0x00 },
98 { 0x26, 0x00 },
99 { 0x27, 0x2d },
100 { 0x28, 0xc0 },
101 { 0x2b, 0x00 },
102 { 0x2c, 0x0c },
103 };
104
105 /* regulator power supply names */
106 static const char *sta32x_supply_names[] = {
107 "Vdda", /* analog supply, 3.3VV */
108 "Vdd3", /* digital supply, 3.3V */
109 "Vcc" /* power amp spply, 10V - 36V */
110 };
111
112 /* codec private data */
113 struct sta32x_priv {
114 struct regmap *regmap;
115 struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
116 struct snd_soc_codec *codec;
117 struct sta32x_platform_data *pdata;
118
119 unsigned int mclk;
120 unsigned int format;
121
122 u32 coef_shadow[STA32X_COEF_COUNT];
123 struct delayed_work watchdog_work;
124 int shutdown;
125 };
126
127 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
128 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
129 static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
130
131 static const char *sta32x_drc_ac[] = {
132 "Anti-Clipping", "Dynamic Range Compression" };
133 static const char *sta32x_auto_eq_mode[] = {
134 "User", "Preset", "Loudness" };
135 static const char *sta32x_auto_gc_mode[] = {
136 "User", "AC no clipping", "AC limited clipping (10%)",
137 "DRC nighttime listening mode" };
138 static const char *sta32x_auto_xo_mode[] = {
139 "User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
140 "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
141 static const char *sta32x_preset_eq_mode[] = {
142 "Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
143 "Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
144 "Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
145 "Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
146 "Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
147 "Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
148 static const char *sta32x_limiter_select[] = {
149 "Limiter Disabled", "Limiter #1", "Limiter #2" };
150 static const char *sta32x_limiter_attack_rate[] = {
151 "3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
152 "0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
153 "0.0645", "0.0564", "0.0501", "0.0451" };
154 static const char *sta32x_limiter_release_rate[] = {
155 "0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
156 "0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
157 "0.0134", "0.0117", "0.0110", "0.0104" };
158
159 static const unsigned int sta32x_limiter_ac_attack_tlv[] = {
160 TLV_DB_RANGE_HEAD(2),
161 0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
162 8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
163 };
164
165 static const unsigned int sta32x_limiter_ac_release_tlv[] = {
166 TLV_DB_RANGE_HEAD(5),
167 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
168 1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
169 2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
170 3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
171 8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
172 };
173
174 static const unsigned int sta32x_limiter_drc_attack_tlv[] = {
175 TLV_DB_RANGE_HEAD(3),
176 0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
177 8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
178 14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
179 };
180
181 static const unsigned int sta32x_limiter_drc_release_tlv[] = {
182 TLV_DB_RANGE_HEAD(5),
183 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
184 1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
185 3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
186 5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
187 13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
188 };
189
190 static const struct soc_enum sta32x_drc_ac_enum =
191 SOC_ENUM_SINGLE(STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
192 2, sta32x_drc_ac);
193 static const struct soc_enum sta32x_auto_eq_enum =
194 SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
195 3, sta32x_auto_eq_mode);
196 static const struct soc_enum sta32x_auto_gc_enum =
197 SOC_ENUM_SINGLE(STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
198 4, sta32x_auto_gc_mode);
199 static const struct soc_enum sta32x_auto_xo_enum =
200 SOC_ENUM_SINGLE(STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
201 16, sta32x_auto_xo_mode);
202 static const struct soc_enum sta32x_preset_eq_enum =
203 SOC_ENUM_SINGLE(STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
204 32, sta32x_preset_eq_mode);
205 static const struct soc_enum sta32x_limiter_ch1_enum =
206 SOC_ENUM_SINGLE(STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
207 3, sta32x_limiter_select);
208 static const struct soc_enum sta32x_limiter_ch2_enum =
209 SOC_ENUM_SINGLE(STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
210 3, sta32x_limiter_select);
211 static const struct soc_enum sta32x_limiter_ch3_enum =
212 SOC_ENUM_SINGLE(STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
213 3, sta32x_limiter_select);
214 static const struct soc_enum sta32x_limiter1_attack_rate_enum =
215 SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxA_SHIFT,
216 16, sta32x_limiter_attack_rate);
217 static const struct soc_enum sta32x_limiter2_attack_rate_enum =
218 SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxA_SHIFT,
219 16, sta32x_limiter_attack_rate);
220 static const struct soc_enum sta32x_limiter1_release_rate_enum =
221 SOC_ENUM_SINGLE(STA32X_L1AR, STA32X_LxR_SHIFT,
222 16, sta32x_limiter_release_rate);
223 static const struct soc_enum sta32x_limiter2_release_rate_enum =
224 SOC_ENUM_SINGLE(STA32X_L2AR, STA32X_LxR_SHIFT,
225 16, sta32x_limiter_release_rate);
226
227 /* byte array controls for setting biquad, mixer, scaling coefficients;
228 * for biquads all five coefficients need to be set in one go,
229 * mixer and pre/postscale coefs can be set individually;
230 * each coef is 24bit, the bytes are ordered in the same way
231 * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
232 */
233
234 static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
235 struct snd_ctl_elem_info *uinfo)
236 {
237 int numcoef = kcontrol->private_value >> 16;
238 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
239 uinfo->count = 3 * numcoef;
240 return 0;
241 }
242
243 static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
244 struct snd_ctl_elem_value *ucontrol)
245 {
246 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
247 int numcoef = kcontrol->private_value >> 16;
248 int index = kcontrol->private_value & 0xffff;
249 unsigned int cfud;
250 int i;
251
252 /* preserve reserved bits in STA32X_CFUD */
253 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
254 /* chip documentation does not say if the bits are self clearing,
255 * so do it explicitly */
256 snd_soc_write(codec, STA32X_CFUD, cfud);
257
258 snd_soc_write(codec, STA32X_CFADDR2, index);
259 if (numcoef == 1)
260 snd_soc_write(codec, STA32X_CFUD, cfud | 0x04);
261 else if (numcoef == 5)
262 snd_soc_write(codec, STA32X_CFUD, cfud | 0x08);
263 else
264 return -EINVAL;
265 for (i = 0; i < 3 * numcoef; i++)
266 ucontrol->value.bytes.data[i] =
267 snd_soc_read(codec, STA32X_B1CF1 + i);
268
269 return 0;
270 }
271
272 static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
273 struct snd_ctl_elem_value *ucontrol)
274 {
275 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
276 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
277 int numcoef = kcontrol->private_value >> 16;
278 int index = kcontrol->private_value & 0xffff;
279 unsigned int cfud;
280 int i;
281
282 /* preserve reserved bits in STA32X_CFUD */
283 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
284 /* chip documentation does not say if the bits are self clearing,
285 * so do it explicitly */
286 snd_soc_write(codec, STA32X_CFUD, cfud);
287
288 snd_soc_write(codec, STA32X_CFADDR2, index);
289 for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
290 sta32x->coef_shadow[index + i] =
291 (ucontrol->value.bytes.data[3 * i] << 16)
292 | (ucontrol->value.bytes.data[3 * i + 1] << 8)
293 | (ucontrol->value.bytes.data[3 * i + 2]);
294 for (i = 0; i < 3 * numcoef; i++)
295 snd_soc_write(codec, STA32X_B1CF1 + i,
296 ucontrol->value.bytes.data[i]);
297 if (numcoef == 1)
298 snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
299 else if (numcoef == 5)
300 snd_soc_write(codec, STA32X_CFUD, cfud | 0x02);
301 else
302 return -EINVAL;
303
304 return 0;
305 }
306
307 static int sta32x_sync_coef_shadow(struct snd_soc_codec *codec)
308 {
309 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
310 unsigned int cfud;
311 int i;
312
313 /* preserve reserved bits in STA32X_CFUD */
314 cfud = snd_soc_read(codec, STA32X_CFUD) & 0xf0;
315
316 for (i = 0; i < STA32X_COEF_COUNT; i++) {
317 snd_soc_write(codec, STA32X_CFADDR2, i);
318 snd_soc_write(codec, STA32X_B1CF1,
319 (sta32x->coef_shadow[i] >> 16) & 0xff);
320 snd_soc_write(codec, STA32X_B1CF2,
321 (sta32x->coef_shadow[i] >> 8) & 0xff);
322 snd_soc_write(codec, STA32X_B1CF3,
323 (sta32x->coef_shadow[i]) & 0xff);
324 /* chip documentation does not say if the bits are
325 * self-clearing, so do it explicitly */
326 snd_soc_write(codec, STA32X_CFUD, cfud);
327 snd_soc_write(codec, STA32X_CFUD, cfud | 0x01);
328 }
329 return 0;
330 }
331
332 static int sta32x_cache_sync(struct snd_soc_codec *codec)
333 {
334 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
335 unsigned int mute;
336 int rc;
337
338 /* mute during register sync */
339 mute = snd_soc_read(codec, STA32X_MMUTE);
340 snd_soc_write(codec, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
341 sta32x_sync_coef_shadow(codec);
342 rc = regcache_sync(sta32x->regmap);
343 snd_soc_write(codec, STA32X_MMUTE, mute);
344 return rc;
345 }
346
347 /* work around ESD issue where sta32x resets and loses all configuration */
348 static void sta32x_watchdog(struct work_struct *work)
349 {
350 struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
351 watchdog_work.work);
352 struct snd_soc_codec *codec = sta32x->codec;
353 unsigned int confa, confa_cached;
354
355 /* check if sta32x has reset itself */
356 confa_cached = snd_soc_read(codec, STA32X_CONFA);
357 regcache_cache_bypass(sta32x->regmap, true);
358 confa = snd_soc_read(codec, STA32X_CONFA);
359 regcache_cache_bypass(sta32x->regmap, false);
360 if (confa != confa_cached) {
361 regcache_mark_dirty(sta32x->regmap);
362 sta32x_cache_sync(codec);
363 }
364
365 if (!sta32x->shutdown)
366 schedule_delayed_work(&sta32x->watchdog_work,
367 round_jiffies_relative(HZ));
368 }
369
370 static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
371 {
372 if (sta32x->pdata->needs_esd_watchdog) {
373 sta32x->shutdown = 0;
374 schedule_delayed_work(&sta32x->watchdog_work,
375 round_jiffies_relative(HZ));
376 }
377 }
378
379 static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
380 {
381 if (sta32x->pdata->needs_esd_watchdog) {
382 sta32x->shutdown = 1;
383 cancel_delayed_work_sync(&sta32x->watchdog_work);
384 }
385 }
386
387 #define SINGLE_COEF(xname, index) \
388 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
389 .info = sta32x_coefficient_info, \
390 .get = sta32x_coefficient_get,\
391 .put = sta32x_coefficient_put, \
392 .private_value = index | (1 << 16) }
393
394 #define BIQUAD_COEFS(xname, index) \
395 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
396 .info = sta32x_coefficient_info, \
397 .get = sta32x_coefficient_get,\
398 .put = sta32x_coefficient_put, \
399 .private_value = index | (5 << 16) }
400
401 static const struct snd_kcontrol_new sta32x_snd_controls[] = {
402 SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
403 SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
404 SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
405 SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
406 SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
407 SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
408 SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
409 SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
410 SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
411 SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
412 SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
413 SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
414 SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
415 SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
416 SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
417 SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
418 SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
419 SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
420 SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
421 SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
422 SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
423 SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
424 SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
425 SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
426 SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
427 SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
428 SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
429 SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
430 SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
431 SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
432 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
433 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
434 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
435 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
436
437 /* depending on mode, the attack/release thresholds have
438 * two different enum definitions; provide both
439 */
440 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
441 16, 0, sta32x_limiter_ac_attack_tlv),
442 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
443 16, 0, sta32x_limiter_ac_attack_tlv),
444 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
445 16, 0, sta32x_limiter_ac_release_tlv),
446 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
447 16, 0, sta32x_limiter_ac_release_tlv),
448 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
449 16, 0, sta32x_limiter_drc_attack_tlv),
450 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
451 16, 0, sta32x_limiter_drc_attack_tlv),
452 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
453 16, 0, sta32x_limiter_drc_release_tlv),
454 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
455 16, 0, sta32x_limiter_drc_release_tlv),
456
457 BIQUAD_COEFS("Ch1 - Biquad 1", 0),
458 BIQUAD_COEFS("Ch1 - Biquad 2", 5),
459 BIQUAD_COEFS("Ch1 - Biquad 3", 10),
460 BIQUAD_COEFS("Ch1 - Biquad 4", 15),
461 BIQUAD_COEFS("Ch2 - Biquad 1", 20),
462 BIQUAD_COEFS("Ch2 - Biquad 2", 25),
463 BIQUAD_COEFS("Ch2 - Biquad 3", 30),
464 BIQUAD_COEFS("Ch2 - Biquad 4", 35),
465 BIQUAD_COEFS("High-pass", 40),
466 BIQUAD_COEFS("Low-pass", 45),
467 SINGLE_COEF("Ch1 - Prescale", 50),
468 SINGLE_COEF("Ch2 - Prescale", 51),
469 SINGLE_COEF("Ch1 - Postscale", 52),
470 SINGLE_COEF("Ch2 - Postscale", 53),
471 SINGLE_COEF("Ch3 - Postscale", 54),
472 SINGLE_COEF("Thermal warning - Postscale", 55),
473 SINGLE_COEF("Ch1 - Mix 1", 56),
474 SINGLE_COEF("Ch1 - Mix 2", 57),
475 SINGLE_COEF("Ch2 - Mix 1", 58),
476 SINGLE_COEF("Ch2 - Mix 2", 59),
477 SINGLE_COEF("Ch3 - Mix 1", 60),
478 SINGLE_COEF("Ch3 - Mix 2", 61),
479 };
480
481 static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
482 SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
483 SND_SOC_DAPM_OUTPUT("LEFT"),
484 SND_SOC_DAPM_OUTPUT("RIGHT"),
485 SND_SOC_DAPM_OUTPUT("SUB"),
486 };
487
488 static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
489 { "LEFT", NULL, "DAC" },
490 { "RIGHT", NULL, "DAC" },
491 { "SUB", NULL, "DAC" },
492 };
493
494 /* MCLK interpolation ratio per fs */
495 static struct {
496 int fs;
497 int ir;
498 } interpolation_ratios[] = {
499 { 32000, 0 },
500 { 44100, 0 },
501 { 48000, 0 },
502 { 88200, 1 },
503 { 96000, 1 },
504 { 176400, 2 },
505 { 192000, 2 },
506 };
507
508 /* MCLK to fs clock ratios */
509 static struct {
510 int ratio;
511 int mcs;
512 } mclk_ratios[3][7] = {
513 { { 768, 0 }, { 512, 1 }, { 384, 2 }, { 256, 3 },
514 { 128, 4 }, { 576, 5 }, { 0, 0 } },
515 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
516 { { 384, 2 }, { 256, 3 }, { 192, 4 }, { 128, 5 }, {64, 0 }, { 0, 0 } },
517 };
518
519
520 /**
521 * sta32x_set_dai_sysclk - configure MCLK
522 * @codec_dai: the codec DAI
523 * @clk_id: the clock ID (ignored)
524 * @freq: the MCLK input frequency
525 * @dir: the clock direction (ignored)
526 *
527 * The value of MCLK is used to determine which sample rates are supported
528 * by the STA32X, based on the mclk_ratios table.
529 *
530 * This function must be called by the machine driver's 'startup' function,
531 * otherwise the list of supported sample rates will not be available in
532 * time for ALSA.
533 *
534 * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
535 * theoretically possible sample rates to be enabled. Call it again with a
536 * proper value set one the external clock is set (most probably you would do
537 * that from a machine's driver 'hw_param' hook.
538 */
539 static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
540 int clk_id, unsigned int freq, int dir)
541 {
542 struct snd_soc_codec *codec = codec_dai->codec;
543 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
544 int i, j, ir, fs;
545 unsigned int rates = 0;
546 unsigned int rate_min = -1;
547 unsigned int rate_max = 0;
548
549 pr_debug("mclk=%u\n", freq);
550 sta32x->mclk = freq;
551
552 if (sta32x->mclk) {
553 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
554 ir = interpolation_ratios[i].ir;
555 fs = interpolation_ratios[i].fs;
556 for (j = 0; mclk_ratios[ir][j].ratio; j++) {
557 if (mclk_ratios[ir][j].ratio * fs == freq) {
558 rates |= snd_pcm_rate_to_rate_bit(fs);
559 if (fs < rate_min)
560 rate_min = fs;
561 if (fs > rate_max)
562 rate_max = fs;
563 break;
564 }
565 }
566 }
567 /* FIXME: soc should support a rate list */
568 rates &= ~SNDRV_PCM_RATE_KNOT;
569
570 if (!rates) {
571 dev_err(codec->dev, "could not find a valid sample rate\n");
572 return -EINVAL;
573 }
574 } else {
575 /* enable all possible rates */
576 rates = STA32X_RATES;
577 rate_min = 32000;
578 rate_max = 192000;
579 }
580
581 codec_dai->driver->playback.rates = rates;
582 codec_dai->driver->playback.rate_min = rate_min;
583 codec_dai->driver->playback.rate_max = rate_max;
584 return 0;
585 }
586
587 /**
588 * sta32x_set_dai_fmt - configure the codec for the selected audio format
589 * @codec_dai: the codec DAI
590 * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
591 *
592 * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
593 * codec accordingly.
594 */
595 static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
596 unsigned int fmt)
597 {
598 struct snd_soc_codec *codec = codec_dai->codec;
599 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
600 u8 confb = snd_soc_read(codec, STA32X_CONFB);
601
602 pr_debug("\n");
603 confb &= ~(STA32X_CONFB_C1IM | STA32X_CONFB_C2IM);
604
605 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
606 case SND_SOC_DAIFMT_CBS_CFS:
607 break;
608 default:
609 return -EINVAL;
610 }
611
612 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
613 case SND_SOC_DAIFMT_I2S:
614 case SND_SOC_DAIFMT_RIGHT_J:
615 case SND_SOC_DAIFMT_LEFT_J:
616 sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
617 break;
618 default:
619 return -EINVAL;
620 }
621
622 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
623 case SND_SOC_DAIFMT_NB_NF:
624 confb |= STA32X_CONFB_C2IM;
625 break;
626 case SND_SOC_DAIFMT_NB_IF:
627 confb |= STA32X_CONFB_C1IM;
628 break;
629 default:
630 return -EINVAL;
631 }
632
633 snd_soc_write(codec, STA32X_CONFB, confb);
634 return 0;
635 }
636
637 /**
638 * sta32x_hw_params - program the STA32X with the given hardware parameters.
639 * @substream: the audio stream
640 * @params: the hardware parameters to set
641 * @dai: the SOC DAI (ignored)
642 *
643 * This function programs the hardware with the values provided.
644 * Specifically, the sample rate and the data format.
645 */
646 static int sta32x_hw_params(struct snd_pcm_substream *substream,
647 struct snd_pcm_hw_params *params,
648 struct snd_soc_dai *dai)
649 {
650 struct snd_soc_codec *codec = dai->codec;
651 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
652 unsigned int rate;
653 int i, mcs = -1, ir = -1;
654 u8 confa, confb;
655
656 rate = params_rate(params);
657 pr_debug("rate: %u\n", rate);
658 for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++)
659 if (interpolation_ratios[i].fs == rate) {
660 ir = interpolation_ratios[i].ir;
661 break;
662 }
663 if (ir < 0)
664 return -EINVAL;
665 for (i = 0; mclk_ratios[ir][i].ratio; i++)
666 if (mclk_ratios[ir][i].ratio * rate == sta32x->mclk) {
667 mcs = mclk_ratios[ir][i].mcs;
668 break;
669 }
670 if (mcs < 0)
671 return -EINVAL;
672
673 confa = snd_soc_read(codec, STA32X_CONFA);
674 confa &= ~(STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK);
675 confa |= (ir << STA32X_CONFA_IR_SHIFT) | (mcs << STA32X_CONFA_MCS_SHIFT);
676
677 confb = snd_soc_read(codec, STA32X_CONFB);
678 confb &= ~(STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB);
679 switch (params_format(params)) {
680 case SNDRV_PCM_FORMAT_S24_LE:
681 case SNDRV_PCM_FORMAT_S24_BE:
682 case SNDRV_PCM_FORMAT_S24_3LE:
683 case SNDRV_PCM_FORMAT_S24_3BE:
684 pr_debug("24bit\n");
685 /* fall through */
686 case SNDRV_PCM_FORMAT_S32_LE:
687 case SNDRV_PCM_FORMAT_S32_BE:
688 pr_debug("24bit or 32bit\n");
689 switch (sta32x->format) {
690 case SND_SOC_DAIFMT_I2S:
691 confb |= 0x0;
692 break;
693 case SND_SOC_DAIFMT_LEFT_J:
694 confb |= 0x1;
695 break;
696 case SND_SOC_DAIFMT_RIGHT_J:
697 confb |= 0x2;
698 break;
699 }
700
701 break;
702 case SNDRV_PCM_FORMAT_S20_3LE:
703 case SNDRV_PCM_FORMAT_S20_3BE:
704 pr_debug("20bit\n");
705 switch (sta32x->format) {
706 case SND_SOC_DAIFMT_I2S:
707 confb |= 0x4;
708 break;
709 case SND_SOC_DAIFMT_LEFT_J:
710 confb |= 0x5;
711 break;
712 case SND_SOC_DAIFMT_RIGHT_J:
713 confb |= 0x6;
714 break;
715 }
716
717 break;
718 case SNDRV_PCM_FORMAT_S18_3LE:
719 case SNDRV_PCM_FORMAT_S18_3BE:
720 pr_debug("18bit\n");
721 switch (sta32x->format) {
722 case SND_SOC_DAIFMT_I2S:
723 confb |= 0x8;
724 break;
725 case SND_SOC_DAIFMT_LEFT_J:
726 confb |= 0x9;
727 break;
728 case SND_SOC_DAIFMT_RIGHT_J:
729 confb |= 0xa;
730 break;
731 }
732
733 break;
734 case SNDRV_PCM_FORMAT_S16_LE:
735 case SNDRV_PCM_FORMAT_S16_BE:
736 pr_debug("16bit\n");
737 switch (sta32x->format) {
738 case SND_SOC_DAIFMT_I2S:
739 confb |= 0x0;
740 break;
741 case SND_SOC_DAIFMT_LEFT_J:
742 confb |= 0xd;
743 break;
744 case SND_SOC_DAIFMT_RIGHT_J:
745 confb |= 0xe;
746 break;
747 }
748
749 break;
750 default:
751 return -EINVAL;
752 }
753
754 snd_soc_write(codec, STA32X_CONFA, confa);
755 snd_soc_write(codec, STA32X_CONFB, confb);
756 return 0;
757 }
758
759 /**
760 * sta32x_set_bias_level - DAPM callback
761 * @codec: the codec device
762 * @level: DAPM power level
763 *
764 * This is called by ALSA to put the codec into low power mode
765 * or to wake it up. If the codec is powered off completely
766 * all registers must be restored after power on.
767 */
768 static int sta32x_set_bias_level(struct snd_soc_codec *codec,
769 enum snd_soc_bias_level level)
770 {
771 int ret;
772 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
773
774 pr_debug("level = %d\n", level);
775 switch (level) {
776 case SND_SOC_BIAS_ON:
777 break;
778
779 case SND_SOC_BIAS_PREPARE:
780 /* Full power on */
781 snd_soc_update_bits(codec, STA32X_CONFF,
782 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
783 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
784 break;
785
786 case SND_SOC_BIAS_STANDBY:
787 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
788 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
789 sta32x->supplies);
790 if (ret != 0) {
791 dev_err(codec->dev,
792 "Failed to enable supplies: %d\n", ret);
793 return ret;
794 }
795
796 sta32x_cache_sync(codec);
797 sta32x_watchdog_start(sta32x);
798 }
799
800 /* Power up to mute */
801 /* FIXME */
802 snd_soc_update_bits(codec, STA32X_CONFF,
803 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
804 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
805
806 break;
807
808 case SND_SOC_BIAS_OFF:
809 /* The chip runs through the power down sequence for us. */
810 snd_soc_update_bits(codec, STA32X_CONFF,
811 STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
812 STA32X_CONFF_PWDN);
813 msleep(300);
814 sta32x_watchdog_stop(sta32x);
815 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
816 sta32x->supplies);
817 break;
818 }
819 codec->dapm.bias_level = level;
820 return 0;
821 }
822
823 static const struct snd_soc_dai_ops sta32x_dai_ops = {
824 .hw_params = sta32x_hw_params,
825 .set_sysclk = sta32x_set_dai_sysclk,
826 .set_fmt = sta32x_set_dai_fmt,
827 };
828
829 static struct snd_soc_dai_driver sta32x_dai = {
830 .name = "STA32X",
831 .playback = {
832 .stream_name = "Playback",
833 .channels_min = 2,
834 .channels_max = 2,
835 .rates = STA32X_RATES,
836 .formats = STA32X_FORMATS,
837 },
838 .ops = &sta32x_dai_ops,
839 };
840
841 #ifdef CONFIG_PM
842 static int sta32x_suspend(struct snd_soc_codec *codec)
843 {
844 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
845 return 0;
846 }
847
848 static int sta32x_resume(struct snd_soc_codec *codec)
849 {
850 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
851 return 0;
852 }
853 #else
854 #define sta32x_suspend NULL
855 #define sta32x_resume NULL
856 #endif
857
858 static int sta32x_probe(struct snd_soc_codec *codec)
859 {
860 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
861 int i, ret = 0, thermal = 0;
862
863 sta32x->codec = codec;
864 sta32x->pdata = dev_get_platdata(codec->dev);
865
866 ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
867 sta32x->supplies);
868 if (ret != 0) {
869 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
870 return ret;
871 }
872
873 /* Tell ASoC what kind of I/O to use to read the registers. ASoC will
874 * then do the I2C transactions itself.
875 */
876 codec->control_data = sta32x->regmap;
877 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP);
878 if (ret < 0) {
879 dev_err(codec->dev, "failed to set cache I/O (ret=%i)\n", ret);
880 goto err;
881 }
882
883 /* Chip documentation explicitly requires that the reset values
884 * of reserved register bits are left untouched.
885 * Write the register default value to cache for reserved registers,
886 * so the write to the these registers are suppressed by the cache
887 * restore code when it skips writes of default registers.
888 */
889 regcache_cache_only(sta32x->regmap, true);
890 snd_soc_write(codec, STA32X_CONFC, 0xc2);
891 snd_soc_write(codec, STA32X_CONFE, 0xc2);
892 snd_soc_write(codec, STA32X_CONFF, 0x5c);
893 snd_soc_write(codec, STA32X_MMUTE, 0x10);
894 snd_soc_write(codec, STA32X_AUTO1, 0x60);
895 snd_soc_write(codec, STA32X_AUTO3, 0x00);
896 snd_soc_write(codec, STA32X_C3CFG, 0x40);
897 regcache_cache_only(sta32x->regmap, false);
898
899 /* set thermal warning adjustment and recovery */
900 if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_ADJUSTMENT_ENABLE))
901 thermal |= STA32X_CONFA_TWAB;
902 if (!(sta32x->pdata->thermal_conf & STA32X_THERMAL_RECOVERY_ENABLE))
903 thermal |= STA32X_CONFA_TWRB;
904 snd_soc_update_bits(codec, STA32X_CONFA,
905 STA32X_CONFA_TWAB | STA32X_CONFA_TWRB,
906 thermal);
907
908 /* select output configuration */
909 snd_soc_update_bits(codec, STA32X_CONFF,
910 STA32X_CONFF_OCFG_MASK,
911 sta32x->pdata->output_conf
912 << STA32X_CONFF_OCFG_SHIFT);
913
914 /* channel to output mapping */
915 snd_soc_update_bits(codec, STA32X_C1CFG,
916 STA32X_CxCFG_OM_MASK,
917 sta32x->pdata->ch1_output_mapping
918 << STA32X_CxCFG_OM_SHIFT);
919 snd_soc_update_bits(codec, STA32X_C2CFG,
920 STA32X_CxCFG_OM_MASK,
921 sta32x->pdata->ch2_output_mapping
922 << STA32X_CxCFG_OM_SHIFT);
923 snd_soc_update_bits(codec, STA32X_C3CFG,
924 STA32X_CxCFG_OM_MASK,
925 sta32x->pdata->ch3_output_mapping
926 << STA32X_CxCFG_OM_SHIFT);
927
928 /* initialize coefficient shadow RAM with reset values */
929 for (i = 4; i <= 49; i += 5)
930 sta32x->coef_shadow[i] = 0x400000;
931 for (i = 50; i <= 54; i++)
932 sta32x->coef_shadow[i] = 0x7fffff;
933 sta32x->coef_shadow[55] = 0x5a9df7;
934 sta32x->coef_shadow[56] = 0x7fffff;
935 sta32x->coef_shadow[59] = 0x7fffff;
936 sta32x->coef_shadow[60] = 0x400000;
937 sta32x->coef_shadow[61] = 0x400000;
938
939 if (sta32x->pdata->needs_esd_watchdog)
940 INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
941
942 sta32x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
943 /* Bias level configuration will have done an extra enable */
944 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
945
946 return 0;
947
948 err:
949 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
950 return ret;
951 }
952
953 static int sta32x_remove(struct snd_soc_codec *codec)
954 {
955 struct sta32x_priv *sta32x = snd_soc_codec_get_drvdata(codec);
956
957 sta32x_watchdog_stop(sta32x);
958 sta32x_set_bias_level(codec, SND_SOC_BIAS_OFF);
959 regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
960
961 return 0;
962 }
963
964 static bool sta32x_reg_is_volatile(struct device *dev, unsigned int reg)
965 {
966 switch (reg) {
967 case STA32X_CONFA ... STA32X_L2ATRT:
968 case STA32X_MPCC1 ... STA32X_FDRC2:
969 return 0;
970 }
971 return 1;
972 }
973
974 static const struct snd_soc_codec_driver sta32x_codec = {
975 .probe = sta32x_probe,
976 .remove = sta32x_remove,
977 .suspend = sta32x_suspend,
978 .resume = sta32x_resume,
979 .set_bias_level = sta32x_set_bias_level,
980 .controls = sta32x_snd_controls,
981 .num_controls = ARRAY_SIZE(sta32x_snd_controls),
982 .dapm_widgets = sta32x_dapm_widgets,
983 .num_dapm_widgets = ARRAY_SIZE(sta32x_dapm_widgets),
984 .dapm_routes = sta32x_dapm_routes,
985 .num_dapm_routes = ARRAY_SIZE(sta32x_dapm_routes),
986 };
987
988 static const struct regmap_config sta32x_regmap = {
989 .reg_bits = 8,
990 .val_bits = 8,
991 .max_register = STA32X_FDRC2,
992 .reg_defaults = sta32x_regs,
993 .num_reg_defaults = ARRAY_SIZE(sta32x_regs),
994 .cache_type = REGCACHE_RBTREE,
995 .volatile_reg = sta32x_reg_is_volatile,
996 };
997
998 static int sta32x_i2c_probe(struct i2c_client *i2c,
999 const struct i2c_device_id *id)
1000 {
1001 struct sta32x_priv *sta32x;
1002 int ret, i;
1003
1004 sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
1005 GFP_KERNEL);
1006 if (!sta32x)
1007 return -ENOMEM;
1008
1009 /* regulators */
1010 for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
1011 sta32x->supplies[i].supply = sta32x_supply_names[i];
1012
1013 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
1014 sta32x->supplies);
1015 if (ret != 0) {
1016 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1017 return ret;
1018 }
1019
1020 sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
1021 if (IS_ERR(sta32x->regmap)) {
1022 ret = PTR_ERR(sta32x->regmap);
1023 dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1024 return ret;
1025 }
1026
1027 i2c_set_clientdata(i2c, sta32x);
1028
1029 ret = snd_soc_register_codec(&i2c->dev, &sta32x_codec, &sta32x_dai, 1);
1030 if (ret != 0)
1031 dev_err(&i2c->dev, "Failed to register codec (%d)\n", ret);
1032
1033 return ret;
1034 }
1035
1036 static int sta32x_i2c_remove(struct i2c_client *client)
1037 {
1038 snd_soc_unregister_codec(&client->dev);
1039 return 0;
1040 }
1041
1042 static const struct i2c_device_id sta32x_i2c_id[] = {
1043 { "sta326", 0 },
1044 { "sta328", 0 },
1045 { "sta329", 0 },
1046 { }
1047 };
1048 MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
1049
1050 static struct i2c_driver sta32x_i2c_driver = {
1051 .driver = {
1052 .name = "sta32x",
1053 .owner = THIS_MODULE,
1054 },
1055 .probe = sta32x_i2c_probe,
1056 .remove = sta32x_i2c_remove,
1057 .id_table = sta32x_i2c_id,
1058 };
1059
1060 module_i2c_driver(sta32x_i2c_driver);
1061
1062 MODULE_DESCRIPTION("ASoC STA32X driver");
1063 MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
1064 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)