2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
11 * Modified 2009-04-13 for proper metering by Florian Faber
14 * Modified 2009-04-14 for native float support by Florian Faber
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
41 #include <linux/init.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/module.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/math64.h>
50 #include <sound/core.h>
51 #include <sound/control.h>
52 #include <sound/pcm.h>
53 #include <sound/pcm_params.h>
54 #include <sound/info.h>
55 #include <sound/asoundef.h>
56 #include <sound/rawmidi.h>
57 #include <sound/hwdep.h>
58 #include <sound/initval.h>
60 #include <sound/hdspm.h>
62 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
63 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
64 static bool enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
;/* Enable this card */
66 module_param_array(index
, int, NULL
, 0444);
67 MODULE_PARM_DESC(index
, "Index value for RME HDSPM interface.");
69 module_param_array(id
, charp
, NULL
, 0444);
70 MODULE_PARM_DESC(id
, "ID string for RME HDSPM interface.");
72 module_param_array(enable
, bool, NULL
, 0444);
73 MODULE_PARM_DESC(enable
, "Enable/disable specific HDSPM soundcards.");
78 "Winfried Ritsch <ritsch_AT_iem.at>, "
79 "Paul Davis <paul@linuxaudiosystems.com>, "
80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
81 "Remy Bruno <remy.bruno@trinnov.com>, "
82 "Florian Faber <faberman@linuxproaudio.org>, "
83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
85 MODULE_DESCRIPTION("RME HDSPM");
86 MODULE_LICENSE("GPL");
87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
89 /* --- Write registers. ---
90 These are defined as byte-offsets from the iobase value. */
92 #define HDSPM_WR_SETTINGS 0
93 #define HDSPM_outputBufferAddress 32
94 #define HDSPM_inputBufferAddress 36
95 #define HDSPM_controlRegister 64
96 #define HDSPM_interruptConfirmation 96
97 #define HDSPM_control2Reg 256 /* not in specs ???????? */
98 #define HDSPM_freqReg 256 /* for AES32 */
99 #define HDSPM_midiDataOut0 352 /* just believe in old code */
100 #define HDSPM_midiDataOut1 356
101 #define HDSPM_eeprom_wr 384 /* for AES32 */
103 /* DMA enable for 64 channels, only Bit 0 is relevant */
104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
107 /* 16 page addresses for each of the 64 channels DMA buffer in and out
108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
109 #define HDSPM_pageAddressBufferOut 8192
110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
116 /* --- Read registers. ---
117 These are defined as byte-offsets from the iobase value */
118 #define HDSPM_statusRegister 0
119 /*#define HDSPM_statusRegister2 96 */
120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
121 * offset 192, for AES32 *and* MADI
122 * => need to check that offset 192 is working on MADI */
123 #define HDSPM_statusRegister2 192
124 #define HDSPM_timecodeRegister 128
127 #define HDSPM_RD_STATUS_0 0
128 #define HDSPM_RD_STATUS_1 64
129 #define HDSPM_RD_STATUS_2 128
130 #define HDSPM_RD_STATUS_3 192
132 #define HDSPM_RD_TCO 256
133 #define HDSPM_RD_PLL_FREQ 512
134 #define HDSPM_WR_TCO 128
136 #define HDSPM_TCO1_TCO_lock 0x00000001
137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
144 #define HDSPM_TCO1_set_TC 0x00000100
145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
149 #define HDSPM_TCO2_TC_run 0x00010000
150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
154 #define HDSPM_TCO2_set_jam_sync 0x00200000
155 #define HDSPM_TCO2_set_flywheel 0x00400000
157 #define HDSPM_TCO2_set_01_4 0x01000000
158 #define HDSPM_TCO2_set_pull_down 0x02000000
159 #define HDSPM_TCO2_set_pull_up 0x04000000
160 #define HDSPM_TCO2_set_freq 0x08000000
161 #define HDSPM_TCO2_set_term_75R 0x10000000
162 #define HDSPM_TCO2_set_input_LSB 0x20000000
163 #define HDSPM_TCO2_set_input_MSB 0x40000000
164 #define HDSPM_TCO2_set_freq_from_app 0x80000000
167 #define HDSPM_midiDataOut0 352
168 #define HDSPM_midiDataOut1 356
169 #define HDSPM_midiDataOut2 368
171 #define HDSPM_midiDataIn0 360
172 #define HDSPM_midiDataIn1 364
173 #define HDSPM_midiDataIn2 372
174 #define HDSPM_midiDataIn3 376
176 /* status is data bytes in MIDI-FIFO (0-128) */
177 #define HDSPM_midiStatusOut0 384
178 #define HDSPM_midiStatusOut1 388
179 #define HDSPM_midiStatusOut2 400
181 #define HDSPM_midiStatusIn0 392
182 #define HDSPM_midiStatusIn1 396
183 #define HDSPM_midiStatusIn2 404
184 #define HDSPM_midiStatusIn3 408
187 /* the meters are regular i/o-mapped registers, but offset
188 considerably from the rest. the peak registers are reset
189 when read; the least-significant 4 bits are full-scale counters;
190 the actual peak value is in the most-significant 24 bits.
193 #define HDSPM_MADI_INPUT_PEAK 4096
194 #define HDSPM_MADI_PLAYBACK_PEAK 4352
195 #define HDSPM_MADI_OUTPUT_PEAK 4608
197 #define HDSPM_MADI_INPUT_RMS_L 6144
198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
199 #define HDSPM_MADI_OUTPUT_RMS_L 6656
201 #define HDSPM_MADI_INPUT_RMS_H 7168
202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
203 #define HDSPM_MADI_OUTPUT_RMS_H 7680
205 /* --- Control Register bits --------- */
206 #define HDSPM_Start (1<<0) /* start engine */
208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
209 #define HDSPM_Latency1 (1<<2) /* where n is defined */
210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
214 register [RayDAT, AIO] */
216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
225 56channelMODE=0 */ /* MADI ONLY*/
226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
229 0=off, 1=on */ /* MADI ONLY */
230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
237 #define HDSPM_SyncRef2 (1<<13)
238 #define HDSPM_SyncRef3 (1<<25)
240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
242 AES additional bits in
243 lower 5 Audiodatabits ??? */
244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
247 #define HDSPM_Midi0InterruptEnable 0x0400000
248 #define HDSPM_Midi1InterruptEnable 0x0800000
249 #define HDSPM_Midi2InterruptEnable 0x0200000
250 #define HDSPM_Midi3InterruptEnable 0x4000000
252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
253 #define HDSPe_FLOAT_FORMAT 0x2000000
255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
259 #define HDSPM_wclk_sel (1<<30)
261 /* --- bit helper defines */
262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
266 #define HDSPM_InputOptical 0
267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
269 HDSPM_SyncRef2|HDSPM_SyncRef3)
271 #define HDSPM_c0_SyncRef0 0x2
272 #define HDSPM_c0_SyncRef1 0x4
273 #define HDSPM_c0_SyncRef2 0x8
274 #define HDSPM_c0_SyncRef3 0x10
275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
280 #define HDSPM_SYNC_FROM_TCO 2
281 #define HDSPM_SYNC_FROM_SYNC_IN 3
283 #define HDSPM_Frequency32KHz HDSPM_Frequency0
284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
296 /* Synccheck Status */
297 #define HDSPM_SYNC_CHECK_NO_LOCK 0
298 #define HDSPM_SYNC_CHECK_LOCK 1
299 #define HDSPM_SYNC_CHECK_SYNC 2
301 /* AutoSync References - used by "autosync_ref" control switch */
302 #define HDSPM_AUTOSYNC_FROM_WORD 0
303 #define HDSPM_AUTOSYNC_FROM_MADI 1
304 #define HDSPM_AUTOSYNC_FROM_TCO 2
305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
306 #define HDSPM_AUTOSYNC_FROM_NONE 4
308 /* Possible sources of MADI input */
309 #define HDSPM_OPTICAL 0 /* optical */
310 #define HDSPM_COAXIAL 1 /* BNC */
312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
315 #define hdspm_encode_in(x) (((x)&0x3)<<14)
316 #define hdspm_decode_in(x) (((x)>>14)&0x3)
318 /* --- control2 register bits --- */
319 #define HDSPM_TMS (1<<0)
320 #define HDSPM_TCK (1<<1)
321 #define HDSPM_TDI (1<<2)
322 #define HDSPM_JTAG (1<<3)
323 #define HDSPM_PWDN (1<<4)
324 #define HDSPM_PROGRAM (1<<5)
325 #define HDSPM_CONFIG_MODE_0 (1<<6)
326 #define HDSPM_CONFIG_MODE_1 (1<<7)
327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
328 #define HDSPM_BIGENDIAN_MODE (1<<9)
329 #define HDSPM_RD_MULTIPLE (1<<10)
331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
332 that do not conflict with specific bits for AES32 seem to be valid also
335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */
345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */
347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */
348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */
350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
351 /* since 64byte accurate, last 6 bits are not used */
355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
365 #define HDSPM_tco_detect 0x08000000
366 #define HDSPM_tco_lock 0x20000000
368 #define HDSPM_s2_tco_detect 0x00000040
369 #define HDSPM_s2_AEBO_D 0x00000080
370 #define HDSPM_s2_AEBI_D 0x00000100
373 #define HDSPM_midi0IRQPending 0x40000000
374 #define HDSPM_midi1IRQPending 0x80000000
375 #define HDSPM_midi2IRQPending 0x20000000
376 #define HDSPM_midi2IRQPendingAES 0x00000020
377 #define HDSPM_midi3IRQPending 0x00200000
379 /* --- status bit helpers */
380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
381 HDSPM_madiFreq2|HDSPM_madiFreq3)
382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
392 /* Status2 Register bits */ /* MADI ONLY */
394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
396 #define HDSPM_version2 (1<<2)
398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */
404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */
406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
407 #define HDSPM_SyncRef1 0x20000
409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
423 #define HDSPM_status1_F_0 0x0400000
424 #define HDSPM_status1_F_1 0x0800000
425 #define HDSPM_status1_F_2 0x1000000
426 #define HDSPM_status1_F_3 0x2000000
427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
432 #define HDSPM_SelSyncRef_WORD 0
433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
440 For AES32, bits for status, status2 and timecode are different
443 #define HDSPM_AES32_wcLock 0x0200000
444 #define HDSPM_AES32_wcSync 0x0100000
445 #define HDSPM_AES32_wcFreq_bit 22
446 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
448 #define HDSPM_AES32_syncref_bit 16
449 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
451 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
452 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
453 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
454 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
455 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
456 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
457 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
458 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
459 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
460 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9
463 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
464 #define HDSPM_LockAES 0x80
465 #define HDSPM_LockAES1 0x80
466 #define HDSPM_LockAES2 0x40
467 #define HDSPM_LockAES3 0x20
468 #define HDSPM_LockAES4 0x10
469 #define HDSPM_LockAES5 0x8
470 #define HDSPM_LockAES6 0x4
471 #define HDSPM_LockAES7 0x2
472 #define HDSPM_LockAES8 0x1
475 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
487 NB: Timecode register doesn't seem to work on AES32 card revision 230
491 #define UNITY_GAIN 32768 /* = 65536/2 */
492 #define MINUS_INFINITY_GAIN 0
494 /* Number of channels for different Speed Modes */
495 #define MADI_SS_CHANNELS 64
496 #define MADI_DS_CHANNELS 32
497 #define MADI_QS_CHANNELS 16
499 #define RAYDAT_SS_CHANNELS 36
500 #define RAYDAT_DS_CHANNELS 20
501 #define RAYDAT_QS_CHANNELS 12
503 #define AIO_IN_SS_CHANNELS 14
504 #define AIO_IN_DS_CHANNELS 10
505 #define AIO_IN_QS_CHANNELS 8
506 #define AIO_OUT_SS_CHANNELS 16
507 #define AIO_OUT_DS_CHANNELS 12
508 #define AIO_OUT_QS_CHANNELS 10
510 #define AES32_CHANNELS 16
512 /* the size of a substream (1 mono data stream) */
513 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
514 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
516 /* the size of the area we need to allocate for DMA transfers. the
517 size is the same regardless of the number of channels, and
518 also the latency to use.
519 for one direction !!!
521 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
522 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
524 #define HDSPM_RAYDAT_REV 211
525 #define HDSPM_AIO_REV 212
526 #define HDSPM_MADIFACE_REV 213
528 /* speed factor modes */
529 #define HDSPM_SPEED_SINGLE 0
530 #define HDSPM_SPEED_DOUBLE 1
531 #define HDSPM_SPEED_QUAD 2
533 /* names for speed modes */
534 static char *hdspm_speed_names
[] = { "single", "double", "quad" };
536 static char *texts_autosync_aes_tco
[] = { "Word Clock",
537 "AES1", "AES2", "AES3", "AES4",
538 "AES5", "AES6", "AES7", "AES8",
540 static char *texts_autosync_aes
[] = { "Word Clock",
541 "AES1", "AES2", "AES3", "AES4",
542 "AES5", "AES6", "AES7", "AES8" };
543 static char *texts_autosync_madi_tco
[] = { "Word Clock",
544 "MADI", "TCO", "Sync In" };
545 static char *texts_autosync_madi
[] = { "Word Clock",
548 static char *texts_autosync_raydat_tco
[] = {
550 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
551 "AES", "SPDIF", "TCO", "Sync In"
553 static char *texts_autosync_raydat
[] = {
555 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
556 "AES", "SPDIF", "Sync In"
558 static char *texts_autosync_aio_tco
[] = {
560 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
562 static char *texts_autosync_aio
[] = { "Word Clock",
563 "ADAT", "AES", "SPDIF", "Sync In" };
565 static char *texts_freq
[] = {
578 static char *texts_ports_madi
[] = {
579 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
580 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
581 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
582 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
583 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
584 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
585 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
586 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
587 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
588 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
589 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
593 static char *texts_ports_raydat_ss
[] = {
594 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
595 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
596 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
597 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
598 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
599 "ADAT4.7", "ADAT4.8",
604 static char *texts_ports_raydat_ds
[] = {
605 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
606 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
607 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
608 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
613 static char *texts_ports_raydat_qs
[] = {
614 "ADAT1.1", "ADAT1.2",
615 "ADAT2.1", "ADAT2.2",
616 "ADAT3.1", "ADAT3.2",
617 "ADAT4.1", "ADAT4.2",
623 static char *texts_ports_aio_in_ss
[] = {
624 "Analogue.L", "Analogue.R",
626 "SPDIF.L", "SPDIF.R",
627 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
631 static char *texts_ports_aio_out_ss
[] = {
632 "Analogue.L", "Analogue.R",
634 "SPDIF.L", "SPDIF.R",
635 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
640 static char *texts_ports_aio_in_ds
[] = {
641 "Analogue.L", "Analogue.R",
643 "SPDIF.L", "SPDIF.R",
644 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
647 static char *texts_ports_aio_out_ds
[] = {
648 "Analogue.L", "Analogue.R",
650 "SPDIF.L", "SPDIF.R",
651 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
655 static char *texts_ports_aio_in_qs
[] = {
656 "Analogue.L", "Analogue.R",
658 "SPDIF.L", "SPDIF.R",
659 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4"
662 static char *texts_ports_aio_out_qs
[] = {
663 "Analogue.L", "Analogue.R",
665 "SPDIF.L", "SPDIF.R",
666 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
670 static char *texts_ports_aes32
[] = {
671 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
672 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
676 /* These tables map the ALSA channels 1..N to the channels that we
677 need to use in order to find the relevant channel buffer. RME
678 refers to this kind of mapping as between "the ADAT channel and
679 the DMA channel." We index it using the logical audio channel,
680 and the value is the DMA channel (i.e. channel buffer number)
681 where the data for that channel can be read/written from/to.
684 static char channel_map_unity_ss
[HDSPM_MAX_CHANNELS
] = {
685 0, 1, 2, 3, 4, 5, 6, 7,
686 8, 9, 10, 11, 12, 13, 14, 15,
687 16, 17, 18, 19, 20, 21, 22, 23,
688 24, 25, 26, 27, 28, 29, 30, 31,
689 32, 33, 34, 35, 36, 37, 38, 39,
690 40, 41, 42, 43, 44, 45, 46, 47,
691 48, 49, 50, 51, 52, 53, 54, 55,
692 56, 57, 58, 59, 60, 61, 62, 63
695 static char channel_map_raydat_ss
[HDSPM_MAX_CHANNELS
] = {
696 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
697 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
698 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
699 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
703 -1, -1, -1, -1, -1, -1, -1, -1,
704 -1, -1, -1, -1, -1, -1, -1, -1,
705 -1, -1, -1, -1, -1, -1, -1, -1,
708 static char channel_map_raydat_ds
[HDSPM_MAX_CHANNELS
] = {
709 4, 5, 6, 7, /* ADAT 1 */
710 8, 9, 10, 11, /* ADAT 2 */
711 12, 13, 14, 15, /* ADAT 3 */
712 16, 17, 18, 19, /* ADAT 4 */
716 -1, -1, -1, -1, -1, -1, -1, -1,
717 -1, -1, -1, -1, -1, -1, -1, -1,
718 -1, -1, -1, -1, -1, -1, -1, -1,
719 -1, -1, -1, -1, -1, -1, -1, -1,
720 -1, -1, -1, -1, -1, -1, -1, -1,
723 static char channel_map_raydat_qs
[HDSPM_MAX_CHANNELS
] = {
731 -1, -1, -1, -1, -1, -1, -1, -1,
732 -1, -1, -1, -1, -1, -1, -1, -1,
733 -1, -1, -1, -1, -1, -1, -1, -1,
734 -1, -1, -1, -1, -1, -1, -1, -1,
735 -1, -1, -1, -1, -1, -1, -1, -1,
736 -1, -1, -1, -1, -1, -1, -1, -1,
739 static char channel_map_aio_in_ss
[HDSPM_MAX_CHANNELS
] = {
742 10, 11, /* spdif in */
743 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
745 -1, -1, -1, -1, -1, -1, -1, -1,
746 -1, -1, -1, -1, -1, -1, -1, -1,
747 -1, -1, -1, -1, -1, -1, -1, -1,
748 -1, -1, -1, -1, -1, -1, -1, -1,
749 -1, -1, -1, -1, -1, -1, -1, -1,
750 -1, -1, -1, -1, -1, -1, -1, -1,
753 static char channel_map_aio_out_ss
[HDSPM_MAX_CHANNELS
] = {
756 10, 11, /* spdif out */
757 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
758 6, 7, /* phone out */
759 -1, -1, -1, -1, -1, -1, -1, -1,
760 -1, -1, -1, -1, -1, -1, -1, -1,
761 -1, -1, -1, -1, -1, -1, -1, -1,
762 -1, -1, -1, -1, -1, -1, -1, -1,
763 -1, -1, -1, -1, -1, -1, -1, -1,
764 -1, -1, -1, -1, -1, -1, -1, -1,
767 static char channel_map_aio_in_ds
[HDSPM_MAX_CHANNELS
] = {
770 10, 11, /* spdif in */
771 12, 14, 16, 18, /* adat in */
772 -1, -1, -1, -1, -1, -1,
773 -1, -1, -1, -1, -1, -1, -1, -1,
774 -1, -1, -1, -1, -1, -1, -1, -1,
775 -1, -1, -1, -1, -1, -1, -1, -1,
776 -1, -1, -1, -1, -1, -1, -1, -1,
777 -1, -1, -1, -1, -1, -1, -1, -1,
778 -1, -1, -1, -1, -1, -1, -1, -1
781 static char channel_map_aio_out_ds
[HDSPM_MAX_CHANNELS
] = {
784 10, 11, /* spdif out */
785 12, 14, 16, 18, /* adat out */
786 6, 7, /* phone out */
788 -1, -1, -1, -1, -1, -1, -1, -1,
789 -1, -1, -1, -1, -1, -1, -1, -1,
790 -1, -1, -1, -1, -1, -1, -1, -1,
791 -1, -1, -1, -1, -1, -1, -1, -1,
792 -1, -1, -1, -1, -1, -1, -1, -1,
793 -1, -1, -1, -1, -1, -1, -1, -1
796 static char channel_map_aio_in_qs
[HDSPM_MAX_CHANNELS
] = {
799 10, 11, /* spdif in */
800 12, 16, /* adat in */
801 -1, -1, -1, -1, -1, -1, -1, -1,
802 -1, -1, -1, -1, -1, -1, -1, -1,
803 -1, -1, -1, -1, -1, -1, -1, -1,
804 -1, -1, -1, -1, -1, -1, -1, -1,
805 -1, -1, -1, -1, -1, -1, -1, -1,
806 -1, -1, -1, -1, -1, -1, -1, -1,
807 -1, -1, -1, -1, -1, -1, -1, -1
810 static char channel_map_aio_out_qs
[HDSPM_MAX_CHANNELS
] = {
813 10, 11, /* spdif out */
814 12, 16, /* adat out */
815 6, 7, /* phone out */
816 -1, -1, -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1,
820 -1, -1, -1, -1, -1, -1, -1, -1,
821 -1, -1, -1, -1, -1, -1, -1, -1,
822 -1, -1, -1, -1, -1, -1, -1, -1
825 static char channel_map_aes32
[HDSPM_MAX_CHANNELS
] = {
826 0, 1, 2, 3, 4, 5, 6, 7,
827 8, 9, 10, 11, 12, 13, 14, 15,
828 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1,
833 -1, -1, -1, -1, -1, -1, -1, -1
839 struct snd_rawmidi
*rmidi
;
840 struct snd_rawmidi_substream
*input
;
841 struct snd_rawmidi_substream
*output
;
842 char istimer
; /* timer in use */
843 struct timer_list timer
;
860 int term
; /* 0 = off, 1 = on */
865 /* only one playback and/or capture stream */
866 struct snd_pcm_substream
*capture_substream
;
867 struct snd_pcm_substream
*playback_substream
;
869 char *card_name
; /* for procinfo */
870 unsigned short firmware_rev
; /* dont know if relevant (yes if AES32)*/
874 int monitor_outs
; /* set up monitoring outs init flag */
876 u32 control_register
; /* cached value */
877 u32 control2_register
; /* cached value */
878 u32 settings_register
;
880 struct hdspm_midi midi
[4];
881 struct tasklet_struct midi_tasklet
;
884 unsigned char ss_in_channels
;
885 unsigned char ds_in_channels
;
886 unsigned char qs_in_channels
;
887 unsigned char ss_out_channels
;
888 unsigned char ds_out_channels
;
889 unsigned char qs_out_channels
;
891 unsigned char max_channels_in
;
892 unsigned char max_channels_out
;
894 signed char *channel_map_in
;
895 signed char *channel_map_out
;
897 signed char *channel_map_in_ss
, *channel_map_in_ds
, *channel_map_in_qs
;
898 signed char *channel_map_out_ss
, *channel_map_out_ds
, *channel_map_out_qs
;
900 char **port_names_in
;
901 char **port_names_out
;
903 char **port_names_in_ss
, **port_names_in_ds
, **port_names_in_qs
;
904 char **port_names_out_ss
, **port_names_out_ds
, **port_names_out_qs
;
906 unsigned char *playback_buffer
; /* suitably aligned address */
907 unsigned char *capture_buffer
; /* suitably aligned address */
909 pid_t capture_pid
; /* process id which uses capture */
910 pid_t playback_pid
; /* process id which uses capture */
911 int running
; /* running status */
913 int last_external_sample_rate
; /* samplerate mystic ... */
914 int last_internal_sample_rate
;
915 int system_sample_rate
;
917 int dev
; /* Hardware vars... */
920 void __iomem
*iobase
;
922 int irq_count
; /* for debug */
925 struct snd_card
*card
; /* one card */
926 struct snd_pcm
*pcm
; /* has one pcm */
927 struct snd_hwdep
*hwdep
; /* and a hwdep for additional ioctl */
928 struct pci_dev
*pci
; /* and an pci info */
931 /* fast alsa mixer */
932 struct snd_kcontrol
*playback_mixer_ctls
[HDSPM_MAX_CHANNELS
];
933 /* but input to much, so not used */
934 struct snd_kcontrol
*input_mixer_ctls
[HDSPM_MAX_CHANNELS
];
935 /* full mixer accessible over mixer ioctl or hwdep-device */
936 struct hdspm_mixer
*mixer
;
938 struct hdspm_tco
*tco
; /* NULL if no TCO detected */
940 char **texts_autosync
;
941 int texts_autosync_items
;
943 cycles_t last_interrupt
;
947 struct hdspm_peak_rms peak_rms
;
951 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids
) = {
953 .vendor
= PCI_VENDOR_ID_XILINX
,
954 .device
= PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI
,
955 .subvendor
= PCI_ANY_ID
,
956 .subdevice
= PCI_ANY_ID
,
963 MODULE_DEVICE_TABLE(pci
, snd_hdspm_ids
);
966 static int snd_hdspm_create_alsa_devices(struct snd_card
*card
,
967 struct hdspm
*hdspm
);
968 static int snd_hdspm_create_pcm(struct snd_card
*card
,
969 struct hdspm
*hdspm
);
971 static inline void snd_hdspm_initialize_midi_flush(struct hdspm
*hdspm
);
972 static inline int hdspm_get_pll_freq(struct hdspm
*hdspm
);
973 static int hdspm_update_simple_mixer_controls(struct hdspm
*hdspm
);
974 static int hdspm_autosync_ref(struct hdspm
*hdspm
);
975 static int snd_hdspm_set_defaults(struct hdspm
*hdspm
);
976 static int hdspm_system_clock_mode(struct hdspm
*hdspm
);
977 static void hdspm_set_sgbuf(struct hdspm
*hdspm
,
978 struct snd_pcm_substream
*substream
,
979 unsigned int reg
, int channels
);
981 static inline int HDSPM_bit2freq(int n
)
983 static const int bit2freq_tab
[] = {
984 0, 32000, 44100, 48000, 64000, 88200,
985 96000, 128000, 176400, 192000 };
988 return bit2freq_tab
[n
];
991 /* Write/read to/from HDSPM with Adresses in Bytes
992 not words but only 32Bit writes are allowed */
994 static inline void hdspm_write(struct hdspm
* hdspm
, unsigned int reg
,
997 writel(val
, hdspm
->iobase
+ reg
);
1000 static inline unsigned int hdspm_read(struct hdspm
* hdspm
, unsigned int reg
)
1002 return readl(hdspm
->iobase
+ reg
);
1005 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1006 mixer is write only on hardware so we have to cache him for read
1007 each fader is a u32, but uses only the first 16 bit */
1009 static inline int hdspm_read_in_gain(struct hdspm
* hdspm
, unsigned int chan
,
1012 if (chan
>= HDSPM_MIXER_CHANNELS
|| in
>= HDSPM_MIXER_CHANNELS
)
1015 return hdspm
->mixer
->ch
[chan
].in
[in
];
1018 static inline int hdspm_read_pb_gain(struct hdspm
* hdspm
, unsigned int chan
,
1021 if (chan
>= HDSPM_MIXER_CHANNELS
|| pb
>= HDSPM_MIXER_CHANNELS
)
1023 return hdspm
->mixer
->ch
[chan
].pb
[pb
];
1026 static int hdspm_write_in_gain(struct hdspm
*hdspm
, unsigned int chan
,
1027 unsigned int in
, unsigned short data
)
1029 if (chan
>= HDSPM_MIXER_CHANNELS
|| in
>= HDSPM_MIXER_CHANNELS
)
1033 HDSPM_MADI_mixerBase
+
1034 ((in
+ 128 * chan
) * sizeof(u32
)),
1035 (hdspm
->mixer
->ch
[chan
].in
[in
] = data
& 0xFFFF));
1039 static int hdspm_write_pb_gain(struct hdspm
*hdspm
, unsigned int chan
,
1040 unsigned int pb
, unsigned short data
)
1042 if (chan
>= HDSPM_MIXER_CHANNELS
|| pb
>= HDSPM_MIXER_CHANNELS
)
1046 HDSPM_MADI_mixerBase
+
1047 ((64 + pb
+ 128 * chan
) * sizeof(u32
)),
1048 (hdspm
->mixer
->ch
[chan
].pb
[pb
] = data
& 0xFFFF));
1053 /* enable DMA for specific channels, now available for DSP-MADI */
1054 static inline void snd_hdspm_enable_in(struct hdspm
* hdspm
, int i
, int v
)
1056 hdspm_write(hdspm
, HDSPM_inputEnableBase
+ (4 * i
), v
);
1059 static inline void snd_hdspm_enable_out(struct hdspm
* hdspm
, int i
, int v
)
1061 hdspm_write(hdspm
, HDSPM_outputEnableBase
+ (4 * i
), v
);
1064 /* check if same process is writing and reading */
1065 static int snd_hdspm_use_is_exclusive(struct hdspm
*hdspm
)
1067 unsigned long flags
;
1070 spin_lock_irqsave(&hdspm
->lock
, flags
);
1071 if ((hdspm
->playback_pid
!= hdspm
->capture_pid
) &&
1072 (hdspm
->playback_pid
>= 0) && (hdspm
->capture_pid
>= 0)) {
1075 spin_unlock_irqrestore(&hdspm
->lock
, flags
);
1079 /* round arbitary sample rates to commonly known rates */
1080 static int hdspm_round_frequency(int rate
)
1090 static int hdspm_tco_sync_check(struct hdspm
*hdspm
);
1091 static int hdspm_sync_in_sync_check(struct hdspm
*hdspm
);
1093 /* check for external sample rate */
1094 static int hdspm_external_sample_rate(struct hdspm
*hdspm
)
1096 unsigned int status
, status2
, timecode
;
1097 int syncref
, rate
= 0, rate_bits
;
1099 switch (hdspm
->io_type
) {
1101 status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
1102 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
1103 timecode
= hdspm_read(hdspm
, HDSPM_timecodeRegister
);
1105 syncref
= hdspm_autosync_ref(hdspm
);
1107 if (syncref
== HDSPM_AES32_AUTOSYNC_FROM_WORD
&&
1108 status
& HDSPM_AES32_wcLock
)
1109 return HDSPM_bit2freq((status
>> HDSPM_AES32_wcFreq_bit
) & 0xF);
1111 if (syncref
>= HDSPM_AES32_AUTOSYNC_FROM_AES1
&&
1112 syncref
<= HDSPM_AES32_AUTOSYNC_FROM_AES8
&&
1113 status2
& (HDSPM_LockAES
>>
1114 (syncref
- HDSPM_AES32_AUTOSYNC_FROM_AES1
)))
1115 return HDSPM_bit2freq((timecode
>> (4*(syncref
-HDSPM_AES32_AUTOSYNC_FROM_AES1
))) & 0xF);
1120 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
1122 if (!(status
& HDSPM_madiLock
)) {
1123 rate
= 0; /* no lock */
1125 switch (status
& (HDSPM_status1_freqMask
)) {
1126 case HDSPM_status1_F_0
*1:
1127 rate
= 32000; break;
1128 case HDSPM_status1_F_0
*2:
1129 rate
= 44100; break;
1130 case HDSPM_status1_F_0
*3:
1131 rate
= 48000; break;
1132 case HDSPM_status1_F_0
*4:
1133 rate
= 64000; break;
1134 case HDSPM_status1_F_0
*5:
1135 rate
= 88200; break;
1136 case HDSPM_status1_F_0
*6:
1137 rate
= 96000; break;
1138 case HDSPM_status1_F_0
*7:
1139 rate
= 128000; break;
1140 case HDSPM_status1_F_0
*8:
1141 rate
= 176400; break;
1142 case HDSPM_status1_F_0
*9:
1143 rate
= 192000; break;
1154 status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
1155 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
1158 /* if wordclock has synced freq and wordclock is valid */
1159 if ((status2
& HDSPM_wcLock
) != 0 &&
1160 (status2
& HDSPM_SelSyncRef0
) == 0) {
1162 rate_bits
= status2
& HDSPM_wcFreqMask
;
1165 switch (rate_bits
) {
1166 case HDSPM_wcFreq32
:
1169 case HDSPM_wcFreq44_1
:
1172 case HDSPM_wcFreq48
:
1175 case HDSPM_wcFreq64
:
1178 case HDSPM_wcFreq88_2
:
1181 case HDSPM_wcFreq96
:
1190 /* if rate detected and Syncref is Word than have it,
1191 * word has priority to MADI
1194 (status2
& HDSPM_SelSyncRefMask
) == HDSPM_SelSyncRef_WORD
)
1197 /* maybe a madi input (which is taken if sel sync is madi) */
1198 if (status
& HDSPM_madiLock
) {
1199 rate_bits
= status
& HDSPM_madiFreqMask
;
1201 switch (rate_bits
) {
1202 case HDSPM_madiFreq32
:
1205 case HDSPM_madiFreq44_1
:
1208 case HDSPM_madiFreq48
:
1211 case HDSPM_madiFreq64
:
1214 case HDSPM_madiFreq88_2
:
1217 case HDSPM_madiFreq96
:
1220 case HDSPM_madiFreq128
:
1223 case HDSPM_madiFreq176_4
:
1226 case HDSPM_madiFreq192
:
1234 } /* endif HDSPM_madiLock */
1236 /* check sample rate from TCO or SYNC_IN */
1238 bool is_valid_input
= 0;
1241 syncref
= hdspm_autosync_ref(hdspm
);
1242 if (HDSPM_AUTOSYNC_FROM_TCO
== syncref
) {
1244 has_sync
= (HDSPM_SYNC_CHECK_SYNC
==
1245 hdspm_tco_sync_check(hdspm
));
1246 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN
== syncref
) {
1248 has_sync
= (HDSPM_SYNC_CHECK_SYNC
==
1249 hdspm_sync_in_sync_check(hdspm
));
1252 if (is_valid_input
&& has_sync
) {
1253 rate
= hdspm_round_frequency(
1254 hdspm_get_pll_freq(hdspm
));
1258 /* QS and DS rates normally can not be detected
1259 * automatically by the card. Only exception is MADI
1260 * in 96k frame mode.
1262 * So if we read SS values (32 .. 48k), check for
1263 * user-provided DS/QS bits in the control register
1264 * and multiply the base frequency accordingly.
1266 if (rate
<= 48000) {
1267 if (hdspm
->control_register
& HDSPM_QuadSpeed
)
1269 else if (hdspm
->control_register
&
1279 /* return latency in samples per period */
1280 static int hdspm_get_latency(struct hdspm
*hdspm
)
1284 n
= hdspm_decode_latency(hdspm
->control_register
);
1286 /* Special case for new RME cards with 32 samples period size.
1287 * The three latency bits in the control register
1288 * (HDSP_LatencyMask) encode latency values of 64 samples as
1289 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1290 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1291 * it corresponds to 32 samples.
1293 if ((7 == n
) && (RayDAT
== hdspm
->io_type
|| AIO
== hdspm
->io_type
))
1296 return 1 << (n
+ 6);
1299 /* Latency function */
1300 static inline void hdspm_compute_period_size(struct hdspm
*hdspm
)
1302 hdspm
->period_bytes
= 4 * hdspm_get_latency(hdspm
);
1306 static snd_pcm_uframes_t
hdspm_hw_pointer(struct hdspm
*hdspm
)
1310 position
= hdspm_read(hdspm
, HDSPM_statusRegister
);
1312 switch (hdspm
->io_type
) {
1315 position
&= HDSPM_BufferPositionMask
;
1316 position
/= 4; /* Bytes per sample */
1319 position
= (position
& HDSPM_BufferID
) ?
1320 (hdspm
->period_bytes
/ 4) : 0;
1327 static inline void hdspm_start_audio(struct hdspm
* s
)
1329 s
->control_register
|= (HDSPM_AudioInterruptEnable
| HDSPM_Start
);
1330 hdspm_write(s
, HDSPM_controlRegister
, s
->control_register
);
1333 static inline void hdspm_stop_audio(struct hdspm
* s
)
1335 s
->control_register
&= ~(HDSPM_Start
| HDSPM_AudioInterruptEnable
);
1336 hdspm_write(s
, HDSPM_controlRegister
, s
->control_register
);
1339 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1340 static void hdspm_silence_playback(struct hdspm
*hdspm
)
1343 int n
= hdspm
->period_bytes
;
1344 void *buf
= hdspm
->playback_buffer
;
1349 for (i
= 0; i
< HDSPM_MAX_CHANNELS
; i
++) {
1351 buf
+= HDSPM_CHANNEL_BUFFER_BYTES
;
1355 static int hdspm_set_interrupt_interval(struct hdspm
*s
, unsigned int frames
)
1359 spin_lock_irq(&s
->lock
);
1362 /* Special case for new RME cards like RayDAT/AIO which
1363 * support period sizes of 32 samples. Since latency is
1364 * encoded in the three bits of HDSP_LatencyMask, we can only
1365 * have values from 0 .. 7. While 0 still means 64 samples and
1366 * 6 represents 4096 samples on all cards, 7 represents 8192
1367 * on older cards and 32 samples on new cards.
1369 * In other words, period size in samples is calculated by
1370 * 2^(n+6) with n ranging from 0 .. 7.
1382 s
->control_register
&= ~HDSPM_LatencyMask
;
1383 s
->control_register
|= hdspm_encode_latency(n
);
1385 hdspm_write(s
, HDSPM_controlRegister
, s
->control_register
);
1387 hdspm_compute_period_size(s
);
1389 spin_unlock_irq(&s
->lock
);
1394 static u64
hdspm_calc_dds_value(struct hdspm
*hdspm
, u64 period
)
1401 switch (hdspm
->io_type
) {
1404 freq_const
= 110069313433624ULL;
1408 freq_const
= 104857600000000ULL;
1411 freq_const
= 131072000000000ULL;
1418 return div_u64(freq_const
, period
);
1422 static void hdspm_set_dds_value(struct hdspm
*hdspm
, int rate
)
1428 else if (rate
>= 56000)
1431 switch (hdspm
->io_type
) {
1433 n
= 131072000000000ULL; /* 125 MHz */
1437 n
= 110069313433624ULL; /* 105 MHz */
1441 n
= 104857600000000ULL; /* 100 MHz */
1448 n
= div_u64(n
, rate
);
1449 /* n should be less than 2^32 for being written to FREQ register */
1450 snd_BUG_ON(n
>> 32);
1451 hdspm_write(hdspm
, HDSPM_freqReg
, (u32
)n
);
1454 /* dummy set rate lets see what happens */
1455 static int hdspm_set_rate(struct hdspm
* hdspm
, int rate
, int called_internally
)
1460 int current_speed
, target_speed
;
1462 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1463 it (e.g. during module initialization).
1466 if (!(hdspm
->control_register
& HDSPM_ClockModeMaster
)) {
1469 if (called_internally
) {
1471 /* request from ctl or card initialization
1472 just make a warning an remember setting
1473 for future master mode switching */
1475 snd_printk(KERN_WARNING
"HDSPM: "
1476 "Warning: device is not running "
1477 "as a clock master.\n");
1481 /* hw_param request while in AutoSync mode */
1483 hdspm_external_sample_rate(hdspm
);
1485 if (hdspm_autosync_ref(hdspm
) ==
1486 HDSPM_AUTOSYNC_FROM_NONE
) {
1488 snd_printk(KERN_WARNING
"HDSPM: "
1489 "Detected no Externel Sync \n");
1492 } else if (rate
!= external_freq
) {
1494 snd_printk(KERN_WARNING
"HDSPM: "
1495 "Warning: No AutoSync source for "
1496 "requested rate\n");
1502 current_rate
= hdspm
->system_sample_rate
;
1504 /* Changing between Singe, Double and Quad speed is not
1505 allowed if any substreams are open. This is because such a change
1506 causes a shift in the location of the DMA buffers and a reduction
1507 in the number of available buffers.
1509 Note that a similar but essentially insoluble problem exists for
1510 externally-driven rate changes. All we can do is to flag rate
1511 changes in the read/write routines.
1514 if (current_rate
<= 48000)
1515 current_speed
= HDSPM_SPEED_SINGLE
;
1516 else if (current_rate
<= 96000)
1517 current_speed
= HDSPM_SPEED_DOUBLE
;
1519 current_speed
= HDSPM_SPEED_QUAD
;
1522 target_speed
= HDSPM_SPEED_SINGLE
;
1523 else if (rate
<= 96000)
1524 target_speed
= HDSPM_SPEED_DOUBLE
;
1526 target_speed
= HDSPM_SPEED_QUAD
;
1530 rate_bits
= HDSPM_Frequency32KHz
;
1533 rate_bits
= HDSPM_Frequency44_1KHz
;
1536 rate_bits
= HDSPM_Frequency48KHz
;
1539 rate_bits
= HDSPM_Frequency64KHz
;
1542 rate_bits
= HDSPM_Frequency88_2KHz
;
1545 rate_bits
= HDSPM_Frequency96KHz
;
1548 rate_bits
= HDSPM_Frequency128KHz
;
1551 rate_bits
= HDSPM_Frequency176_4KHz
;
1554 rate_bits
= HDSPM_Frequency192KHz
;
1560 if (current_speed
!= target_speed
1561 && (hdspm
->capture_pid
>= 0 || hdspm
->playback_pid
>= 0)) {
1564 "cannot change from %s speed to %s speed mode "
1565 "(capture PID = %d, playback PID = %d)\n",
1566 hdspm_speed_names
[current_speed
],
1567 hdspm_speed_names
[target_speed
],
1568 hdspm
->capture_pid
, hdspm
->playback_pid
);
1572 hdspm
->control_register
&= ~HDSPM_FrequencyMask
;
1573 hdspm
->control_register
|= rate_bits
;
1574 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
1576 /* For AES32, need to set DDS value in FREQ register
1577 For MADI, also apparently */
1578 hdspm_set_dds_value(hdspm
, rate
);
1580 if (AES32
== hdspm
->io_type
&& rate
!= current_rate
)
1581 hdspm_write(hdspm
, HDSPM_eeprom_wr
, 0);
1583 hdspm
->system_sample_rate
= rate
;
1585 if (rate
<= 48000) {
1586 hdspm
->channel_map_in
= hdspm
->channel_map_in_ss
;
1587 hdspm
->channel_map_out
= hdspm
->channel_map_out_ss
;
1588 hdspm
->max_channels_in
= hdspm
->ss_in_channels
;
1589 hdspm
->max_channels_out
= hdspm
->ss_out_channels
;
1590 hdspm
->port_names_in
= hdspm
->port_names_in_ss
;
1591 hdspm
->port_names_out
= hdspm
->port_names_out_ss
;
1592 } else if (rate
<= 96000) {
1593 hdspm
->channel_map_in
= hdspm
->channel_map_in_ds
;
1594 hdspm
->channel_map_out
= hdspm
->channel_map_out_ds
;
1595 hdspm
->max_channels_in
= hdspm
->ds_in_channels
;
1596 hdspm
->max_channels_out
= hdspm
->ds_out_channels
;
1597 hdspm
->port_names_in
= hdspm
->port_names_in_ds
;
1598 hdspm
->port_names_out
= hdspm
->port_names_out_ds
;
1600 hdspm
->channel_map_in
= hdspm
->channel_map_in_qs
;
1601 hdspm
->channel_map_out
= hdspm
->channel_map_out_qs
;
1602 hdspm
->max_channels_in
= hdspm
->qs_in_channels
;
1603 hdspm
->max_channels_out
= hdspm
->qs_out_channels
;
1604 hdspm
->port_names_in
= hdspm
->port_names_in_qs
;
1605 hdspm
->port_names_out
= hdspm
->port_names_out_qs
;
1614 /* mainly for init to 0 on load */
1615 static void all_in_all_mixer(struct hdspm
* hdspm
, int sgain
)
1620 if (sgain
> UNITY_GAIN
)
1627 for (i
= 0; i
< HDSPM_MIXER_CHANNELS
; i
++)
1628 for (j
= 0; j
< HDSPM_MIXER_CHANNELS
; j
++) {
1629 hdspm_write_in_gain(hdspm
, i
, j
, gain
);
1630 hdspm_write_pb_gain(hdspm
, i
, j
, gain
);
1634 /*----------------------------------------------------------------------------
1636 ----------------------------------------------------------------------------*/
1638 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm
*hdspm
,
1641 /* the hardware already does the relevant bit-mask with 0xff */
1642 return hdspm_read(hdspm
, hdspm
->midi
[id
].dataIn
);
1645 static inline void snd_hdspm_midi_write_byte (struct hdspm
*hdspm
, int id
,
1648 /* the hardware already does the relevant bit-mask with 0xff */
1649 return hdspm_write(hdspm
, hdspm
->midi
[id
].dataOut
, val
);
1652 static inline int snd_hdspm_midi_input_available (struct hdspm
*hdspm
, int id
)
1654 return hdspm_read(hdspm
, hdspm
->midi
[id
].statusIn
) & 0xFF;
1657 static inline int snd_hdspm_midi_output_possible (struct hdspm
*hdspm
, int id
)
1659 int fifo_bytes_used
;
1661 fifo_bytes_used
= hdspm_read(hdspm
, hdspm
->midi
[id
].statusOut
) & 0xFF;
1663 if (fifo_bytes_used
< 128)
1664 return 128 - fifo_bytes_used
;
1669 static void snd_hdspm_flush_midi_input(struct hdspm
*hdspm
, int id
)
1671 while (snd_hdspm_midi_input_available (hdspm
, id
))
1672 snd_hdspm_midi_read_byte (hdspm
, id
);
1675 static int snd_hdspm_midi_output_write (struct hdspm_midi
*hmidi
)
1677 unsigned long flags
;
1681 unsigned char buf
[128];
1683 /* Output is not interrupt driven */
1685 spin_lock_irqsave (&hmidi
->lock
, flags
);
1686 if (hmidi
->output
&&
1687 !snd_rawmidi_transmit_empty (hmidi
->output
)) {
1688 n_pending
= snd_hdspm_midi_output_possible (hmidi
->hdspm
,
1690 if (n_pending
> 0) {
1691 if (n_pending
> (int)sizeof (buf
))
1692 n_pending
= sizeof (buf
);
1694 to_write
= snd_rawmidi_transmit (hmidi
->output
, buf
,
1697 for (i
= 0; i
< to_write
; ++i
)
1698 snd_hdspm_midi_write_byte (hmidi
->hdspm
,
1704 spin_unlock_irqrestore (&hmidi
->lock
, flags
);
1708 static int snd_hdspm_midi_input_read (struct hdspm_midi
*hmidi
)
1710 unsigned char buf
[128]; /* this buffer is designed to match the MIDI
1713 unsigned long flags
;
1717 spin_lock_irqsave (&hmidi
->lock
, flags
);
1718 n_pending
= snd_hdspm_midi_input_available (hmidi
->hdspm
, hmidi
->id
);
1719 if (n_pending
> 0) {
1721 if (n_pending
> (int)sizeof (buf
))
1722 n_pending
= sizeof (buf
);
1723 for (i
= 0; i
< n_pending
; ++i
)
1724 buf
[i
] = snd_hdspm_midi_read_byte (hmidi
->hdspm
,
1727 snd_rawmidi_receive (hmidi
->input
, buf
,
1730 /* flush the MIDI input FIFO */
1732 snd_hdspm_midi_read_byte (hmidi
->hdspm
,
1737 spin_unlock_irqrestore(&hmidi
->lock
, flags
);
1739 spin_lock_irqsave(&hmidi
->hdspm
->lock
, flags
);
1740 hmidi
->hdspm
->control_register
|= hmidi
->ie
;
1741 hdspm_write(hmidi
->hdspm
, HDSPM_controlRegister
,
1742 hmidi
->hdspm
->control_register
);
1743 spin_unlock_irqrestore(&hmidi
->hdspm
->lock
, flags
);
1745 return snd_hdspm_midi_output_write (hmidi
);
1749 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream
*substream
, int up
)
1751 struct hdspm
*hdspm
;
1752 struct hdspm_midi
*hmidi
;
1753 unsigned long flags
;
1755 hmidi
= substream
->rmidi
->private_data
;
1756 hdspm
= hmidi
->hdspm
;
1758 spin_lock_irqsave (&hdspm
->lock
, flags
);
1760 if (!(hdspm
->control_register
& hmidi
->ie
)) {
1761 snd_hdspm_flush_midi_input (hdspm
, hmidi
->id
);
1762 hdspm
->control_register
|= hmidi
->ie
;
1765 hdspm
->control_register
&= ~hmidi
->ie
;
1768 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
1769 spin_unlock_irqrestore (&hdspm
->lock
, flags
);
1772 static void snd_hdspm_midi_output_timer(unsigned long data
)
1774 struct hdspm_midi
*hmidi
= (struct hdspm_midi
*) data
;
1775 unsigned long flags
;
1777 snd_hdspm_midi_output_write(hmidi
);
1778 spin_lock_irqsave (&hmidi
->lock
, flags
);
1780 /* this does not bump hmidi->istimer, because the
1781 kernel automatically removed the timer when it
1782 expired, and we are now adding it back, thus
1783 leaving istimer wherever it was set before.
1786 if (hmidi
->istimer
) {
1787 hmidi
->timer
.expires
= 1 + jiffies
;
1788 add_timer(&hmidi
->timer
);
1791 spin_unlock_irqrestore (&hmidi
->lock
, flags
);
1795 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream
*substream
, int up
)
1797 struct hdspm_midi
*hmidi
;
1798 unsigned long flags
;
1800 hmidi
= substream
->rmidi
->private_data
;
1801 spin_lock_irqsave (&hmidi
->lock
, flags
);
1803 if (!hmidi
->istimer
) {
1804 init_timer(&hmidi
->timer
);
1805 hmidi
->timer
.function
= snd_hdspm_midi_output_timer
;
1806 hmidi
->timer
.data
= (unsigned long) hmidi
;
1807 hmidi
->timer
.expires
= 1 + jiffies
;
1808 add_timer(&hmidi
->timer
);
1812 if (hmidi
->istimer
&& --hmidi
->istimer
<= 0)
1813 del_timer (&hmidi
->timer
);
1815 spin_unlock_irqrestore (&hmidi
->lock
, flags
);
1817 snd_hdspm_midi_output_write(hmidi
);
1820 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream
*substream
)
1822 struct hdspm_midi
*hmidi
;
1824 hmidi
= substream
->rmidi
->private_data
;
1825 spin_lock_irq (&hmidi
->lock
);
1826 snd_hdspm_flush_midi_input (hmidi
->hdspm
, hmidi
->id
);
1827 hmidi
->input
= substream
;
1828 spin_unlock_irq (&hmidi
->lock
);
1833 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream
*substream
)
1835 struct hdspm_midi
*hmidi
;
1837 hmidi
= substream
->rmidi
->private_data
;
1838 spin_lock_irq (&hmidi
->lock
);
1839 hmidi
->output
= substream
;
1840 spin_unlock_irq (&hmidi
->lock
);
1845 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream
*substream
)
1847 struct hdspm_midi
*hmidi
;
1849 snd_hdspm_midi_input_trigger (substream
, 0);
1851 hmidi
= substream
->rmidi
->private_data
;
1852 spin_lock_irq (&hmidi
->lock
);
1853 hmidi
->input
= NULL
;
1854 spin_unlock_irq (&hmidi
->lock
);
1859 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream
*substream
)
1861 struct hdspm_midi
*hmidi
;
1863 snd_hdspm_midi_output_trigger (substream
, 0);
1865 hmidi
= substream
->rmidi
->private_data
;
1866 spin_lock_irq (&hmidi
->lock
);
1867 hmidi
->output
= NULL
;
1868 spin_unlock_irq (&hmidi
->lock
);
1873 static struct snd_rawmidi_ops snd_hdspm_midi_output
=
1875 .open
= snd_hdspm_midi_output_open
,
1876 .close
= snd_hdspm_midi_output_close
,
1877 .trigger
= snd_hdspm_midi_output_trigger
,
1880 static struct snd_rawmidi_ops snd_hdspm_midi_input
=
1882 .open
= snd_hdspm_midi_input_open
,
1883 .close
= snd_hdspm_midi_input_close
,
1884 .trigger
= snd_hdspm_midi_input_trigger
,
1887 static int snd_hdspm_create_midi(struct snd_card
*card
,
1888 struct hdspm
*hdspm
, int id
)
1893 hdspm
->midi
[id
].id
= id
;
1894 hdspm
->midi
[id
].hdspm
= hdspm
;
1895 spin_lock_init (&hdspm
->midi
[id
].lock
);
1898 if (MADIface
== hdspm
->io_type
) {
1899 /* MIDI-over-MADI on HDSPe MADIface */
1900 hdspm
->midi
[0].dataIn
= HDSPM_midiDataIn2
;
1901 hdspm
->midi
[0].statusIn
= HDSPM_midiStatusIn2
;
1902 hdspm
->midi
[0].dataOut
= HDSPM_midiDataOut2
;
1903 hdspm
->midi
[0].statusOut
= HDSPM_midiStatusOut2
;
1904 hdspm
->midi
[0].ie
= HDSPM_Midi2InterruptEnable
;
1905 hdspm
->midi
[0].irq
= HDSPM_midi2IRQPending
;
1907 hdspm
->midi
[0].dataIn
= HDSPM_midiDataIn0
;
1908 hdspm
->midi
[0].statusIn
= HDSPM_midiStatusIn0
;
1909 hdspm
->midi
[0].dataOut
= HDSPM_midiDataOut0
;
1910 hdspm
->midi
[0].statusOut
= HDSPM_midiStatusOut0
;
1911 hdspm
->midi
[0].ie
= HDSPM_Midi0InterruptEnable
;
1912 hdspm
->midi
[0].irq
= HDSPM_midi0IRQPending
;
1914 } else if (1 == id
) {
1915 hdspm
->midi
[1].dataIn
= HDSPM_midiDataIn1
;
1916 hdspm
->midi
[1].statusIn
= HDSPM_midiStatusIn1
;
1917 hdspm
->midi
[1].dataOut
= HDSPM_midiDataOut1
;
1918 hdspm
->midi
[1].statusOut
= HDSPM_midiStatusOut1
;
1919 hdspm
->midi
[1].ie
= HDSPM_Midi1InterruptEnable
;
1920 hdspm
->midi
[1].irq
= HDSPM_midi1IRQPending
;
1921 } else if ((2 == id
) && (MADI
== hdspm
->io_type
)) {
1922 /* MIDI-over-MADI on HDSPe MADI */
1923 hdspm
->midi
[2].dataIn
= HDSPM_midiDataIn2
;
1924 hdspm
->midi
[2].statusIn
= HDSPM_midiStatusIn2
;
1925 hdspm
->midi
[2].dataOut
= HDSPM_midiDataOut2
;
1926 hdspm
->midi
[2].statusOut
= HDSPM_midiStatusOut2
;
1927 hdspm
->midi
[2].ie
= HDSPM_Midi2InterruptEnable
;
1928 hdspm
->midi
[2].irq
= HDSPM_midi2IRQPending
;
1929 } else if (2 == id
) {
1930 /* TCO MTC, read only */
1931 hdspm
->midi
[2].dataIn
= HDSPM_midiDataIn2
;
1932 hdspm
->midi
[2].statusIn
= HDSPM_midiStatusIn2
;
1933 hdspm
->midi
[2].dataOut
= -1;
1934 hdspm
->midi
[2].statusOut
= -1;
1935 hdspm
->midi
[2].ie
= HDSPM_Midi2InterruptEnable
;
1936 hdspm
->midi
[2].irq
= HDSPM_midi2IRQPendingAES
;
1937 } else if (3 == id
) {
1938 /* TCO MTC on HDSPe MADI */
1939 hdspm
->midi
[3].dataIn
= HDSPM_midiDataIn3
;
1940 hdspm
->midi
[3].statusIn
= HDSPM_midiStatusIn3
;
1941 hdspm
->midi
[3].dataOut
= -1;
1942 hdspm
->midi
[3].statusOut
= -1;
1943 hdspm
->midi
[3].ie
= HDSPM_Midi3InterruptEnable
;
1944 hdspm
->midi
[3].irq
= HDSPM_midi3IRQPending
;
1947 if ((id
< 2) || ((2 == id
) && ((MADI
== hdspm
->io_type
) ||
1948 (MADIface
== hdspm
->io_type
)))) {
1949 if ((id
== 0) && (MADIface
== hdspm
->io_type
)) {
1950 sprintf(buf
, "%s MIDIoverMADI", card
->shortname
);
1951 } else if ((id
== 2) && (MADI
== hdspm
->io_type
)) {
1952 sprintf(buf
, "%s MIDIoverMADI", card
->shortname
);
1954 sprintf(buf
, "%s MIDI %d", card
->shortname
, id
+1);
1956 err
= snd_rawmidi_new(card
, buf
, id
, 1, 1,
1957 &hdspm
->midi
[id
].rmidi
);
1961 sprintf(hdspm
->midi
[id
].rmidi
->name
, "%s MIDI %d",
1963 hdspm
->midi
[id
].rmidi
->private_data
= &hdspm
->midi
[id
];
1965 snd_rawmidi_set_ops(hdspm
->midi
[id
].rmidi
,
1966 SNDRV_RAWMIDI_STREAM_OUTPUT
,
1967 &snd_hdspm_midi_output
);
1968 snd_rawmidi_set_ops(hdspm
->midi
[id
].rmidi
,
1969 SNDRV_RAWMIDI_STREAM_INPUT
,
1970 &snd_hdspm_midi_input
);
1972 hdspm
->midi
[id
].rmidi
->info_flags
|=
1973 SNDRV_RAWMIDI_INFO_OUTPUT
|
1974 SNDRV_RAWMIDI_INFO_INPUT
|
1975 SNDRV_RAWMIDI_INFO_DUPLEX
;
1977 /* TCO MTC, read only */
1978 sprintf(buf
, "%s MTC %d", card
->shortname
, id
+1);
1979 err
= snd_rawmidi_new(card
, buf
, id
, 1, 1,
1980 &hdspm
->midi
[id
].rmidi
);
1984 sprintf(hdspm
->midi
[id
].rmidi
->name
,
1985 "%s MTC %d", card
->id
, id
+1);
1986 hdspm
->midi
[id
].rmidi
->private_data
= &hdspm
->midi
[id
];
1988 snd_rawmidi_set_ops(hdspm
->midi
[id
].rmidi
,
1989 SNDRV_RAWMIDI_STREAM_INPUT
,
1990 &snd_hdspm_midi_input
);
1992 hdspm
->midi
[id
].rmidi
->info_flags
|= SNDRV_RAWMIDI_INFO_INPUT
;
1999 static void hdspm_midi_tasklet(unsigned long arg
)
2001 struct hdspm
*hdspm
= (struct hdspm
*)arg
;
2004 while (i
< hdspm
->midiPorts
) {
2005 if (hdspm
->midi
[i
].pending
)
2006 snd_hdspm_midi_input_read(&hdspm
->midi
[i
]);
2013 /*-----------------------------------------------------------------------------
2015 ----------------------------------------------------------------------------*/
2017 /* get the system sample rate which is set */
2020 static inline int hdspm_get_pll_freq(struct hdspm
*hdspm
)
2022 unsigned int period
, rate
;
2024 period
= hdspm_read(hdspm
, HDSPM_RD_PLL_FREQ
);
2025 rate
= hdspm_calc_dds_value(hdspm
, period
);
2031 * Calculate the real sample rate from the
2032 * current DDS value.
2034 static int hdspm_get_system_sample_rate(struct hdspm
*hdspm
)
2038 rate
= hdspm_get_pll_freq(hdspm
);
2040 if (rate
> 207000) {
2041 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2042 if (0 == hdspm_system_clock_mode(hdspm
)) {
2043 /* master mode, return internal sample rate */
2044 rate
= hdspm
->system_sample_rate
;
2046 /* slave mode, return external sample rate */
2047 rate
= hdspm_external_sample_rate(hdspm
);
2055 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2056 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2059 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2060 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2061 .info = snd_hdspm_info_system_sample_rate, \
2062 .put = snd_hdspm_put_system_sample_rate, \
2063 .get = snd_hdspm_get_system_sample_rate \
2066 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol
*kcontrol
,
2067 struct snd_ctl_elem_info
*uinfo
)
2069 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
2071 uinfo
->value
.integer
.min
= 27000;
2072 uinfo
->value
.integer
.max
= 207000;
2073 uinfo
->value
.integer
.step
= 1;
2078 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol
*kcontrol
,
2079 struct snd_ctl_elem_value
*
2082 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2084 ucontrol
->value
.integer
.value
[0] = hdspm_get_system_sample_rate(hdspm
);
2088 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol
*kcontrol
,
2089 struct snd_ctl_elem_value
*
2092 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2094 hdspm_set_dds_value(hdspm
, ucontrol
->value
.enumerated
.item
[0]);
2100 * Returns the WordClock sample rate class for the given card.
2102 static int hdspm_get_wc_sample_rate(struct hdspm
*hdspm
)
2106 switch (hdspm
->io_type
) {
2109 status
= hdspm_read(hdspm
, HDSPM_RD_STATUS_1
);
2110 return (status
>> 16) & 0xF;
2122 * Returns the TCO sample rate class for the given card.
2124 static int hdspm_get_tco_sample_rate(struct hdspm
*hdspm
)
2129 switch (hdspm
->io_type
) {
2132 status
= hdspm_read(hdspm
, HDSPM_RD_STATUS_1
);
2133 return (status
>> 20) & 0xF;
2145 * Returns the SYNC_IN sample rate class for the given card.
2147 static int hdspm_get_sync_in_sample_rate(struct hdspm
*hdspm
)
2152 switch (hdspm
->io_type
) {
2155 status
= hdspm_read(hdspm
, HDSPM_RD_STATUS_2
);
2156 return (status
>> 12) & 0xF;
2168 * Returns the sample rate class for input source <idx> for
2169 * 'new style' cards like the AIO and RayDAT.
2171 static int hdspm_get_s1_sample_rate(struct hdspm
*hdspm
, unsigned int idx
)
2173 int status
= hdspm_read(hdspm
, HDSPM_RD_STATUS_2
);
2175 return (status
>> (idx
*4)) & 0xF;
2178 #define ENUMERATED_CTL_INFO(info, texts) \
2180 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \
2182 uinfo->value.enumerated.items = ARRAY_SIZE(texts); \
2183 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \
2184 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; \
2185 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \
2190 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2191 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2193 .private_value = xindex, \
2194 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2195 .info = snd_hdspm_info_autosync_sample_rate, \
2196 .get = snd_hdspm_get_autosync_sample_rate \
2200 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol
*kcontrol
,
2201 struct snd_ctl_elem_info
*uinfo
)
2203 ENUMERATED_CTL_INFO(uinfo
, texts_freq
);
2208 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol
*kcontrol
,
2209 struct snd_ctl_elem_value
*
2212 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2214 switch (hdspm
->io_type
) {
2216 switch (kcontrol
->private_value
) {
2218 ucontrol
->value
.enumerated
.item
[0] =
2219 hdspm_get_wc_sample_rate(hdspm
);
2222 ucontrol
->value
.enumerated
.item
[0] =
2223 hdspm_get_tco_sample_rate(hdspm
);
2226 ucontrol
->value
.enumerated
.item
[0] =
2227 hdspm_get_sync_in_sample_rate(hdspm
);
2230 ucontrol
->value
.enumerated
.item
[0] =
2231 hdspm_get_s1_sample_rate(hdspm
,
2232 kcontrol
->private_value
-1);
2237 switch (kcontrol
->private_value
) {
2239 ucontrol
->value
.enumerated
.item
[0] =
2240 hdspm_get_wc_sample_rate(hdspm
);
2243 ucontrol
->value
.enumerated
.item
[0] =
2244 hdspm_get_tco_sample_rate(hdspm
);
2246 case 5: /* SYNC_IN */
2247 ucontrol
->value
.enumerated
.item
[0] =
2248 hdspm_get_sync_in_sample_rate(hdspm
);
2251 ucontrol
->value
.enumerated
.item
[0] =
2252 hdspm_get_s1_sample_rate(hdspm
,
2253 ucontrol
->id
.index
-1);
2259 switch (kcontrol
->private_value
) {
2261 ucontrol
->value
.enumerated
.item
[0] =
2262 hdspm_get_wc_sample_rate(hdspm
);
2265 ucontrol
->value
.enumerated
.item
[0] =
2266 hdspm_get_tco_sample_rate(hdspm
);
2268 case 10: /* SYNC_IN */
2269 ucontrol
->value
.enumerated
.item
[0] =
2270 hdspm_get_sync_in_sample_rate(hdspm
);
2272 default: /* AES1 to AES8 */
2273 ucontrol
->value
.enumerated
.item
[0] =
2274 hdspm_get_s1_sample_rate(hdspm
,
2275 kcontrol
->private_value
-1);
2283 int rate
= hdspm_external_sample_rate(hdspm
);
2284 int i
, selected_rate
= 0;
2285 for (i
= 1; i
< 10; i
++)
2286 if (HDSPM_bit2freq(i
) == rate
) {
2290 ucontrol
->value
.enumerated
.item
[0] = selected_rate
;
2302 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2303 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2306 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2307 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2308 .info = snd_hdspm_info_system_clock_mode, \
2309 .get = snd_hdspm_get_system_clock_mode, \
2310 .put = snd_hdspm_put_system_clock_mode, \
2315 * Returns the system clock mode for the given card.
2316 * @returns 0 - master, 1 - slave
2318 static int hdspm_system_clock_mode(struct hdspm
*hdspm
)
2320 switch (hdspm
->io_type
) {
2323 if (hdspm
->settings_register
& HDSPM_c0Master
)
2328 if (hdspm
->control_register
& HDSPM_ClockModeMaster
)
2337 * Sets the system clock mode.
2338 * @param mode 0 - master, 1 - slave
2340 static void hdspm_set_system_clock_mode(struct hdspm
*hdspm
, int mode
)
2342 switch (hdspm
->io_type
) {
2346 hdspm
->settings_register
|= HDSPM_c0Master
;
2348 hdspm
->settings_register
&= ~HDSPM_c0Master
;
2350 hdspm_write(hdspm
, HDSPM_WR_SETTINGS
, hdspm
->settings_register
);
2355 hdspm
->control_register
|= HDSPM_ClockModeMaster
;
2357 hdspm
->control_register
&= ~HDSPM_ClockModeMaster
;
2359 hdspm_write(hdspm
, HDSPM_controlRegister
,
2360 hdspm
->control_register
);
2365 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol
*kcontrol
,
2366 struct snd_ctl_elem_info
*uinfo
)
2368 static char *texts
[] = { "Master", "AutoSync" };
2369 ENUMERATED_CTL_INFO(uinfo
, texts
);
2373 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol
*kcontrol
,
2374 struct snd_ctl_elem_value
*ucontrol
)
2376 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2378 ucontrol
->value
.enumerated
.item
[0] = hdspm_system_clock_mode(hdspm
);
2382 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol
*kcontrol
,
2383 struct snd_ctl_elem_value
*ucontrol
)
2385 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2388 if (!snd_hdspm_use_is_exclusive(hdspm
))
2391 val
= ucontrol
->value
.enumerated
.item
[0];
2397 hdspm_set_system_clock_mode(hdspm
, val
);
2403 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2404 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2407 .info = snd_hdspm_info_clock_source, \
2408 .get = snd_hdspm_get_clock_source, \
2409 .put = snd_hdspm_put_clock_source \
2413 static int hdspm_clock_source(struct hdspm
* hdspm
)
2415 switch (hdspm
->system_sample_rate
) {
2416 case 32000: return 0;
2417 case 44100: return 1;
2418 case 48000: return 2;
2419 case 64000: return 3;
2420 case 88200: return 4;
2421 case 96000: return 5;
2422 case 128000: return 6;
2423 case 176400: return 7;
2424 case 192000: return 8;
2430 static int hdspm_set_clock_source(struct hdspm
* hdspm
, int mode
)
2435 rate
= 32000; break;
2437 rate
= 44100; break;
2439 rate
= 48000; break;
2441 rate
= 64000; break;
2443 rate
= 88200; break;
2445 rate
= 96000; break;
2447 rate
= 128000; break;
2449 rate
= 176400; break;
2451 rate
= 192000; break;
2455 hdspm_set_rate(hdspm
, rate
, 1);
2459 static int snd_hdspm_info_clock_source(struct snd_kcontrol
*kcontrol
,
2460 struct snd_ctl_elem_info
*uinfo
)
2462 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2464 uinfo
->value
.enumerated
.items
= 9;
2466 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2467 uinfo
->value
.enumerated
.item
=
2468 uinfo
->value
.enumerated
.items
- 1;
2470 strcpy(uinfo
->value
.enumerated
.name
,
2471 texts_freq
[uinfo
->value
.enumerated
.item
+1]);
2476 static int snd_hdspm_get_clock_source(struct snd_kcontrol
*kcontrol
,
2477 struct snd_ctl_elem_value
*ucontrol
)
2479 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2481 ucontrol
->value
.enumerated
.item
[0] = hdspm_clock_source(hdspm
);
2485 static int snd_hdspm_put_clock_source(struct snd_kcontrol
*kcontrol
,
2486 struct snd_ctl_elem_value
*ucontrol
)
2488 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2492 if (!snd_hdspm_use_is_exclusive(hdspm
))
2494 val
= ucontrol
->value
.enumerated
.item
[0];
2499 spin_lock_irq(&hdspm
->lock
);
2500 if (val
!= hdspm_clock_source(hdspm
))
2501 change
= (hdspm_set_clock_source(hdspm
, val
) == 0) ? 1 : 0;
2504 spin_unlock_irq(&hdspm
->lock
);
2509 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2510 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2513 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2514 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2515 .info = snd_hdspm_info_pref_sync_ref, \
2516 .get = snd_hdspm_get_pref_sync_ref, \
2517 .put = snd_hdspm_put_pref_sync_ref \
2522 * Returns the current preferred sync reference setting.
2523 * The semantics of the return value are depending on the
2524 * card, please see the comments for clarification.
2526 static int hdspm_pref_sync_ref(struct hdspm
* hdspm
)
2528 switch (hdspm
->io_type
) {
2530 switch (hdspm
->control_register
& HDSPM_SyncRefMask
) {
2531 case 0: return 0; /* WC */
2532 case HDSPM_SyncRef0
: return 1; /* AES 1 */
2533 case HDSPM_SyncRef1
: return 2; /* AES 2 */
2534 case HDSPM_SyncRef1
+HDSPM_SyncRef0
: return 3; /* AES 3 */
2535 case HDSPM_SyncRef2
: return 4; /* AES 4 */
2536 case HDSPM_SyncRef2
+HDSPM_SyncRef0
: return 5; /* AES 5 */
2537 case HDSPM_SyncRef2
+HDSPM_SyncRef1
: return 6; /* AES 6 */
2538 case HDSPM_SyncRef2
+HDSPM_SyncRef1
+HDSPM_SyncRef0
:
2539 return 7; /* AES 7 */
2540 case HDSPM_SyncRef3
: return 8; /* AES 8 */
2541 case HDSPM_SyncRef3
+HDSPM_SyncRef0
: return 9; /* TCO */
2548 switch (hdspm
->control_register
& HDSPM_SyncRefMask
) {
2549 case 0: return 0; /* WC */
2550 case HDSPM_SyncRef0
: return 1; /* MADI */
2551 case HDSPM_SyncRef1
: return 2; /* TCO */
2552 case HDSPM_SyncRef1
+HDSPM_SyncRef0
:
2553 return 3; /* SYNC_IN */
2556 switch (hdspm
->control_register
& HDSPM_SyncRefMask
) {
2557 case 0: return 0; /* WC */
2558 case HDSPM_SyncRef0
: return 1; /* MADI */
2559 case HDSPM_SyncRef1
+HDSPM_SyncRef0
:
2560 return 2; /* SYNC_IN */
2567 switch ((hdspm
->settings_register
&
2568 HDSPM_c0_SyncRefMask
) / HDSPM_c0_SyncRef0
) {
2569 case 0: return 0; /* WC */
2570 case 3: return 1; /* ADAT 1 */
2571 case 4: return 2; /* ADAT 2 */
2572 case 5: return 3; /* ADAT 3 */
2573 case 6: return 4; /* ADAT 4 */
2574 case 1: return 5; /* AES */
2575 case 2: return 6; /* SPDIF */
2576 case 9: return 7; /* TCO */
2577 case 10: return 8; /* SYNC_IN */
2580 switch ((hdspm
->settings_register
&
2581 HDSPM_c0_SyncRefMask
) / HDSPM_c0_SyncRef0
) {
2582 case 0: return 0; /* WC */
2583 case 3: return 1; /* ADAT 1 */
2584 case 4: return 2; /* ADAT 2 */
2585 case 5: return 3; /* ADAT 3 */
2586 case 6: return 4; /* ADAT 4 */
2587 case 1: return 5; /* AES */
2588 case 2: return 6; /* SPDIF */
2589 case 10: return 7; /* SYNC_IN */
2597 switch ((hdspm
->settings_register
&
2598 HDSPM_c0_SyncRefMask
) / HDSPM_c0_SyncRef0
) {
2599 case 0: return 0; /* WC */
2600 case 3: return 1; /* ADAT */
2601 case 1: return 2; /* AES */
2602 case 2: return 3; /* SPDIF */
2603 case 9: return 4; /* TCO */
2604 case 10: return 5; /* SYNC_IN */
2607 switch ((hdspm
->settings_register
&
2608 HDSPM_c0_SyncRefMask
) / HDSPM_c0_SyncRef0
) {
2609 case 0: return 0; /* WC */
2610 case 3: return 1; /* ADAT */
2611 case 1: return 2; /* AES */
2612 case 2: return 3; /* SPDIF */
2613 case 10: return 4; /* SYNC_IN */
2625 * Set the preferred sync reference to <pref>. The semantics
2626 * of <pref> are depending on the card type, see the comments
2627 * for clarification.
2629 static int hdspm_set_pref_sync_ref(struct hdspm
* hdspm
, int pref
)
2633 switch (hdspm
->io_type
) {
2635 hdspm
->control_register
&= ~HDSPM_SyncRefMask
;
2640 hdspm
->control_register
|= HDSPM_SyncRef0
;
2643 hdspm
->control_register
|= HDSPM_SyncRef1
;
2646 hdspm
->control_register
|=
2647 HDSPM_SyncRef1
+HDSPM_SyncRef0
;
2650 hdspm
->control_register
|= HDSPM_SyncRef2
;
2653 hdspm
->control_register
|=
2654 HDSPM_SyncRef2
+HDSPM_SyncRef0
;
2657 hdspm
->control_register
|=
2658 HDSPM_SyncRef2
+HDSPM_SyncRef1
;
2661 hdspm
->control_register
|=
2662 HDSPM_SyncRef2
+HDSPM_SyncRef1
+HDSPM_SyncRef0
;
2665 hdspm
->control_register
|= HDSPM_SyncRef3
;
2668 hdspm
->control_register
|=
2669 HDSPM_SyncRef3
+HDSPM_SyncRef0
;
2679 hdspm
->control_register
&= ~HDSPM_SyncRefMask
;
2685 hdspm
->control_register
|= HDSPM_SyncRef0
;
2688 hdspm
->control_register
|= HDSPM_SyncRef1
;
2690 case 3: /* SYNC_IN */
2691 hdspm
->control_register
|=
2692 HDSPM_SyncRef0
+HDSPM_SyncRef1
;
2702 hdspm
->control_register
|= HDSPM_SyncRef0
;
2704 case 2: /* SYNC_IN */
2705 hdspm
->control_register
|=
2706 HDSPM_SyncRef0
+HDSPM_SyncRef1
;
2718 case 0: p
= 0; break; /* WC */
2719 case 1: p
= 3; break; /* ADAT 1 */
2720 case 2: p
= 4; break; /* ADAT 2 */
2721 case 3: p
= 5; break; /* ADAT 3 */
2722 case 4: p
= 6; break; /* ADAT 4 */
2723 case 5: p
= 1; break; /* AES */
2724 case 6: p
= 2; break; /* SPDIF */
2725 case 7: p
= 9; break; /* TCO */
2726 case 8: p
= 10; break; /* SYNC_IN */
2731 case 0: p
= 0; break; /* WC */
2732 case 1: p
= 3; break; /* ADAT 1 */
2733 case 2: p
= 4; break; /* ADAT 2 */
2734 case 3: p
= 5; break; /* ADAT 3 */
2735 case 4: p
= 6; break; /* ADAT 4 */
2736 case 5: p
= 1; break; /* AES */
2737 case 6: p
= 2; break; /* SPDIF */
2738 case 7: p
= 10; break; /* SYNC_IN */
2747 case 0: p
= 0; break; /* WC */
2748 case 1: p
= 3; break; /* ADAT */
2749 case 2: p
= 1; break; /* AES */
2750 case 3: p
= 2; break; /* SPDIF */
2751 case 4: p
= 9; break; /* TCO */
2752 case 5: p
= 10; break; /* SYNC_IN */
2757 case 0: p
= 0; break; /* WC */
2758 case 1: p
= 3; break; /* ADAT */
2759 case 2: p
= 1; break; /* AES */
2760 case 3: p
= 2; break; /* SPDIF */
2761 case 4: p
= 10; break; /* SYNC_IN */
2768 switch (hdspm
->io_type
) {
2771 hdspm
->settings_register
&= ~HDSPM_c0_SyncRefMask
;
2772 hdspm
->settings_register
|= HDSPM_c0_SyncRef0
* p
;
2773 hdspm_write(hdspm
, HDSPM_WR_SETTINGS
, hdspm
->settings_register
);
2779 hdspm_write(hdspm
, HDSPM_controlRegister
,
2780 hdspm
->control_register
);
2787 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol
*kcontrol
,
2788 struct snd_ctl_elem_info
*uinfo
)
2790 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2792 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2794 uinfo
->value
.enumerated
.items
= hdspm
->texts_autosync_items
;
2796 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2797 uinfo
->value
.enumerated
.item
=
2798 uinfo
->value
.enumerated
.items
- 1;
2800 strcpy(uinfo
->value
.enumerated
.name
,
2801 hdspm
->texts_autosync
[uinfo
->value
.enumerated
.item
]);
2806 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol
*kcontrol
,
2807 struct snd_ctl_elem_value
*ucontrol
)
2809 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2810 int psf
= hdspm_pref_sync_ref(hdspm
);
2813 ucontrol
->value
.enumerated
.item
[0] = psf
;
2820 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol
*kcontrol
,
2821 struct snd_ctl_elem_value
*ucontrol
)
2823 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2824 int val
, change
= 0;
2826 if (!snd_hdspm_use_is_exclusive(hdspm
))
2829 val
= ucontrol
->value
.enumerated
.item
[0];
2833 else if (val
>= hdspm
->texts_autosync_items
)
2834 val
= hdspm
->texts_autosync_items
-1;
2836 spin_lock_irq(&hdspm
->lock
);
2837 if (val
!= hdspm_pref_sync_ref(hdspm
))
2838 change
= (0 == hdspm_set_pref_sync_ref(hdspm
, val
)) ? 1 : 0;
2840 spin_unlock_irq(&hdspm
->lock
);
2845 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
2846 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2849 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2850 .info = snd_hdspm_info_autosync_ref, \
2851 .get = snd_hdspm_get_autosync_ref, \
2854 static int hdspm_autosync_ref(struct hdspm
*hdspm
)
2856 if (AES32
== hdspm
->io_type
) {
2857 unsigned int status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
2858 unsigned int syncref
=
2859 (status
>> HDSPM_AES32_syncref_bit
) & 0xF;
2861 return HDSPM_AES32_AUTOSYNC_FROM_WORD
;
2864 return HDSPM_AES32_AUTOSYNC_FROM_NONE
;
2865 } else if (MADI
== hdspm
->io_type
) {
2866 /* This looks at the autosync selected sync reference */
2867 unsigned int status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
2869 switch (status2
& HDSPM_SelSyncRefMask
) {
2870 case HDSPM_SelSyncRef_WORD
:
2871 return HDSPM_AUTOSYNC_FROM_WORD
;
2872 case HDSPM_SelSyncRef_MADI
:
2873 return HDSPM_AUTOSYNC_FROM_MADI
;
2874 case HDSPM_SelSyncRef_TCO
:
2875 return HDSPM_AUTOSYNC_FROM_TCO
;
2876 case HDSPM_SelSyncRef_SyncIn
:
2877 return HDSPM_AUTOSYNC_FROM_SYNC_IN
;
2878 case HDSPM_SelSyncRef_NVALID
:
2879 return HDSPM_AUTOSYNC_FROM_NONE
;
2889 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol
*kcontrol
,
2890 struct snd_ctl_elem_info
*uinfo
)
2892 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2894 if (AES32
== hdspm
->io_type
) {
2895 static char *texts
[] = { "WordClock", "AES1", "AES2", "AES3",
2896 "AES4", "AES5", "AES6", "AES7", "AES8", "None"};
2898 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2900 uinfo
->value
.enumerated
.items
= 10;
2901 if (uinfo
->value
.enumerated
.item
>=
2902 uinfo
->value
.enumerated
.items
)
2903 uinfo
->value
.enumerated
.item
=
2904 uinfo
->value
.enumerated
.items
- 1;
2905 strcpy(uinfo
->value
.enumerated
.name
,
2906 texts
[uinfo
->value
.enumerated
.item
]);
2907 } else if (MADI
== hdspm
->io_type
) {
2908 static char *texts
[] = {"Word Clock", "MADI", "TCO",
2909 "Sync In", "None" };
2911 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2913 uinfo
->value
.enumerated
.items
= 5;
2914 if (uinfo
->value
.enumerated
.item
>=
2915 uinfo
->value
.enumerated
.items
)
2916 uinfo
->value
.enumerated
.item
=
2917 uinfo
->value
.enumerated
.items
- 1;
2918 strcpy(uinfo
->value
.enumerated
.name
,
2919 texts
[uinfo
->value
.enumerated
.item
]);
2924 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol
*kcontrol
,
2925 struct snd_ctl_elem_value
*ucontrol
)
2927 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2929 ucontrol
->value
.enumerated
.item
[0] = hdspm_autosync_ref(hdspm
);
2935 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
2936 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2938 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
2939 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2940 .info = snd_hdspm_info_tco_video_input_format, \
2941 .get = snd_hdspm_get_tco_video_input_format, \
2944 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol
*kcontrol
,
2945 struct snd_ctl_elem_info
*uinfo
)
2947 static char *texts
[] = {"No video", "NTSC", "PAL"};
2948 ENUMERATED_CTL_INFO(uinfo
, texts
);
2952 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol
*kcontrol
,
2953 struct snd_ctl_elem_value
*ucontrol
)
2958 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
2959 status
= hdspm_read(hdspm
, HDSPM_RD_TCO
+ 4);
2960 switch (status
& (HDSPM_TCO1_Video_Input_Format_NTSC
|
2961 HDSPM_TCO1_Video_Input_Format_PAL
)) {
2962 case HDSPM_TCO1_Video_Input_Format_NTSC
:
2966 case HDSPM_TCO1_Video_Input_Format_PAL
:
2975 ucontrol
->value
.enumerated
.item
[0] = ret
;
2981 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
2982 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2984 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
2985 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2986 .info = snd_hdspm_info_tco_ltc_frames, \
2987 .get = snd_hdspm_get_tco_ltc_frames, \
2990 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol
*kcontrol
,
2991 struct snd_ctl_elem_info
*uinfo
)
2993 static char *texts
[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
2995 ENUMERATED_CTL_INFO(uinfo
, texts
);
2999 static int hdspm_tco_ltc_frames(struct hdspm
*hdspm
)
3004 status
= hdspm_read(hdspm
, HDSPM_RD_TCO
+ 4);
3005 if (status
& HDSPM_TCO1_LTC_Input_valid
) {
3006 switch (status
& (HDSPM_TCO1_LTC_Format_LSB
|
3007 HDSPM_TCO1_LTC_Format_MSB
)) {
3012 case HDSPM_TCO1_LTC_Format_LSB
:
3016 case HDSPM_TCO1_LTC_Format_MSB
:
3030 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol
*kcontrol
,
3031 struct snd_ctl_elem_value
*ucontrol
)
3033 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3035 ucontrol
->value
.enumerated
.item
[0] = hdspm_tco_ltc_frames(hdspm
);
3039 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3040 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3042 .private_value = xindex, \
3043 .info = snd_hdspm_info_toggle_setting, \
3044 .get = snd_hdspm_get_toggle_setting, \
3045 .put = snd_hdspm_put_toggle_setting \
3048 static int hdspm_toggle_setting(struct hdspm
*hdspm
, u32 regmask
)
3050 return (hdspm
->control_register
& regmask
) ? 1 : 0;
3053 static int hdspm_set_toggle_setting(struct hdspm
*hdspm
, u32 regmask
, int out
)
3056 hdspm
->control_register
|= regmask
;
3058 hdspm
->control_register
&= ~regmask
;
3059 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
3064 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info
3066 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol
*kcontrol
,
3067 struct snd_ctl_elem_value
*ucontrol
)
3069 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3070 u32 regmask
= kcontrol
->private_value
;
3072 spin_lock_irq(&hdspm
->lock
);
3073 ucontrol
->value
.integer
.value
[0] = hdspm_toggle_setting(hdspm
, regmask
);
3074 spin_unlock_irq(&hdspm
->lock
);
3078 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol
*kcontrol
,
3079 struct snd_ctl_elem_value
*ucontrol
)
3081 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3082 u32 regmask
= kcontrol
->private_value
;
3086 if (!snd_hdspm_use_is_exclusive(hdspm
))
3088 val
= ucontrol
->value
.integer
.value
[0] & 1;
3089 spin_lock_irq(&hdspm
->lock
);
3090 change
= (int) val
!= hdspm_toggle_setting(hdspm
, regmask
);
3091 hdspm_set_toggle_setting(hdspm
, regmask
, val
);
3092 spin_unlock_irq(&hdspm
->lock
);
3096 #define HDSPM_INPUT_SELECT(xname, xindex) \
3097 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3100 .info = snd_hdspm_info_input_select, \
3101 .get = snd_hdspm_get_input_select, \
3102 .put = snd_hdspm_put_input_select \
3105 static int hdspm_input_select(struct hdspm
* hdspm
)
3107 return (hdspm
->control_register
& HDSPM_InputSelect0
) ? 1 : 0;
3110 static int hdspm_set_input_select(struct hdspm
* hdspm
, int out
)
3113 hdspm
->control_register
|= HDSPM_InputSelect0
;
3115 hdspm
->control_register
&= ~HDSPM_InputSelect0
;
3116 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
3121 static int snd_hdspm_info_input_select(struct snd_kcontrol
*kcontrol
,
3122 struct snd_ctl_elem_info
*uinfo
)
3124 static char *texts
[] = { "optical", "coaxial" };
3125 ENUMERATED_CTL_INFO(uinfo
, texts
);
3129 static int snd_hdspm_get_input_select(struct snd_kcontrol
*kcontrol
,
3130 struct snd_ctl_elem_value
*ucontrol
)
3132 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3134 spin_lock_irq(&hdspm
->lock
);
3135 ucontrol
->value
.enumerated
.item
[0] = hdspm_input_select(hdspm
);
3136 spin_unlock_irq(&hdspm
->lock
);
3140 static int snd_hdspm_put_input_select(struct snd_kcontrol
*kcontrol
,
3141 struct snd_ctl_elem_value
*ucontrol
)
3143 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3147 if (!snd_hdspm_use_is_exclusive(hdspm
))
3149 val
= ucontrol
->value
.integer
.value
[0] & 1;
3150 spin_lock_irq(&hdspm
->lock
);
3151 change
= (int) val
!= hdspm_input_select(hdspm
);
3152 hdspm_set_input_select(hdspm
, val
);
3153 spin_unlock_irq(&hdspm
->lock
);
3158 #define HDSPM_DS_WIRE(xname, xindex) \
3159 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3162 .info = snd_hdspm_info_ds_wire, \
3163 .get = snd_hdspm_get_ds_wire, \
3164 .put = snd_hdspm_put_ds_wire \
3167 static int hdspm_ds_wire(struct hdspm
* hdspm
)
3169 return (hdspm
->control_register
& HDSPM_DS_DoubleWire
) ? 1 : 0;
3172 static int hdspm_set_ds_wire(struct hdspm
* hdspm
, int ds
)
3175 hdspm
->control_register
|= HDSPM_DS_DoubleWire
;
3177 hdspm
->control_register
&= ~HDSPM_DS_DoubleWire
;
3178 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
3183 static int snd_hdspm_info_ds_wire(struct snd_kcontrol
*kcontrol
,
3184 struct snd_ctl_elem_info
*uinfo
)
3186 static char *texts
[] = { "Single", "Double" };
3187 ENUMERATED_CTL_INFO(uinfo
, texts
);
3191 static int snd_hdspm_get_ds_wire(struct snd_kcontrol
*kcontrol
,
3192 struct snd_ctl_elem_value
*ucontrol
)
3194 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3196 spin_lock_irq(&hdspm
->lock
);
3197 ucontrol
->value
.enumerated
.item
[0] = hdspm_ds_wire(hdspm
);
3198 spin_unlock_irq(&hdspm
->lock
);
3202 static int snd_hdspm_put_ds_wire(struct snd_kcontrol
*kcontrol
,
3203 struct snd_ctl_elem_value
*ucontrol
)
3205 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3209 if (!snd_hdspm_use_is_exclusive(hdspm
))
3211 val
= ucontrol
->value
.integer
.value
[0] & 1;
3212 spin_lock_irq(&hdspm
->lock
);
3213 change
= (int) val
!= hdspm_ds_wire(hdspm
);
3214 hdspm_set_ds_wire(hdspm
, val
);
3215 spin_unlock_irq(&hdspm
->lock
);
3220 #define HDSPM_QS_WIRE(xname, xindex) \
3221 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3224 .info = snd_hdspm_info_qs_wire, \
3225 .get = snd_hdspm_get_qs_wire, \
3226 .put = snd_hdspm_put_qs_wire \
3229 static int hdspm_qs_wire(struct hdspm
* hdspm
)
3231 if (hdspm
->control_register
& HDSPM_QS_DoubleWire
)
3233 if (hdspm
->control_register
& HDSPM_QS_QuadWire
)
3238 static int hdspm_set_qs_wire(struct hdspm
* hdspm
, int mode
)
3240 hdspm
->control_register
&= ~(HDSPM_QS_DoubleWire
| HDSPM_QS_QuadWire
);
3245 hdspm
->control_register
|= HDSPM_QS_DoubleWire
;
3248 hdspm
->control_register
|= HDSPM_QS_QuadWire
;
3251 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
3256 static int snd_hdspm_info_qs_wire(struct snd_kcontrol
*kcontrol
,
3257 struct snd_ctl_elem_info
*uinfo
)
3259 static char *texts
[] = { "Single", "Double", "Quad" };
3260 ENUMERATED_CTL_INFO(uinfo
, texts
);
3264 static int snd_hdspm_get_qs_wire(struct snd_kcontrol
*kcontrol
,
3265 struct snd_ctl_elem_value
*ucontrol
)
3267 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3269 spin_lock_irq(&hdspm
->lock
);
3270 ucontrol
->value
.enumerated
.item
[0] = hdspm_qs_wire(hdspm
);
3271 spin_unlock_irq(&hdspm
->lock
);
3275 static int snd_hdspm_put_qs_wire(struct snd_kcontrol
*kcontrol
,
3276 struct snd_ctl_elem_value
*ucontrol
)
3278 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3282 if (!snd_hdspm_use_is_exclusive(hdspm
))
3284 val
= ucontrol
->value
.integer
.value
[0];
3289 spin_lock_irq(&hdspm
->lock
);
3290 change
= val
!= hdspm_qs_wire(hdspm
);
3291 hdspm_set_qs_wire(hdspm
, val
);
3292 spin_unlock_irq(&hdspm
->lock
);
3296 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3297 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3300 .info = snd_hdspm_info_madi_speedmode, \
3301 .get = snd_hdspm_get_madi_speedmode, \
3302 .put = snd_hdspm_put_madi_speedmode \
3305 static int hdspm_madi_speedmode(struct hdspm
*hdspm
)
3307 if (hdspm
->control_register
& HDSPM_QuadSpeed
)
3309 if (hdspm
->control_register
& HDSPM_DoubleSpeed
)
3314 static int hdspm_set_madi_speedmode(struct hdspm
*hdspm
, int mode
)
3316 hdspm
->control_register
&= ~(HDSPM_DoubleSpeed
| HDSPM_QuadSpeed
);
3321 hdspm
->control_register
|= HDSPM_DoubleSpeed
;
3324 hdspm
->control_register
|= HDSPM_QuadSpeed
;
3327 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
3332 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol
*kcontrol
,
3333 struct snd_ctl_elem_info
*uinfo
)
3335 static char *texts
[] = { "Single", "Double", "Quad" };
3336 ENUMERATED_CTL_INFO(uinfo
, texts
);
3340 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol
*kcontrol
,
3341 struct snd_ctl_elem_value
*ucontrol
)
3343 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3345 spin_lock_irq(&hdspm
->lock
);
3346 ucontrol
->value
.enumerated
.item
[0] = hdspm_madi_speedmode(hdspm
);
3347 spin_unlock_irq(&hdspm
->lock
);
3351 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol
*kcontrol
,
3352 struct snd_ctl_elem_value
*ucontrol
)
3354 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3358 if (!snd_hdspm_use_is_exclusive(hdspm
))
3360 val
= ucontrol
->value
.integer
.value
[0];
3365 spin_lock_irq(&hdspm
->lock
);
3366 change
= val
!= hdspm_madi_speedmode(hdspm
);
3367 hdspm_set_madi_speedmode(hdspm
, val
);
3368 spin_unlock_irq(&hdspm
->lock
);
3372 #define HDSPM_MIXER(xname, xindex) \
3373 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3377 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3378 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3379 .info = snd_hdspm_info_mixer, \
3380 .get = snd_hdspm_get_mixer, \
3381 .put = snd_hdspm_put_mixer \
3384 static int snd_hdspm_info_mixer(struct snd_kcontrol
*kcontrol
,
3385 struct snd_ctl_elem_info
*uinfo
)
3387 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
3389 uinfo
->value
.integer
.min
= 0;
3390 uinfo
->value
.integer
.max
= 65535;
3391 uinfo
->value
.integer
.step
= 1;
3395 static int snd_hdspm_get_mixer(struct snd_kcontrol
*kcontrol
,
3396 struct snd_ctl_elem_value
*ucontrol
)
3398 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3402 source
= ucontrol
->value
.integer
.value
[0];
3405 else if (source
>= 2 * HDSPM_MAX_CHANNELS
)
3406 source
= 2 * HDSPM_MAX_CHANNELS
- 1;
3408 destination
= ucontrol
->value
.integer
.value
[1];
3409 if (destination
< 0)
3411 else if (destination
>= HDSPM_MAX_CHANNELS
)
3412 destination
= HDSPM_MAX_CHANNELS
- 1;
3414 spin_lock_irq(&hdspm
->lock
);
3415 if (source
>= HDSPM_MAX_CHANNELS
)
3416 ucontrol
->value
.integer
.value
[2] =
3417 hdspm_read_pb_gain(hdspm
, destination
,
3418 source
- HDSPM_MAX_CHANNELS
);
3420 ucontrol
->value
.integer
.value
[2] =
3421 hdspm_read_in_gain(hdspm
, destination
, source
);
3423 spin_unlock_irq(&hdspm
->lock
);
3428 static int snd_hdspm_put_mixer(struct snd_kcontrol
*kcontrol
,
3429 struct snd_ctl_elem_value
*ucontrol
)
3431 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3437 if (!snd_hdspm_use_is_exclusive(hdspm
))
3440 source
= ucontrol
->value
.integer
.value
[0];
3441 destination
= ucontrol
->value
.integer
.value
[1];
3443 if (source
< 0 || source
>= 2 * HDSPM_MAX_CHANNELS
)
3445 if (destination
< 0 || destination
>= HDSPM_MAX_CHANNELS
)
3448 gain
= ucontrol
->value
.integer
.value
[2];
3450 spin_lock_irq(&hdspm
->lock
);
3452 if (source
>= HDSPM_MAX_CHANNELS
)
3453 change
= gain
!= hdspm_read_pb_gain(hdspm
, destination
,
3455 HDSPM_MAX_CHANNELS
);
3457 change
= gain
!= hdspm_read_in_gain(hdspm
, destination
,
3461 if (source
>= HDSPM_MAX_CHANNELS
)
3462 hdspm_write_pb_gain(hdspm
, destination
,
3463 source
- HDSPM_MAX_CHANNELS
,
3466 hdspm_write_in_gain(hdspm
, destination
, source
,
3469 spin_unlock_irq(&hdspm
->lock
);
3474 /* The simple mixer control(s) provide gain control for the
3475 basic 1:1 mappings of playback streams to output
3479 #define HDSPM_PLAYBACK_MIXER \
3480 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3481 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3482 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3483 .info = snd_hdspm_info_playback_mixer, \
3484 .get = snd_hdspm_get_playback_mixer, \
3485 .put = snd_hdspm_put_playback_mixer \
3488 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol
*kcontrol
,
3489 struct snd_ctl_elem_info
*uinfo
)
3491 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_INTEGER
;
3493 uinfo
->value
.integer
.min
= 0;
3494 uinfo
->value
.integer
.max
= 64;
3495 uinfo
->value
.integer
.step
= 1;
3499 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol
*kcontrol
,
3500 struct snd_ctl_elem_value
*ucontrol
)
3502 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3505 channel
= ucontrol
->id
.index
- 1;
3507 if (snd_BUG_ON(channel
< 0 || channel
>= HDSPM_MAX_CHANNELS
))
3510 spin_lock_irq(&hdspm
->lock
);
3511 ucontrol
->value
.integer
.value
[0] =
3512 (hdspm_read_pb_gain(hdspm
, channel
, channel
)*64)/UNITY_GAIN
;
3513 spin_unlock_irq(&hdspm
->lock
);
3518 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol
*kcontrol
,
3519 struct snd_ctl_elem_value
*ucontrol
)
3521 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3526 if (!snd_hdspm_use_is_exclusive(hdspm
))
3529 channel
= ucontrol
->id
.index
- 1;
3531 if (snd_BUG_ON(channel
< 0 || channel
>= HDSPM_MAX_CHANNELS
))
3534 gain
= ucontrol
->value
.integer
.value
[0]*UNITY_GAIN
/64;
3536 spin_lock_irq(&hdspm
->lock
);
3538 gain
!= hdspm_read_pb_gain(hdspm
, channel
,
3541 hdspm_write_pb_gain(hdspm
, channel
, channel
,
3543 spin_unlock_irq(&hdspm
->lock
);
3547 #define HDSPM_SYNC_CHECK(xname, xindex) \
3548 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3550 .private_value = xindex, \
3551 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3552 .info = snd_hdspm_info_sync_check, \
3553 .get = snd_hdspm_get_sync_check \
3556 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3557 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3559 .private_value = xindex, \
3560 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3561 .info = snd_hdspm_tco_info_lock_check, \
3562 .get = snd_hdspm_get_sync_check \
3567 static int snd_hdspm_info_sync_check(struct snd_kcontrol
*kcontrol
,
3568 struct snd_ctl_elem_info
*uinfo
)
3570 static char *texts
[] = { "No Lock", "Lock", "Sync", "N/A" };
3571 ENUMERATED_CTL_INFO(uinfo
, texts
);
3575 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol
*kcontrol
,
3576 struct snd_ctl_elem_info
*uinfo
)
3578 static char *texts
[] = { "No Lock", "Lock" };
3579 ENUMERATED_CTL_INFO(uinfo
, texts
);
3583 static int hdspm_wc_sync_check(struct hdspm
*hdspm
)
3585 int status
, status2
;
3587 switch (hdspm
->io_type
) {
3589 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
3590 if (status
& HDSPM_AES32_wcLock
) {
3591 if (status
& HDSPM_AES32_wcSync
)
3600 status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
3601 if (status2
& HDSPM_wcLock
) {
3602 if (status2
& HDSPM_wcSync
)
3612 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
3614 if (status
& 0x2000000)
3616 else if (status
& 0x1000000)
3631 static int hdspm_madi_sync_check(struct hdspm
*hdspm
)
3633 int status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
3634 if (status
& HDSPM_madiLock
) {
3635 if (status
& HDSPM_madiSync
)
3644 static int hdspm_s1_sync_check(struct hdspm
*hdspm
, int idx
)
3646 int status
, lock
, sync
;
3648 status
= hdspm_read(hdspm
, HDSPM_RD_STATUS_1
);
3650 lock
= (status
& (0x1<<idx
)) ? 1 : 0;
3651 sync
= (status
& (0x100<<idx
)) ? 1 : 0;
3661 static int hdspm_sync_in_sync_check(struct hdspm
*hdspm
)
3663 int status
, lock
= 0, sync
= 0;
3665 switch (hdspm
->io_type
) {
3668 status
= hdspm_read(hdspm
, HDSPM_RD_STATUS_3
);
3669 lock
= (status
& 0x400) ? 1 : 0;
3670 sync
= (status
& 0x800) ? 1 : 0;
3674 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
3675 lock
= (status
& HDSPM_syncInLock
) ? 1 : 0;
3676 sync
= (status
& HDSPM_syncInSync
) ? 1 : 0;
3680 status
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
3681 lock
= (status
& 0x100000) ? 1 : 0;
3682 sync
= (status
& 0x200000) ? 1 : 0;
3697 static int hdspm_aes_sync_check(struct hdspm
*hdspm
, int idx
)
3699 int status2
, lock
, sync
;
3700 status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
3702 lock
= (status2
& (0x0080 >> idx
)) ? 1 : 0;
3703 sync
= (status2
& (0x8000 >> idx
)) ? 1 : 0;
3712 static int hdspm_tco_input_check(struct hdspm
*hdspm
, u32 mask
)
3715 status
= hdspm_read(hdspm
, HDSPM_RD_TCO
+ 4);
3717 return (status
& mask
) ? 1 : 0;
3721 static int hdspm_tco_sync_check(struct hdspm
*hdspm
)
3726 switch (hdspm
->io_type
) {
3729 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
3730 if (status
& HDSPM_tcoLock
) {
3731 if (status
& HDSPM_tcoSync
)
3742 status
= hdspm_read(hdspm
, HDSPM_RD_STATUS_1
);
3744 if (status
& 0x8000000)
3745 return 2; /* Sync */
3746 if (status
& 0x4000000)
3747 return 1; /* Lock */
3748 return 0; /* No signal */
3760 static int snd_hdspm_get_sync_check(struct snd_kcontrol
*kcontrol
,
3761 struct snd_ctl_elem_value
*ucontrol
)
3763 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3766 switch (hdspm
->io_type
) {
3768 switch (kcontrol
->private_value
) {
3770 val
= hdspm_wc_sync_check(hdspm
); break;
3772 val
= hdspm_tco_sync_check(hdspm
); break;
3773 case 8: /* SYNC IN */
3774 val
= hdspm_sync_in_sync_check(hdspm
); break;
3776 val
= hdspm_s1_sync_check(hdspm
,
3777 kcontrol
->private_value
-1);
3782 switch (kcontrol
->private_value
) {
3784 val
= hdspm_wc_sync_check(hdspm
); break;
3786 val
= hdspm_tco_sync_check(hdspm
); break;
3787 case 5: /* SYNC IN */
3788 val
= hdspm_sync_in_sync_check(hdspm
); break;
3790 val
= hdspm_s1_sync_check(hdspm
, ucontrol
->id
.index
-1);
3795 switch (kcontrol
->private_value
) {
3797 val
= hdspm_wc_sync_check(hdspm
); break;
3799 val
= hdspm_madi_sync_check(hdspm
); break;
3801 val
= hdspm_tco_sync_check(hdspm
); break;
3802 case 3: /* SYNC_IN */
3803 val
= hdspm_sync_in_sync_check(hdspm
); break;
3808 val
= hdspm_madi_sync_check(hdspm
); /* MADI */
3812 switch (kcontrol
->private_value
) {
3814 val
= hdspm_wc_sync_check(hdspm
); break;
3816 val
= hdspm_tco_sync_check(hdspm
); break;
3817 case 10 /* SYNC IN */:
3818 val
= hdspm_sync_in_sync_check(hdspm
); break;
3819 default: /* AES1 to AES8 */
3820 val
= hdspm_aes_sync_check(hdspm
,
3821 kcontrol
->private_value
-1);
3828 switch (kcontrol
->private_value
) {
3830 /* Check TCO for lock state of its current input */
3831 val
= hdspm_tco_input_check(hdspm
, HDSPM_TCO1_TCO_lock
);
3834 /* Check TCO for valid time code on LTC input. */
3835 val
= hdspm_tco_input_check(hdspm
,
3836 HDSPM_TCO1_LTC_Input_valid
);
3846 ucontrol
->value
.enumerated
.item
[0] = val
;
3855 static void hdspm_tco_write(struct hdspm
*hdspm
)
3857 unsigned int tc
[4] = { 0, 0, 0, 0};
3859 switch (hdspm
->tco
->input
) {
3861 tc
[2] |= HDSPM_TCO2_set_input_MSB
;
3864 tc
[2] |= HDSPM_TCO2_set_input_LSB
;
3870 switch (hdspm
->tco
->framerate
) {
3872 tc
[1] |= HDSPM_TCO1_LTC_Format_LSB
;
3875 tc
[1] |= HDSPM_TCO1_LTC_Format_MSB
;
3878 tc
[1] |= HDSPM_TCO1_LTC_Format_MSB
+
3879 HDSPM_TCO1_set_drop_frame_flag
;
3882 tc
[1] |= HDSPM_TCO1_LTC_Format_LSB
+
3883 HDSPM_TCO1_LTC_Format_MSB
;
3886 tc
[1] |= HDSPM_TCO1_LTC_Format_LSB
+
3887 HDSPM_TCO1_LTC_Format_MSB
+
3888 HDSPM_TCO1_set_drop_frame_flag
;
3894 switch (hdspm
->tco
->wordclock
) {
3896 tc
[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB
;
3899 tc
[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB
;
3905 switch (hdspm
->tco
->samplerate
) {
3907 tc
[2] |= HDSPM_TCO2_set_freq
;
3910 tc
[2] |= HDSPM_TCO2_set_freq_from_app
;
3916 switch (hdspm
->tco
->pull
) {
3918 tc
[2] |= HDSPM_TCO2_set_pull_up
;
3921 tc
[2] |= HDSPM_TCO2_set_pull_down
;
3924 tc
[2] |= HDSPM_TCO2_set_pull_up
+ HDSPM_TCO2_set_01_4
;
3927 tc
[2] |= HDSPM_TCO2_set_pull_down
+ HDSPM_TCO2_set_01_4
;
3933 if (1 == hdspm
->tco
->term
) {
3934 tc
[2] |= HDSPM_TCO2_set_term_75R
;
3937 hdspm_write(hdspm
, HDSPM_WR_TCO
, tc
[0]);
3938 hdspm_write(hdspm
, HDSPM_WR_TCO
+4, tc
[1]);
3939 hdspm_write(hdspm
, HDSPM_WR_TCO
+8, tc
[2]);
3940 hdspm_write(hdspm
, HDSPM_WR_TCO
+12, tc
[3]);
3944 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
3945 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3948 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3949 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3950 .info = snd_hdspm_info_tco_sample_rate, \
3951 .get = snd_hdspm_get_tco_sample_rate, \
3952 .put = snd_hdspm_put_tco_sample_rate \
3955 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol
*kcontrol
,
3956 struct snd_ctl_elem_info
*uinfo
)
3958 static char *texts
[] = { "44.1 kHz", "48 kHz" };
3959 ENUMERATED_CTL_INFO(uinfo
, texts
);
3963 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol
*kcontrol
,
3964 struct snd_ctl_elem_value
*ucontrol
)
3966 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3968 ucontrol
->value
.enumerated
.item
[0] = hdspm
->tco
->samplerate
;
3973 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol
*kcontrol
,
3974 struct snd_ctl_elem_value
*ucontrol
)
3976 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
3978 if (hdspm
->tco
->samplerate
!= ucontrol
->value
.enumerated
.item
[0]) {
3979 hdspm
->tco
->samplerate
= ucontrol
->value
.enumerated
.item
[0];
3981 hdspm_tco_write(hdspm
);
3990 #define HDSPM_TCO_PULL(xname, xindex) \
3991 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3994 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
3995 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3996 .info = snd_hdspm_info_tco_pull, \
3997 .get = snd_hdspm_get_tco_pull, \
3998 .put = snd_hdspm_put_tco_pull \
4001 static int snd_hdspm_info_tco_pull(struct snd_kcontrol
*kcontrol
,
4002 struct snd_ctl_elem_info
*uinfo
)
4004 static char *texts
[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" };
4005 ENUMERATED_CTL_INFO(uinfo
, texts
);
4009 static int snd_hdspm_get_tco_pull(struct snd_kcontrol
*kcontrol
,
4010 struct snd_ctl_elem_value
*ucontrol
)
4012 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4014 ucontrol
->value
.enumerated
.item
[0] = hdspm
->tco
->pull
;
4019 static int snd_hdspm_put_tco_pull(struct snd_kcontrol
*kcontrol
,
4020 struct snd_ctl_elem_value
*ucontrol
)
4022 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4024 if (hdspm
->tco
->pull
!= ucontrol
->value
.enumerated
.item
[0]) {
4025 hdspm
->tco
->pull
= ucontrol
->value
.enumerated
.item
[0];
4027 hdspm_tco_write(hdspm
);
4035 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4036 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4039 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4040 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4041 .info = snd_hdspm_info_tco_wck_conversion, \
4042 .get = snd_hdspm_get_tco_wck_conversion, \
4043 .put = snd_hdspm_put_tco_wck_conversion \
4046 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol
*kcontrol
,
4047 struct snd_ctl_elem_info
*uinfo
)
4049 static char *texts
[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4050 ENUMERATED_CTL_INFO(uinfo
, texts
);
4054 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol
*kcontrol
,
4055 struct snd_ctl_elem_value
*ucontrol
)
4057 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4059 ucontrol
->value
.enumerated
.item
[0] = hdspm
->tco
->wordclock
;
4064 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol
*kcontrol
,
4065 struct snd_ctl_elem_value
*ucontrol
)
4067 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4069 if (hdspm
->tco
->wordclock
!= ucontrol
->value
.enumerated
.item
[0]) {
4070 hdspm
->tco
->wordclock
= ucontrol
->value
.enumerated
.item
[0];
4072 hdspm_tco_write(hdspm
);
4081 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4082 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4085 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4086 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4087 .info = snd_hdspm_info_tco_frame_rate, \
4088 .get = snd_hdspm_get_tco_frame_rate, \
4089 .put = snd_hdspm_put_tco_frame_rate \
4092 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol
*kcontrol
,
4093 struct snd_ctl_elem_info
*uinfo
)
4095 static char *texts
[] = { "24 fps", "25 fps", "29.97fps",
4096 "29.97 dfps", "30 fps", "30 dfps" };
4097 ENUMERATED_CTL_INFO(uinfo
, texts
);
4101 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol
*kcontrol
,
4102 struct snd_ctl_elem_value
*ucontrol
)
4104 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4106 ucontrol
->value
.enumerated
.item
[0] = hdspm
->tco
->framerate
;
4111 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol
*kcontrol
,
4112 struct snd_ctl_elem_value
*ucontrol
)
4114 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4116 if (hdspm
->tco
->framerate
!= ucontrol
->value
.enumerated
.item
[0]) {
4117 hdspm
->tco
->framerate
= ucontrol
->value
.enumerated
.item
[0];
4119 hdspm_tco_write(hdspm
);
4128 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4129 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4132 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4133 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4134 .info = snd_hdspm_info_tco_sync_source, \
4135 .get = snd_hdspm_get_tco_sync_source, \
4136 .put = snd_hdspm_put_tco_sync_source \
4139 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol
*kcontrol
,
4140 struct snd_ctl_elem_info
*uinfo
)
4142 static char *texts
[] = { "LTC", "Video", "WCK" };
4143 ENUMERATED_CTL_INFO(uinfo
, texts
);
4147 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol
*kcontrol
,
4148 struct snd_ctl_elem_value
*ucontrol
)
4150 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4152 ucontrol
->value
.enumerated
.item
[0] = hdspm
->tco
->input
;
4157 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol
*kcontrol
,
4158 struct snd_ctl_elem_value
*ucontrol
)
4160 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4162 if (hdspm
->tco
->input
!= ucontrol
->value
.enumerated
.item
[0]) {
4163 hdspm
->tco
->input
= ucontrol
->value
.enumerated
.item
[0];
4165 hdspm_tco_write(hdspm
);
4174 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4175 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4178 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4179 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4180 .info = snd_hdspm_info_tco_word_term, \
4181 .get = snd_hdspm_get_tco_word_term, \
4182 .put = snd_hdspm_put_tco_word_term \
4185 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol
*kcontrol
,
4186 struct snd_ctl_elem_info
*uinfo
)
4188 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
4190 uinfo
->value
.integer
.min
= 0;
4191 uinfo
->value
.integer
.max
= 1;
4197 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol
*kcontrol
,
4198 struct snd_ctl_elem_value
*ucontrol
)
4200 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4202 ucontrol
->value
.enumerated
.item
[0] = hdspm
->tco
->term
;
4208 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol
*kcontrol
,
4209 struct snd_ctl_elem_value
*ucontrol
)
4211 struct hdspm
*hdspm
= snd_kcontrol_chip(kcontrol
);
4213 if (hdspm
->tco
->term
!= ucontrol
->value
.enumerated
.item
[0]) {
4214 hdspm
->tco
->term
= ucontrol
->value
.enumerated
.item
[0];
4216 hdspm_tco_write(hdspm
);
4227 static struct snd_kcontrol_new snd_hdspm_controls_madi
[] = {
4228 HDSPM_MIXER("Mixer", 0),
4229 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4230 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4231 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4232 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4233 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4234 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4235 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4236 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4237 HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4238 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4239 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut
),
4240 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch
),
4241 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX
),
4242 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms
),
4243 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp
),
4244 HDSPM_INPUT_SELECT("Input Select", 0),
4245 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4249 static struct snd_kcontrol_new snd_hdspm_controls_madiface
[] = {
4250 HDSPM_MIXER("Mixer", 0),
4251 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4252 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4253 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4254 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4255 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4256 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch
),
4257 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms
),
4258 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp
),
4259 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4262 static struct snd_kcontrol_new snd_hdspm_controls_aio
[] = {
4263 HDSPM_MIXER("Mixer", 0),
4264 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4265 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4266 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4267 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4268 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4269 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4270 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4271 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4272 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4273 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4274 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4275 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4276 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4277 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4278 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4279 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4280 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4281 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5)
4284 HDSPM_INPUT_SELECT("Input Select", 0),
4285 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4286 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4287 HDSPM_SPDIF_IN("SPDIF In", 0);
4288 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4289 HDSPM_INPUT_LEVEL("Input Level", 0);
4290 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4291 HDSPM_PHONES("Phones", 0);
4295 static struct snd_kcontrol_new snd_hdspm_controls_raydat
[] = {
4296 HDSPM_MIXER("Mixer", 0),
4297 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4298 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4299 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4300 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4301 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4302 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4303 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4304 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4305 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4306 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4307 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4308 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4309 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4310 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4311 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4312 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4313 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4314 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4315 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4316 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4317 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4318 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8)
4321 static struct snd_kcontrol_new snd_hdspm_controls_aes32
[] = {
4322 HDSPM_MIXER("Mixer", 0),
4323 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4324 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4325 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4326 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4327 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4328 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4329 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4330 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4331 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4332 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4333 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4334 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4335 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4336 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4337 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4338 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4339 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4340 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4341 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4342 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4343 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4344 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4345 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4346 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4347 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4348 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4349 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4350 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4351 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut
),
4352 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis
),
4353 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby
),
4354 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional
),
4355 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms
),
4356 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4357 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4362 /* Control elements for the optional TCO module */
4363 static struct snd_kcontrol_new snd_hdspm_controls_tco
[] = {
4364 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4365 HDSPM_TCO_PULL("TCO Pull", 0),
4366 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4367 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4368 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4369 HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4370 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4371 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4372 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4373 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4377 static struct snd_kcontrol_new snd_hdspm_playback_mixer
= HDSPM_PLAYBACK_MIXER
;
4380 static int hdspm_update_simple_mixer_controls(struct hdspm
* hdspm
)
4384 for (i
= hdspm
->ds_out_channels
; i
< hdspm
->ss_out_channels
; ++i
) {
4385 if (hdspm
->system_sample_rate
> 48000) {
4386 hdspm
->playback_mixer_ctls
[i
]->vd
[0].access
=
4387 SNDRV_CTL_ELEM_ACCESS_INACTIVE
|
4388 SNDRV_CTL_ELEM_ACCESS_READ
|
4389 SNDRV_CTL_ELEM_ACCESS_VOLATILE
;
4391 hdspm
->playback_mixer_ctls
[i
]->vd
[0].access
=
4392 SNDRV_CTL_ELEM_ACCESS_READWRITE
|
4393 SNDRV_CTL_ELEM_ACCESS_VOLATILE
;
4395 snd_ctl_notify(hdspm
->card
, SNDRV_CTL_EVENT_MASK_VALUE
|
4396 SNDRV_CTL_EVENT_MASK_INFO
,
4397 &hdspm
->playback_mixer_ctls
[i
]->id
);
4404 static int snd_hdspm_create_controls(struct snd_card
*card
,
4405 struct hdspm
*hdspm
)
4407 unsigned int idx
, limit
;
4409 struct snd_kcontrol
*kctl
;
4410 struct snd_kcontrol_new
*list
= NULL
;
4412 switch (hdspm
->io_type
) {
4414 list
= snd_hdspm_controls_madi
;
4415 limit
= ARRAY_SIZE(snd_hdspm_controls_madi
);
4418 list
= snd_hdspm_controls_madiface
;
4419 limit
= ARRAY_SIZE(snd_hdspm_controls_madiface
);
4422 list
= snd_hdspm_controls_aio
;
4423 limit
= ARRAY_SIZE(snd_hdspm_controls_aio
);
4426 list
= snd_hdspm_controls_raydat
;
4427 limit
= ARRAY_SIZE(snd_hdspm_controls_raydat
);
4430 list
= snd_hdspm_controls_aes32
;
4431 limit
= ARRAY_SIZE(snd_hdspm_controls_aes32
);
4436 for (idx
= 0; idx
< limit
; idx
++) {
4437 err
= snd_ctl_add(card
,
4438 snd_ctl_new1(&list
[idx
], hdspm
));
4445 /* create simple 1:1 playback mixer controls */
4446 snd_hdspm_playback_mixer
.name
= "Chn";
4447 if (hdspm
->system_sample_rate
>= 128000) {
4448 limit
= hdspm
->qs_out_channels
;
4449 } else if (hdspm
->system_sample_rate
>= 64000) {
4450 limit
= hdspm
->ds_out_channels
;
4452 limit
= hdspm
->ss_out_channels
;
4454 for (idx
= 0; idx
< limit
; ++idx
) {
4455 snd_hdspm_playback_mixer
.index
= idx
+ 1;
4456 kctl
= snd_ctl_new1(&snd_hdspm_playback_mixer
, hdspm
);
4457 err
= snd_ctl_add(card
, kctl
);
4460 hdspm
->playback_mixer_ctls
[idx
] = kctl
;
4465 /* add tco control elements */
4466 list
= snd_hdspm_controls_tco
;
4467 limit
= ARRAY_SIZE(snd_hdspm_controls_tco
);
4468 for (idx
= 0; idx
< limit
; idx
++) {
4469 err
= snd_ctl_add(card
,
4470 snd_ctl_new1(&list
[idx
], hdspm
));
4479 /*------------------------------------------------------------
4481 ------------------------------------------------------------*/
4484 snd_hdspm_proc_read_madi(struct snd_info_entry
* entry
,
4485 struct snd_info_buffer
*buffer
)
4487 struct hdspm
*hdspm
= entry
->private_data
;
4488 unsigned int status
, status2
, control
, freq
;
4490 char *pref_sync_ref
;
4492 char *system_clock_mode
;
4497 int a
, ltc
, frames
, seconds
, minutes
, hours
;
4498 unsigned int period
;
4502 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
4503 status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
4504 control
= hdspm
->control_register
;
4505 freq
= hdspm_read(hdspm
, HDSPM_timecodeRegister
);
4507 snd_iprintf(buffer
, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4508 hdspm
->card_name
, hdspm
->card
->number
+ 1,
4509 hdspm
->firmware_rev
,
4510 (status2
& HDSPM_version0
) |
4511 (status2
& HDSPM_version1
) | (status2
&
4514 snd_iprintf(buffer
, "HW Serial: 0x%06x%06x\n",
4515 (hdspm_read(hdspm
, HDSPM_midiStatusIn1
)>>8) & 0xFFFFFF,
4518 snd_iprintf(buffer
, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4519 hdspm
->irq
, hdspm
->port
, (unsigned long)hdspm
->iobase
);
4521 snd_iprintf(buffer
, "--- System ---\n");
4524 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4525 status
& HDSPM_audioIRQPending
,
4526 (status
& HDSPM_midi0IRQPending
) ? 1 : 0,
4527 (status
& HDSPM_midi1IRQPending
) ? 1 : 0,
4530 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4531 "estimated= %ld (bytes)\n",
4532 ((status
& HDSPM_BufferID
) ? 1 : 0),
4533 (status
& HDSPM_BufferPositionMask
),
4534 (status
& HDSPM_BufferPositionMask
) %
4535 (2 * (int)hdspm
->period_bytes
),
4536 ((status
& HDSPM_BufferPositionMask
) - 64) %
4537 (2 * (int)hdspm
->period_bytes
),
4538 (long) hdspm_hw_pointer(hdspm
) * 4);
4541 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4542 hdspm_read(hdspm
, HDSPM_midiStatusOut0
) & 0xFF,
4543 hdspm_read(hdspm
, HDSPM_midiStatusOut1
) & 0xFF,
4544 hdspm_read(hdspm
, HDSPM_midiStatusIn0
) & 0xFF,
4545 hdspm_read(hdspm
, HDSPM_midiStatusIn1
) & 0xFF);
4547 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4548 hdspm_read(hdspm
, HDSPM_midiStatusIn2
) & 0xFF,
4549 hdspm_read(hdspm
, HDSPM_midiStatusOut2
) & 0xFF);
4551 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4553 hdspm
->control_register
, hdspm
->control2_register
,
4555 if (status
& HDSPM_tco_detect
) {
4556 snd_iprintf(buffer
, "TCO module detected.\n");
4557 a
= hdspm_read(hdspm
, HDSPM_RD_TCO
+4);
4558 if (a
& HDSPM_TCO1_LTC_Input_valid
) {
4559 snd_iprintf(buffer
, " LTC valid, ");
4560 switch (a
& (HDSPM_TCO1_LTC_Format_LSB
|
4561 HDSPM_TCO1_LTC_Format_MSB
)) {
4563 snd_iprintf(buffer
, "24 fps, ");
4565 case HDSPM_TCO1_LTC_Format_LSB
:
4566 snd_iprintf(buffer
, "25 fps, ");
4568 case HDSPM_TCO1_LTC_Format_MSB
:
4569 snd_iprintf(buffer
, "29.97 fps, ");
4572 snd_iprintf(buffer
, "30 fps, ");
4575 if (a
& HDSPM_TCO1_set_drop_frame_flag
) {
4576 snd_iprintf(buffer
, "drop frame\n");
4578 snd_iprintf(buffer
, "full frame\n");
4581 snd_iprintf(buffer
, " no LTC\n");
4583 if (a
& HDSPM_TCO1_Video_Input_Format_NTSC
) {
4584 snd_iprintf(buffer
, " Video: NTSC\n");
4585 } else if (a
& HDSPM_TCO1_Video_Input_Format_PAL
) {
4586 snd_iprintf(buffer
, " Video: PAL\n");
4588 snd_iprintf(buffer
, " No video\n");
4590 if (a
& HDSPM_TCO1_TCO_lock
) {
4591 snd_iprintf(buffer
, " Sync: lock\n");
4593 snd_iprintf(buffer
, " Sync: no lock\n");
4596 switch (hdspm
->io_type
) {
4599 freq_const
= 110069313433624ULL;
4603 freq_const
= 104857600000000ULL;
4606 break; /* no TCO possible */
4609 period
= hdspm_read(hdspm
, HDSPM_RD_PLL_FREQ
);
4610 snd_iprintf(buffer
, " period: %u\n", period
);
4613 /* rate = freq_const/period; */
4614 rate
= div_u64(freq_const
, period
);
4616 if (control
& HDSPM_QuadSpeed
) {
4618 } else if (control
& HDSPM_DoubleSpeed
) {
4622 snd_iprintf(buffer
, " Frequency: %u Hz\n",
4623 (unsigned int) rate
);
4625 ltc
= hdspm_read(hdspm
, HDSPM_RD_TCO
);
4628 frames
+= (ltc
& 0x3) * 10;
4630 seconds
= ltc
& 0xF;
4632 seconds
+= (ltc
& 0x7) * 10;
4634 minutes
= ltc
& 0xF;
4636 minutes
+= (ltc
& 0x7) * 10;
4640 hours
+= (ltc
& 0x3) * 10;
4642 " LTC In: %02d:%02d:%02d:%02d\n",
4643 hours
, minutes
, seconds
, frames
);
4646 snd_iprintf(buffer
, "No TCO module detected.\n");
4649 snd_iprintf(buffer
, "--- Settings ---\n");
4651 x
= hdspm_get_latency(hdspm
);
4654 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4655 x
, (unsigned long) hdspm
->period_bytes
);
4657 snd_iprintf(buffer
, "Line out: %s\n",
4658 (hdspm
->control_register
& HDSPM_LineOut
) ? "on " : "off");
4660 switch (hdspm
->control_register
& HDSPM_InputMask
) {
4661 case HDSPM_InputOptical
:
4664 case HDSPM_InputCoaxial
:
4672 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4674 (hdspm
->control_register
& HDSPM_clr_tms
) ? "on" : "off",
4675 (hdspm
->control_register
& HDSPM_TX_64ch
) ? "64" : "56",
4676 (hdspm
->control_register
& HDSPM_AutoInp
) ? "on" : "off");
4679 if (!(hdspm
->control_register
& HDSPM_ClockModeMaster
))
4680 system_clock_mode
= "AutoSync";
4682 system_clock_mode
= "Master";
4683 snd_iprintf(buffer
, "AutoSync Reference: %s\n", system_clock_mode
);
4685 switch (hdspm_pref_sync_ref(hdspm
)) {
4686 case HDSPM_SYNC_FROM_WORD
:
4687 pref_sync_ref
= "Word Clock";
4689 case HDSPM_SYNC_FROM_MADI
:
4690 pref_sync_ref
= "MADI Sync";
4692 case HDSPM_SYNC_FROM_TCO
:
4693 pref_sync_ref
= "TCO";
4695 case HDSPM_SYNC_FROM_SYNC_IN
:
4696 pref_sync_ref
= "Sync In";
4699 pref_sync_ref
= "XXXX Clock";
4702 snd_iprintf(buffer
, "Preferred Sync Reference: %s\n",
4705 snd_iprintf(buffer
, "System Clock Frequency: %d\n",
4706 hdspm
->system_sample_rate
);
4709 snd_iprintf(buffer
, "--- Status:\n");
4711 x
= status
& HDSPM_madiSync
;
4712 x2
= status2
& HDSPM_wcSync
;
4714 snd_iprintf(buffer
, "Inputs MADI=%s, WordClock=%s\n",
4715 (status
& HDSPM_madiLock
) ? (x
? "Sync" : "Lock") :
4717 (status2
& HDSPM_wcLock
) ? (x2
? "Sync" : "Lock") :
4720 switch (hdspm_autosync_ref(hdspm
)) {
4721 case HDSPM_AUTOSYNC_FROM_SYNC_IN
:
4722 autosync_ref
= "Sync In";
4724 case HDSPM_AUTOSYNC_FROM_TCO
:
4725 autosync_ref
= "TCO";
4727 case HDSPM_AUTOSYNC_FROM_WORD
:
4728 autosync_ref
= "Word Clock";
4730 case HDSPM_AUTOSYNC_FROM_MADI
:
4731 autosync_ref
= "MADI Sync";
4733 case HDSPM_AUTOSYNC_FROM_NONE
:
4734 autosync_ref
= "Input not valid";
4737 autosync_ref
= "---";
4741 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
4742 autosync_ref
, hdspm_external_sample_rate(hdspm
),
4743 (status
& HDSPM_madiFreqMask
) >> 22,
4744 (status2
& HDSPM_wcFreqMask
) >> 5);
4746 snd_iprintf(buffer
, "Input: %s, Mode=%s\n",
4747 (status
& HDSPM_AB_int
) ? "Coax" : "Optical",
4748 (status
& HDSPM_RX_64ch
) ? "64 channels" :
4751 snd_iprintf(buffer
, "\n");
4755 snd_hdspm_proc_read_aes32(struct snd_info_entry
* entry
,
4756 struct snd_info_buffer
*buffer
)
4758 struct hdspm
*hdspm
= entry
->private_data
;
4759 unsigned int status
;
4760 unsigned int status2
;
4761 unsigned int timecode
;
4762 unsigned int wcLock
, wcSync
;
4767 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
4768 status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
4769 timecode
= hdspm_read(hdspm
, HDSPM_timecodeRegister
);
4771 snd_iprintf(buffer
, "%s (Card #%d) Rev.%x\n",
4772 hdspm
->card_name
, hdspm
->card
->number
+ 1,
4773 hdspm
->firmware_rev
);
4775 snd_iprintf(buffer
, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4776 hdspm
->irq
, hdspm
->port
, (unsigned long)hdspm
->iobase
);
4778 snd_iprintf(buffer
, "--- System ---\n");
4781 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4782 status
& HDSPM_audioIRQPending
,
4783 (status
& HDSPM_midi0IRQPending
) ? 1 : 0,
4784 (status
& HDSPM_midi1IRQPending
) ? 1 : 0,
4787 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4788 "estimated= %ld (bytes)\n",
4789 ((status
& HDSPM_BufferID
) ? 1 : 0),
4790 (status
& HDSPM_BufferPositionMask
),
4791 (status
& HDSPM_BufferPositionMask
) %
4792 (2 * (int)hdspm
->period_bytes
),
4793 ((status
& HDSPM_BufferPositionMask
) - 64) %
4794 (2 * (int)hdspm
->period_bytes
),
4795 (long) hdspm_hw_pointer(hdspm
) * 4);
4798 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4799 hdspm_read(hdspm
, HDSPM_midiStatusOut0
) & 0xFF,
4800 hdspm_read(hdspm
, HDSPM_midiStatusOut1
) & 0xFF,
4801 hdspm_read(hdspm
, HDSPM_midiStatusIn0
) & 0xFF,
4802 hdspm_read(hdspm
, HDSPM_midiStatusIn1
) & 0xFF);
4804 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4805 hdspm_read(hdspm
, HDSPM_midiStatusIn2
) & 0xFF,
4806 hdspm_read(hdspm
, HDSPM_midiStatusOut2
) & 0xFF);
4808 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4810 hdspm
->control_register
, hdspm
->control2_register
,
4813 snd_iprintf(buffer
, "--- Settings ---\n");
4815 x
= hdspm_get_latency(hdspm
);
4818 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4819 x
, (unsigned long) hdspm
->period_bytes
);
4821 snd_iprintf(buffer
, "Line out: %s\n",
4823 control_register
& HDSPM_LineOut
) ? "on " : "off");
4826 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
4828 control_register
& HDSPM_clr_tms
) ? "on" : "off",
4830 control_register
& HDSPM_Emphasis
) ? "on" : "off",
4832 control_register
& HDSPM_Dolby
) ? "on" : "off");
4835 pref_syncref
= hdspm_pref_sync_ref(hdspm
);
4836 if (pref_syncref
== 0)
4837 snd_iprintf(buffer
, "Preferred Sync Reference: Word Clock\n");
4839 snd_iprintf(buffer
, "Preferred Sync Reference: AES%d\n",
4842 snd_iprintf(buffer
, "System Clock Frequency: %d\n",
4843 hdspm
->system_sample_rate
);
4845 snd_iprintf(buffer
, "Double speed: %s\n",
4846 hdspm
->control_register
& HDSPM_DS_DoubleWire
?
4847 "Double wire" : "Single wire");
4848 snd_iprintf(buffer
, "Quad speed: %s\n",
4849 hdspm
->control_register
& HDSPM_QS_DoubleWire
?
4851 hdspm
->control_register
& HDSPM_QS_QuadWire
?
4852 "Quad wire" : "Single wire");
4854 snd_iprintf(buffer
, "--- Status:\n");
4856 wcLock
= status
& HDSPM_AES32_wcLock
;
4857 wcSync
= wcLock
&& (status
& HDSPM_AES32_wcSync
);
4859 snd_iprintf(buffer
, "Word: %s Frequency: %d\n",
4860 (wcLock
) ? (wcSync
? "Sync " : "Lock ") : "No Lock",
4861 HDSPM_bit2freq((status
>> HDSPM_AES32_wcFreq_bit
) & 0xF));
4863 for (x
= 0; x
< 8; x
++) {
4864 snd_iprintf(buffer
, "AES%d: %s Frequency: %d\n",
4866 (status2
& (HDSPM_LockAES
>> x
)) ?
4867 "Sync " : "No Lock",
4868 HDSPM_bit2freq((timecode
>> (4*x
)) & 0xF));
4871 switch (hdspm_autosync_ref(hdspm
)) {
4872 case HDSPM_AES32_AUTOSYNC_FROM_NONE
:
4873 autosync_ref
= "None"; break;
4874 case HDSPM_AES32_AUTOSYNC_FROM_WORD
:
4875 autosync_ref
= "Word Clock"; break;
4876 case HDSPM_AES32_AUTOSYNC_FROM_AES1
:
4877 autosync_ref
= "AES1"; break;
4878 case HDSPM_AES32_AUTOSYNC_FROM_AES2
:
4879 autosync_ref
= "AES2"; break;
4880 case HDSPM_AES32_AUTOSYNC_FROM_AES3
:
4881 autosync_ref
= "AES3"; break;
4882 case HDSPM_AES32_AUTOSYNC_FROM_AES4
:
4883 autosync_ref
= "AES4"; break;
4884 case HDSPM_AES32_AUTOSYNC_FROM_AES5
:
4885 autosync_ref
= "AES5"; break;
4886 case HDSPM_AES32_AUTOSYNC_FROM_AES6
:
4887 autosync_ref
= "AES6"; break;
4888 case HDSPM_AES32_AUTOSYNC_FROM_AES7
:
4889 autosync_ref
= "AES7"; break;
4890 case HDSPM_AES32_AUTOSYNC_FROM_AES8
:
4891 autosync_ref
= "AES8"; break;
4893 autosync_ref
= "---"; break;
4895 snd_iprintf(buffer
, "AutoSync ref = %s\n", autosync_ref
);
4897 snd_iprintf(buffer
, "\n");
4901 snd_hdspm_proc_read_raydat(struct snd_info_entry
*entry
,
4902 struct snd_info_buffer
*buffer
)
4904 struct hdspm
*hdspm
= entry
->private_data
;
4905 unsigned int status1
, status2
, status3
, control
, i
;
4906 unsigned int lock
, sync
;
4908 status1
= hdspm_read(hdspm
, HDSPM_RD_STATUS_1
); /* s1 */
4909 status2
= hdspm_read(hdspm
, HDSPM_RD_STATUS_2
); /* freq */
4910 status3
= hdspm_read(hdspm
, HDSPM_RD_STATUS_3
); /* s2 */
4912 control
= hdspm
->control_register
;
4914 snd_iprintf(buffer
, "STATUS1: 0x%08x\n", status1
);
4915 snd_iprintf(buffer
, "STATUS2: 0x%08x\n", status2
);
4916 snd_iprintf(buffer
, "STATUS3: 0x%08x\n", status3
);
4919 snd_iprintf(buffer
, "\n*** CLOCK MODE\n\n");
4921 snd_iprintf(buffer
, "Clock mode : %s\n",
4922 (hdspm_system_clock_mode(hdspm
) == 0) ? "master" : "slave");
4923 snd_iprintf(buffer
, "System frequency: %d Hz\n",
4924 hdspm_get_system_sample_rate(hdspm
));
4926 snd_iprintf(buffer
, "\n*** INPUT STATUS\n\n");
4931 for (i
= 0; i
< 8; i
++) {
4932 snd_iprintf(buffer
, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
4934 (status1
& lock
) ? 1 : 0,
4935 (status1
& sync
) ? 1 : 0,
4936 texts_freq
[(status2
>> (i
* 4)) & 0xF]);
4942 snd_iprintf(buffer
, "WC input: Lock %d, Sync %d, Freq %s\n",
4943 (status1
& 0x1000000) ? 1 : 0,
4944 (status1
& 0x2000000) ? 1 : 0,
4945 texts_freq
[(status1
>> 16) & 0xF]);
4947 snd_iprintf(buffer
, "TCO input: Lock %d, Sync %d, Freq %s\n",
4948 (status1
& 0x4000000) ? 1 : 0,
4949 (status1
& 0x8000000) ? 1 : 0,
4950 texts_freq
[(status1
>> 20) & 0xF]);
4952 snd_iprintf(buffer
, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
4953 (status3
& 0x400) ? 1 : 0,
4954 (status3
& 0x800) ? 1 : 0,
4955 texts_freq
[(status2
>> 12) & 0xF]);
4959 #ifdef CONFIG_SND_DEBUG
4961 snd_hdspm_proc_read_debug(struct snd_info_entry
*entry
,
4962 struct snd_info_buffer
*buffer
)
4964 struct hdspm
*hdspm
= entry
->private_data
;
4968 for (i
= 0; i
< 256 /* 1024*64 */; i
+= j
) {
4969 snd_iprintf(buffer
, "0x%08X: ", i
);
4970 for (j
= 0; j
< 16; j
+= 4)
4971 snd_iprintf(buffer
, "%08X ", hdspm_read(hdspm
, i
+ j
));
4972 snd_iprintf(buffer
, "\n");
4978 static void snd_hdspm_proc_ports_in(struct snd_info_entry
*entry
,
4979 struct snd_info_buffer
*buffer
)
4981 struct hdspm
*hdspm
= entry
->private_data
;
4984 snd_iprintf(buffer
, "# generated by hdspm\n");
4986 for (i
= 0; i
< hdspm
->max_channels_in
; i
++) {
4987 snd_iprintf(buffer
, "%d=%s\n", i
+1, hdspm
->port_names_in
[i
]);
4991 static void snd_hdspm_proc_ports_out(struct snd_info_entry
*entry
,
4992 struct snd_info_buffer
*buffer
)
4994 struct hdspm
*hdspm
= entry
->private_data
;
4997 snd_iprintf(buffer
, "# generated by hdspm\n");
4999 for (i
= 0; i
< hdspm
->max_channels_out
; i
++) {
5000 snd_iprintf(buffer
, "%d=%s\n", i
+1, hdspm
->port_names_out
[i
]);
5005 static void snd_hdspm_proc_init(struct hdspm
*hdspm
)
5007 struct snd_info_entry
*entry
;
5009 if (!snd_card_proc_new(hdspm
->card
, "hdspm", &entry
)) {
5010 switch (hdspm
->io_type
) {
5012 snd_info_set_text_ops(entry
, hdspm
,
5013 snd_hdspm_proc_read_aes32
);
5016 snd_info_set_text_ops(entry
, hdspm
,
5017 snd_hdspm_proc_read_madi
);
5020 /* snd_info_set_text_ops(entry, hdspm,
5021 snd_hdspm_proc_read_madiface); */
5024 snd_info_set_text_ops(entry
, hdspm
,
5025 snd_hdspm_proc_read_raydat
);
5032 if (!snd_card_proc_new(hdspm
->card
, "ports.in", &entry
)) {
5033 snd_info_set_text_ops(entry
, hdspm
, snd_hdspm_proc_ports_in
);
5036 if (!snd_card_proc_new(hdspm
->card
, "ports.out", &entry
)) {
5037 snd_info_set_text_ops(entry
, hdspm
, snd_hdspm_proc_ports_out
);
5040 #ifdef CONFIG_SND_DEBUG
5041 /* debug file to read all hdspm registers */
5042 if (!snd_card_proc_new(hdspm
->card
, "debug", &entry
))
5043 snd_info_set_text_ops(entry
, hdspm
,
5044 snd_hdspm_proc_read_debug
);
5048 /*------------------------------------------------------------
5050 ------------------------------------------------------------*/
5052 static int snd_hdspm_set_defaults(struct hdspm
* hdspm
)
5054 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5055 hold it (e.g. during module initialization).
5060 hdspm
->settings_register
= 0;
5062 switch (hdspm
->io_type
) {
5065 hdspm
->control_register
=
5066 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5071 hdspm
->settings_register
= 0x1 + 0x1000;
5072 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5074 hdspm
->control_register
=
5075 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5079 hdspm
->control_register
=
5080 HDSPM_ClockModeMaster
| /* Master Cloack Mode on */
5081 hdspm_encode_latency(7) | /* latency max=8192samples */
5082 HDSPM_SyncRef0
| /* AES1 is syncclock */
5083 HDSPM_LineOut
| /* Analog output in */
5084 HDSPM_Professional
; /* Professional mode */
5088 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
5090 if (AES32
== hdspm
->io_type
) {
5091 /* No control2 register for AES32 */
5092 #ifdef SNDRV_BIG_ENDIAN
5093 hdspm
->control2_register
= HDSPM_BIGENDIAN_MODE
;
5095 hdspm
->control2_register
= 0;
5098 hdspm_write(hdspm
, HDSPM_control2Reg
, hdspm
->control2_register
);
5100 hdspm_compute_period_size(hdspm
);
5102 /* silence everything */
5104 all_in_all_mixer(hdspm
, 0 * UNITY_GAIN
);
5106 if (hdspm
->io_type
== AIO
|| hdspm
->io_type
== RayDAT
) {
5107 hdspm_write(hdspm
, HDSPM_WR_SETTINGS
, hdspm
->settings_register
);
5110 /* set a default rate so that the channel map is set up. */
5111 hdspm_set_rate(hdspm
, 48000, 1);
5117 /*------------------------------------------------------------
5119 ------------------------------------------------------------*/
5121 static irqreturn_t
snd_hdspm_interrupt(int irq
, void *dev_id
)
5123 struct hdspm
*hdspm
= (struct hdspm
*) dev_id
;
5124 unsigned int status
;
5125 int i
, audio
, midi
, schedule
= 0;
5128 status
= hdspm_read(hdspm
, HDSPM_statusRegister
);
5130 audio
= status
& HDSPM_audioIRQPending
;
5131 midi
= status
& (HDSPM_midi0IRQPending
| HDSPM_midi1IRQPending
|
5132 HDSPM_midi2IRQPending
| HDSPM_midi3IRQPending
);
5134 /* now = get_cycles(); */
5136 * LAT_2..LAT_0 period counter (win) counter (mac)
5137 * 6 4096 ~256053425 ~514672358
5138 * 5 2048 ~128024983 ~257373821
5139 * 4 1024 ~64023706 ~128718089
5140 * 3 512 ~32005945 ~64385999
5141 * 2 256 ~16003039 ~32260176
5142 * 1 128 ~7998738 ~16194507
5143 * 0 64 ~3998231 ~8191558
5146 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n",
5147 now-hdspm->last_interrupt, status & 0xFFC0);
5148 hdspm->last_interrupt = now;
5151 if (!audio
&& !midi
)
5154 hdspm_write(hdspm
, HDSPM_interruptConfirmation
, 0);
5159 if (hdspm
->capture_substream
)
5160 snd_pcm_period_elapsed(hdspm
->capture_substream
);
5162 if (hdspm
->playback_substream
)
5163 snd_pcm_period_elapsed(hdspm
->playback_substream
);
5168 while (i
< hdspm
->midiPorts
) {
5169 if ((hdspm_read(hdspm
,
5170 hdspm
->midi
[i
].statusIn
) & 0xff) &&
5171 (status
& hdspm
->midi
[i
].irq
)) {
5172 /* we disable interrupts for this input until
5173 * processing is done
5175 hdspm
->control_register
&= ~hdspm
->midi
[i
].ie
;
5176 hdspm_write(hdspm
, HDSPM_controlRegister
,
5177 hdspm
->control_register
);
5178 hdspm
->midi
[i
].pending
= 1;
5186 tasklet_hi_schedule(&hdspm
->midi_tasklet
);
5192 /*------------------------------------------------------------
5194 ------------------------------------------------------------*/
5197 static snd_pcm_uframes_t
snd_hdspm_hw_pointer(struct snd_pcm_substream
5200 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5201 return hdspm_hw_pointer(hdspm
);
5205 static int snd_hdspm_reset(struct snd_pcm_substream
*substream
)
5207 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
5208 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5209 struct snd_pcm_substream
*other
;
5211 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
5212 other
= hdspm
->capture_substream
;
5214 other
= hdspm
->playback_substream
;
5217 runtime
->status
->hw_ptr
= hdspm_hw_pointer(hdspm
);
5219 runtime
->status
->hw_ptr
= 0;
5221 struct snd_pcm_substream
*s
;
5222 struct snd_pcm_runtime
*oruntime
= other
->runtime
;
5223 snd_pcm_group_for_each_entry(s
, substream
) {
5225 oruntime
->status
->hw_ptr
=
5226 runtime
->status
->hw_ptr
;
5234 static int snd_hdspm_hw_params(struct snd_pcm_substream
*substream
,
5235 struct snd_pcm_hw_params
*params
)
5237 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5243 spin_lock_irq(&hdspm
->lock
);
5245 if (substream
->pstr
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
5246 this_pid
= hdspm
->playback_pid
;
5247 other_pid
= hdspm
->capture_pid
;
5249 this_pid
= hdspm
->capture_pid
;
5250 other_pid
= hdspm
->playback_pid
;
5253 if (other_pid
> 0 && this_pid
!= other_pid
) {
5255 /* The other stream is open, and not by the same
5256 task as this one. Make sure that the parameters
5257 that matter are the same.
5260 if (params_rate(params
) != hdspm
->system_sample_rate
) {
5261 spin_unlock_irq(&hdspm
->lock
);
5262 _snd_pcm_hw_param_setempty(params
,
5263 SNDRV_PCM_HW_PARAM_RATE
);
5267 if (params_period_size(params
) != hdspm
->period_bytes
/ 4) {
5268 spin_unlock_irq(&hdspm
->lock
);
5269 _snd_pcm_hw_param_setempty(params
,
5270 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
);
5276 spin_unlock_irq(&hdspm
->lock
);
5278 /* how to make sure that the rate matches an externally-set one ? */
5280 spin_lock_irq(&hdspm
->lock
);
5281 err
= hdspm_set_rate(hdspm
, params_rate(params
), 0);
5283 snd_printk(KERN_INFO
"err on hdspm_set_rate: %d\n", err
);
5284 spin_unlock_irq(&hdspm
->lock
);
5285 _snd_pcm_hw_param_setempty(params
,
5286 SNDRV_PCM_HW_PARAM_RATE
);
5289 spin_unlock_irq(&hdspm
->lock
);
5291 err
= hdspm_set_interrupt_interval(hdspm
,
5292 params_period_size(params
));
5294 snd_printk(KERN_INFO
"err on hdspm_set_interrupt_interval: %d\n", err
);
5295 _snd_pcm_hw_param_setempty(params
,
5296 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
);
5300 /* Memory allocation, takashi's method, dont know if we should
5303 /* malloc all buffer even if not enabled to get sure */
5304 /* Update for MADI rev 204: we need to allocate for all channels,
5305 * otherwise it doesn't work at 96kHz */
5308 snd_pcm_lib_malloc_pages(substream
, HDSPM_DMA_AREA_BYTES
);
5310 snd_printk(KERN_INFO
"err on snd_pcm_lib_malloc_pages: %d\n", err
);
5314 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
5316 hdspm_set_sgbuf(hdspm
, substream
, HDSPM_pageAddressBufferOut
,
5317 params_channels(params
));
5319 for (i
= 0; i
< params_channels(params
); ++i
)
5320 snd_hdspm_enable_out(hdspm
, i
, 1);
5322 hdspm
->playback_buffer
=
5323 (unsigned char *) substream
->runtime
->dma_area
;
5324 snd_printdd("Allocated sample buffer for playback at %p\n",
5325 hdspm
->playback_buffer
);
5327 hdspm_set_sgbuf(hdspm
, substream
, HDSPM_pageAddressBufferIn
,
5328 params_channels(params
));
5330 for (i
= 0; i
< params_channels(params
); ++i
)
5331 snd_hdspm_enable_in(hdspm
, i
, 1);
5333 hdspm
->capture_buffer
=
5334 (unsigned char *) substream
->runtime
->dma_area
;
5335 snd_printdd("Allocated sample buffer for capture at %p\n",
5336 hdspm
->capture_buffer
);
5340 snd_printdd("Allocated sample buffer for %s at 0x%08X\n",
5341 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5342 "playback" : "capture",
5343 snd_pcm_sgbuf_get_addr(substream, 0));
5346 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5347 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5348 "playback" : "capture",
5349 params_rate(params), params_channels(params),
5350 params_buffer_size(params));
5354 /* Switch to native float format if requested */
5355 if (SNDRV_PCM_FORMAT_FLOAT_LE
== params_format(params
)) {
5356 if (!(hdspm
->control_register
& HDSPe_FLOAT_FORMAT
))
5357 snd_printk(KERN_INFO
"hdspm: Switching to native 32bit LE float format.\n");
5359 hdspm
->control_register
|= HDSPe_FLOAT_FORMAT
;
5360 } else if (SNDRV_PCM_FORMAT_S32_LE
== params_format(params
)) {
5361 if (hdspm
->control_register
& HDSPe_FLOAT_FORMAT
)
5362 snd_printk(KERN_INFO
"hdspm: Switching to native 32bit LE integer format.\n");
5364 hdspm
->control_register
&= ~HDSPe_FLOAT_FORMAT
;
5366 hdspm_write(hdspm
, HDSPM_controlRegister
, hdspm
->control_register
);
5371 static int snd_hdspm_hw_free(struct snd_pcm_substream
*substream
)
5374 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5376 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
5378 /* params_channels(params) should be enough,
5379 but to get sure in case of error */
5380 for (i
= 0; i
< hdspm
->max_channels_out
; ++i
)
5381 snd_hdspm_enable_out(hdspm
, i
, 0);
5383 hdspm
->playback_buffer
= NULL
;
5385 for (i
= 0; i
< hdspm
->max_channels_in
; ++i
)
5386 snd_hdspm_enable_in(hdspm
, i
, 0);
5388 hdspm
->capture_buffer
= NULL
;
5392 snd_pcm_lib_free_pages(substream
);
5398 static int snd_hdspm_channel_info(struct snd_pcm_substream
*substream
,
5399 struct snd_pcm_channel_info
*info
)
5401 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5403 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
) {
5404 if (snd_BUG_ON(info
->channel
>= hdspm
->max_channels_out
)) {
5405 snd_printk(KERN_INFO
"snd_hdspm_channel_info: output channel out of range (%d)\n", info
->channel
);
5409 if (hdspm
->channel_map_out
[info
->channel
] < 0) {
5410 snd_printk(KERN_INFO
"snd_hdspm_channel_info: output channel %d mapped out\n", info
->channel
);
5414 info
->offset
= hdspm
->channel_map_out
[info
->channel
] *
5415 HDSPM_CHANNEL_BUFFER_BYTES
;
5417 if (snd_BUG_ON(info
->channel
>= hdspm
->max_channels_in
)) {
5418 snd_printk(KERN_INFO
"snd_hdspm_channel_info: input channel out of range (%d)\n", info
->channel
);
5422 if (hdspm
->channel_map_in
[info
->channel
] < 0) {
5423 snd_printk(KERN_INFO
"snd_hdspm_channel_info: input channel %d mapped out\n", info
->channel
);
5427 info
->offset
= hdspm
->channel_map_in
[info
->channel
] *
5428 HDSPM_CHANNEL_BUFFER_BYTES
;
5437 static int snd_hdspm_ioctl(struct snd_pcm_substream
*substream
,
5438 unsigned int cmd
, void *arg
)
5441 case SNDRV_PCM_IOCTL1_RESET
:
5442 return snd_hdspm_reset(substream
);
5444 case SNDRV_PCM_IOCTL1_CHANNEL_INFO
:
5446 struct snd_pcm_channel_info
*info
= arg
;
5447 return snd_hdspm_channel_info(substream
, info
);
5453 return snd_pcm_lib_ioctl(substream
, cmd
, arg
);
5456 static int snd_hdspm_trigger(struct snd_pcm_substream
*substream
, int cmd
)
5458 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5459 struct snd_pcm_substream
*other
;
5462 spin_lock(&hdspm
->lock
);
5463 running
= hdspm
->running
;
5465 case SNDRV_PCM_TRIGGER_START
:
5466 running
|= 1 << substream
->stream
;
5468 case SNDRV_PCM_TRIGGER_STOP
:
5469 running
&= ~(1 << substream
->stream
);
5473 spin_unlock(&hdspm
->lock
);
5476 if (substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
5477 other
= hdspm
->capture_substream
;
5479 other
= hdspm
->playback_substream
;
5482 struct snd_pcm_substream
*s
;
5483 snd_pcm_group_for_each_entry(s
, substream
) {
5485 snd_pcm_trigger_done(s
, substream
);
5486 if (cmd
== SNDRV_PCM_TRIGGER_START
)
5487 running
|= 1 << s
->stream
;
5489 running
&= ~(1 << s
->stream
);
5493 if (cmd
== SNDRV_PCM_TRIGGER_START
) {
5494 if (!(running
& (1 << SNDRV_PCM_STREAM_PLAYBACK
))
5495 && substream
->stream
==
5496 SNDRV_PCM_STREAM_CAPTURE
)
5497 hdspm_silence_playback(hdspm
);
5500 substream
->stream
== SNDRV_PCM_STREAM_PLAYBACK
)
5501 hdspm_silence_playback(hdspm
);
5504 if (substream
->stream
== SNDRV_PCM_STREAM_CAPTURE
)
5505 hdspm_silence_playback(hdspm
);
5508 snd_pcm_trigger_done(substream
, substream
);
5509 if (!hdspm
->running
&& running
)
5510 hdspm_start_audio(hdspm
);
5511 else if (hdspm
->running
&& !running
)
5512 hdspm_stop_audio(hdspm
);
5513 hdspm
->running
= running
;
5514 spin_unlock(&hdspm
->lock
);
5519 static int snd_hdspm_prepare(struct snd_pcm_substream
*substream
)
5524 static struct snd_pcm_hardware snd_hdspm_playback_subinfo
= {
5525 .info
= (SNDRV_PCM_INFO_MMAP
|
5526 SNDRV_PCM_INFO_MMAP_VALID
|
5527 SNDRV_PCM_INFO_NONINTERLEAVED
|
5528 SNDRV_PCM_INFO_SYNC_START
| SNDRV_PCM_INFO_DOUBLE
),
5529 .formats
= SNDRV_PCM_FMTBIT_S32_LE
,
5530 .rates
= (SNDRV_PCM_RATE_32000
|
5531 SNDRV_PCM_RATE_44100
|
5532 SNDRV_PCM_RATE_48000
|
5533 SNDRV_PCM_RATE_64000
|
5534 SNDRV_PCM_RATE_88200
| SNDRV_PCM_RATE_96000
|
5535 SNDRV_PCM_RATE_176400
| SNDRV_PCM_RATE_192000
),
5539 .channels_max
= HDSPM_MAX_CHANNELS
,
5541 HDSPM_CHANNEL_BUFFER_BYTES
* HDSPM_MAX_CHANNELS
,
5542 .period_bytes_min
= (32 * 4),
5543 .period_bytes_max
= (8192 * 4) * HDSPM_MAX_CHANNELS
,
5549 static struct snd_pcm_hardware snd_hdspm_capture_subinfo
= {
5550 .info
= (SNDRV_PCM_INFO_MMAP
|
5551 SNDRV_PCM_INFO_MMAP_VALID
|
5552 SNDRV_PCM_INFO_NONINTERLEAVED
|
5553 SNDRV_PCM_INFO_SYNC_START
),
5554 .formats
= SNDRV_PCM_FMTBIT_S32_LE
,
5555 .rates
= (SNDRV_PCM_RATE_32000
|
5556 SNDRV_PCM_RATE_44100
|
5557 SNDRV_PCM_RATE_48000
|
5558 SNDRV_PCM_RATE_64000
|
5559 SNDRV_PCM_RATE_88200
| SNDRV_PCM_RATE_96000
|
5560 SNDRV_PCM_RATE_176400
| SNDRV_PCM_RATE_192000
),
5564 .channels_max
= HDSPM_MAX_CHANNELS
,
5566 HDSPM_CHANNEL_BUFFER_BYTES
* HDSPM_MAX_CHANNELS
,
5567 .period_bytes_min
= (32 * 4),
5568 .period_bytes_max
= (8192 * 4) * HDSPM_MAX_CHANNELS
,
5574 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params
*params
,
5575 struct snd_pcm_hw_rule
*rule
)
5577 struct hdspm
*hdspm
= rule
->private;
5578 struct snd_interval
*c
=
5579 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
5580 struct snd_interval
*r
=
5581 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
5583 if (r
->min
> 96000 && r
->max
<= 192000) {
5584 struct snd_interval t
= {
5585 .min
= hdspm
->qs_in_channels
,
5586 .max
= hdspm
->qs_in_channels
,
5589 return snd_interval_refine(c
, &t
);
5590 } else if (r
->min
> 48000 && r
->max
<= 96000) {
5591 struct snd_interval t
= {
5592 .min
= hdspm
->ds_in_channels
,
5593 .max
= hdspm
->ds_in_channels
,
5596 return snd_interval_refine(c
, &t
);
5597 } else if (r
->max
< 64000) {
5598 struct snd_interval t
= {
5599 .min
= hdspm
->ss_in_channels
,
5600 .max
= hdspm
->ss_in_channels
,
5603 return snd_interval_refine(c
, &t
);
5609 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params
*params
,
5610 struct snd_pcm_hw_rule
* rule
)
5612 struct hdspm
*hdspm
= rule
->private;
5613 struct snd_interval
*c
=
5614 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
5615 struct snd_interval
*r
=
5616 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
5618 if (r
->min
> 96000 && r
->max
<= 192000) {
5619 struct snd_interval t
= {
5620 .min
= hdspm
->qs_out_channels
,
5621 .max
= hdspm
->qs_out_channels
,
5624 return snd_interval_refine(c
, &t
);
5625 } else if (r
->min
> 48000 && r
->max
<= 96000) {
5626 struct snd_interval t
= {
5627 .min
= hdspm
->ds_out_channels
,
5628 .max
= hdspm
->ds_out_channels
,
5631 return snd_interval_refine(c
, &t
);
5632 } else if (r
->max
< 64000) {
5633 struct snd_interval t
= {
5634 .min
= hdspm
->ss_out_channels
,
5635 .max
= hdspm
->ss_out_channels
,
5638 return snd_interval_refine(c
, &t
);
5644 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params
*params
,
5645 struct snd_pcm_hw_rule
* rule
)
5647 struct hdspm
*hdspm
= rule
->private;
5648 struct snd_interval
*c
=
5649 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
5650 struct snd_interval
*r
=
5651 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
5653 if (c
->min
>= hdspm
->ss_in_channels
) {
5654 struct snd_interval t
= {
5659 return snd_interval_refine(r
, &t
);
5660 } else if (c
->max
<= hdspm
->qs_in_channels
) {
5661 struct snd_interval t
= {
5666 return snd_interval_refine(r
, &t
);
5667 } else if (c
->max
<= hdspm
->ds_in_channels
) {
5668 struct snd_interval t
= {
5673 return snd_interval_refine(r
, &t
);
5678 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params
*params
,
5679 struct snd_pcm_hw_rule
*rule
)
5681 struct hdspm
*hdspm
= rule
->private;
5682 struct snd_interval
*c
=
5683 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_CHANNELS
);
5684 struct snd_interval
*r
=
5685 hw_param_interval(params
, SNDRV_PCM_HW_PARAM_RATE
);
5687 if (c
->min
>= hdspm
->ss_out_channels
) {
5688 struct snd_interval t
= {
5693 return snd_interval_refine(r
, &t
);
5694 } else if (c
->max
<= hdspm
->qs_out_channels
) {
5695 struct snd_interval t
= {
5700 return snd_interval_refine(r
, &t
);
5701 } else if (c
->max
<= hdspm
->ds_out_channels
) {
5702 struct snd_interval t
= {
5707 return snd_interval_refine(r
, &t
);
5713 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params
*params
,
5714 struct snd_pcm_hw_rule
*rule
)
5716 unsigned int list
[3];
5717 struct hdspm
*hdspm
= rule
->private;
5718 struct snd_interval
*c
= hw_param_interval(params
,
5719 SNDRV_PCM_HW_PARAM_CHANNELS
);
5721 list
[0] = hdspm
->qs_in_channels
;
5722 list
[1] = hdspm
->ds_in_channels
;
5723 list
[2] = hdspm
->ss_in_channels
;
5724 return snd_interval_list(c
, 3, list
, 0);
5727 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params
*params
,
5728 struct snd_pcm_hw_rule
*rule
)
5730 unsigned int list
[3];
5731 struct hdspm
*hdspm
= rule
->private;
5732 struct snd_interval
*c
= hw_param_interval(params
,
5733 SNDRV_PCM_HW_PARAM_CHANNELS
);
5735 list
[0] = hdspm
->qs_out_channels
;
5736 list
[1] = hdspm
->ds_out_channels
;
5737 list
[2] = hdspm
->ss_out_channels
;
5738 return snd_interval_list(c
, 3, list
, 0);
5742 static unsigned int hdspm_aes32_sample_rates
[] = {
5743 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
5746 static struct snd_pcm_hw_constraint_list
5747 hdspm_hw_constraints_aes32_sample_rates
= {
5748 .count
= ARRAY_SIZE(hdspm_aes32_sample_rates
),
5749 .list
= hdspm_aes32_sample_rates
,
5753 static int snd_hdspm_playback_open(struct snd_pcm_substream
*substream
)
5755 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5756 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
5758 spin_lock_irq(&hdspm
->lock
);
5760 snd_pcm_set_sync(substream
);
5763 runtime
->hw
= snd_hdspm_playback_subinfo
;
5765 if (hdspm
->capture_substream
== NULL
)
5766 hdspm_stop_audio(hdspm
);
5768 hdspm
->playback_pid
= current
->pid
;
5769 hdspm
->playback_substream
= substream
;
5771 spin_unlock_irq(&hdspm
->lock
);
5773 snd_pcm_hw_constraint_msbits(runtime
, 0, 32, 24);
5774 snd_pcm_hw_constraint_pow2(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE
);
5776 switch (hdspm
->io_type
) {
5779 snd_pcm_hw_constraint_minmax(runtime
,
5780 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
,
5782 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
5783 snd_pcm_hw_constraint_minmax(runtime
,
5784 SNDRV_PCM_HW_PARAM_BUFFER_SIZE
,
5789 snd_pcm_hw_constraint_minmax(runtime
,
5790 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
,
5795 if (AES32
== hdspm
->io_type
) {
5796 runtime
->hw
.rates
|= SNDRV_PCM_RATE_KNOT
;
5797 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
5798 &hdspm_hw_constraints_aes32_sample_rates
);
5800 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
5801 snd_hdspm_hw_rule_rate_out_channels
, hdspm
,
5802 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
5805 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
5806 snd_hdspm_hw_rule_out_channels
, hdspm
,
5807 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
5809 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
5810 snd_hdspm_hw_rule_out_channels_rate
, hdspm
,
5811 SNDRV_PCM_HW_PARAM_RATE
, -1);
5816 static int snd_hdspm_playback_release(struct snd_pcm_substream
*substream
)
5818 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5820 spin_lock_irq(&hdspm
->lock
);
5822 hdspm
->playback_pid
= -1;
5823 hdspm
->playback_substream
= NULL
;
5825 spin_unlock_irq(&hdspm
->lock
);
5831 static int snd_hdspm_capture_open(struct snd_pcm_substream
*substream
)
5833 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5834 struct snd_pcm_runtime
*runtime
= substream
->runtime
;
5836 spin_lock_irq(&hdspm
->lock
);
5837 snd_pcm_set_sync(substream
);
5838 runtime
->hw
= snd_hdspm_capture_subinfo
;
5840 if (hdspm
->playback_substream
== NULL
)
5841 hdspm_stop_audio(hdspm
);
5843 hdspm
->capture_pid
= current
->pid
;
5844 hdspm
->capture_substream
= substream
;
5846 spin_unlock_irq(&hdspm
->lock
);
5848 snd_pcm_hw_constraint_msbits(runtime
, 0, 32, 24);
5849 snd_pcm_hw_constraint_pow2(runtime
, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE
);
5851 switch (hdspm
->io_type
) {
5854 snd_pcm_hw_constraint_minmax(runtime
,
5855 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
,
5857 snd_pcm_hw_constraint_minmax(runtime
,
5858 SNDRV_PCM_HW_PARAM_BUFFER_SIZE
,
5863 snd_pcm_hw_constraint_minmax(runtime
,
5864 SNDRV_PCM_HW_PARAM_PERIOD_SIZE
,
5869 if (AES32
== hdspm
->io_type
) {
5870 runtime
->hw
.rates
|= SNDRV_PCM_RATE_KNOT
;
5871 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
5872 &hdspm_hw_constraints_aes32_sample_rates
);
5874 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_RATE
,
5875 snd_hdspm_hw_rule_rate_in_channels
, hdspm
,
5876 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
5879 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
5880 snd_hdspm_hw_rule_in_channels
, hdspm
,
5881 SNDRV_PCM_HW_PARAM_CHANNELS
, -1);
5883 snd_pcm_hw_rule_add(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
,
5884 snd_hdspm_hw_rule_in_channels_rate
, hdspm
,
5885 SNDRV_PCM_HW_PARAM_RATE
, -1);
5890 static int snd_hdspm_capture_release(struct snd_pcm_substream
*substream
)
5892 struct hdspm
*hdspm
= snd_pcm_substream_chip(substream
);
5894 spin_lock_irq(&hdspm
->lock
);
5896 hdspm
->capture_pid
= -1;
5897 hdspm
->capture_substream
= NULL
;
5899 spin_unlock_irq(&hdspm
->lock
);
5903 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep
*hw
, struct file
*file
)
5905 /* we have nothing to initialize but the call is required */
5909 static inline int copy_u32_le(void __user
*dest
, void __iomem
*src
)
5911 u32 val
= readl(src
);
5912 return copy_to_user(dest
, &val
, 4);
5915 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep
*hw
, struct file
*file
,
5916 unsigned int cmd
, unsigned long arg
)
5918 void __user
*argp
= (void __user
*)arg
;
5919 struct hdspm
*hdspm
= hw
->private_data
;
5920 struct hdspm_mixer_ioctl mixer
;
5921 struct hdspm_config info
;
5922 struct hdspm_status status
;
5923 struct hdspm_version hdspm_version
;
5924 struct hdspm_peak_rms
*levels
;
5925 struct hdspm_ltc ltc
;
5926 unsigned int statusregister
;
5927 long unsigned int s
;
5932 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS
:
5933 levels
= &hdspm
->peak_rms
;
5934 for (i
= 0; i
< HDSPM_MAX_CHANNELS
; i
++) {
5935 levels
->input_peaks
[i
] =
5936 readl(hdspm
->iobase
+
5937 HDSPM_MADI_INPUT_PEAK
+ i
*4);
5938 levels
->playback_peaks
[i
] =
5939 readl(hdspm
->iobase
+
5940 HDSPM_MADI_PLAYBACK_PEAK
+ i
*4);
5941 levels
->output_peaks
[i
] =
5942 readl(hdspm
->iobase
+
5943 HDSPM_MADI_OUTPUT_PEAK
+ i
*4);
5945 levels
->input_rms
[i
] =
5946 ((uint64_t) readl(hdspm
->iobase
+
5947 HDSPM_MADI_INPUT_RMS_H
+ i
*4) << 32) |
5948 (uint64_t) readl(hdspm
->iobase
+
5949 HDSPM_MADI_INPUT_RMS_L
+ i
*4);
5950 levels
->playback_rms
[i
] =
5951 ((uint64_t)readl(hdspm
->iobase
+
5952 HDSPM_MADI_PLAYBACK_RMS_H
+i
*4) << 32) |
5953 (uint64_t)readl(hdspm
->iobase
+
5954 HDSPM_MADI_PLAYBACK_RMS_L
+ i
*4);
5955 levels
->output_rms
[i
] =
5956 ((uint64_t)readl(hdspm
->iobase
+
5957 HDSPM_MADI_OUTPUT_RMS_H
+ i
*4) << 32) |
5958 (uint64_t)readl(hdspm
->iobase
+
5959 HDSPM_MADI_OUTPUT_RMS_L
+ i
*4);
5962 if (hdspm
->system_sample_rate
> 96000) {
5964 } else if (hdspm
->system_sample_rate
> 48000) {
5969 levels
->status2
= hdspm_read(hdspm
, HDSPM_statusRegister2
);
5971 s
= copy_to_user(argp
, levels
, sizeof(struct hdspm_peak_rms
));
5973 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu
5974 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
5980 case SNDRV_HDSPM_IOCTL_GET_LTC
:
5981 ltc
.ltc
= hdspm_read(hdspm
, HDSPM_RD_TCO
);
5982 i
= hdspm_read(hdspm
, HDSPM_RD_TCO
+ 4);
5983 if (i
& HDSPM_TCO1_LTC_Input_valid
) {
5984 switch (i
& (HDSPM_TCO1_LTC_Format_LSB
|
5985 HDSPM_TCO1_LTC_Format_MSB
)) {
5987 ltc
.format
= fps_24
;
5989 case HDSPM_TCO1_LTC_Format_LSB
:
5990 ltc
.format
= fps_25
;
5992 case HDSPM_TCO1_LTC_Format_MSB
:
5993 ltc
.format
= fps_2997
;
5999 if (i
& HDSPM_TCO1_set_drop_frame_flag
) {
6000 ltc
.frame
= drop_frame
;
6002 ltc
.frame
= full_frame
;
6005 ltc
.format
= format_invalid
;
6006 ltc
.frame
= frame_invalid
;
6008 if (i
& HDSPM_TCO1_Video_Input_Format_NTSC
) {
6009 ltc
.input_format
= ntsc
;
6010 } else if (i
& HDSPM_TCO1_Video_Input_Format_PAL
) {
6011 ltc
.input_format
= pal
;
6013 ltc
.input_format
= no_video
;
6016 s
= copy_to_user(argp
, <c
, sizeof(struct hdspm_ltc
));
6019 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6025 case SNDRV_HDSPM_IOCTL_GET_CONFIG
:
6027 memset(&info
, 0, sizeof(info
));
6028 spin_lock_irq(&hdspm
->lock
);
6029 info
.pref_sync_ref
= hdspm_pref_sync_ref(hdspm
);
6030 info
.wordclock_sync_check
= hdspm_wc_sync_check(hdspm
);
6032 info
.system_sample_rate
= hdspm
->system_sample_rate
;
6033 info
.autosync_sample_rate
=
6034 hdspm_external_sample_rate(hdspm
);
6035 info
.system_clock_mode
= hdspm_system_clock_mode(hdspm
);
6036 info
.clock_source
= hdspm_clock_source(hdspm
);
6037 info
.autosync_ref
= hdspm_autosync_ref(hdspm
);
6038 info
.line_out
= hdspm_toggle_setting(hdspm
, HDSPM_LineOut
);
6040 spin_unlock_irq(&hdspm
->lock
);
6041 if (copy_to_user(argp
, &info
, sizeof(info
)))
6045 case SNDRV_HDSPM_IOCTL_GET_STATUS
:
6046 memset(&status
, 0, sizeof(status
));
6048 status
.card_type
= hdspm
->io_type
;
6050 status
.autosync_source
= hdspm_autosync_ref(hdspm
);
6052 status
.card_clock
= 110069313433624ULL;
6053 status
.master_period
= hdspm_read(hdspm
, HDSPM_RD_PLL_FREQ
);
6055 switch (hdspm
->io_type
) {
6058 status
.card_specific
.madi
.sync_wc
=
6059 hdspm_wc_sync_check(hdspm
);
6060 status
.card_specific
.madi
.sync_madi
=
6061 hdspm_madi_sync_check(hdspm
);
6062 status
.card_specific
.madi
.sync_tco
=
6063 hdspm_tco_sync_check(hdspm
);
6064 status
.card_specific
.madi
.sync_in
=
6065 hdspm_sync_in_sync_check(hdspm
);
6068 hdspm_read(hdspm
, HDSPM_statusRegister
);
6069 status
.card_specific
.madi
.madi_input
=
6070 (statusregister
& HDSPM_AB_int
) ? 1 : 0;
6071 status
.card_specific
.madi
.channel_format
=
6072 (statusregister
& HDSPM_RX_64ch
) ? 1 : 0;
6073 /* TODO: Mac driver sets it when f_s>48kHz */
6074 status
.card_specific
.madi
.frame_format
= 0;
6080 if (copy_to_user(argp
, &status
, sizeof(status
)))
6086 case SNDRV_HDSPM_IOCTL_GET_VERSION
:
6087 memset(&hdspm_version
, 0, sizeof(hdspm_version
));
6089 hdspm_version
.card_type
= hdspm
->io_type
;
6090 strncpy(hdspm_version
.cardname
, hdspm
->card_name
,
6091 sizeof(hdspm_version
.cardname
));
6092 hdspm_version
.serial
= hdspm
->serial
;
6093 hdspm_version
.firmware_rev
= hdspm
->firmware_rev
;
6094 hdspm_version
.addons
= 0;
6096 hdspm_version
.addons
|= HDSPM_ADDON_TCO
;
6098 if (copy_to_user(argp
, &hdspm_version
,
6099 sizeof(hdspm_version
)))
6103 case SNDRV_HDSPM_IOCTL_GET_MIXER
:
6104 if (copy_from_user(&mixer
, argp
, sizeof(mixer
)))
6106 if (copy_to_user((void __user
*)mixer
.mixer
, hdspm
->mixer
,
6107 sizeof(struct hdspm_mixer
)))
6117 static struct snd_pcm_ops snd_hdspm_playback_ops
= {
6118 .open
= snd_hdspm_playback_open
,
6119 .close
= snd_hdspm_playback_release
,
6120 .ioctl
= snd_hdspm_ioctl
,
6121 .hw_params
= snd_hdspm_hw_params
,
6122 .hw_free
= snd_hdspm_hw_free
,
6123 .prepare
= snd_hdspm_prepare
,
6124 .trigger
= snd_hdspm_trigger
,
6125 .pointer
= snd_hdspm_hw_pointer
,
6126 .page
= snd_pcm_sgbuf_ops_page
,
6129 static struct snd_pcm_ops snd_hdspm_capture_ops
= {
6130 .open
= snd_hdspm_capture_open
,
6131 .close
= snd_hdspm_capture_release
,
6132 .ioctl
= snd_hdspm_ioctl
,
6133 .hw_params
= snd_hdspm_hw_params
,
6134 .hw_free
= snd_hdspm_hw_free
,
6135 .prepare
= snd_hdspm_prepare
,
6136 .trigger
= snd_hdspm_trigger
,
6137 .pointer
= snd_hdspm_hw_pointer
,
6138 .page
= snd_pcm_sgbuf_ops_page
,
6141 static int snd_hdspm_create_hwdep(struct snd_card
*card
,
6142 struct hdspm
*hdspm
)
6144 struct snd_hwdep
*hw
;
6147 err
= snd_hwdep_new(card
, "HDSPM hwdep", 0, &hw
);
6152 hw
->private_data
= hdspm
;
6153 strcpy(hw
->name
, "HDSPM hwdep interface");
6155 hw
->ops
.open
= snd_hdspm_hwdep_dummy_op
;
6156 hw
->ops
.ioctl
= snd_hdspm_hwdep_ioctl
;
6157 hw
->ops
.ioctl_compat
= snd_hdspm_hwdep_ioctl
;
6158 hw
->ops
.release
= snd_hdspm_hwdep_dummy_op
;
6164 /*------------------------------------------------------------
6166 ------------------------------------------------------------*/
6167 static int snd_hdspm_preallocate_memory(struct hdspm
*hdspm
)
6170 struct snd_pcm
*pcm
;
6175 wanted
= HDSPM_DMA_AREA_BYTES
;
6178 snd_pcm_lib_preallocate_pages_for_all(pcm
,
6179 SNDRV_DMA_TYPE_DEV_SG
,
6180 snd_dma_pci_data(hdspm
->pci
),
6184 snd_printdd("Could not preallocate %zd Bytes\n", wanted
);
6188 snd_printdd(" Preallocated %zd Bytes\n", wanted
);
6194 static void hdspm_set_sgbuf(struct hdspm
*hdspm
,
6195 struct snd_pcm_substream
*substream
,
6196 unsigned int reg
, int channels
)
6200 /* continuous memory segment */
6201 for (i
= 0; i
< (channels
* 16); i
++)
6202 hdspm_write(hdspm
, reg
+ 4 * i
,
6203 snd_pcm_sgbuf_get_addr(substream
, 4096 * i
));
6207 /* ------------- ALSA Devices ---------------------------- */
6208 static int snd_hdspm_create_pcm(struct snd_card
*card
,
6209 struct hdspm
*hdspm
)
6211 struct snd_pcm
*pcm
;
6214 err
= snd_pcm_new(card
, hdspm
->card_name
, 0, 1, 1, &pcm
);
6219 pcm
->private_data
= hdspm
;
6220 strcpy(pcm
->name
, hdspm
->card_name
);
6222 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
,
6223 &snd_hdspm_playback_ops
);
6224 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
,
6225 &snd_hdspm_capture_ops
);
6227 pcm
->info_flags
= SNDRV_PCM_INFO_JOINT_DUPLEX
;
6229 err
= snd_hdspm_preallocate_memory(hdspm
);
6236 static inline void snd_hdspm_initialize_midi_flush(struct hdspm
* hdspm
)
6240 for (i
= 0; i
< hdspm
->midiPorts
; i
++)
6241 snd_hdspm_flush_midi_input(hdspm
, i
);
6244 static int snd_hdspm_create_alsa_devices(struct snd_card
*card
,
6245 struct hdspm
*hdspm
)
6249 snd_printdd("Create card...\n");
6250 err
= snd_hdspm_create_pcm(card
, hdspm
);
6255 while (i
< hdspm
->midiPorts
) {
6256 err
= snd_hdspm_create_midi(card
, hdspm
, i
);
6263 err
= snd_hdspm_create_controls(card
, hdspm
);
6267 err
= snd_hdspm_create_hwdep(card
, hdspm
);
6271 snd_printdd("proc init...\n");
6272 snd_hdspm_proc_init(hdspm
);
6274 hdspm
->system_sample_rate
= -1;
6275 hdspm
->last_external_sample_rate
= -1;
6276 hdspm
->last_internal_sample_rate
= -1;
6277 hdspm
->playback_pid
= -1;
6278 hdspm
->capture_pid
= -1;
6279 hdspm
->capture_substream
= NULL
;
6280 hdspm
->playback_substream
= NULL
;
6282 snd_printdd("Set defaults...\n");
6283 err
= snd_hdspm_set_defaults(hdspm
);
6287 snd_printdd("Update mixer controls...\n");
6288 hdspm_update_simple_mixer_controls(hdspm
);
6290 snd_printdd("Initializeing complete ???\n");
6292 err
= snd_card_register(card
);
6294 snd_printk(KERN_ERR
"HDSPM: error registering card\n");
6298 snd_printdd("... yes now\n");
6303 static int snd_hdspm_create(struct snd_card
*card
,
6304 struct hdspm
*hdspm
)
6307 struct pci_dev
*pci
= hdspm
->pci
;
6309 unsigned long io_extent
;
6314 spin_lock_init(&hdspm
->lock
);
6316 pci_read_config_word(hdspm
->pci
,
6317 PCI_CLASS_REVISION
, &hdspm
->firmware_rev
);
6319 strcpy(card
->mixername
, "Xilinx FPGA");
6320 strcpy(card
->driver
, "HDSPM");
6322 switch (hdspm
->firmware_rev
) {
6323 case HDSPM_RAYDAT_REV
:
6324 hdspm
->io_type
= RayDAT
;
6325 hdspm
->card_name
= "RME RayDAT";
6326 hdspm
->midiPorts
= 2;
6329 hdspm
->io_type
= AIO
;
6330 hdspm
->card_name
= "RME AIO";
6331 hdspm
->midiPorts
= 1;
6333 case HDSPM_MADIFACE_REV
:
6334 hdspm
->io_type
= MADIface
;
6335 hdspm
->card_name
= "RME MADIface";
6336 hdspm
->midiPorts
= 1;
6339 if ((hdspm
->firmware_rev
== 0xf0) ||
6340 ((hdspm
->firmware_rev
>= 0xe6) &&
6341 (hdspm
->firmware_rev
<= 0xea))) {
6342 hdspm
->io_type
= AES32
;
6343 hdspm
->card_name
= "RME AES32";
6344 hdspm
->midiPorts
= 2;
6345 } else if ((hdspm
->firmware_rev
== 0xd2) ||
6346 ((hdspm
->firmware_rev
>= 0xc8) &&
6347 (hdspm
->firmware_rev
<= 0xcf))) {
6348 hdspm
->io_type
= MADI
;
6349 hdspm
->card_name
= "RME MADI";
6350 hdspm
->midiPorts
= 3;
6353 "HDSPM: unknown firmware revision %x\n",
6354 hdspm
->firmware_rev
);
6359 err
= pci_enable_device(pci
);
6363 pci_set_master(hdspm
->pci
);
6365 err
= pci_request_regions(pci
, "hdspm");
6369 hdspm
->port
= pci_resource_start(pci
, 0);
6370 io_extent
= pci_resource_len(pci
, 0);
6372 snd_printdd("grabbed memory region 0x%lx-0x%lx\n",
6373 hdspm
->port
, hdspm
->port
+ io_extent
- 1);
6375 hdspm
->iobase
= ioremap_nocache(hdspm
->port
, io_extent
);
6376 if (!hdspm
->iobase
) {
6377 snd_printk(KERN_ERR
"HDSPM: "
6378 "unable to remap region 0x%lx-0x%lx\n",
6379 hdspm
->port
, hdspm
->port
+ io_extent
- 1);
6382 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n",
6383 (unsigned long)hdspm
->iobase
, hdspm
->port
,
6384 hdspm
->port
+ io_extent
- 1);
6386 if (request_irq(pci
->irq
, snd_hdspm_interrupt
,
6387 IRQF_SHARED
, KBUILD_MODNAME
, hdspm
)) {
6388 snd_printk(KERN_ERR
"HDSPM: unable to use IRQ %d\n", pci
->irq
);
6392 snd_printdd("use IRQ %d\n", pci
->irq
);
6394 hdspm
->irq
= pci
->irq
;
6396 snd_printdd("kmalloc Mixer memory of %zd Bytes\n",
6397 sizeof(struct hdspm_mixer
));
6398 hdspm
->mixer
= kzalloc(sizeof(struct hdspm_mixer
), GFP_KERNEL
);
6399 if (!hdspm
->mixer
) {
6400 snd_printk(KERN_ERR
"HDSPM: "
6401 "unable to kmalloc Mixer memory of %d Bytes\n",
6402 (int)sizeof(struct hdspm_mixer
));
6406 hdspm
->port_names_in
= NULL
;
6407 hdspm
->port_names_out
= NULL
;
6409 switch (hdspm
->io_type
) {
6411 hdspm
->ss_in_channels
= hdspm
->ss_out_channels
= AES32_CHANNELS
;
6412 hdspm
->ds_in_channels
= hdspm
->ds_out_channels
= AES32_CHANNELS
;
6413 hdspm
->qs_in_channels
= hdspm
->qs_out_channels
= AES32_CHANNELS
;
6415 hdspm
->channel_map_in_ss
= hdspm
->channel_map_out_ss
=
6417 hdspm
->channel_map_in_ds
= hdspm
->channel_map_out_ds
=
6419 hdspm
->channel_map_in_qs
= hdspm
->channel_map_out_qs
=
6421 hdspm
->port_names_in_ss
= hdspm
->port_names_out_ss
=
6423 hdspm
->port_names_in_ds
= hdspm
->port_names_out_ds
=
6425 hdspm
->port_names_in_qs
= hdspm
->port_names_out_qs
=
6428 hdspm
->max_channels_out
= hdspm
->max_channels_in
=
6430 hdspm
->port_names_in
= hdspm
->port_names_out
=
6432 hdspm
->channel_map_in
= hdspm
->channel_map_out
=
6439 hdspm
->ss_in_channels
= hdspm
->ss_out_channels
=
6441 hdspm
->ds_in_channels
= hdspm
->ds_out_channels
=
6443 hdspm
->qs_in_channels
= hdspm
->qs_out_channels
=
6446 hdspm
->channel_map_in_ss
= hdspm
->channel_map_out_ss
=
6447 channel_map_unity_ss
;
6448 hdspm
->channel_map_in_ds
= hdspm
->channel_map_out_ds
=
6449 channel_map_unity_ss
;
6450 hdspm
->channel_map_in_qs
= hdspm
->channel_map_out_qs
=
6451 channel_map_unity_ss
;
6453 hdspm
->port_names_in_ss
= hdspm
->port_names_out_ss
=
6455 hdspm
->port_names_in_ds
= hdspm
->port_names_out_ds
=
6457 hdspm
->port_names_in_qs
= hdspm
->port_names_out_qs
=
6462 if (0 == (hdspm_read(hdspm
, HDSPM_statusRegister2
) & HDSPM_s2_AEBI_D
)) {
6463 snd_printk(KERN_INFO
"HDSPM: AEB input board found, but not supported\n");
6466 hdspm
->ss_in_channels
= AIO_IN_SS_CHANNELS
;
6467 hdspm
->ds_in_channels
= AIO_IN_DS_CHANNELS
;
6468 hdspm
->qs_in_channels
= AIO_IN_QS_CHANNELS
;
6469 hdspm
->ss_out_channels
= AIO_OUT_SS_CHANNELS
;
6470 hdspm
->ds_out_channels
= AIO_OUT_DS_CHANNELS
;
6471 hdspm
->qs_out_channels
= AIO_OUT_QS_CHANNELS
;
6473 hdspm
->channel_map_out_ss
= channel_map_aio_out_ss
;
6474 hdspm
->channel_map_out_ds
= channel_map_aio_out_ds
;
6475 hdspm
->channel_map_out_qs
= channel_map_aio_out_qs
;
6477 hdspm
->channel_map_in_ss
= channel_map_aio_in_ss
;
6478 hdspm
->channel_map_in_ds
= channel_map_aio_in_ds
;
6479 hdspm
->channel_map_in_qs
= channel_map_aio_in_qs
;
6481 hdspm
->port_names_in_ss
= texts_ports_aio_in_ss
;
6482 hdspm
->port_names_out_ss
= texts_ports_aio_out_ss
;
6483 hdspm
->port_names_in_ds
= texts_ports_aio_in_ds
;
6484 hdspm
->port_names_out_ds
= texts_ports_aio_out_ds
;
6485 hdspm
->port_names_in_qs
= texts_ports_aio_in_qs
;
6486 hdspm
->port_names_out_qs
= texts_ports_aio_out_qs
;
6491 hdspm
->ss_in_channels
= hdspm
->ss_out_channels
=
6493 hdspm
->ds_in_channels
= hdspm
->ds_out_channels
=
6495 hdspm
->qs_in_channels
= hdspm
->qs_out_channels
=
6498 hdspm
->max_channels_in
= RAYDAT_SS_CHANNELS
;
6499 hdspm
->max_channels_out
= RAYDAT_SS_CHANNELS
;
6501 hdspm
->channel_map_in_ss
= hdspm
->channel_map_out_ss
=
6502 channel_map_raydat_ss
;
6503 hdspm
->channel_map_in_ds
= hdspm
->channel_map_out_ds
=
6504 channel_map_raydat_ds
;
6505 hdspm
->channel_map_in_qs
= hdspm
->channel_map_out_qs
=
6506 channel_map_raydat_qs
;
6507 hdspm
->channel_map_in
= hdspm
->channel_map_out
=
6508 channel_map_raydat_ss
;
6510 hdspm
->port_names_in_ss
= hdspm
->port_names_out_ss
=
6511 texts_ports_raydat_ss
;
6512 hdspm
->port_names_in_ds
= hdspm
->port_names_out_ds
=
6513 texts_ports_raydat_ds
;
6514 hdspm
->port_names_in_qs
= hdspm
->port_names_out_qs
=
6515 texts_ports_raydat_qs
;
6523 switch (hdspm
->io_type
) {
6526 if (hdspm_read(hdspm
, HDSPM_statusRegister2
) &
6527 HDSPM_s2_tco_detect
) {
6529 hdspm
->tco
= kzalloc(sizeof(struct hdspm_tco
),
6531 if (NULL
!= hdspm
->tco
) {
6532 hdspm_tco_write(hdspm
);
6534 snd_printk(KERN_INFO
"HDSPM: AIO/RayDAT TCO module found\n");
6541 if (hdspm_read(hdspm
, HDSPM_statusRegister
) & HDSPM_tco_detect
) {
6543 hdspm
->tco
= kzalloc(sizeof(struct hdspm_tco
),
6545 if (NULL
!= hdspm
->tco
) {
6546 hdspm_tco_write(hdspm
);
6548 snd_printk(KERN_INFO
"HDSPM: MADI TCO module found\n");
6559 switch (hdspm
->io_type
) {
6562 hdspm
->texts_autosync
= texts_autosync_aes_tco
;
6563 hdspm
->texts_autosync_items
= 10;
6565 hdspm
->texts_autosync
= texts_autosync_aes
;
6566 hdspm
->texts_autosync_items
= 9;
6572 hdspm
->texts_autosync
= texts_autosync_madi_tco
;
6573 hdspm
->texts_autosync_items
= 4;
6575 hdspm
->texts_autosync
= texts_autosync_madi
;
6576 hdspm
->texts_autosync_items
= 3;
6586 hdspm
->texts_autosync
= texts_autosync_raydat_tco
;
6587 hdspm
->texts_autosync_items
= 9;
6589 hdspm
->texts_autosync
= texts_autosync_raydat
;
6590 hdspm
->texts_autosync_items
= 8;
6596 hdspm
->texts_autosync
= texts_autosync_aio_tco
;
6597 hdspm
->texts_autosync_items
= 6;
6599 hdspm
->texts_autosync
= texts_autosync_aio
;
6600 hdspm
->texts_autosync_items
= 5;
6606 tasklet_init(&hdspm
->midi_tasklet
,
6607 hdspm_midi_tasklet
, (unsigned long) hdspm
);
6610 if (hdspm
->io_type
!= MADIface
) {
6611 hdspm
->serial
= (hdspm_read(hdspm
,
6612 HDSPM_midiStatusIn0
)>>8) & 0xFFFFFF;
6613 /* id contains either a user-provided value or the default
6614 * NULL. If it's the default, we're safe to
6615 * fill card->id with the serial number.
6617 * If the serial number is 0xFFFFFF, then we're dealing with
6618 * an old PCI revision that comes without a sane number. In
6619 * this case, we don't set card->id to avoid collisions
6620 * when running with multiple cards.
6622 if (NULL
== id
[hdspm
->dev
] && hdspm
->serial
!= 0xFFFFFF) {
6623 sprintf(card
->id
, "HDSPMx%06x", hdspm
->serial
);
6624 snd_card_set_id(card
, card
->id
);
6628 snd_printdd("create alsa devices.\n");
6629 err
= snd_hdspm_create_alsa_devices(card
, hdspm
);
6633 snd_hdspm_initialize_midi_flush(hdspm
);
6639 static int snd_hdspm_free(struct hdspm
* hdspm
)
6644 /* stop th audio, and cancel all interrupts */
6645 hdspm
->control_register
&=
6646 ~(HDSPM_Start
| HDSPM_AudioInterruptEnable
|
6647 HDSPM_Midi0InterruptEnable
| HDSPM_Midi1InterruptEnable
|
6648 HDSPM_Midi2InterruptEnable
| HDSPM_Midi3InterruptEnable
);
6649 hdspm_write(hdspm
, HDSPM_controlRegister
,
6650 hdspm
->control_register
);
6653 if (hdspm
->irq
>= 0)
6654 free_irq(hdspm
->irq
, (void *) hdspm
);
6656 kfree(hdspm
->mixer
);
6659 iounmap(hdspm
->iobase
);
6662 pci_release_regions(hdspm
->pci
);
6664 pci_disable_device(hdspm
->pci
);
6669 static void snd_hdspm_card_free(struct snd_card
*card
)
6671 struct hdspm
*hdspm
= card
->private_data
;
6674 snd_hdspm_free(hdspm
);
6678 static int snd_hdspm_probe(struct pci_dev
*pci
,
6679 const struct pci_device_id
*pci_id
)
6682 struct hdspm
*hdspm
;
6683 struct snd_card
*card
;
6686 if (dev
>= SNDRV_CARDS
)
6693 err
= snd_card_create(index
[dev
], id
[dev
],
6694 THIS_MODULE
, sizeof(struct hdspm
), &card
);
6698 hdspm
= card
->private_data
;
6699 card
->private_free
= snd_hdspm_card_free
;
6703 snd_card_set_dev(card
, &pci
->dev
);
6705 err
= snd_hdspm_create(card
, hdspm
);
6707 snd_card_free(card
);
6711 if (hdspm
->io_type
!= MADIface
) {
6712 sprintf(card
->shortname
, "%s_%x",
6715 sprintf(card
->longname
, "%s S/N 0x%x at 0x%lx, irq %d",
6718 hdspm
->port
, hdspm
->irq
);
6720 sprintf(card
->shortname
, "%s", hdspm
->card_name
);
6721 sprintf(card
->longname
, "%s at 0x%lx, irq %d",
6722 hdspm
->card_name
, hdspm
->port
, hdspm
->irq
);
6725 err
= snd_card_register(card
);
6727 snd_card_free(card
);
6731 pci_set_drvdata(pci
, card
);
6737 static void snd_hdspm_remove(struct pci_dev
*pci
)
6739 snd_card_free(pci_get_drvdata(pci
));
6740 pci_set_drvdata(pci
, NULL
);
6743 static struct pci_driver hdspm_driver
= {
6744 .name
= KBUILD_MODNAME
,
6745 .id_table
= snd_hdspm_ids
,
6746 .probe
= snd_hdspm_probe
,
6747 .remove
= snd_hdspm_remove
,
6750 module_pci_driver(hdspm_driver
);