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ALSA: hda/ca0132 - Fix recording from mode id 0x8
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / sound / pci / hda / patch_ca0132.c
1 /*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/pci.h>
28 #include <linux/mutex.h>
29 #include <linux/module.h>
30 #include <linux/firmware.h>
31 #include <sound/core.h>
32 #include "hda_codec.h"
33 #include "hda_local.h"
34 #include "hda_auto_parser.h"
35 #include "hda_jack.h"
36
37 #include "ca0132_regs.h"
38
39 /* Enable this to see controls for tuning purpose. */
40 /*#define ENABLE_TUNING_CONTROLS*/
41
42 #define FLOAT_ZERO 0x00000000
43 #define FLOAT_ONE 0x3f800000
44 #define FLOAT_TWO 0x40000000
45 #define FLOAT_MINUS_5 0xc0a00000
46
47 #define UNSOL_TAG_HP 0x10
48 #define UNSOL_TAG_AMIC1 0x12
49 #define UNSOL_TAG_DSP 0x16
50
51 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
52 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
53
54 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
55 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
56 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
57
58 #define MASTERCONTROL 0x80
59 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
60 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
61
62 #define WIDGET_CHIP_CTRL 0x15
63 #define WIDGET_DSP_CTRL 0x16
64
65 #define MEM_CONNID_MICIN1 3
66 #define MEM_CONNID_MICIN2 5
67 #define MEM_CONNID_MICOUT1 12
68 #define MEM_CONNID_MICOUT2 14
69 #define MEM_CONNID_WUH 10
70 #define MEM_CONNID_DSP 16
71 #define MEM_CONNID_DMIC 100
72
73 #define SCP_SET 0
74 #define SCP_GET 1
75
76 #define EFX_FILE "ctefx.bin"
77
78 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
79 MODULE_FIRMWARE(EFX_FILE);
80 #endif
81
82 static char *dirstr[2] = { "Playback", "Capture" };
83
84 enum {
85 SPEAKER_OUT,
86 HEADPHONE_OUT
87 };
88
89 enum {
90 DIGITAL_MIC,
91 LINE_MIC_IN
92 };
93
94 enum {
95 #define VNODE_START_NID 0x80
96 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
97 VNID_MIC,
98 VNID_HP_SEL,
99 VNID_AMIC1_SEL,
100 VNID_HP_ASEL,
101 VNID_AMIC1_ASEL,
102 VNODE_END_NID,
103 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
104
105 #define EFFECT_START_NID 0x90
106 #define OUT_EFFECT_START_NID EFFECT_START_NID
107 SURROUND = OUT_EFFECT_START_NID,
108 CRYSTALIZER,
109 DIALOG_PLUS,
110 SMART_VOLUME,
111 X_BASS,
112 EQUALIZER,
113 OUT_EFFECT_END_NID,
114 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
115
116 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
117 ECHO_CANCELLATION = IN_EFFECT_START_NID,
118 VOICE_FOCUS,
119 MIC_SVM,
120 NOISE_REDUCTION,
121 IN_EFFECT_END_NID,
122 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
123
124 VOICEFX = IN_EFFECT_END_NID,
125 PLAY_ENHANCEMENT,
126 CRYSTAL_VOICE,
127 EFFECT_END_NID
128 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
129 };
130
131 /* Effects values size*/
132 #define EFFECT_VALS_MAX_COUNT 12
133
134 /* Latency introduced by DSP blocks in milliseconds. */
135 #define DSP_CAPTURE_INIT_LATENCY 0
136 #define DSP_CRYSTAL_VOICE_LATENCY 124
137 #define DSP_PLAYBACK_INIT_LATENCY 13
138 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
139 #define DSP_SPEAKER_OUT_LATENCY 7
140
141 struct ct_effect {
142 char name[44];
143 hda_nid_t nid;
144 int mid; /*effect module ID*/
145 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
146 int direct; /* 0:output; 1:input*/
147 int params; /* number of default non-on/off params */
148 /*effect default values, 1st is on/off. */
149 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
150 };
151
152 #define EFX_DIR_OUT 0
153 #define EFX_DIR_IN 1
154
155 static struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
156 { .name = "Surround",
157 .nid = SURROUND,
158 .mid = 0x96,
159 .reqs = {0, 1},
160 .direct = EFX_DIR_OUT,
161 .params = 1,
162 .def_vals = {0x3F800000, 0x3F2B851F}
163 },
164 { .name = "Crystalizer",
165 .nid = CRYSTALIZER,
166 .mid = 0x96,
167 .reqs = {7, 8},
168 .direct = EFX_DIR_OUT,
169 .params = 1,
170 .def_vals = {0x3F800000, 0x3F266666}
171 },
172 { .name = "Dialog Plus",
173 .nid = DIALOG_PLUS,
174 .mid = 0x96,
175 .reqs = {2, 3},
176 .direct = EFX_DIR_OUT,
177 .params = 1,
178 .def_vals = {0x00000000, 0x3F000000}
179 },
180 { .name = "Smart Volume",
181 .nid = SMART_VOLUME,
182 .mid = 0x96,
183 .reqs = {4, 5, 6},
184 .direct = EFX_DIR_OUT,
185 .params = 2,
186 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
187 },
188 { .name = "X-Bass",
189 .nid = X_BASS,
190 .mid = 0x96,
191 .reqs = {24, 23, 25},
192 .direct = EFX_DIR_OUT,
193 .params = 2,
194 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
195 },
196 { .name = "Equalizer",
197 .nid = EQUALIZER,
198 .mid = 0x96,
199 .reqs = {9, 10, 11, 12, 13, 14,
200 15, 16, 17, 18, 19, 20},
201 .direct = EFX_DIR_OUT,
202 .params = 11,
203 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
204 0x00000000, 0x00000000, 0x00000000, 0x00000000,
205 0x00000000, 0x00000000, 0x00000000, 0x00000000}
206 },
207 { .name = "Echo Cancellation",
208 .nid = ECHO_CANCELLATION,
209 .mid = 0x95,
210 .reqs = {0, 1, 2, 3},
211 .direct = EFX_DIR_IN,
212 .params = 3,
213 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
214 },
215 { .name = "Voice Focus",
216 .nid = VOICE_FOCUS,
217 .mid = 0x95,
218 .reqs = {6, 7, 8, 9},
219 .direct = EFX_DIR_IN,
220 .params = 3,
221 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
222 },
223 { .name = "Mic SVM",
224 .nid = MIC_SVM,
225 .mid = 0x95,
226 .reqs = {44, 45},
227 .direct = EFX_DIR_IN,
228 .params = 1,
229 .def_vals = {0x00000000, 0x3F3D70A4}
230 },
231 { .name = "Noise Reduction",
232 .nid = NOISE_REDUCTION,
233 .mid = 0x95,
234 .reqs = {4, 5},
235 .direct = EFX_DIR_IN,
236 .params = 1,
237 .def_vals = {0x3F800000, 0x3F000000}
238 },
239 { .name = "VoiceFX",
240 .nid = VOICEFX,
241 .mid = 0x95,
242 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
243 .direct = EFX_DIR_IN,
244 .params = 8,
245 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
246 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
247 0x00000000}
248 }
249 };
250
251 /* Tuning controls */
252 #ifdef ENABLE_TUNING_CONTROLS
253
254 enum {
255 #define TUNING_CTL_START_NID 0xC0
256 WEDGE_ANGLE = TUNING_CTL_START_NID,
257 SVM_LEVEL,
258 EQUALIZER_BAND_0,
259 EQUALIZER_BAND_1,
260 EQUALIZER_BAND_2,
261 EQUALIZER_BAND_3,
262 EQUALIZER_BAND_4,
263 EQUALIZER_BAND_5,
264 EQUALIZER_BAND_6,
265 EQUALIZER_BAND_7,
266 EQUALIZER_BAND_8,
267 EQUALIZER_BAND_9,
268 TUNING_CTL_END_NID
269 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
270 };
271
272 struct ct_tuning_ctl {
273 char name[44];
274 hda_nid_t parent_nid;
275 hda_nid_t nid;
276 int mid; /*effect module ID*/
277 int req; /*effect module request*/
278 int direct; /* 0:output; 1:input*/
279 unsigned int def_val;/*effect default values*/
280 };
281
282 static struct ct_tuning_ctl ca0132_tuning_ctls[] = {
283 { .name = "Wedge Angle",
284 .parent_nid = VOICE_FOCUS,
285 .nid = WEDGE_ANGLE,
286 .mid = 0x95,
287 .req = 8,
288 .direct = EFX_DIR_IN,
289 .def_val = 0x41F00000
290 },
291 { .name = "SVM Level",
292 .parent_nid = MIC_SVM,
293 .nid = SVM_LEVEL,
294 .mid = 0x95,
295 .req = 45,
296 .direct = EFX_DIR_IN,
297 .def_val = 0x3F3D70A4
298 },
299 { .name = "EQ Band0",
300 .parent_nid = EQUALIZER,
301 .nid = EQUALIZER_BAND_0,
302 .mid = 0x96,
303 .req = 11,
304 .direct = EFX_DIR_OUT,
305 .def_val = 0x00000000
306 },
307 { .name = "EQ Band1",
308 .parent_nid = EQUALIZER,
309 .nid = EQUALIZER_BAND_1,
310 .mid = 0x96,
311 .req = 12,
312 .direct = EFX_DIR_OUT,
313 .def_val = 0x00000000
314 },
315 { .name = "EQ Band2",
316 .parent_nid = EQUALIZER,
317 .nid = EQUALIZER_BAND_2,
318 .mid = 0x96,
319 .req = 13,
320 .direct = EFX_DIR_OUT,
321 .def_val = 0x00000000
322 },
323 { .name = "EQ Band3",
324 .parent_nid = EQUALIZER,
325 .nid = EQUALIZER_BAND_3,
326 .mid = 0x96,
327 .req = 14,
328 .direct = EFX_DIR_OUT,
329 .def_val = 0x00000000
330 },
331 { .name = "EQ Band4",
332 .parent_nid = EQUALIZER,
333 .nid = EQUALIZER_BAND_4,
334 .mid = 0x96,
335 .req = 15,
336 .direct = EFX_DIR_OUT,
337 .def_val = 0x00000000
338 },
339 { .name = "EQ Band5",
340 .parent_nid = EQUALIZER,
341 .nid = EQUALIZER_BAND_5,
342 .mid = 0x96,
343 .req = 16,
344 .direct = EFX_DIR_OUT,
345 .def_val = 0x00000000
346 },
347 { .name = "EQ Band6",
348 .parent_nid = EQUALIZER,
349 .nid = EQUALIZER_BAND_6,
350 .mid = 0x96,
351 .req = 17,
352 .direct = EFX_DIR_OUT,
353 .def_val = 0x00000000
354 },
355 { .name = "EQ Band7",
356 .parent_nid = EQUALIZER,
357 .nid = EQUALIZER_BAND_7,
358 .mid = 0x96,
359 .req = 18,
360 .direct = EFX_DIR_OUT,
361 .def_val = 0x00000000
362 },
363 { .name = "EQ Band8",
364 .parent_nid = EQUALIZER,
365 .nid = EQUALIZER_BAND_8,
366 .mid = 0x96,
367 .req = 19,
368 .direct = EFX_DIR_OUT,
369 .def_val = 0x00000000
370 },
371 { .name = "EQ Band9",
372 .parent_nid = EQUALIZER,
373 .nid = EQUALIZER_BAND_9,
374 .mid = 0x96,
375 .req = 20,
376 .direct = EFX_DIR_OUT,
377 .def_val = 0x00000000
378 }
379 };
380 #endif
381
382 /* Voice FX Presets */
383 #define VOICEFX_MAX_PARAM_COUNT 9
384
385 struct ct_voicefx {
386 char *name;
387 hda_nid_t nid;
388 int mid;
389 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
390 };
391
392 struct ct_voicefx_preset {
393 char *name; /*preset name*/
394 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
395 };
396
397 static struct ct_voicefx ca0132_voicefx = {
398 .name = "VoiceFX Capture Switch",
399 .nid = VOICEFX,
400 .mid = 0x95,
401 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
402 };
403
404 static struct ct_voicefx_preset ca0132_voicefx_presets[] = {
405 { .name = "Neutral",
406 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
407 0x44FA0000, 0x3F800000, 0x3F800000,
408 0x3F800000, 0x00000000, 0x00000000 }
409 },
410 { .name = "Female2Male",
411 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
412 0x44FA0000, 0x3F19999A, 0x3F866666,
413 0x3F800000, 0x00000000, 0x00000000 }
414 },
415 { .name = "Male2Female",
416 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
417 0x450AC000, 0x4017AE14, 0x3F6B851F,
418 0x3F800000, 0x00000000, 0x00000000 }
419 },
420 { .name = "ScrappyKid",
421 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
422 0x44FA0000, 0x40400000, 0x3F28F5C3,
423 0x3F800000, 0x00000000, 0x00000000 }
424 },
425 { .name = "Elderly",
426 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
427 0x44E10000, 0x3FB33333, 0x3FB9999A,
428 0x3F800000, 0x3E3A2E43, 0x00000000 }
429 },
430 { .name = "Orc",
431 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
432 0x45098000, 0x3F266666, 0x3FC00000,
433 0x3F800000, 0x00000000, 0x00000000 }
434 },
435 { .name = "Elf",
436 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
437 0x45193000, 0x3F8E147B, 0x3F75C28F,
438 0x3F800000, 0x00000000, 0x00000000 }
439 },
440 { .name = "Dwarf",
441 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
442 0x45007000, 0x3F451EB8, 0x3F7851EC,
443 0x3F800000, 0x00000000, 0x00000000 }
444 },
445 { .name = "AlienBrute",
446 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
447 0x451F6000, 0x3F266666, 0x3FA7D945,
448 0x3F800000, 0x3CF5C28F, 0x00000000 }
449 },
450 { .name = "Robot",
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x44FA0000, 0x3FB2718B, 0x3F800000,
453 0xBC07010E, 0x00000000, 0x00000000 }
454 },
455 { .name = "Marine",
456 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
457 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
458 0x3F0A3D71, 0x00000000, 0x00000000 }
459 },
460 { .name = "Emo",
461 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
462 0x44FA0000, 0x3F800000, 0x3F800000,
463 0x3E4CCCCD, 0x00000000, 0x00000000 }
464 },
465 { .name = "DeepVoice",
466 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
467 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
468 0x3F800000, 0x00000000, 0x00000000 }
469 },
470 { .name = "Munchkin",
471 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
472 0x44FA0000, 0x3F800000, 0x3F1A043C,
473 0x3F800000, 0x00000000, 0x00000000 }
474 }
475 };
476
477 enum hda_cmd_vendor_io {
478 /* for DspIO node */
479 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
480 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
481
482 VENDOR_DSPIO_STATUS = 0xF01,
483 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
484 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
485 VENDOR_DSPIO_DSP_INIT = 0x703,
486 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
487 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
488
489 /* for ChipIO node */
490 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
491 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
492 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
493 VENDOR_CHIPIO_DATA_LOW = 0x300,
494 VENDOR_CHIPIO_DATA_HIGH = 0x400,
495
496 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
497 VENDOR_CHIPIO_STATUS = 0xF01,
498 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
499 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
500
501 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
502 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
503
504 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
505 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
506
507 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
508 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
509 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
510 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
511 VENDOR_CHIPIO_FLAG_SET = 0x70F,
512 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
513 VENDOR_CHIPIO_PARAM_SET = 0x710,
514 VENDOR_CHIPIO_PARAM_GET = 0xF10,
515
516 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
517 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
518 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
519 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
520
521 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
522 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
523 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
524 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
525
526 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
527 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
528 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
529 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
530 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
531 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
532
533 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
534 };
535
536 /*
537 * Control flag IDs
538 */
539 enum control_flag_id {
540 /* Connection manager stream setup is bypassed/enabled */
541 CONTROL_FLAG_C_MGR = 0,
542 /* DSP DMA is bypassed/enabled */
543 CONTROL_FLAG_DMA = 1,
544 /* 8051 'idle' mode is disabled/enabled */
545 CONTROL_FLAG_IDLE_ENABLE = 2,
546 /* Tracker for the SPDIF-in path is bypassed/enabled */
547 CONTROL_FLAG_TRACKER = 3,
548 /* DigitalOut to Spdif2Out connection is disabled/enabled */
549 CONTROL_FLAG_SPDIF2OUT = 4,
550 /* Digital Microphone is disabled/enabled */
551 CONTROL_FLAG_DMIC = 5,
552 /* ADC_B rate is 48 kHz/96 kHz */
553 CONTROL_FLAG_ADC_B_96KHZ = 6,
554 /* ADC_C rate is 48 kHz/96 kHz */
555 CONTROL_FLAG_ADC_C_96KHZ = 7,
556 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
557 CONTROL_FLAG_DAC_96KHZ = 8,
558 /* DSP rate is 48 kHz/96 kHz */
559 CONTROL_FLAG_DSP_96KHZ = 9,
560 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
561 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
562 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
563 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
564 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
565 CONTROL_FLAG_DECODE_LOOP = 12,
566 /* De-emphasis filter on DAC-1 disabled/enabled */
567 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
568 /* De-emphasis filter on DAC-2 disabled/enabled */
569 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
570 /* De-emphasis filter on DAC-3 disabled/enabled */
571 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
572 /* High-pass filter on ADC_B disabled/enabled */
573 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
574 /* High-pass filter on ADC_C disabled/enabled */
575 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
576 /* Common mode on Port_A disabled/enabled */
577 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
578 /* Common mode on Port_D disabled/enabled */
579 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
580 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
581 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
582 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
583 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
584 /* ASI rate is 48kHz/96kHz */
585 CONTROL_FLAG_ASI_96KHZ = 22,
586 /* DAC power settings able to control attached ports no/yes */
587 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
588 /* Clock Stop OK reporting is disabled/enabled */
589 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
590 /* Number of control flags */
591 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
592 };
593
594 /*
595 * Control parameter IDs
596 */
597 enum control_param_id {
598 /* 0: None, 1: Mic1In*/
599 CONTROL_PARAM_VIP_SOURCE = 1,
600 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
601 CONTROL_PARAM_SPDIF1_SOURCE = 2,
602 /* Port A output stage gain setting to use when 16 Ohm output
603 * impedance is selected*/
604 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
605 /* Port D output stage gain setting to use when 16 Ohm output
606 * impedance is selected*/
607 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
608
609 /* Stream Control */
610
611 /* Select stream with the given ID */
612 CONTROL_PARAM_STREAM_ID = 24,
613 /* Source connection point for the selected stream */
614 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
615 /* Destination connection point for the selected stream */
616 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
617 /* Number of audio channels in the selected stream */
618 CONTROL_PARAM_STREAMS_CHANNELS = 27,
619 /*Enable control for the selected stream */
620 CONTROL_PARAM_STREAM_CONTROL = 28,
621
622 /* Connection Point Control */
623
624 /* Select connection point with the given ID */
625 CONTROL_PARAM_CONN_POINT_ID = 29,
626 /* Connection point sample rate */
627 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
628
629 /* Node Control */
630
631 /* Select HDA node with the given ID */
632 CONTROL_PARAM_NODE_ID = 31
633 };
634
635 /*
636 * Dsp Io Status codes
637 */
638 enum hda_vendor_status_dspio {
639 /* Success */
640 VENDOR_STATUS_DSPIO_OK = 0x00,
641 /* Busy, unable to accept new command, the host must retry */
642 VENDOR_STATUS_DSPIO_BUSY = 0x01,
643 /* SCP command queue is full */
644 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
645 /* SCP response queue is empty */
646 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
647 };
648
649 /*
650 * Chip Io Status codes
651 */
652 enum hda_vendor_status_chipio {
653 /* Success */
654 VENDOR_STATUS_CHIPIO_OK = 0x00,
655 /* Busy, unable to accept new command, the host must retry */
656 VENDOR_STATUS_CHIPIO_BUSY = 0x01
657 };
658
659 /*
660 * CA0132 sample rate
661 */
662 enum ca0132_sample_rate {
663 SR_6_000 = 0x00,
664 SR_8_000 = 0x01,
665 SR_9_600 = 0x02,
666 SR_11_025 = 0x03,
667 SR_16_000 = 0x04,
668 SR_22_050 = 0x05,
669 SR_24_000 = 0x06,
670 SR_32_000 = 0x07,
671 SR_44_100 = 0x08,
672 SR_48_000 = 0x09,
673 SR_88_200 = 0x0A,
674 SR_96_000 = 0x0B,
675 SR_144_000 = 0x0C,
676 SR_176_400 = 0x0D,
677 SR_192_000 = 0x0E,
678 SR_384_000 = 0x0F,
679
680 SR_COUNT = 0x10,
681
682 SR_RATE_UNKNOWN = 0x1F
683 };
684
685 enum dsp_download_state {
686 DSP_DOWNLOAD_FAILED = -1,
687 DSP_DOWNLOAD_INIT = 0,
688 DSP_DOWNLOADING = 1,
689 DSP_DOWNLOADED = 2
690 };
691
692 /* retrieve parameters from hda format */
693 #define get_hdafmt_chs(fmt) (fmt & 0xf)
694 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
695 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
696 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
697
698 /*
699 * CA0132 specific
700 */
701
702 struct ca0132_spec {
703 struct snd_kcontrol_new *mixers[5];
704 unsigned int num_mixers;
705 const struct hda_verb *base_init_verbs;
706 const struct hda_verb *base_exit_verbs;
707 const struct hda_verb *init_verbs[5];
708 unsigned int num_init_verbs; /* exclude base init verbs */
709 struct auto_pin_cfg autocfg;
710
711 /* Nodes configurations */
712 struct hda_multi_out multiout;
713 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
714 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
715 unsigned int num_outputs;
716 hda_nid_t input_pins[AUTO_PIN_LAST];
717 hda_nid_t adcs[AUTO_PIN_LAST];
718 hda_nid_t dig_out;
719 hda_nid_t dig_in;
720 unsigned int num_inputs;
721 hda_nid_t shared_mic_nid;
722 hda_nid_t shared_out_nid;
723 struct hda_pcm pcm_rec[5]; /* PCM information */
724
725 /* chip access */
726 struct mutex chipio_mutex; /* chip access mutex */
727 u32 curr_chip_addx;
728
729 /* DSP download related */
730 enum dsp_download_state dsp_state;
731 unsigned int dsp_stream_id;
732 unsigned int wait_scp;
733 unsigned int wait_scp_header;
734 unsigned int wait_num_data;
735 unsigned int scp_resp_header;
736 unsigned int scp_resp_data[4];
737 unsigned int scp_resp_count;
738
739 /* mixer and effects related */
740 unsigned char dmic_ctl;
741 int cur_out_type;
742 int cur_mic_type;
743 long vnode_lvol[VNODES_COUNT];
744 long vnode_rvol[VNODES_COUNT];
745 long vnode_lswitch[VNODES_COUNT];
746 long vnode_rswitch[VNODES_COUNT];
747 long effects_switch[EFFECTS_COUNT];
748 long voicefx_val;
749 long cur_mic_boost;
750
751 struct hda_codec *codec;
752 struct delayed_work unsol_hp_work;
753
754 #ifdef ENABLE_TUNING_CONTROLS
755 long cur_ctl_vals[TUNING_CTLS_COUNT];
756 #endif
757 };
758
759 /*
760 * CA0132 codec access
761 */
762 unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
763 unsigned int verb, unsigned int parm, unsigned int *res)
764 {
765 unsigned int response;
766 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
767 *res = response;
768
769 return ((response == -1) ? -1 : 0);
770 }
771
772 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
773 unsigned short converter_format, unsigned int *res)
774 {
775 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
776 converter_format & 0xffff, res);
777 }
778
779 static int codec_set_converter_stream_channel(struct hda_codec *codec,
780 hda_nid_t nid, unsigned char stream,
781 unsigned char channel, unsigned int *res)
782 {
783 unsigned char converter_stream_channel = 0;
784
785 converter_stream_channel = (stream << 4) | (channel & 0x0f);
786 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
787 converter_stream_channel, res);
788 }
789
790 /* Chip access helper function */
791 static int chipio_send(struct hda_codec *codec,
792 unsigned int reg,
793 unsigned int data)
794 {
795 unsigned int res;
796 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
797
798 /* send bits of data specified by reg */
799 do {
800 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
801 reg, data);
802 if (res == VENDOR_STATUS_CHIPIO_OK)
803 return 0;
804 msleep(20);
805 } while (time_before(jiffies, timeout));
806
807 return -EIO;
808 }
809
810 /*
811 * Write chip address through the vendor widget -- NOT protected by the Mutex!
812 */
813 static int chipio_write_address(struct hda_codec *codec,
814 unsigned int chip_addx)
815 {
816 struct ca0132_spec *spec = codec->spec;
817 int res;
818
819 if (spec->curr_chip_addx == chip_addx)
820 return 0;
821
822 /* send low 16 bits of the address */
823 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
824 chip_addx & 0xffff);
825
826 if (res != -EIO) {
827 /* send high 16 bits of the address */
828 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
829 chip_addx >> 16);
830 }
831
832 spec->curr_chip_addx = (res < 0) ? ~0UL : chip_addx;
833
834 return res;
835 }
836
837 /*
838 * Write data through the vendor widget -- NOT protected by the Mutex!
839 */
840 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
841 {
842 struct ca0132_spec *spec = codec->spec;
843 int res;
844
845 /* send low 16 bits of the data */
846 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
847
848 if (res != -EIO) {
849 /* send high 16 bits of the data */
850 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
851 data >> 16);
852 }
853
854 /*If no error encountered, automatically increment the address
855 as per chip behaviour*/
856 spec->curr_chip_addx = (res != -EIO) ?
857 (spec->curr_chip_addx + 4) : ~0UL;
858 return res;
859 }
860
861 /*
862 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
863 */
864 static int chipio_write_data_multiple(struct hda_codec *codec,
865 const u32 *data,
866 unsigned int count)
867 {
868 int status = 0;
869
870 if (data == NULL) {
871 snd_printdd(KERN_ERR "chipio_write_data null ptr\n");
872 return -EINVAL;
873 }
874
875 while ((count-- != 0) && (status == 0))
876 status = chipio_write_data(codec, *data++);
877
878 return status;
879 }
880
881
882 /*
883 * Read data through the vendor widget -- NOT protected by the Mutex!
884 */
885 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
886 {
887 struct ca0132_spec *spec = codec->spec;
888 int res;
889
890 /* post read */
891 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
892
893 if (res != -EIO) {
894 /* read status */
895 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
896 }
897
898 if (res != -EIO) {
899 /* read data */
900 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
901 VENDOR_CHIPIO_HIC_READ_DATA,
902 0);
903 }
904
905 /*If no error encountered, automatically increment the address
906 as per chip behaviour*/
907 spec->curr_chip_addx = (res != -EIO) ?
908 (spec->curr_chip_addx + 4) : ~0UL;
909 return res;
910 }
911
912 /*
913 * Write given value to the given address through the chip I/O widget.
914 * protected by the Mutex
915 */
916 static int chipio_write(struct hda_codec *codec,
917 unsigned int chip_addx, const unsigned int data)
918 {
919 struct ca0132_spec *spec = codec->spec;
920 int err;
921
922 mutex_lock(&spec->chipio_mutex);
923
924 /* write the address, and if successful proceed to write data */
925 err = chipio_write_address(codec, chip_addx);
926 if (err < 0)
927 goto exit;
928
929 err = chipio_write_data(codec, data);
930 if (err < 0)
931 goto exit;
932
933 exit:
934 mutex_unlock(&spec->chipio_mutex);
935 return err;
936 }
937
938 /*
939 * Write multiple values to the given address through the chip I/O widget.
940 * protected by the Mutex
941 */
942 static int chipio_write_multiple(struct hda_codec *codec,
943 u32 chip_addx,
944 const u32 *data,
945 unsigned int count)
946 {
947 struct ca0132_spec *spec = codec->spec;
948 int status;
949
950 mutex_lock(&spec->chipio_mutex);
951 status = chipio_write_address(codec, chip_addx);
952 if (status < 0)
953 goto error;
954
955 status = chipio_write_data_multiple(codec, data, count);
956 error:
957 mutex_unlock(&spec->chipio_mutex);
958
959 return status;
960 }
961
962 /*
963 * Read the given address through the chip I/O widget
964 * protected by the Mutex
965 */
966 static int chipio_read(struct hda_codec *codec,
967 unsigned int chip_addx, unsigned int *data)
968 {
969 struct ca0132_spec *spec = codec->spec;
970 int err;
971
972 mutex_lock(&spec->chipio_mutex);
973
974 /* write the address, and if successful proceed to write data */
975 err = chipio_write_address(codec, chip_addx);
976 if (err < 0)
977 goto exit;
978
979 err = chipio_read_data(codec, data);
980 if (err < 0)
981 goto exit;
982
983 exit:
984 mutex_unlock(&spec->chipio_mutex);
985 return err;
986 }
987
988 /*
989 * Set chip control flags through the chip I/O widget.
990 */
991 static void chipio_set_control_flag(struct hda_codec *codec,
992 enum control_flag_id flag_id,
993 bool flag_state)
994 {
995 unsigned int val;
996 unsigned int flag_bit;
997
998 flag_bit = (flag_state ? 1 : 0);
999 val = (flag_bit << 7) | (flag_id);
1000 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1001 VENDOR_CHIPIO_FLAG_SET, val);
1002 }
1003
1004 /*
1005 * Set chip parameters through the chip I/O widget.
1006 */
1007 static void chipio_set_control_param(struct hda_codec *codec,
1008 enum control_param_id param_id, int param_val)
1009 {
1010 struct ca0132_spec *spec = codec->spec;
1011 int val;
1012
1013 if ((param_id < 32) && (param_val < 8)) {
1014 val = (param_val << 5) | (param_id);
1015 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1016 VENDOR_CHIPIO_PARAM_SET, val);
1017 } else {
1018 mutex_lock(&spec->chipio_mutex);
1019 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1020 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1021 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1022 param_id);
1023 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1024 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1025 param_val);
1026 }
1027 mutex_unlock(&spec->chipio_mutex);
1028 }
1029 }
1030
1031 /*
1032 * Set sampling rate of the connection point.
1033 */
1034 static void chipio_set_conn_rate(struct hda_codec *codec,
1035 int connid, enum ca0132_sample_rate rate)
1036 {
1037 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1038 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1039 rate);
1040 }
1041
1042 /*
1043 * Enable clocks.
1044 */
1045 static void chipio_enable_clocks(struct hda_codec *codec)
1046 {
1047 struct ca0132_spec *spec = codec->spec;
1048
1049 mutex_lock(&spec->chipio_mutex);
1050 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1051 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1052 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1053 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1054 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1055 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1056 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1057 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1058 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1059 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1060 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1061 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1062 mutex_unlock(&spec->chipio_mutex);
1063 }
1064
1065 /*
1066 * CA0132 DSP IO stuffs
1067 */
1068 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1069 unsigned int data)
1070 {
1071 int res;
1072 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1073
1074 /* send bits of data specified by reg to dsp */
1075 do {
1076 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1077 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1078 return res;
1079 msleep(20);
1080 } while (time_before(jiffies, timeout));
1081
1082 return -EIO;
1083 }
1084
1085 /*
1086 * Wait for DSP to be ready for commands
1087 */
1088 static void dspio_write_wait(struct hda_codec *codec)
1089 {
1090 int status;
1091 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1092
1093 do {
1094 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1095 VENDOR_DSPIO_STATUS, 0);
1096 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1097 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1098 break;
1099 msleep(1);
1100 } while (time_before(jiffies, timeout));
1101 }
1102
1103 /*
1104 * Write SCP data to DSP
1105 */
1106 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1107 {
1108 struct ca0132_spec *spec = codec->spec;
1109 int status;
1110
1111 dspio_write_wait(codec);
1112
1113 mutex_lock(&spec->chipio_mutex);
1114 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1115 scp_data & 0xffff);
1116 if (status < 0)
1117 goto error;
1118
1119 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1120 scp_data >> 16);
1121 if (status < 0)
1122 goto error;
1123
1124 /* OK, now check if the write itself has executed*/
1125 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1126 VENDOR_DSPIO_STATUS, 0);
1127 error:
1128 mutex_unlock(&spec->chipio_mutex);
1129
1130 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1131 -EIO : 0;
1132 }
1133
1134 /*
1135 * Write multiple SCP data to DSP
1136 */
1137 static int dspio_write_multiple(struct hda_codec *codec,
1138 unsigned int *buffer, unsigned int size)
1139 {
1140 int status = 0;
1141 unsigned int count;
1142
1143 if ((buffer == NULL))
1144 return -EINVAL;
1145
1146 count = 0;
1147 while (count < size) {
1148 status = dspio_write(codec, *buffer++);
1149 if (status != 0)
1150 break;
1151 count++;
1152 }
1153
1154 return status;
1155 }
1156
1157 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1158 {
1159 int status;
1160
1161 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1162 if (status == -EIO)
1163 return status;
1164
1165 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1166 if (status == -EIO ||
1167 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1168 return -EIO;
1169
1170 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1171 VENDOR_DSPIO_SCP_READ_DATA, 0);
1172
1173 return 0;
1174 }
1175
1176 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1177 unsigned int *buf_size, unsigned int size_count)
1178 {
1179 int status = 0;
1180 unsigned int size = *buf_size;
1181 unsigned int count;
1182 unsigned int skip_count;
1183 unsigned int dummy;
1184
1185 if ((buffer == NULL))
1186 return -1;
1187
1188 count = 0;
1189 while (count < size && count < size_count) {
1190 status = dspio_read(codec, buffer++);
1191 if (status != 0)
1192 break;
1193 count++;
1194 }
1195
1196 skip_count = count;
1197 if (status == 0) {
1198 while (skip_count < size) {
1199 status = dspio_read(codec, &dummy);
1200 if (status != 0)
1201 break;
1202 skip_count++;
1203 }
1204 }
1205 *buf_size = count;
1206
1207 return status;
1208 }
1209
1210 /*
1211 * Construct the SCP header using corresponding fields
1212 */
1213 static inline unsigned int
1214 make_scp_header(unsigned int target_id, unsigned int source_id,
1215 unsigned int get_flag, unsigned int req,
1216 unsigned int device_flag, unsigned int resp_flag,
1217 unsigned int error_flag, unsigned int data_size)
1218 {
1219 unsigned int header = 0;
1220
1221 header = (data_size & 0x1f) << 27;
1222 header |= (error_flag & 0x01) << 26;
1223 header |= (resp_flag & 0x01) << 25;
1224 header |= (device_flag & 0x01) << 24;
1225 header |= (req & 0x7f) << 17;
1226 header |= (get_flag & 0x01) << 16;
1227 header |= (source_id & 0xff) << 8;
1228 header |= target_id & 0xff;
1229
1230 return header;
1231 }
1232
1233 /*
1234 * Extract corresponding fields from SCP header
1235 */
1236 static inline void
1237 extract_scp_header(unsigned int header,
1238 unsigned int *target_id, unsigned int *source_id,
1239 unsigned int *get_flag, unsigned int *req,
1240 unsigned int *device_flag, unsigned int *resp_flag,
1241 unsigned int *error_flag, unsigned int *data_size)
1242 {
1243 if (data_size)
1244 *data_size = (header >> 27) & 0x1f;
1245 if (error_flag)
1246 *error_flag = (header >> 26) & 0x01;
1247 if (resp_flag)
1248 *resp_flag = (header >> 25) & 0x01;
1249 if (device_flag)
1250 *device_flag = (header >> 24) & 0x01;
1251 if (req)
1252 *req = (header >> 17) & 0x7f;
1253 if (get_flag)
1254 *get_flag = (header >> 16) & 0x01;
1255 if (source_id)
1256 *source_id = (header >> 8) & 0xff;
1257 if (target_id)
1258 *target_id = header & 0xff;
1259 }
1260
1261 #define SCP_MAX_DATA_WORDS (16)
1262
1263 /* Structure to contain any SCP message */
1264 struct scp_msg {
1265 unsigned int hdr;
1266 unsigned int data[SCP_MAX_DATA_WORDS];
1267 };
1268
1269 static void dspio_clear_response_queue(struct hda_codec *codec)
1270 {
1271 unsigned int dummy = 0;
1272 int status = -1;
1273
1274 /* clear all from the response queue */
1275 do {
1276 status = dspio_read(codec, &dummy);
1277 } while (status == 0);
1278 }
1279
1280 static int dspio_get_response_data(struct hda_codec *codec)
1281 {
1282 struct ca0132_spec *spec = codec->spec;
1283 unsigned int data = 0;
1284 unsigned int count;
1285
1286 if (dspio_read(codec, &data) < 0)
1287 return -EIO;
1288
1289 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1290 spec->scp_resp_header = data;
1291 spec->scp_resp_count = data >> 27;
1292 count = spec->wait_num_data;
1293 dspio_read_multiple(codec, spec->scp_resp_data,
1294 &spec->scp_resp_count, count);
1295 return 0;
1296 }
1297
1298 return -EIO;
1299 }
1300
1301 /*
1302 * Send SCP message to DSP
1303 */
1304 static int dspio_send_scp_message(struct hda_codec *codec,
1305 unsigned char *send_buf,
1306 unsigned int send_buf_size,
1307 unsigned char *return_buf,
1308 unsigned int return_buf_size,
1309 unsigned int *bytes_returned)
1310 {
1311 struct ca0132_spec *spec = codec->spec;
1312 int status = -1;
1313 unsigned int scp_send_size = 0;
1314 unsigned int total_size;
1315 bool waiting_for_resp = false;
1316 unsigned int header;
1317 struct scp_msg *ret_msg;
1318 unsigned int resp_src_id, resp_target_id;
1319 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1320
1321 if (bytes_returned)
1322 *bytes_returned = 0;
1323
1324 /* get scp header from buffer */
1325 header = *((unsigned int *)send_buf);
1326 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1327 &device_flag, NULL, NULL, &data_size);
1328 scp_send_size = data_size + 1;
1329 total_size = (scp_send_size * 4);
1330
1331 if (send_buf_size < total_size)
1332 return -EINVAL;
1333
1334 if (get_flag || device_flag) {
1335 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1336 return -EINVAL;
1337
1338 spec->wait_scp_header = *((unsigned int *)send_buf);
1339
1340 /* swap source id with target id */
1341 resp_target_id = src_id;
1342 resp_src_id = target_id;
1343 spec->wait_scp_header &= 0xffff0000;
1344 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1345 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1346 spec->wait_scp = 1;
1347 waiting_for_resp = true;
1348 }
1349
1350 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1351 scp_send_size);
1352 if (status < 0) {
1353 spec->wait_scp = 0;
1354 return status;
1355 }
1356
1357 if (waiting_for_resp) {
1358 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1359 memset(return_buf, 0, return_buf_size);
1360 do {
1361 msleep(20);
1362 } while (spec->wait_scp && time_before(jiffies, timeout));
1363 waiting_for_resp = false;
1364 if (!spec->wait_scp) {
1365 ret_msg = (struct scp_msg *)return_buf;
1366 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1367 memcpy(&ret_msg->data, spec->scp_resp_data,
1368 spec->wait_num_data);
1369 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1370 status = 0;
1371 } else {
1372 status = -EIO;
1373 }
1374 spec->wait_scp = 0;
1375 }
1376
1377 return status;
1378 }
1379
1380 /**
1381 * Prepare and send the SCP message to DSP
1382 * @codec: the HDA codec
1383 * @mod_id: ID of the DSP module to send the command
1384 * @req: ID of request to send to the DSP module
1385 * @dir: SET or GET
1386 * @data: pointer to the data to send with the request, request specific
1387 * @len: length of the data, in bytes
1388 * @reply: point to the buffer to hold data returned for a reply
1389 * @reply_len: length of the reply buffer returned from GET
1390 *
1391 * Returns zero or a negative error code.
1392 */
1393 static int dspio_scp(struct hda_codec *codec,
1394 int mod_id, int req, int dir, void *data, unsigned int len,
1395 void *reply, unsigned int *reply_len)
1396 {
1397 int status = 0;
1398 struct scp_msg scp_send, scp_reply;
1399 unsigned int ret_bytes, send_size, ret_size;
1400 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1401 unsigned int reply_data_size;
1402
1403 memset(&scp_send, 0, sizeof(scp_send));
1404 memset(&scp_reply, 0, sizeof(scp_reply));
1405
1406 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1407 return -EINVAL;
1408
1409 if (dir == SCP_GET && reply == NULL) {
1410 snd_printdd(KERN_ERR "dspio_scp get but has no buffer\n");
1411 return -EINVAL;
1412 }
1413
1414 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1415 snd_printdd(KERN_ERR "dspio_scp bad resp buf len parms\n");
1416 return -EINVAL;
1417 }
1418
1419 scp_send.hdr = make_scp_header(mod_id, 0x20, (dir == SCP_GET), req,
1420 0, 0, 0, len/sizeof(unsigned int));
1421 if (data != NULL && len > 0) {
1422 len = min((unsigned int)(sizeof(scp_send.data)), len);
1423 memcpy(scp_send.data, data, len);
1424 }
1425
1426 ret_bytes = 0;
1427 send_size = sizeof(unsigned int) + len;
1428 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1429 send_size, (unsigned char *)&scp_reply,
1430 sizeof(scp_reply), &ret_bytes);
1431
1432 if (status < 0) {
1433 snd_printdd(KERN_ERR "dspio_scp: send scp msg failed\n");
1434 return status;
1435 }
1436
1437 /* extract send and reply headers members */
1438 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1439 NULL, NULL, NULL, NULL, NULL);
1440 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1441 &reply_resp_flag, &reply_error_flag,
1442 &reply_data_size);
1443
1444 if (!send_get_flag)
1445 return 0;
1446
1447 if (reply_resp_flag && !reply_error_flag) {
1448 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1449 / sizeof(unsigned int);
1450
1451 if (*reply_len < ret_size*sizeof(unsigned int)) {
1452 snd_printdd(KERN_ERR "reply too long for buf\n");
1453 return -EINVAL;
1454 } else if (ret_size != reply_data_size) {
1455 snd_printdd(KERN_ERR "RetLen and HdrLen .NE.\n");
1456 return -EINVAL;
1457 } else {
1458 *reply_len = ret_size*sizeof(unsigned int);
1459 memcpy(reply, scp_reply.data, *reply_len);
1460 }
1461 } else {
1462 snd_printdd(KERN_ERR "reply ill-formed or errflag set\n");
1463 return -EIO;
1464 }
1465
1466 return status;
1467 }
1468
1469 /*
1470 * Set DSP parameters
1471 */
1472 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1473 int req, void *data, unsigned int len)
1474 {
1475 return dspio_scp(codec, mod_id, req, SCP_SET, data, len, NULL, NULL);
1476 }
1477
1478 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1479 int req, unsigned int data)
1480 {
1481 return dspio_set_param(codec, mod_id, req, &data, sizeof(unsigned int));
1482 }
1483
1484 /*
1485 * Allocate a DSP DMA channel via an SCP message
1486 */
1487 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1488 {
1489 int status = 0;
1490 unsigned int size = sizeof(dma_chan);
1491
1492 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- begin\n");
1493 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1494 SCP_GET, NULL, 0, dma_chan, &size);
1495
1496 if (status < 0) {
1497 snd_printdd(KERN_INFO "dspio_alloc_dma_chan: SCP Failed\n");
1498 return status;
1499 }
1500
1501 if ((*dma_chan + 1) == 0) {
1502 snd_printdd(KERN_INFO "no free dma channels to allocate\n");
1503 return -EBUSY;
1504 }
1505
1506 snd_printdd("dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1507 snd_printdd(KERN_INFO " dspio_alloc_dma_chan() -- complete\n");
1508
1509 return status;
1510 }
1511
1512 /*
1513 * Free a DSP DMA via an SCP message
1514 */
1515 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1516 {
1517 int status = 0;
1518 unsigned int dummy = 0;
1519
1520 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- begin\n");
1521 snd_printdd("dspio_free_dma_chan: chan=%d\n", dma_chan);
1522
1523 status = dspio_scp(codec, MASTERCONTROL, MASTERCONTROL_ALLOC_DMA_CHAN,
1524 SCP_SET, &dma_chan, sizeof(dma_chan), NULL, &dummy);
1525
1526 if (status < 0) {
1527 snd_printdd(KERN_INFO "dspio_free_dma_chan: SCP Failed\n");
1528 return status;
1529 }
1530
1531 snd_printdd(KERN_INFO " dspio_free_dma_chan() -- complete\n");
1532
1533 return status;
1534 }
1535
1536 /*
1537 * (Re)start the DSP
1538 */
1539 static int dsp_set_run_state(struct hda_codec *codec)
1540 {
1541 unsigned int dbg_ctrl_reg;
1542 unsigned int halt_state;
1543 int err;
1544
1545 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1546 if (err < 0)
1547 return err;
1548
1549 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1550 DSP_DBGCNTL_STATE_LOBIT;
1551
1552 if (halt_state != 0) {
1553 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1554 DSP_DBGCNTL_SS_MASK);
1555 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1556 dbg_ctrl_reg);
1557 if (err < 0)
1558 return err;
1559
1560 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1561 DSP_DBGCNTL_EXEC_MASK;
1562 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1563 dbg_ctrl_reg);
1564 if (err < 0)
1565 return err;
1566 }
1567
1568 return 0;
1569 }
1570
1571 /*
1572 * Reset the DSP
1573 */
1574 static int dsp_reset(struct hda_codec *codec)
1575 {
1576 unsigned int res;
1577 int retry = 20;
1578
1579 snd_printdd("dsp_reset\n");
1580 do {
1581 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
1582 retry--;
1583 } while (res == -EIO && retry);
1584
1585 if (!retry) {
1586 snd_printdd("dsp_reset timeout\n");
1587 return -EIO;
1588 }
1589
1590 return 0;
1591 }
1592
1593 /*
1594 * Convert chip address to DSP address
1595 */
1596 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
1597 bool *code, bool *yram)
1598 {
1599 *code = *yram = false;
1600
1601 if (UC_RANGE(chip_addx, 1)) {
1602 *code = true;
1603 return UC_OFF(chip_addx);
1604 } else if (X_RANGE_ALL(chip_addx, 1)) {
1605 return X_OFF(chip_addx);
1606 } else if (Y_RANGE_ALL(chip_addx, 1)) {
1607 *yram = true;
1608 return Y_OFF(chip_addx);
1609 }
1610
1611 return INVALID_CHIP_ADDRESS;
1612 }
1613
1614 /*
1615 * Check if the DSP DMA is active
1616 */
1617 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
1618 {
1619 unsigned int dma_chnlstart_reg;
1620
1621 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
1622
1623 return ((dma_chnlstart_reg & (1 <<
1624 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
1625 }
1626
1627 static int dsp_dma_setup_common(struct hda_codec *codec,
1628 unsigned int chip_addx,
1629 unsigned int dma_chan,
1630 unsigned int port_map_mask,
1631 bool ovly)
1632 {
1633 int status = 0;
1634 unsigned int chnl_prop;
1635 unsigned int dsp_addx;
1636 unsigned int active;
1637 bool code, yram;
1638
1639 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Begin ---------\n");
1640
1641 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
1642 snd_printdd(KERN_ERR "dma chan num invalid\n");
1643 return -EINVAL;
1644 }
1645
1646 if (dsp_is_dma_active(codec, dma_chan)) {
1647 snd_printdd(KERN_ERR "dma already active\n");
1648 return -EBUSY;
1649 }
1650
1651 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1652
1653 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1654 snd_printdd(KERN_ERR "invalid chip addr\n");
1655 return -ENXIO;
1656 }
1657
1658 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
1659 active = 0;
1660
1661 snd_printdd(KERN_INFO " dsp_dma_setup_common() start reg pgm\n");
1662
1663 if (ovly) {
1664 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
1665 &chnl_prop);
1666
1667 if (status < 0) {
1668 snd_printdd(KERN_ERR "read CHNLPROP Reg fail\n");
1669 return status;
1670 }
1671 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read CHNLPROP\n");
1672 }
1673
1674 if (!code)
1675 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1676 else
1677 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
1678
1679 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
1680
1681 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
1682 if (status < 0) {
1683 snd_printdd(KERN_ERR "write CHNLPROP Reg fail\n");
1684 return status;
1685 }
1686 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write CHNLPROP\n");
1687
1688 if (ovly) {
1689 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
1690 &active);
1691
1692 if (status < 0) {
1693 snd_printdd(KERN_ERR "read ACTIVE Reg fail\n");
1694 return status;
1695 }
1696 snd_printdd(KERN_INFO "dsp_dma_setup_common() Read ACTIVE\n");
1697 }
1698
1699 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
1700 DSPDMAC_ACTIVE_AAR_MASK;
1701
1702 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
1703 if (status < 0) {
1704 snd_printdd(KERN_ERR "write ACTIVE Reg fail\n");
1705 return status;
1706 }
1707
1708 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write ACTIVE\n");
1709
1710 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
1711 port_map_mask);
1712 if (status < 0) {
1713 snd_printdd(KERN_ERR "write AUDCHSEL Reg fail\n");
1714 return status;
1715 }
1716 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write AUDCHSEL\n");
1717
1718 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
1719 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
1720 if (status < 0) {
1721 snd_printdd(KERN_ERR "write IRQCNT Reg fail\n");
1722 return status;
1723 }
1724 snd_printdd(KERN_INFO " dsp_dma_setup_common() Write IRQCNT\n");
1725
1726 snd_printdd(
1727 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
1728 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
1729 chip_addx, dsp_addx, dma_chan,
1730 port_map_mask, chnl_prop, active);
1731
1732 snd_printdd(KERN_INFO "-- dsp_dma_setup_common() -- Complete ------\n");
1733
1734 return 0;
1735 }
1736
1737 /*
1738 * Setup the DSP DMA per-transfer-specific registers
1739 */
1740 static int dsp_dma_setup(struct hda_codec *codec,
1741 unsigned int chip_addx,
1742 unsigned int count,
1743 unsigned int dma_chan)
1744 {
1745 int status = 0;
1746 bool code, yram;
1747 unsigned int dsp_addx;
1748 unsigned int addr_field;
1749 unsigned int incr_field;
1750 unsigned int base_cnt;
1751 unsigned int cur_cnt;
1752 unsigned int dma_cfg = 0;
1753 unsigned int adr_ofs = 0;
1754 unsigned int xfr_cnt = 0;
1755 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
1756 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
1757
1758 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Begin ---------\n");
1759
1760 if (count > max_dma_count) {
1761 snd_printdd(KERN_ERR "count too big\n");
1762 return -EINVAL;
1763 }
1764
1765 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
1766 if (dsp_addx == INVALID_CHIP_ADDRESS) {
1767 snd_printdd(KERN_ERR "invalid chip addr\n");
1768 return -ENXIO;
1769 }
1770
1771 snd_printdd(KERN_INFO " dsp_dma_setup() start reg pgm\n");
1772
1773 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
1774 incr_field = 0;
1775
1776 if (!code) {
1777 addr_field <<= 1;
1778 if (yram)
1779 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
1780
1781 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
1782 }
1783
1784 dma_cfg = addr_field + incr_field;
1785 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
1786 dma_cfg);
1787 if (status < 0) {
1788 snd_printdd(KERN_ERR "write DMACFG Reg fail\n");
1789 return status;
1790 }
1791 snd_printdd(KERN_INFO " dsp_dma_setup() Write DMACFG\n");
1792
1793 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
1794 (code ? 0 : 1));
1795
1796 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
1797 adr_ofs);
1798 if (status < 0) {
1799 snd_printdd(KERN_ERR "write DSPADROFS Reg fail\n");
1800 return status;
1801 }
1802 snd_printdd(KERN_INFO " dsp_dma_setup() Write DSPADROFS\n");
1803
1804 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
1805
1806 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
1807
1808 xfr_cnt = base_cnt | cur_cnt;
1809
1810 status = chipio_write(codec,
1811 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
1812 if (status < 0) {
1813 snd_printdd(KERN_ERR "write XFRCNT Reg fail\n");
1814 return status;
1815 }
1816 snd_printdd(KERN_INFO " dsp_dma_setup() Write XFRCNT\n");
1817
1818 snd_printdd(
1819 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
1820 "ADROFS=0x%x, XFRCNT=0x%x\n",
1821 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
1822
1823 snd_printdd(KERN_INFO "-- dsp_dma_setup() -- Complete ---------\n");
1824
1825 return 0;
1826 }
1827
1828 /*
1829 * Start the DSP DMA
1830 */
1831 static int dsp_dma_start(struct hda_codec *codec,
1832 unsigned int dma_chan, bool ovly)
1833 {
1834 unsigned int reg = 0;
1835 int status = 0;
1836
1837 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Begin ---------\n");
1838
1839 if (ovly) {
1840 status = chipio_read(codec,
1841 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1842
1843 if (status < 0) {
1844 snd_printdd(KERN_ERR "read CHNLSTART reg fail\n");
1845 return status;
1846 }
1847 snd_printdd(KERN_INFO "-- dsp_dma_start() Read CHNLSTART\n");
1848
1849 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1850 DSPDMAC_CHNLSTART_DIS_MASK);
1851 }
1852
1853 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1854 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
1855 if (status < 0) {
1856 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n");
1857 return status;
1858 }
1859 snd_printdd(KERN_INFO "-- dsp_dma_start() -- Complete ---------\n");
1860
1861 return status;
1862 }
1863
1864 /*
1865 * Stop the DSP DMA
1866 */
1867 static int dsp_dma_stop(struct hda_codec *codec,
1868 unsigned int dma_chan, bool ovly)
1869 {
1870 unsigned int reg = 0;
1871 int status = 0;
1872
1873 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Begin ---------\n");
1874
1875 if (ovly) {
1876 status = chipio_read(codec,
1877 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
1878
1879 if (status < 0) {
1880 snd_printdd(KERN_ERR "read CHNLSTART reg fail\n");
1881 return status;
1882 }
1883 snd_printdd(KERN_INFO "-- dsp_dma_stop() Read CHNLSTART\n");
1884 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
1885 DSPDMAC_CHNLSTART_DIS_MASK);
1886 }
1887
1888 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
1889 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
1890 if (status < 0) {
1891 snd_printdd(KERN_ERR "write CHNLSTART reg fail\n");
1892 return status;
1893 }
1894 snd_printdd(KERN_INFO "-- dsp_dma_stop() -- Complete ---------\n");
1895
1896 return status;
1897 }
1898
1899 /**
1900 * Allocate router ports
1901 *
1902 * @codec: the HDA codec
1903 * @num_chans: number of channels in the stream
1904 * @ports_per_channel: number of ports per channel
1905 * @start_device: start device
1906 * @port_map: pointer to the port list to hold the allocated ports
1907 *
1908 * Returns zero or a negative error code.
1909 */
1910 static int dsp_allocate_router_ports(struct hda_codec *codec,
1911 unsigned int num_chans,
1912 unsigned int ports_per_channel,
1913 unsigned int start_device,
1914 unsigned int *port_map)
1915 {
1916 int status = 0;
1917 int res;
1918 u8 val;
1919
1920 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1921 if (status < 0)
1922 return status;
1923
1924 val = start_device << 6;
1925 val |= (ports_per_channel - 1) << 4;
1926 val |= num_chans - 1;
1927
1928 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1929 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
1930 val);
1931
1932 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1933 VENDOR_CHIPIO_PORT_ALLOC_SET,
1934 MEM_CONNID_DSP);
1935
1936 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1937 if (status < 0)
1938 return status;
1939
1940 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1941 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
1942
1943 *port_map = res;
1944
1945 return (res < 0) ? res : 0;
1946 }
1947
1948 /*
1949 * Free router ports
1950 */
1951 static int dsp_free_router_ports(struct hda_codec *codec)
1952 {
1953 int status = 0;
1954
1955 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1956 if (status < 0)
1957 return status;
1958
1959 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1960 VENDOR_CHIPIO_PORT_FREE_SET,
1961 MEM_CONNID_DSP);
1962
1963 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1964
1965 return status;
1966 }
1967
1968 /*
1969 * Allocate DSP ports for the download stream
1970 */
1971 static int dsp_allocate_ports(struct hda_codec *codec,
1972 unsigned int num_chans,
1973 unsigned int rate_multi, unsigned int *port_map)
1974 {
1975 int status;
1976
1977 snd_printdd(KERN_INFO " dsp_allocate_ports() -- begin\n");
1978
1979 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
1980 snd_printdd(KERN_ERR "bad rate multiple\n");
1981 return -EINVAL;
1982 }
1983
1984 status = dsp_allocate_router_ports(codec, num_chans,
1985 rate_multi, 0, port_map);
1986
1987 snd_printdd(KERN_INFO " dsp_allocate_ports() -- complete\n");
1988
1989 return status;
1990 }
1991
1992 static int dsp_allocate_ports_format(struct hda_codec *codec,
1993 const unsigned short fmt,
1994 unsigned int *port_map)
1995 {
1996 int status;
1997 unsigned int num_chans;
1998
1999 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2000 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2001 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2002
2003 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2004 snd_printdd(KERN_ERR "bad rate multiple\n");
2005 return -EINVAL;
2006 }
2007
2008 num_chans = get_hdafmt_chs(fmt) + 1;
2009
2010 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2011
2012 return status;
2013 }
2014
2015 /*
2016 * free DSP ports
2017 */
2018 static int dsp_free_ports(struct hda_codec *codec)
2019 {
2020 int status;
2021
2022 snd_printdd(KERN_INFO " dsp_free_ports() -- begin\n");
2023
2024 status = dsp_free_router_ports(codec);
2025 if (status < 0) {
2026 snd_printdd(KERN_ERR "free router ports fail\n");
2027 return status;
2028 }
2029 snd_printdd(KERN_INFO " dsp_free_ports() -- complete\n");
2030
2031 return status;
2032 }
2033
2034 /*
2035 * HDA DMA engine stuffs for DSP code download
2036 */
2037 struct dma_engine {
2038 struct hda_codec *codec;
2039 unsigned short m_converter_format;
2040 struct snd_dma_buffer *dmab;
2041 unsigned int buf_size;
2042 };
2043
2044
2045 enum dma_state {
2046 DMA_STATE_STOP = 0,
2047 DMA_STATE_RUN = 1
2048 };
2049
2050 static int dma_convert_to_hda_format(
2051 unsigned int sample_rate,
2052 unsigned short channels,
2053 unsigned short *hda_format)
2054 {
2055 unsigned int format_val;
2056
2057 format_val = snd_hda_calc_stream_format(
2058 sample_rate,
2059 channels,
2060 SNDRV_PCM_FORMAT_S32_LE,
2061 32, 0);
2062
2063 if (hda_format)
2064 *hda_format = (unsigned short)format_val;
2065
2066 return 0;
2067 }
2068
2069 /*
2070 * Reset DMA for DSP download
2071 */
2072 static int dma_reset(struct dma_engine *dma)
2073 {
2074 struct hda_codec *codec = dma->codec;
2075 struct ca0132_spec *spec = codec->spec;
2076 int status;
2077
2078 if (dma->dmab->area)
2079 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2080
2081 status = snd_hda_codec_load_dsp_prepare(codec,
2082 dma->m_converter_format,
2083 dma->buf_size,
2084 dma->dmab);
2085 if (status < 0)
2086 return status;
2087 spec->dsp_stream_id = status;
2088 return 0;
2089 }
2090
2091 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2092 {
2093 bool cmd;
2094
2095 snd_printdd("dma_set_state state=%d\n", state);
2096
2097 switch (state) {
2098 case DMA_STATE_STOP:
2099 cmd = false;
2100 break;
2101 case DMA_STATE_RUN:
2102 cmd = true;
2103 break;
2104 default:
2105 return 0;
2106 }
2107
2108 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2109 return 0;
2110 }
2111
2112 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2113 {
2114 return dma->dmab->bytes;
2115 }
2116
2117 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2118 {
2119 return dma->dmab->area;
2120 }
2121
2122 static int dma_xfer(struct dma_engine *dma,
2123 const unsigned int *data,
2124 unsigned int count)
2125 {
2126 memcpy(dma->dmab->area, data, count);
2127 return 0;
2128 }
2129
2130 static void dma_get_converter_format(
2131 struct dma_engine *dma,
2132 unsigned short *format)
2133 {
2134 if (format)
2135 *format = dma->m_converter_format;
2136 }
2137
2138 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2139 {
2140 struct ca0132_spec *spec = dma->codec->spec;
2141
2142 return spec->dsp_stream_id;
2143 }
2144
2145 struct dsp_image_seg {
2146 u32 magic;
2147 u32 chip_addr;
2148 u32 count;
2149 u32 data[0];
2150 };
2151
2152 static const u32 g_magic_value = 0x4c46584d;
2153 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2154
2155 static bool is_valid(const struct dsp_image_seg *p)
2156 {
2157 return p->magic == g_magic_value;
2158 }
2159
2160 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2161 {
2162 return g_chip_addr_magic_value == p->chip_addr;
2163 }
2164
2165 static bool is_last(const struct dsp_image_seg *p)
2166 {
2167 return p->count == 0;
2168 }
2169
2170 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2171 {
2172 return sizeof(*p) + p->count*sizeof(u32);
2173 }
2174
2175 static const struct dsp_image_seg *get_next_seg_ptr(
2176 const struct dsp_image_seg *p)
2177 {
2178 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2179 }
2180
2181 /*
2182 * CA0132 chip DSP transfer stuffs. For DSP download.
2183 */
2184 #define INVALID_DMA_CHANNEL (~0U)
2185
2186 /*
2187 * Program a list of address/data pairs via the ChipIO widget.
2188 * The segment data is in the format of successive pairs of words.
2189 * These are repeated as indicated by the segment's count field.
2190 */
2191 static int dspxfr_hci_write(struct hda_codec *codec,
2192 const struct dsp_image_seg *fls)
2193 {
2194 int status;
2195 const u32 *data;
2196 unsigned int count;
2197
2198 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2199 snd_printdd(KERN_ERR "hci_write invalid params\n");
2200 return -EINVAL;
2201 }
2202
2203 count = fls->count;
2204 data = (u32 *)(fls->data);
2205 while (count >= 2) {
2206 status = chipio_write(codec, data[0], data[1]);
2207 if (status < 0) {
2208 snd_printdd(KERN_ERR "hci_write chipio failed\n");
2209 return status;
2210 }
2211 count -= 2;
2212 data += 2;
2213 }
2214 return 0;
2215 }
2216
2217 /**
2218 * Write a block of data into DSP code or data RAM using pre-allocated
2219 * DMA engine.
2220 *
2221 * @codec: the HDA codec
2222 * @fls: pointer to a fast load image
2223 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2224 * no relocation
2225 * @dma_engine: pointer to DMA engine to be used for DSP download
2226 * @dma_chan: The number of DMA channels used for DSP download
2227 * @port_map_mask: port mapping
2228 * @ovly: TRUE if overlay format is required
2229 *
2230 * Returns zero or a negative error code.
2231 */
2232 static int dspxfr_one_seg(struct hda_codec *codec,
2233 const struct dsp_image_seg *fls,
2234 unsigned int reloc,
2235 struct dma_engine *dma_engine,
2236 unsigned int dma_chan,
2237 unsigned int port_map_mask,
2238 bool ovly)
2239 {
2240 int status = 0;
2241 bool comm_dma_setup_done = false;
2242 const unsigned int *data;
2243 unsigned int chip_addx;
2244 unsigned int words_to_write;
2245 unsigned int buffer_size_words;
2246 unsigned char *buffer_addx;
2247 unsigned short hda_format;
2248 unsigned int sample_rate_div;
2249 unsigned int sample_rate_mul;
2250 unsigned int num_chans;
2251 unsigned int hda_frame_size_words;
2252 unsigned int remainder_words;
2253 const u32 *data_remainder;
2254 u32 chip_addx_remainder;
2255 unsigned int run_size_words;
2256 const struct dsp_image_seg *hci_write = NULL;
2257 unsigned long timeout;
2258 bool dma_active;
2259
2260 if (fls == NULL)
2261 return -EINVAL;
2262 if (is_hci_prog_list_seg(fls)) {
2263 hci_write = fls;
2264 fls = get_next_seg_ptr(fls);
2265 }
2266
2267 if (hci_write && (!fls || is_last(fls))) {
2268 snd_printdd("hci_write\n");
2269 return dspxfr_hci_write(codec, hci_write);
2270 }
2271
2272 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2273 snd_printdd("Invalid Params\n");
2274 return -EINVAL;
2275 }
2276
2277 data = fls->data;
2278 chip_addx = fls->chip_addr,
2279 words_to_write = fls->count;
2280
2281 if (!words_to_write)
2282 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2283 if (reloc)
2284 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2285
2286 if (!UC_RANGE(chip_addx, words_to_write) &&
2287 !X_RANGE_ALL(chip_addx, words_to_write) &&
2288 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2289 snd_printdd("Invalid chip_addx Params\n");
2290 return -EINVAL;
2291 }
2292
2293 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2294 sizeof(u32);
2295
2296 buffer_addx = dma_get_buffer_addr(dma_engine);
2297
2298 if (buffer_addx == NULL) {
2299 snd_printdd(KERN_ERR "dma_engine buffer NULL\n");
2300 return -EINVAL;
2301 }
2302
2303 dma_get_converter_format(dma_engine, &hda_format);
2304 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2305 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2306 num_chans = get_hdafmt_chs(hda_format) + 1;
2307
2308 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2309 (num_chans * sample_rate_mul / sample_rate_div));
2310
2311 if (hda_frame_size_words == 0) {
2312 snd_printdd(KERN_ERR "frmsz zero\n");
2313 return -EINVAL;
2314 }
2315
2316 buffer_size_words = min(buffer_size_words,
2317 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2318 65536 : 32768));
2319 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2320 snd_printdd(
2321 "chpadr=0x%08x frmsz=%u nchan=%u "
2322 "rate_mul=%u div=%u bufsz=%u\n",
2323 chip_addx, hda_frame_size_words, num_chans,
2324 sample_rate_mul, sample_rate_div, buffer_size_words);
2325
2326 if (buffer_size_words < hda_frame_size_words) {
2327 snd_printdd(KERN_ERR "dspxfr_one_seg:failed\n");
2328 return -EINVAL;
2329 }
2330
2331 remainder_words = words_to_write % hda_frame_size_words;
2332 data_remainder = data;
2333 chip_addx_remainder = chip_addx;
2334
2335 data += remainder_words;
2336 chip_addx += remainder_words*sizeof(u32);
2337 words_to_write -= remainder_words;
2338
2339 while (words_to_write != 0) {
2340 run_size_words = min(buffer_size_words, words_to_write);
2341 snd_printdd("dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2342 words_to_write, run_size_words, remainder_words);
2343 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2344 if (!comm_dma_setup_done) {
2345 status = dsp_dma_stop(codec, dma_chan, ovly);
2346 if (status < 0)
2347 return status;
2348 status = dsp_dma_setup_common(codec, chip_addx,
2349 dma_chan, port_map_mask, ovly);
2350 if (status < 0)
2351 return status;
2352 comm_dma_setup_done = true;
2353 }
2354
2355 status = dsp_dma_setup(codec, chip_addx,
2356 run_size_words, dma_chan);
2357 if (status < 0)
2358 return status;
2359 status = dsp_dma_start(codec, dma_chan, ovly);
2360 if (status < 0)
2361 return status;
2362 if (!dsp_is_dma_active(codec, dma_chan)) {
2363 snd_printdd(KERN_ERR "dspxfr:DMA did not start\n");
2364 return -EIO;
2365 }
2366 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2367 if (status < 0)
2368 return status;
2369 if (remainder_words != 0) {
2370 status = chipio_write_multiple(codec,
2371 chip_addx_remainder,
2372 data_remainder,
2373 remainder_words);
2374 if (status < 0)
2375 return status;
2376 remainder_words = 0;
2377 }
2378 if (hci_write) {
2379 status = dspxfr_hci_write(codec, hci_write);
2380 if (status < 0)
2381 return status;
2382 hci_write = NULL;
2383 }
2384
2385 timeout = jiffies + msecs_to_jiffies(2000);
2386 do {
2387 dma_active = dsp_is_dma_active(codec, dma_chan);
2388 if (!dma_active)
2389 break;
2390 msleep(20);
2391 } while (time_before(jiffies, timeout));
2392 if (dma_active)
2393 break;
2394
2395 snd_printdd(KERN_INFO "+++++ DMA complete\n");
2396 dma_set_state(dma_engine, DMA_STATE_STOP);
2397 status = dma_reset(dma_engine);
2398
2399 if (status < 0)
2400 return status;
2401
2402 data += run_size_words;
2403 chip_addx += run_size_words*sizeof(u32);
2404 words_to_write -= run_size_words;
2405 }
2406
2407 if (remainder_words != 0) {
2408 status = chipio_write_multiple(codec, chip_addx_remainder,
2409 data_remainder, remainder_words);
2410 }
2411
2412 return status;
2413 }
2414
2415 /**
2416 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2417 *
2418 * @codec: the HDA codec
2419 * @fls_data: pointer to a fast load image
2420 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2421 * no relocation
2422 * @sample_rate: sampling rate of the stream used for DSP download
2423 * @number_channels: channels of the stream used for DSP download
2424 * @ovly: TRUE if overlay format is required
2425 *
2426 * Returns zero or a negative error code.
2427 */
2428 static int dspxfr_image(struct hda_codec *codec,
2429 const struct dsp_image_seg *fls_data,
2430 unsigned int reloc,
2431 unsigned int sample_rate,
2432 unsigned short channels,
2433 bool ovly)
2434 {
2435 struct ca0132_spec *spec = codec->spec;
2436 int status;
2437 unsigned short hda_format = 0;
2438 unsigned int response;
2439 unsigned char stream_id = 0;
2440 struct dma_engine *dma_engine;
2441 unsigned int dma_chan;
2442 unsigned int port_map_mask;
2443
2444 if (fls_data == NULL)
2445 return -EINVAL;
2446
2447 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2448 if (!dma_engine)
2449 return -ENOMEM;
2450
2451 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2452 if (!dma_engine->dmab) {
2453 kfree(dma_engine);
2454 return -ENOMEM;
2455 }
2456
2457 dma_engine->codec = codec;
2458 dma_convert_to_hda_format(sample_rate, channels, &hda_format);
2459 dma_engine->m_converter_format = hda_format;
2460 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2461 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2462
2463 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2464
2465 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2466 hda_format, &response);
2467
2468 if (status < 0) {
2469 snd_printdd(KERN_ERR "set converter format fail\n");
2470 goto exit;
2471 }
2472
2473 status = snd_hda_codec_load_dsp_prepare(codec,
2474 dma_engine->m_converter_format,
2475 dma_engine->buf_size,
2476 dma_engine->dmab);
2477 if (status < 0)
2478 goto exit;
2479 spec->dsp_stream_id = status;
2480
2481 if (ovly) {
2482 status = dspio_alloc_dma_chan(codec, &dma_chan);
2483 if (status < 0) {
2484 snd_printdd(KERN_ERR "alloc dmachan fail\n");
2485 dma_chan = INVALID_DMA_CHANNEL;
2486 goto exit;
2487 }
2488 }
2489
2490 port_map_mask = 0;
2491 status = dsp_allocate_ports_format(codec, hda_format,
2492 &port_map_mask);
2493 if (status < 0) {
2494 snd_printdd(KERN_ERR "alloc ports fail\n");
2495 goto exit;
2496 }
2497
2498 stream_id = dma_get_stream_id(dma_engine);
2499 status = codec_set_converter_stream_channel(codec,
2500 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2501 if (status < 0) {
2502 snd_printdd(KERN_ERR "set stream chan fail\n");
2503 goto exit;
2504 }
2505
2506 while ((fls_data != NULL) && !is_last(fls_data)) {
2507 if (!is_valid(fls_data)) {
2508 snd_printdd(KERN_ERR "FLS check fail\n");
2509 status = -EINVAL;
2510 goto exit;
2511 }
2512 status = dspxfr_one_seg(codec, fls_data, reloc,
2513 dma_engine, dma_chan,
2514 port_map_mask, ovly);
2515 if (status < 0)
2516 break;
2517
2518 if (is_hci_prog_list_seg(fls_data))
2519 fls_data = get_next_seg_ptr(fls_data);
2520
2521 if ((fls_data != NULL) && !is_last(fls_data))
2522 fls_data = get_next_seg_ptr(fls_data);
2523 }
2524
2525 if (port_map_mask != 0)
2526 status = dsp_free_ports(codec);
2527
2528 if (status < 0)
2529 goto exit;
2530
2531 status = codec_set_converter_stream_channel(codec,
2532 WIDGET_CHIP_CTRL, 0, 0, &response);
2533
2534 exit:
2535 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2536 dspio_free_dma_chan(codec, dma_chan);
2537
2538 if (dma_engine->dmab->area)
2539 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2540 kfree(dma_engine->dmab);
2541 kfree(dma_engine);
2542
2543 return status;
2544 }
2545
2546 /*
2547 * CA0132 DSP download stuffs.
2548 */
2549 static void dspload_post_setup(struct hda_codec *codec)
2550 {
2551 snd_printdd(KERN_INFO "---- dspload_post_setup ------\n");
2552
2553 /*set DSP speaker to 2.0 configuration*/
2554 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2555 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2556
2557 /*update write pointer*/
2558 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2559 }
2560
2561 /**
2562 * Download DSP from a DSP Image Fast Load structure. This structure is a
2563 * linear, non-constant sized element array of structures, each of which
2564 * contain the count of the data to be loaded, the data itself, and the
2565 * corresponding starting chip address of the starting data location.
2566 *
2567 * @codec: the HDA codec
2568 * @fls: pointer to a fast load image
2569 * @ovly: TRUE if overlay format is required
2570 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2571 * no relocation
2572 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2573 * @router_chans: number of audio router channels to be allocated (0 means use
2574 * internal defaults; max is 32)
2575 *
2576 * Returns zero or a negative error code.
2577 */
2578 static int dspload_image(struct hda_codec *codec,
2579 const struct dsp_image_seg *fls,
2580 bool ovly,
2581 unsigned int reloc,
2582 bool autostart,
2583 int router_chans)
2584 {
2585 int status = 0;
2586 unsigned int sample_rate;
2587 unsigned short channels;
2588
2589 snd_printdd(KERN_INFO "---- dspload_image begin ------\n");
2590 if (router_chans == 0) {
2591 if (!ovly)
2592 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
2593 else
2594 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
2595 }
2596
2597 sample_rate = 48000;
2598 channels = (unsigned short)router_chans;
2599
2600 while (channels > 16) {
2601 sample_rate *= 2;
2602 channels /= 2;
2603 }
2604
2605 do {
2606 snd_printdd(KERN_INFO "Ready to program DMA\n");
2607 if (!ovly)
2608 status = dsp_reset(codec);
2609
2610 if (status < 0)
2611 break;
2612
2613 snd_printdd(KERN_INFO "dsp_reset() complete\n");
2614 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
2615 ovly);
2616
2617 if (status < 0)
2618 break;
2619
2620 snd_printdd(KERN_INFO "dspxfr_image() complete\n");
2621 if (autostart && !ovly) {
2622 dspload_post_setup(codec);
2623 status = dsp_set_run_state(codec);
2624 }
2625
2626 snd_printdd(KERN_INFO "LOAD FINISHED\n");
2627 } while (0);
2628
2629 return status;
2630 }
2631
2632 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
2633 static bool dspload_is_loaded(struct hda_codec *codec)
2634 {
2635 unsigned int data = 0;
2636 int status = 0;
2637
2638 status = chipio_read(codec, 0x40004, &data);
2639 if ((status < 0) || (data != 1))
2640 return false;
2641
2642 return true;
2643 }
2644 #else
2645 #define dspload_is_loaded(codec) false
2646 #endif
2647
2648 static bool dspload_wait_loaded(struct hda_codec *codec)
2649 {
2650 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
2651
2652 do {
2653 if (dspload_is_loaded(codec)) {
2654 pr_info("ca0132 DOWNLOAD OK :-) DSP IS RUNNING.\n");
2655 return true;
2656 }
2657 msleep(20);
2658 } while (time_before(jiffies, timeout));
2659
2660 pr_err("ca0132 DOWNLOAD FAILED!!! DSP IS NOT RUNNING.\n");
2661 return false;
2662 }
2663
2664 /*
2665 * PCM callbacks
2666 */
2667 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2668 struct hda_codec *codec,
2669 unsigned int stream_tag,
2670 unsigned int format,
2671 struct snd_pcm_substream *substream)
2672 {
2673 struct ca0132_spec *spec = codec->spec;
2674
2675 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
2676
2677 return 0;
2678 }
2679
2680 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2681 struct hda_codec *codec,
2682 struct snd_pcm_substream *substream)
2683 {
2684 struct ca0132_spec *spec = codec->spec;
2685
2686 if (spec->dsp_state == DSP_DOWNLOADING)
2687 return 0;
2688
2689 /*If Playback effects are on, allow stream some time to flush
2690 *effects tail*/
2691 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
2692 msleep(50);
2693
2694 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
2695
2696 return 0;
2697 }
2698
2699 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
2700 struct hda_codec *codec,
2701 struct snd_pcm_substream *substream)
2702 {
2703 struct ca0132_spec *spec = codec->spec;
2704 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
2705 struct snd_pcm_runtime *runtime = substream->runtime;
2706
2707 if (spec->dsp_state != DSP_DOWNLOADED)
2708 return 0;
2709
2710 /* Add latency if playback enhancement and either effect is enabled. */
2711 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
2712 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
2713 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
2714 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
2715 }
2716
2717 /* Applying Speaker EQ adds latency as well. */
2718 if (spec->cur_out_type == SPEAKER_OUT)
2719 latency += DSP_SPEAKER_OUT_LATENCY;
2720
2721 return (latency * runtime->rate) / 1000;
2722 }
2723
2724 /*
2725 * Digital out
2726 */
2727 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
2728 struct hda_codec *codec,
2729 struct snd_pcm_substream *substream)
2730 {
2731 struct ca0132_spec *spec = codec->spec;
2732 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2733 }
2734
2735 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2736 struct hda_codec *codec,
2737 unsigned int stream_tag,
2738 unsigned int format,
2739 struct snd_pcm_substream *substream)
2740 {
2741 struct ca0132_spec *spec = codec->spec;
2742 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2743 stream_tag, format, substream);
2744 }
2745
2746 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
2747 struct hda_codec *codec,
2748 struct snd_pcm_substream *substream)
2749 {
2750 struct ca0132_spec *spec = codec->spec;
2751 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
2752 }
2753
2754 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
2755 struct hda_codec *codec,
2756 struct snd_pcm_substream *substream)
2757 {
2758 struct ca0132_spec *spec = codec->spec;
2759 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2760 }
2761
2762 /*
2763 * Analog capture
2764 */
2765 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
2766 struct hda_codec *codec,
2767 unsigned int stream_tag,
2768 unsigned int format,
2769 struct snd_pcm_substream *substream)
2770 {
2771 snd_hda_codec_setup_stream(codec, hinfo->nid,
2772 stream_tag, 0, format);
2773
2774 return 0;
2775 }
2776
2777 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
2778 struct hda_codec *codec,
2779 struct snd_pcm_substream *substream)
2780 {
2781 struct ca0132_spec *spec = codec->spec;
2782
2783 if (spec->dsp_state == DSP_DOWNLOADING)
2784 return 0;
2785
2786 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
2787 return 0;
2788 }
2789
2790 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
2791 struct hda_codec *codec,
2792 struct snd_pcm_substream *substream)
2793 {
2794 struct ca0132_spec *spec = codec->spec;
2795 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
2796 struct snd_pcm_runtime *runtime = substream->runtime;
2797
2798 if (spec->dsp_state != DSP_DOWNLOADED)
2799 return 0;
2800
2801 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
2802 latency += DSP_CRYSTAL_VOICE_LATENCY;
2803
2804 return (latency * runtime->rate) / 1000;
2805 }
2806
2807 /*
2808 * Controls stuffs.
2809 */
2810
2811 /*
2812 * Mixer controls helpers.
2813 */
2814 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
2815 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2816 .name = xname, \
2817 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2818 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2819 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
2820 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
2821 .info = ca0132_volume_info, \
2822 .get = ca0132_volume_get, \
2823 .put = ca0132_volume_put, \
2824 .tlv = { .c = ca0132_volume_tlv }, \
2825 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2826
2827 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
2828 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2829 .name = xname, \
2830 .subdevice = HDA_SUBDEV_AMP_FLAG, \
2831 .info = snd_hda_mixer_amp_switch_info, \
2832 .get = ca0132_switch_get, \
2833 .put = ca0132_switch_put, \
2834 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
2835
2836 /* stereo */
2837 #define CA0132_CODEC_VOL(xname, nid, dir) \
2838 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
2839 #define CA0132_CODEC_MUTE(xname, nid, dir) \
2840 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
2841
2842 /* The followings are for tuning of products */
2843 #ifdef ENABLE_TUNING_CONTROLS
2844
2845 static unsigned int voice_focus_vals_lookup[] = {
2846 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
2847 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
2848 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
2849 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
2850 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
2851 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
2852 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
2853 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
2854 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
2855 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
2856 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
2857 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
2858 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
2859 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
2860 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
2861 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
2862 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
2863 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
2864 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
2865 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
2866 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
2867 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
2868 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
2869 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
2870 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
2871 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
2872 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
2873 };
2874
2875 static unsigned int mic_svm_vals_lookup[] = {
2876 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
2877 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
2878 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
2879 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
2880 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
2881 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
2882 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
2883 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
2884 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
2885 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
2886 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
2887 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
2888 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
2889 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
2890 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
2891 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
2892 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
2893 };
2894
2895 static unsigned int equalizer_vals_lookup[] = {
2896 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
2897 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
2898 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
2899 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
2900 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
2901 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
2902 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
2903 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
2904 0x41C00000
2905 };
2906
2907 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
2908 unsigned int *lookup, int idx)
2909 {
2910 int i = 0;
2911
2912 for (i = 0; i < TUNING_CTLS_COUNT; i++)
2913 if (nid == ca0132_tuning_ctls[i].nid)
2914 break;
2915
2916 snd_hda_power_up(codec);
2917 dspio_set_param(codec, ca0132_tuning_ctls[i].mid,
2918 ca0132_tuning_ctls[i].req,
2919 &(lookup[idx]), sizeof(unsigned int));
2920 snd_hda_power_down(codec);
2921
2922 return 1;
2923 }
2924
2925 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
2926 struct snd_ctl_elem_value *ucontrol)
2927 {
2928 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2929 struct ca0132_spec *spec = codec->spec;
2930 hda_nid_t nid = get_amp_nid(kcontrol);
2931 long *valp = ucontrol->value.integer.value;
2932 int idx = nid - TUNING_CTL_START_NID;
2933
2934 *valp = spec->cur_ctl_vals[idx];
2935 return 0;
2936 }
2937
2938 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
2939 struct snd_ctl_elem_info *uinfo)
2940 {
2941 int chs = get_amp_channels(kcontrol);
2942 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2943 uinfo->count = chs == 3 ? 2 : 1;
2944 uinfo->value.integer.min = 20;
2945 uinfo->value.integer.max = 180;
2946 uinfo->value.integer.step = 1;
2947
2948 return 0;
2949 }
2950
2951 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
2952 struct snd_ctl_elem_value *ucontrol)
2953 {
2954 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2955 struct ca0132_spec *spec = codec->spec;
2956 hda_nid_t nid = get_amp_nid(kcontrol);
2957 long *valp = ucontrol->value.integer.value;
2958 int idx;
2959
2960 idx = nid - TUNING_CTL_START_NID;
2961 /* any change? */
2962 if (spec->cur_ctl_vals[idx] == *valp)
2963 return 0;
2964
2965 spec->cur_ctl_vals[idx] = *valp;
2966
2967 idx = *valp - 20;
2968 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
2969
2970 return 1;
2971 }
2972
2973 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
2974 struct snd_ctl_elem_info *uinfo)
2975 {
2976 int chs = get_amp_channels(kcontrol);
2977 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2978 uinfo->count = chs == 3 ? 2 : 1;
2979 uinfo->value.integer.min = 0;
2980 uinfo->value.integer.max = 100;
2981 uinfo->value.integer.step = 1;
2982
2983 return 0;
2984 }
2985
2986 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
2987 struct snd_ctl_elem_value *ucontrol)
2988 {
2989 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
2990 struct ca0132_spec *spec = codec->spec;
2991 hda_nid_t nid = get_amp_nid(kcontrol);
2992 long *valp = ucontrol->value.integer.value;
2993 int idx;
2994
2995 idx = nid - TUNING_CTL_START_NID;
2996 /* any change? */
2997 if (spec->cur_ctl_vals[idx] == *valp)
2998 return 0;
2999
3000 spec->cur_ctl_vals[idx] = *valp;
3001
3002 idx = *valp;
3003 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3004
3005 return 0;
3006 }
3007
3008 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3009 struct snd_ctl_elem_info *uinfo)
3010 {
3011 int chs = get_amp_channels(kcontrol);
3012 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3013 uinfo->count = chs == 3 ? 2 : 1;
3014 uinfo->value.integer.min = 0;
3015 uinfo->value.integer.max = 48;
3016 uinfo->value.integer.step = 1;
3017
3018 return 0;
3019 }
3020
3021 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3022 struct snd_ctl_elem_value *ucontrol)
3023 {
3024 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3025 struct ca0132_spec *spec = codec->spec;
3026 hda_nid_t nid = get_amp_nid(kcontrol);
3027 long *valp = ucontrol->value.integer.value;
3028 int idx;
3029
3030 idx = nid - TUNING_CTL_START_NID;
3031 /* any change? */
3032 if (spec->cur_ctl_vals[idx] == *valp)
3033 return 0;
3034
3035 spec->cur_ctl_vals[idx] = *valp;
3036
3037 idx = *valp;
3038 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3039
3040 return 1;
3041 }
3042
3043 static const DECLARE_TLV_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3044 static const DECLARE_TLV_DB_SCALE(eq_db_scale, -2400, 100, 0);
3045
3046 static int add_tuning_control(struct hda_codec *codec,
3047 hda_nid_t pnid, hda_nid_t nid,
3048 const char *name, int dir)
3049 {
3050 char namestr[44];
3051 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3052 struct snd_kcontrol_new knew =
3053 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3054
3055 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3056 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3057 knew.tlv.c = 0;
3058 knew.tlv.p = 0;
3059 switch (pnid) {
3060 case VOICE_FOCUS:
3061 knew.info = voice_focus_ctl_info;
3062 knew.get = tuning_ctl_get;
3063 knew.put = voice_focus_ctl_put;
3064 knew.tlv.p = voice_focus_db_scale;
3065 break;
3066 case MIC_SVM:
3067 knew.info = mic_svm_ctl_info;
3068 knew.get = tuning_ctl_get;
3069 knew.put = mic_svm_ctl_put;
3070 break;
3071 case EQUALIZER:
3072 knew.info = equalizer_ctl_info;
3073 knew.get = tuning_ctl_get;
3074 knew.put = equalizer_ctl_put;
3075 knew.tlv.p = eq_db_scale;
3076 break;
3077 default:
3078 return 0;
3079 }
3080 knew.private_value =
3081 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3082 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3083 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3084 }
3085
3086 static int add_tuning_ctls(struct hda_codec *codec)
3087 {
3088 int i;
3089 int err;
3090
3091 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3092 err = add_tuning_control(codec,
3093 ca0132_tuning_ctls[i].parent_nid,
3094 ca0132_tuning_ctls[i].nid,
3095 ca0132_tuning_ctls[i].name,
3096 ca0132_tuning_ctls[i].direct);
3097 if (err < 0)
3098 return err;
3099 }
3100
3101 return 0;
3102 }
3103
3104 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3105 {
3106 struct ca0132_spec *spec = codec->spec;
3107 int i;
3108
3109 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3110 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3111 /* SVM level defaults to 0.74. */
3112 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3113
3114 /* EQ defaults to 0dB. */
3115 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3116 spec->cur_ctl_vals[i] = 24;
3117 }
3118 #endif /*ENABLE_TUNING_CONTROLS*/
3119
3120 /*
3121 * Select the active output.
3122 * If autodetect is enabled, output will be selected based on jack detection.
3123 * If jack inserted, headphone will be selected, else built-in speakers
3124 * If autodetect is disabled, output will be selected based on selection.
3125 */
3126 static int ca0132_select_out(struct hda_codec *codec)
3127 {
3128 struct ca0132_spec *spec = codec->spec;
3129 unsigned int pin_ctl;
3130 int jack_present;
3131 int auto_jack;
3132 unsigned int tmp;
3133 int err;
3134
3135 snd_printdd(KERN_INFO "ca0132_select_out\n");
3136
3137 snd_hda_power_up(codec);
3138
3139 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3140
3141 if (auto_jack)
3142 jack_present = snd_hda_jack_detect(codec, spec->out_pins[1]);
3143 else
3144 jack_present =
3145 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3146
3147 if (jack_present)
3148 spec->cur_out_type = HEADPHONE_OUT;
3149 else
3150 spec->cur_out_type = SPEAKER_OUT;
3151
3152 if (spec->cur_out_type == SPEAKER_OUT) {
3153 snd_printdd(KERN_INFO "ca0132_select_out speaker\n");
3154 /*speaker out config*/
3155 tmp = FLOAT_ONE;
3156 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3157 if (err < 0)
3158 goto exit;
3159 /*enable speaker EQ*/
3160 tmp = FLOAT_ONE;
3161 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3162 if (err < 0)
3163 goto exit;
3164
3165 /* Setup EAPD */
3166 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3167 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3168 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3169 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3170 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3171 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3172 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3173 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3174
3175 /* disable headphone node */
3176 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3177 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3178 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3179 pin_ctl & ~PIN_HP);
3180 /* enable speaker node */
3181 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3182 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3183 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3184 pin_ctl | PIN_OUT);
3185 } else {
3186 snd_printdd(KERN_INFO "ca0132_select_out hp\n");
3187 /*headphone out config*/
3188 tmp = FLOAT_ZERO;
3189 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3190 if (err < 0)
3191 goto exit;
3192 /*disable speaker EQ*/
3193 tmp = FLOAT_ZERO;
3194 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3195 if (err < 0)
3196 goto exit;
3197
3198 /* Setup EAPD */
3199 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3200 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3201 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3202 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3203 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3204 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3205 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3206 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3207
3208 /* disable speaker*/
3209 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3210 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3211 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3212 pin_ctl & ~PIN_HP);
3213 /* enable headphone*/
3214 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3215 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3216 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3217 pin_ctl | PIN_HP);
3218 }
3219
3220 exit:
3221 snd_hda_power_down(codec);
3222
3223 return err < 0 ? err : 0;
3224 }
3225
3226 static void ca0132_unsol_hp_delayed(struct work_struct *work)
3227 {
3228 struct ca0132_spec *spec = container_of(
3229 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
3230 ca0132_select_out(spec->codec);
3231 snd_hda_jack_report_sync(spec->codec);
3232 }
3233
3234 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
3235 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
3236 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
3237
3238 /*
3239 * Select the active VIP source
3240 */
3241 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
3242 {
3243 struct ca0132_spec *spec = codec->spec;
3244 unsigned int tmp;
3245
3246 if (spec->dsp_state != DSP_DOWNLOADED)
3247 return 0;
3248
3249 /* if CrystalVoice if off, vipsource should be 0 */
3250 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
3251 (val == 0)) {
3252 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
3253 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
3254 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
3255 if (spec->cur_mic_type == DIGITAL_MIC)
3256 tmp = FLOAT_TWO;
3257 else
3258 tmp = FLOAT_ONE;
3259 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3260 tmp = FLOAT_ZERO;
3261 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3262 } else {
3263 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
3264 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
3265 if (spec->cur_mic_type == DIGITAL_MIC)
3266 tmp = FLOAT_TWO;
3267 else
3268 tmp = FLOAT_ONE;
3269 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
3270 tmp = FLOAT_ONE;
3271 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
3272 msleep(20);
3273 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
3274 }
3275
3276 return 1;
3277 }
3278
3279 /*
3280 * Select the active microphone.
3281 * If autodetect is enabled, mic will be selected based on jack detection.
3282 * If jack inserted, ext.mic will be selected, else built-in mic
3283 * If autodetect is disabled, mic will be selected based on selection.
3284 */
3285 static int ca0132_select_mic(struct hda_codec *codec)
3286 {
3287 struct ca0132_spec *spec = codec->spec;
3288 int jack_present;
3289 int auto_jack;
3290
3291 snd_printdd(KERN_INFO "ca0132_select_mic\n");
3292
3293 snd_hda_power_up(codec);
3294
3295 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3296
3297 if (auto_jack)
3298 jack_present = snd_hda_jack_detect(codec, spec->input_pins[0]);
3299 else
3300 jack_present =
3301 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
3302
3303 if (jack_present)
3304 spec->cur_mic_type = LINE_MIC_IN;
3305 else
3306 spec->cur_mic_type = DIGITAL_MIC;
3307
3308 if (spec->cur_mic_type == DIGITAL_MIC) {
3309 /* enable digital Mic */
3310 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
3311 ca0132_set_dmic(codec, 1);
3312 ca0132_mic_boost_set(codec, 0);
3313 /* set voice focus */
3314 ca0132_effects_set(codec, VOICE_FOCUS,
3315 spec->effects_switch
3316 [VOICE_FOCUS - EFFECT_START_NID]);
3317 } else {
3318 /* disable digital Mic */
3319 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
3320 ca0132_set_dmic(codec, 0);
3321 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
3322 /* disable voice focus */
3323 ca0132_effects_set(codec, VOICE_FOCUS, 0);
3324 }
3325
3326 snd_hda_power_down(codec);
3327
3328 return 0;
3329 }
3330
3331 /*
3332 * Check if VNODE settings take effect immediately.
3333 */
3334 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
3335 hda_nid_t vnid,
3336 hda_nid_t *shared_nid)
3337 {
3338 struct ca0132_spec *spec = codec->spec;
3339 hda_nid_t nid;
3340
3341 switch (vnid) {
3342 case VNID_SPK:
3343 nid = spec->shared_out_nid;
3344 break;
3345 case VNID_MIC:
3346 nid = spec->shared_mic_nid;
3347 break;
3348 default:
3349 return false;
3350 }
3351
3352 if (shared_nid)
3353 *shared_nid = nid;
3354
3355 return true;
3356 }
3357
3358 /*
3359 * The following functions are control change helpers.
3360 * They return 0 if no changed. Return 1 if changed.
3361 */
3362 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
3363 {
3364 struct ca0132_spec *spec = codec->spec;
3365 unsigned int tmp;
3366
3367 /* based on CrystalVoice state to enable VoiceFX. */
3368 if (enable) {
3369 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
3370 FLOAT_ONE : FLOAT_ZERO;
3371 } else {
3372 tmp = FLOAT_ZERO;
3373 }
3374
3375 dspio_set_uint_param(codec, ca0132_voicefx.mid,
3376 ca0132_voicefx.reqs[0], tmp);
3377
3378 return 1;
3379 }
3380
3381 /*
3382 * Set the effects parameters
3383 */
3384 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
3385 {
3386 struct ca0132_spec *spec = codec->spec;
3387 unsigned int on;
3388 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3389 int err = 0;
3390 int idx = nid - EFFECT_START_NID;
3391
3392 if ((idx < 0) || (idx >= num_fx))
3393 return 0; /* no changed */
3394
3395 /* for out effect, qualify with PE */
3396 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
3397 /* if PE if off, turn off out effects. */
3398 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3399 val = 0;
3400 }
3401
3402 /* for in effect, qualify with CrystalVoice */
3403 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
3404 /* if CrystalVoice if off, turn off in effects. */
3405 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3406 val = 0;
3407
3408 /* Voice Focus applies to 2-ch Mic, Digital Mic */
3409 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
3410 val = 0;
3411 }
3412
3413 snd_printdd(KERN_INFO "ca0132_effect_set: nid=0x%x, val=%ld\n",
3414 nid, val);
3415
3416 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
3417 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
3418 ca0132_effects[idx].reqs[0], on);
3419
3420 if (err < 0)
3421 return 0; /* no changed */
3422
3423 return 1;
3424 }
3425
3426 /*
3427 * Turn on/off Playback Enhancements
3428 */
3429 static int ca0132_pe_switch_set(struct hda_codec *codec)
3430 {
3431 struct ca0132_spec *spec = codec->spec;
3432 hda_nid_t nid;
3433 int i, ret = 0;
3434
3435 snd_printdd(KERN_INFO "ca0132_pe_switch_set: val=%ld\n",
3436 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
3437
3438 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
3439 nid = OUT_EFFECT_START_NID;
3440 /* PE affects all out effects */
3441 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
3442 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3443
3444 return ret;
3445 }
3446
3447 /* Check if Mic1 is streaming, if so, stop streaming */
3448 static int stop_mic1(struct hda_codec *codec)
3449 {
3450 struct ca0132_spec *spec = codec->spec;
3451 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
3452 AC_VERB_GET_CONV, 0);
3453 if (oldval != 0)
3454 snd_hda_codec_write(codec, spec->adcs[0], 0,
3455 AC_VERB_SET_CHANNEL_STREAMID,
3456 0);
3457 return oldval;
3458 }
3459
3460 /* Resume Mic1 streaming if it was stopped. */
3461 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
3462 {
3463 struct ca0132_spec *spec = codec->spec;
3464 /* Restore the previous stream and channel */
3465 if (oldval != 0)
3466 snd_hda_codec_write(codec, spec->adcs[0], 0,
3467 AC_VERB_SET_CHANNEL_STREAMID,
3468 oldval);
3469 }
3470
3471 /*
3472 * Turn on/off CrystalVoice
3473 */
3474 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
3475 {
3476 struct ca0132_spec *spec = codec->spec;
3477 hda_nid_t nid;
3478 int i, ret = 0;
3479 unsigned int oldval;
3480
3481 snd_printdd(KERN_INFO "ca0132_cvoice_switch_set: val=%ld\n",
3482 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
3483
3484 i = IN_EFFECT_START_NID - EFFECT_START_NID;
3485 nid = IN_EFFECT_START_NID;
3486 /* CrystalVoice affects all in effects */
3487 for (; nid < IN_EFFECT_END_NID; nid++, i++)
3488 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
3489
3490 /* including VoiceFX */
3491 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
3492
3493 /* set correct vipsource */
3494 oldval = stop_mic1(codec);
3495 ret |= ca0132_set_vipsource(codec, 1);
3496 resume_mic1(codec, oldval);
3497 return ret;
3498 }
3499
3500 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
3501 {
3502 struct ca0132_spec *spec = codec->spec;
3503 int ret = 0;
3504
3505 if (val) /* on */
3506 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3507 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
3508 else /* off */
3509 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
3510 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
3511
3512 return ret;
3513 }
3514
3515 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
3516 struct snd_ctl_elem_value *ucontrol)
3517 {
3518 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3519 hda_nid_t nid = get_amp_nid(kcontrol);
3520 hda_nid_t shared_nid = 0;
3521 bool effective;
3522 int ret = 0;
3523 struct ca0132_spec *spec = codec->spec;
3524 int auto_jack;
3525
3526 if (nid == VNID_HP_SEL) {
3527 auto_jack =
3528 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3529 if (!auto_jack)
3530 ca0132_select_out(codec);
3531 return 1;
3532 }
3533
3534 if (nid == VNID_AMIC1_SEL) {
3535 auto_jack =
3536 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
3537 if (!auto_jack)
3538 ca0132_select_mic(codec);
3539 return 1;
3540 }
3541
3542 if (nid == VNID_HP_ASEL) {
3543 ca0132_select_out(codec);
3544 return 1;
3545 }
3546
3547 if (nid == VNID_AMIC1_ASEL) {
3548 ca0132_select_mic(codec);
3549 return 1;
3550 }
3551
3552 /* if effective conditions, then update hw immediately. */
3553 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3554 if (effective) {
3555 int dir = get_amp_direction(kcontrol);
3556 int ch = get_amp_channels(kcontrol);
3557 unsigned long pval;
3558
3559 mutex_lock(&codec->control_mutex);
3560 pval = kcontrol->private_value;
3561 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3562 0, dir);
3563 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
3564 kcontrol->private_value = pval;
3565 mutex_unlock(&codec->control_mutex);
3566 }
3567
3568 return ret;
3569 }
3570 /* End of control change helpers. */
3571
3572 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
3573 struct snd_ctl_elem_info *uinfo)
3574 {
3575 unsigned int items = sizeof(ca0132_voicefx_presets)
3576 / sizeof(struct ct_voicefx_preset);
3577
3578 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3579 uinfo->count = 1;
3580 uinfo->value.enumerated.items = items;
3581 if (uinfo->value.enumerated.item >= items)
3582 uinfo->value.enumerated.item = items - 1;
3583 strcpy(uinfo->value.enumerated.name,
3584 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
3585 return 0;
3586 }
3587
3588 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
3589 struct snd_ctl_elem_value *ucontrol)
3590 {
3591 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3592 struct ca0132_spec *spec = codec->spec;
3593
3594 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
3595 return 0;
3596 }
3597
3598 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
3599 struct snd_ctl_elem_value *ucontrol)
3600 {
3601 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3602 struct ca0132_spec *spec = codec->spec;
3603 int i, err = 0;
3604 int sel = ucontrol->value.enumerated.item[0];
3605 unsigned int items = sizeof(ca0132_voicefx_presets)
3606 / sizeof(struct ct_voicefx_preset);
3607
3608 if (sel >= items)
3609 return 0;
3610
3611 snd_printdd(KERN_INFO "ca0132_voicefx_put: sel=%d, preset=%s\n",
3612 sel, ca0132_voicefx_presets[sel].name);
3613
3614 /*
3615 * Idx 0 is default.
3616 * Default needs to qualify with CrystalVoice state.
3617 */
3618 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
3619 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
3620 ca0132_voicefx.reqs[i],
3621 ca0132_voicefx_presets[sel].vals[i]);
3622 if (err < 0)
3623 break;
3624 }
3625
3626 if (err >= 0) {
3627 spec->voicefx_val = sel;
3628 /* enable voice fx */
3629 ca0132_voicefx_set(codec, (sel ? 1 : 0));
3630 }
3631
3632 return 1;
3633 }
3634
3635 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
3636 struct snd_ctl_elem_value *ucontrol)
3637 {
3638 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3639 struct ca0132_spec *spec = codec->spec;
3640 hda_nid_t nid = get_amp_nid(kcontrol);
3641 int ch = get_amp_channels(kcontrol);
3642 long *valp = ucontrol->value.integer.value;
3643
3644 /* vnode */
3645 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3646 if (ch & 1) {
3647 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
3648 valp++;
3649 }
3650 if (ch & 2) {
3651 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
3652 valp++;
3653 }
3654 return 0;
3655 }
3656
3657 /* effects, include PE and CrystalVoice */
3658 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
3659 *valp = spec->effects_switch[nid - EFFECT_START_NID];
3660 return 0;
3661 }
3662
3663 /* mic boost */
3664 if (nid == spec->input_pins[0]) {
3665 *valp = spec->cur_mic_boost;
3666 return 0;
3667 }
3668
3669 return 0;
3670 }
3671
3672 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
3673 struct snd_ctl_elem_value *ucontrol)
3674 {
3675 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3676 struct ca0132_spec *spec = codec->spec;
3677 hda_nid_t nid = get_amp_nid(kcontrol);
3678 int ch = get_amp_channels(kcontrol);
3679 long *valp = ucontrol->value.integer.value;
3680 int changed = 1;
3681
3682 snd_printdd(KERN_INFO "ca0132_switch_put: nid=0x%x, val=%ld\n",
3683 nid, *valp);
3684
3685 snd_hda_power_up(codec);
3686 /* vnode */
3687 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
3688 if (ch & 1) {
3689 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
3690 valp++;
3691 }
3692 if (ch & 2) {
3693 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
3694 valp++;
3695 }
3696 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
3697 goto exit;
3698 }
3699
3700 /* PE */
3701 if (nid == PLAY_ENHANCEMENT) {
3702 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3703 changed = ca0132_pe_switch_set(codec);
3704 goto exit;
3705 }
3706
3707 /* CrystalVoice */
3708 if (nid == CRYSTAL_VOICE) {
3709 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3710 changed = ca0132_cvoice_switch_set(codec);
3711 goto exit;
3712 }
3713
3714 /* out and in effects */
3715 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
3716 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
3717 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
3718 changed = ca0132_effects_set(codec, nid, *valp);
3719 goto exit;
3720 }
3721
3722 /* mic boost */
3723 if (nid == spec->input_pins[0]) {
3724 spec->cur_mic_boost = *valp;
3725
3726 /* Mic boost does not apply to Digital Mic */
3727 if (spec->cur_mic_type != DIGITAL_MIC)
3728 changed = ca0132_mic_boost_set(codec, *valp);
3729 goto exit;
3730 }
3731
3732 exit:
3733 snd_hda_power_down(codec);
3734 return changed;
3735 }
3736
3737 /*
3738 * Volume related
3739 */
3740 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
3741 struct snd_ctl_elem_info *uinfo)
3742 {
3743 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3744 struct ca0132_spec *spec = codec->spec;
3745 hda_nid_t nid = get_amp_nid(kcontrol);
3746 int ch = get_amp_channels(kcontrol);
3747 int dir = get_amp_direction(kcontrol);
3748 unsigned long pval;
3749 int err;
3750
3751 switch (nid) {
3752 case VNID_SPK:
3753 /* follow shared_out info */
3754 nid = spec->shared_out_nid;
3755 mutex_lock(&codec->control_mutex);
3756 pval = kcontrol->private_value;
3757 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3758 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3759 kcontrol->private_value = pval;
3760 mutex_unlock(&codec->control_mutex);
3761 break;
3762 case VNID_MIC:
3763 /* follow shared_mic info */
3764 nid = spec->shared_mic_nid;
3765 mutex_lock(&codec->control_mutex);
3766 pval = kcontrol->private_value;
3767 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3768 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3769 kcontrol->private_value = pval;
3770 mutex_unlock(&codec->control_mutex);
3771 break;
3772 default:
3773 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
3774 }
3775 return err;
3776 }
3777
3778 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
3779 struct snd_ctl_elem_value *ucontrol)
3780 {
3781 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3782 struct ca0132_spec *spec = codec->spec;
3783 hda_nid_t nid = get_amp_nid(kcontrol);
3784 int ch = get_amp_channels(kcontrol);
3785 long *valp = ucontrol->value.integer.value;
3786
3787 /* store the left and right volume */
3788 if (ch & 1) {
3789 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
3790 valp++;
3791 }
3792 if (ch & 2) {
3793 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
3794 valp++;
3795 }
3796 return 0;
3797 }
3798
3799 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
3800 struct snd_ctl_elem_value *ucontrol)
3801 {
3802 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3803 struct ca0132_spec *spec = codec->spec;
3804 hda_nid_t nid = get_amp_nid(kcontrol);
3805 int ch = get_amp_channels(kcontrol);
3806 long *valp = ucontrol->value.integer.value;
3807 hda_nid_t shared_nid = 0;
3808 bool effective;
3809 int changed = 1;
3810
3811 /* store the left and right volume */
3812 if (ch & 1) {
3813 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
3814 valp++;
3815 }
3816 if (ch & 2) {
3817 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
3818 valp++;
3819 }
3820
3821 /* if effective conditions, then update hw immediately. */
3822 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
3823 if (effective) {
3824 int dir = get_amp_direction(kcontrol);
3825 unsigned long pval;
3826
3827 snd_hda_power_up(codec);
3828 mutex_lock(&codec->control_mutex);
3829 pval = kcontrol->private_value;
3830 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
3831 0, dir);
3832 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
3833 kcontrol->private_value = pval;
3834 mutex_unlock(&codec->control_mutex);
3835 snd_hda_power_down(codec);
3836 }
3837
3838 return changed;
3839 }
3840
3841 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
3842 unsigned int size, unsigned int __user *tlv)
3843 {
3844 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3845 struct ca0132_spec *spec = codec->spec;
3846 hda_nid_t nid = get_amp_nid(kcontrol);
3847 int ch = get_amp_channels(kcontrol);
3848 int dir = get_amp_direction(kcontrol);
3849 unsigned long pval;
3850 int err;
3851
3852 switch (nid) {
3853 case VNID_SPK:
3854 /* follow shared_out tlv */
3855 nid = spec->shared_out_nid;
3856 mutex_lock(&codec->control_mutex);
3857 pval = kcontrol->private_value;
3858 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3859 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3860 kcontrol->private_value = pval;
3861 mutex_unlock(&codec->control_mutex);
3862 break;
3863 case VNID_MIC:
3864 /* follow shared_mic tlv */
3865 nid = spec->shared_mic_nid;
3866 mutex_lock(&codec->control_mutex);
3867 pval = kcontrol->private_value;
3868 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
3869 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3870 kcontrol->private_value = pval;
3871 mutex_unlock(&codec->control_mutex);
3872 break;
3873 default:
3874 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
3875 }
3876 return err;
3877 }
3878
3879 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
3880 const char *pfx, int dir)
3881 {
3882 char namestr[44];
3883 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3884 struct snd_kcontrol_new knew =
3885 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
3886 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
3887 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3888 }
3889
3890 static int add_voicefx(struct hda_codec *codec)
3891 {
3892 struct snd_kcontrol_new knew =
3893 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
3894 VOICEFX, 1, 0, HDA_INPUT);
3895 knew.info = ca0132_voicefx_info;
3896 knew.get = ca0132_voicefx_get;
3897 knew.put = ca0132_voicefx_put;
3898 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
3899 }
3900
3901 /*
3902 * When changing Node IDs for Mixer Controls below, make sure to update
3903 * Node IDs in ca0132_config() as well.
3904 */
3905 static struct snd_kcontrol_new ca0132_mixer[] = {
3906 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
3907 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
3908 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
3909 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
3910 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
3911 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
3912 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
3913 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
3914 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
3915 0x12, 1, HDA_INPUT),
3916 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
3917 VNID_HP_SEL, 1, HDA_OUTPUT),
3918 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
3919 VNID_AMIC1_SEL, 1, HDA_INPUT),
3920 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
3921 VNID_HP_ASEL, 1, HDA_OUTPUT),
3922 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
3923 VNID_AMIC1_ASEL, 1, HDA_INPUT),
3924 { } /* end */
3925 };
3926
3927 static int ca0132_build_controls(struct hda_codec *codec)
3928 {
3929 struct ca0132_spec *spec = codec->spec;
3930 int i, num_fx;
3931 int err = 0;
3932
3933 /* Add Mixer controls */
3934 for (i = 0; i < spec->num_mixers; i++) {
3935 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
3936 if (err < 0)
3937 return err;
3938 }
3939
3940 /* Add in and out effects controls.
3941 * VoiceFX, PE and CrystalVoice are added separately.
3942 */
3943 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
3944 for (i = 0; i < num_fx; i++) {
3945 err = add_fx_switch(codec, ca0132_effects[i].nid,
3946 ca0132_effects[i].name,
3947 ca0132_effects[i].direct);
3948 if (err < 0)
3949 return err;
3950 }
3951
3952 err = add_fx_switch(codec, PLAY_ENHANCEMENT, "PlayEnhancement", 0);
3953 if (err < 0)
3954 return err;
3955
3956 err = add_fx_switch(codec, CRYSTAL_VOICE, "CrystalVoice", 1);
3957 if (err < 0)
3958 return err;
3959
3960 add_voicefx(codec);
3961
3962 #ifdef ENABLE_TUNING_CONTROLS
3963 add_tuning_ctls(codec);
3964 #endif
3965
3966 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
3967 if (err < 0)
3968 return err;
3969
3970 if (spec->dig_out) {
3971 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
3972 spec->dig_out);
3973 if (err < 0)
3974 return err;
3975 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
3976 if (err < 0)
3977 return err;
3978 /* spec->multiout.share_spdif = 1; */
3979 }
3980
3981 if (spec->dig_in) {
3982 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
3983 if (err < 0)
3984 return err;
3985 }
3986 return 0;
3987 }
3988
3989 /*
3990 * PCM
3991 */
3992 static struct hda_pcm_stream ca0132_pcm_analog_playback = {
3993 .substreams = 1,
3994 .channels_min = 2,
3995 .channels_max = 6,
3996 .ops = {
3997 .prepare = ca0132_playback_pcm_prepare,
3998 .cleanup = ca0132_playback_pcm_cleanup,
3999 .get_delay = ca0132_playback_pcm_delay,
4000 },
4001 };
4002
4003 static struct hda_pcm_stream ca0132_pcm_analog_capture = {
4004 .substreams = 1,
4005 .channels_min = 2,
4006 .channels_max = 2,
4007 .ops = {
4008 .prepare = ca0132_capture_pcm_prepare,
4009 .cleanup = ca0132_capture_pcm_cleanup,
4010 .get_delay = ca0132_capture_pcm_delay,
4011 },
4012 };
4013
4014 static struct hda_pcm_stream ca0132_pcm_digital_playback = {
4015 .substreams = 1,
4016 .channels_min = 2,
4017 .channels_max = 2,
4018 .ops = {
4019 .open = ca0132_dig_playback_pcm_open,
4020 .close = ca0132_dig_playback_pcm_close,
4021 .prepare = ca0132_dig_playback_pcm_prepare,
4022 .cleanup = ca0132_dig_playback_pcm_cleanup
4023 },
4024 };
4025
4026 static struct hda_pcm_stream ca0132_pcm_digital_capture = {
4027 .substreams = 1,
4028 .channels_min = 2,
4029 .channels_max = 2,
4030 };
4031
4032 static int ca0132_build_pcms(struct hda_codec *codec)
4033 {
4034 struct ca0132_spec *spec = codec->spec;
4035 struct hda_pcm *info = spec->pcm_rec;
4036
4037 codec->pcm_info = info;
4038 codec->num_pcms = 0;
4039
4040 info->name = "CA0132 Analog";
4041 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
4042 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
4043 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
4044 spec->multiout.max_channels;
4045 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4046 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4047 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
4048 codec->num_pcms++;
4049
4050 info++;
4051 info->name = "CA0132 Analog Mic-In2";
4052 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4053 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4054 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
4055 codec->num_pcms++;
4056
4057 info++;
4058 info->name = "CA0132 What U Hear";
4059 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
4060 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
4061 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
4062 codec->num_pcms++;
4063
4064 if (!spec->dig_out && !spec->dig_in)
4065 return 0;
4066
4067 info++;
4068 info->name = "CA0132 Digital";
4069 info->pcm_type = HDA_PCM_TYPE_SPDIF;
4070 if (spec->dig_out) {
4071 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
4072 ca0132_pcm_digital_playback;
4073 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
4074 }
4075 if (spec->dig_in) {
4076 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
4077 ca0132_pcm_digital_capture;
4078 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
4079 }
4080 codec->num_pcms++;
4081
4082 return 0;
4083 }
4084
4085 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
4086 {
4087 if (pin) {
4088 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
4089 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
4090 snd_hda_codec_write(codec, pin, 0,
4091 AC_VERB_SET_AMP_GAIN_MUTE,
4092 AMP_OUT_UNMUTE);
4093 }
4094 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
4095 snd_hda_codec_write(codec, dac, 0,
4096 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
4097 }
4098
4099 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
4100 {
4101 if (pin) {
4102 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
4103 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
4104 snd_hda_codec_write(codec, pin, 0,
4105 AC_VERB_SET_AMP_GAIN_MUTE,
4106 AMP_IN_UNMUTE(0));
4107 }
4108 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
4109 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
4110 AMP_IN_UNMUTE(0));
4111
4112 /* init to 0 dB and unmute. */
4113 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4114 HDA_AMP_VOLMASK, 0x5a);
4115 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
4116 HDA_AMP_MUTE, 0);
4117 }
4118 }
4119
4120 static void ca0132_init_unsol(struct hda_codec *codec)
4121 {
4122 snd_hda_jack_detect_enable(codec, UNSOL_TAG_HP, UNSOL_TAG_HP);
4123 snd_hda_jack_detect_enable(codec, UNSOL_TAG_AMIC1, UNSOL_TAG_AMIC1);
4124 }
4125
4126 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
4127 {
4128 unsigned int caps;
4129
4130 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
4131 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
4132 snd_hda_override_amp_caps(codec, nid, dir, caps);
4133 }
4134
4135 /*
4136 * Switch between Digital built-in mic and analog mic.
4137 */
4138 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
4139 {
4140 struct ca0132_spec *spec = codec->spec;
4141 unsigned int tmp;
4142 u8 val;
4143 unsigned int oldval;
4144
4145 snd_printdd(KERN_INFO "ca0132_set_dmic: enable=%d\n", enable);
4146
4147 oldval = stop_mic1(codec);
4148 ca0132_set_vipsource(codec, 0);
4149 if (enable) {
4150 /* set DMic input as 2-ch */
4151 tmp = FLOAT_TWO;
4152 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4153
4154 val = spec->dmic_ctl;
4155 val |= 0x80;
4156 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4157 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4158
4159 if (!(spec->dmic_ctl & 0x20))
4160 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
4161 } else {
4162 /* set AMic input as mono */
4163 tmp = FLOAT_ONE;
4164 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4165
4166 val = spec->dmic_ctl;
4167 /* clear bit7 and bit5 to disable dmic */
4168 val &= 0x5f;
4169 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4170 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4171
4172 if (!(spec->dmic_ctl & 0x20))
4173 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
4174 }
4175 ca0132_set_vipsource(codec, 1);
4176 resume_mic1(codec, oldval);
4177 }
4178
4179 /*
4180 * Initialization for Digital Mic.
4181 */
4182 static void ca0132_init_dmic(struct hda_codec *codec)
4183 {
4184 struct ca0132_spec *spec = codec->spec;
4185 u8 val;
4186
4187 /* Setup Digital Mic here, but don't enable.
4188 * Enable based on jack detect.
4189 */
4190
4191 /* MCLK uses MPIO1, set to enable.
4192 * Bit 2-0: MPIO select
4193 * Bit 3: set to disable
4194 * Bit 7-4: reserved
4195 */
4196 val = 0x01;
4197 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4198 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
4199
4200 /* Data1 uses MPIO3. Data2 not use
4201 * Bit 2-0: Data1 MPIO select
4202 * Bit 3: set disable Data1
4203 * Bit 6-4: Data2 MPIO select
4204 * Bit 7: set disable Data2
4205 */
4206 val = 0x83;
4207 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4208 VENDOR_CHIPIO_DMIC_PIN_SET, val);
4209
4210 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
4211 * Bit 3-0: Channel mask
4212 * Bit 4: set for 48KHz, clear for 32KHz
4213 * Bit 5: mode
4214 * Bit 6: set to select Data2, clear for Data1
4215 * Bit 7: set to enable DMic, clear for AMic
4216 */
4217 val = 0x23;
4218 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
4219 spec->dmic_ctl = val;
4220 snd_hda_codec_write(codec, spec->input_pins[0], 0,
4221 VENDOR_CHIPIO_DMIC_CTL_SET, val);
4222 }
4223
4224 /*
4225 * Initialization for Analog Mic 2
4226 */
4227 static void ca0132_init_analog_mic2(struct hda_codec *codec)
4228 {
4229 struct ca0132_spec *spec = codec->spec;
4230
4231 mutex_lock(&spec->chipio_mutex);
4232 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4233 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
4234 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4235 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4236 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4237 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4238 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4239 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
4240 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4241 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
4242 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
4243 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
4244 mutex_unlock(&spec->chipio_mutex);
4245 }
4246
4247 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
4248 {
4249 struct ca0132_spec *spec = codec->spec;
4250 int i;
4251 hda_nid_t nid;
4252
4253 snd_printdd(KERN_INFO "ca0132_refresh_widget_caps.\n");
4254 nid = codec->start_nid;
4255 for (i = 0; i < codec->num_nodes; i++, nid++)
4256 codec->wcaps[i] = snd_hda_param_read(codec, nid,
4257 AC_PAR_AUDIO_WIDGET_CAP);
4258
4259 for (i = 0; i < spec->multiout.num_dacs; i++)
4260 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
4261
4262 for (i = 0; i < spec->num_outputs; i++)
4263 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
4264
4265 for (i = 0; i < spec->num_inputs; i++) {
4266 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
4267 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
4268 }
4269 }
4270
4271 /*
4272 * Setup default parameters for DSP
4273 */
4274 static void ca0132_setup_defaults(struct hda_codec *codec)
4275 {
4276 struct ca0132_spec *spec = codec->spec;
4277 unsigned int tmp;
4278 int num_fx;
4279 int idx, i;
4280
4281 if (spec->dsp_state != DSP_DOWNLOADED)
4282 return;
4283
4284 /* out, in effects + voicefx */
4285 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
4286 for (idx = 0; idx < num_fx; idx++) {
4287 for (i = 0; i <= ca0132_effects[idx].params; i++) {
4288 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4289 ca0132_effects[idx].reqs[i],
4290 ca0132_effects[idx].def_vals[i]);
4291 }
4292 }
4293
4294 /*remove DSP headroom*/
4295 tmp = FLOAT_ZERO;
4296 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
4297
4298 /*set speaker EQ bypass attenuation*/
4299 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
4300
4301 /* set AMic1 and AMic2 as mono mic */
4302 tmp = FLOAT_ONE;
4303 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4304 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
4305
4306 /* set AMic1 as CrystalVoice input */
4307 tmp = FLOAT_ONE;
4308 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4309
4310 /* set WUH source */
4311 tmp = FLOAT_TWO;
4312 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
4313 }
4314
4315 /*
4316 * Initialization of flags in chip
4317 */
4318 static void ca0132_init_flags(struct hda_codec *codec)
4319 {
4320 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
4321 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
4322 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
4323 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
4324 chipio_set_control_flag(codec, CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
4325 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
4326 }
4327
4328 /*
4329 * Initialization of parameters in chip
4330 */
4331 static void ca0132_init_params(struct hda_codec *codec)
4332 {
4333 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
4334 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
4335 }
4336
4337 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
4338 {
4339 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
4340 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
4341 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
4342 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
4343 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
4344 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
4345
4346 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4347 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4348 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
4349 }
4350
4351 static bool ca0132_download_dsp_images(struct hda_codec *codec)
4352 {
4353 bool dsp_loaded = false;
4354 const struct dsp_image_seg *dsp_os_image;
4355 const struct firmware *fw_entry;
4356
4357 if (request_firmware(&fw_entry, EFX_FILE, codec->bus->card->dev) != 0)
4358 return false;
4359
4360 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
4361 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
4362 pr_err("ca0132 dspload_image failed.\n");
4363 goto exit_download;
4364 }
4365
4366 dsp_loaded = dspload_wait_loaded(codec);
4367
4368 exit_download:
4369 release_firmware(fw_entry);
4370
4371 return dsp_loaded;
4372 }
4373
4374 static void ca0132_download_dsp(struct hda_codec *codec)
4375 {
4376 struct ca0132_spec *spec = codec->spec;
4377
4378 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
4379 return; /* NOP */
4380 #endif
4381
4382 chipio_enable_clocks(codec);
4383 spec->dsp_state = DSP_DOWNLOADING;
4384 if (!ca0132_download_dsp_images(codec))
4385 spec->dsp_state = DSP_DOWNLOAD_FAILED;
4386 else
4387 spec->dsp_state = DSP_DOWNLOADED;
4388
4389 if (spec->dsp_state == DSP_DOWNLOADED)
4390 ca0132_set_dsp_msr(codec, true);
4391 }
4392
4393 static void ca0132_process_dsp_response(struct hda_codec *codec)
4394 {
4395 struct ca0132_spec *spec = codec->spec;
4396
4397 snd_printdd(KERN_INFO "ca0132_process_dsp_response\n");
4398 if (spec->wait_scp) {
4399 if (dspio_get_response_data(codec) >= 0)
4400 spec->wait_scp = 0;
4401 }
4402
4403 dspio_clear_response_queue(codec);
4404 }
4405
4406 static void ca0132_unsol_event(struct hda_codec *codec, unsigned int res)
4407 {
4408 struct ca0132_spec *spec = codec->spec;
4409
4410 if (((res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f) == UNSOL_TAG_DSP) {
4411 ca0132_process_dsp_response(codec);
4412 } else {
4413 res = snd_hda_jack_get_action(codec,
4414 (res >> AC_UNSOL_RES_TAG_SHIFT) & 0x3f);
4415
4416 snd_printdd(KERN_INFO "snd_hda_jack_get_action: 0x%x\n", res);
4417
4418 switch (res) {
4419 case UNSOL_TAG_HP:
4420 /* Delay enabling the HP amp, to let the mic-detection
4421 * state machine run.
4422 */
4423 cancel_delayed_work_sync(&spec->unsol_hp_work);
4424 queue_delayed_work(codec->bus->workq,
4425 &spec->unsol_hp_work,
4426 msecs_to_jiffies(500));
4427 break;
4428 case UNSOL_TAG_AMIC1:
4429 ca0132_select_mic(codec);
4430 snd_hda_jack_report_sync(codec);
4431 break;
4432 default:
4433 break;
4434 }
4435 }
4436 }
4437
4438 /*
4439 * Verbs tables.
4440 */
4441
4442 /* Sends before DSP download. */
4443 static struct hda_verb ca0132_base_init_verbs[] = {
4444 /*enable ct extension*/
4445 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
4446 /*enable DSP node unsol, needed for DSP download*/
4447 {0x16, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_DSP},
4448 {}
4449 };
4450
4451 /* Send at exit. */
4452 static struct hda_verb ca0132_base_exit_verbs[] = {
4453 /*set afg to D3*/
4454 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
4455 /*disable ct extension*/
4456 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
4457 {}
4458 };
4459
4460 /* Other verbs tables. Sends after DSP download. */
4461 static struct hda_verb ca0132_init_verbs0[] = {
4462 /* chip init verbs */
4463 {0x15, 0x70D, 0xF0},
4464 {0x15, 0x70E, 0xFE},
4465 {0x15, 0x707, 0x75},
4466 {0x15, 0x707, 0xD3},
4467 {0x15, 0x707, 0x09},
4468 {0x15, 0x707, 0x53},
4469 {0x15, 0x707, 0xD4},
4470 {0x15, 0x707, 0xEF},
4471 {0x15, 0x707, 0x75},
4472 {0x15, 0x707, 0xD3},
4473 {0x15, 0x707, 0x09},
4474 {0x15, 0x707, 0x02},
4475 {0x15, 0x707, 0x37},
4476 {0x15, 0x707, 0x78},
4477 {0x15, 0x53C, 0xCE},
4478 {0x15, 0x575, 0xC9},
4479 {0x15, 0x53D, 0xCE},
4480 {0x15, 0x5B7, 0xC9},
4481 {0x15, 0x70D, 0xE8},
4482 {0x15, 0x70E, 0xFE},
4483 {0x15, 0x707, 0x02},
4484 {0x15, 0x707, 0x68},
4485 {0x15, 0x707, 0x62},
4486 {0x15, 0x53A, 0xCE},
4487 {0x15, 0x546, 0xC9},
4488 {0x15, 0x53B, 0xCE},
4489 {0x15, 0x5E8, 0xC9},
4490 {0x15, 0x717, 0x0D},
4491 {0x15, 0x718, 0x20},
4492 {}
4493 };
4494
4495 static struct hda_verb ca0132_init_verbs1[] = {
4496 {0x10, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_HP},
4497 {0x12, AC_VERB_SET_UNSOLICITED_ENABLE, AC_USRSP_EN | UNSOL_TAG_AMIC1},
4498 /* config EAPD */
4499 {0x0b, 0x78D, 0x00},
4500 /*{0x0b, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4501 /*{0x10, 0x78D, 0x02},*/
4502 /*{0x10, AC_VERB_SET_EAPD_BTLENABLE, 0x02},*/
4503 {}
4504 };
4505
4506 static void ca0132_init_chip(struct hda_codec *codec)
4507 {
4508 struct ca0132_spec *spec = codec->spec;
4509 int num_fx;
4510 int i;
4511 unsigned int on;
4512
4513 mutex_init(&spec->chipio_mutex);
4514
4515 spec->cur_out_type = SPEAKER_OUT;
4516 spec->cur_mic_type = DIGITAL_MIC;
4517 spec->cur_mic_boost = 0;
4518
4519 for (i = 0; i < VNODES_COUNT; i++) {
4520 spec->vnode_lvol[i] = 0x5a;
4521 spec->vnode_rvol[i] = 0x5a;
4522 spec->vnode_lswitch[i] = 0;
4523 spec->vnode_rswitch[i] = 0;
4524 }
4525
4526 /*
4527 * Default states for effects are in ca0132_effects[].
4528 */
4529 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4530 for (i = 0; i < num_fx; i++) {
4531 on = (unsigned int)ca0132_effects[i].reqs[0];
4532 spec->effects_switch[i] = on ? 1 : 0;
4533 }
4534
4535 spec->voicefx_val = 0;
4536 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
4537 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
4538
4539 #ifdef ENABLE_TUNING_CONTROLS
4540 ca0132_init_tuning_defaults(codec);
4541 #endif
4542 }
4543
4544 static void ca0132_exit_chip(struct hda_codec *codec)
4545 {
4546 /* put any chip cleanup stuffs here. */
4547
4548 if (dspload_is_loaded(codec))
4549 dsp_reset(codec);
4550 }
4551
4552 static int ca0132_init(struct hda_codec *codec)
4553 {
4554 struct ca0132_spec *spec = codec->spec;
4555 struct auto_pin_cfg *cfg = &spec->autocfg;
4556 int i;
4557
4558 spec->dsp_state = DSP_DOWNLOAD_INIT;
4559 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
4560
4561 snd_hda_power_up(codec);
4562
4563 ca0132_init_params(codec);
4564 ca0132_init_flags(codec);
4565 snd_hda_sequence_write(codec, spec->base_init_verbs);
4566 ca0132_download_dsp(codec);
4567 ca0132_refresh_widget_caps(codec);
4568 ca0132_setup_defaults(codec);
4569 ca0132_init_analog_mic2(codec);
4570 ca0132_init_dmic(codec);
4571
4572 for (i = 0; i < spec->num_outputs; i++)
4573 init_output(codec, spec->out_pins[i], spec->dacs[0]);
4574
4575 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
4576
4577 for (i = 0; i < spec->num_inputs; i++)
4578 init_input(codec, spec->input_pins[i], spec->adcs[i]);
4579
4580 init_input(codec, cfg->dig_in_pin, spec->dig_in);
4581
4582 for (i = 0; i < spec->num_init_verbs; i++)
4583 snd_hda_sequence_write(codec, spec->init_verbs[i]);
4584
4585 ca0132_init_unsol(codec);
4586
4587 ca0132_select_out(codec);
4588 ca0132_select_mic(codec);
4589
4590 snd_hda_jack_report_sync(codec);
4591
4592 snd_hda_power_down(codec);
4593
4594 return 0;
4595 }
4596
4597 static void ca0132_free(struct hda_codec *codec)
4598 {
4599 struct ca0132_spec *spec = codec->spec;
4600
4601 cancel_delayed_work_sync(&spec->unsol_hp_work);
4602 snd_hda_power_up(codec);
4603 snd_hda_sequence_write(codec, spec->base_exit_verbs);
4604 ca0132_exit_chip(codec);
4605 snd_hda_power_down(codec);
4606 kfree(codec->spec);
4607 }
4608
4609 static struct hda_codec_ops ca0132_patch_ops = {
4610 .build_controls = ca0132_build_controls,
4611 .build_pcms = ca0132_build_pcms,
4612 .init = ca0132_init,
4613 .free = ca0132_free,
4614 .unsol_event = ca0132_unsol_event,
4615 };
4616
4617 static void ca0132_config(struct hda_codec *codec)
4618 {
4619 struct ca0132_spec *spec = codec->spec;
4620 struct auto_pin_cfg *cfg = &spec->autocfg;
4621
4622 spec->dacs[0] = 0x2;
4623 spec->dacs[1] = 0x3;
4624 spec->dacs[2] = 0x4;
4625
4626 spec->multiout.dac_nids = spec->dacs;
4627 spec->multiout.num_dacs = 3;
4628 spec->multiout.max_channels = 2;
4629
4630 spec->num_outputs = 2;
4631 spec->out_pins[0] = 0x0b; /* speaker out */
4632 spec->out_pins[1] = 0x10; /* headphone out */
4633 spec->shared_out_nid = 0x2;
4634
4635 spec->num_inputs = 3;
4636 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
4637 spec->adcs[1] = 0x8; /* analog mic2 */
4638 spec->adcs[2] = 0xa; /* what u hear */
4639 spec->shared_mic_nid = 0x7;
4640
4641 spec->input_pins[0] = 0x12;
4642 spec->input_pins[1] = 0x11;
4643 spec->input_pins[2] = 0x13;
4644
4645 /* SPDIF I/O */
4646 spec->dig_out = 0x05;
4647 spec->multiout.dig_out_nid = spec->dig_out;
4648 cfg->dig_out_pins[0] = 0x0c;
4649 cfg->dig_outs = 1;
4650 cfg->dig_out_type[0] = HDA_PCM_TYPE_SPDIF;
4651 spec->dig_in = 0x09;
4652 cfg->dig_in_pin = 0x0e;
4653 cfg->dig_in_type = HDA_PCM_TYPE_SPDIF;
4654 }
4655
4656 static int patch_ca0132(struct hda_codec *codec)
4657 {
4658 struct ca0132_spec *spec;
4659 int err;
4660
4661 snd_printdd("patch_ca0132\n");
4662
4663 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
4664 if (!spec)
4665 return -ENOMEM;
4666 codec->spec = spec;
4667 spec->codec = codec;
4668
4669 spec->num_mixers = 1;
4670 spec->mixers[0] = ca0132_mixer;
4671
4672 spec->base_init_verbs = ca0132_base_init_verbs;
4673 spec->base_exit_verbs = ca0132_base_exit_verbs;
4674 spec->init_verbs[0] = ca0132_init_verbs0;
4675 spec->init_verbs[1] = ca0132_init_verbs1;
4676 spec->num_init_verbs = 2;
4677
4678 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
4679
4680 ca0132_init_chip(codec);
4681
4682 ca0132_config(codec);
4683
4684 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
4685 if (err < 0)
4686 return err;
4687
4688 codec->patch_ops = ca0132_patch_ops;
4689 codec->pcm_format_first = 1;
4690 codec->no_sticky_stream = 1;
4691
4692 return 0;
4693 }
4694
4695 /*
4696 * patch entries
4697 */
4698 static struct hda_codec_preset snd_hda_preset_ca0132[] = {
4699 { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
4700 {} /* terminator */
4701 };
4702
4703 MODULE_ALIAS("snd-hda-codec-id:11020011");
4704
4705 MODULE_LICENSE("GPL");
4706 MODULE_DESCRIPTION("Creative Sound Core3D codec");
4707
4708 static struct hda_codec_preset_list ca0132_list = {
4709 .preset = snd_hda_preset_ca0132,
4710 .owner = THIS_MODULE,
4711 };
4712
4713 static int __init patch_ca0132_init(void)
4714 {
4715 return snd_hda_add_codec_preset(&ca0132_list);
4716 }
4717
4718 static void __exit patch_ca0132_exit(void)
4719 {
4720 snd_hda_delete_codec_preset(&ca0132_list);
4721 }
4722
4723 module_init(patch_ca0132_init)
4724 module_exit(patch_ca0132_exit)
kernel source for telekom puls (alcatel/mediatek)