include/mach/mt_pwm.h

   1 /*******************************************************************************
   2 * mt6575_pwm.h PWM Drvier
   3 *
   4 * Copyright (c) 2010, Media Teck.inc
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public Licence,
   8 * version 2, as publish by the Free Software Foundation.
   9 *
  10 * This program is distributed and in hope it will be useful, but WITHOUT
  11 * ANY WARRNTY; without even the implied warranty of MERCHANTABITLITY or
  12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13 * more details.
  14 *
  15 *
  16 ********************************************************************************
  17 * Author : Chagnlei Gao (changlei.gao@mediatek.com)
  18 ********************************************************************************
  19 */
  20
  21 #ifndef __MT_PWM_H__
  22 #define __MT_PWM_H__
  23
  24 #include <mach/mt_typedefs.h>
  25 #include <mach/mt_pwm_hal.h>
  26
  27 struct pwm_easy_config {
  28         U32 pwm_no;
  29         U32 duty;
  30         U32 clk_src;
  31         U32 clk_div;
  32         U16 duration;
  33         BOOL pmic_pad;
  34 };
  35 struct pwm_spec_config {
  36         U32 pwm_no;
  37         U32 mode;
  38         U32 clk_div;
  39         U32 clk_src;
  40         BOOL intr;
  41         BOOL pmic_pad;
  42
  43         union {
  44                 /* for old mode */
  45                 struct _PWM_OLDMODE_REGS {
  46                         U16 IDLE_VALUE;
  47                         U16 GUARD_VALUE;
  48                         U16 GDURATION;
  49                         U16 WAVE_NUM;
  50                         U16 DATA_WIDTH;
  51                         U16 THRESH;
  52                 } PWM_MODE_OLD_REGS;
  53
  54                 /* for fifo mode */
  55                 struct _PWM_MODE_FIFO_REGS {
  56                         U32 IDLE_VALUE;
  57                         U32 GUARD_VALUE;
  58                         U32 STOP_BITPOS_VALUE;
  59                         U16 HDURATION;
  60                         U16 LDURATION;
  61                         U32 GDURATION;
  62                         U32 SEND_DATA0;
  63                         U32 SEND_DATA1;
  64                         U32 WAVE_NUM;
  65                 } PWM_MODE_FIFO_REGS;
  66 /*
  67                 //for memory mode
  68                 struct _PWM_MODE_MEMORY_REGS {
  69                         U32 IDLE_VALUE;
  70                         U32 GUARD_VALUE;
  71                         U32 STOP_BITPOS_VALUE;
  72                         U16 HDURATION;
  73                         U16 LDURATION;
  74                         U16 GDURATION;
  75                         U32  * BUF0_BASE_ADDR;
  76                         U32 BUF0_SIZE;
  77                         U16 WAVE_NUM;
  78                 }PWM_MODE_MEMORY_REGS;
  79
  80                 //for RANDOM mode
  81                 struct _PWM_MODE_RANDOM_REGS {
  82                         U16 IDLE_VALUE;
  83                         U16 GUARD_VALUE;
  84                         U32 STOP_BITPOS_VALUE;
  85                         U16 HDURATION;
  86                         U16 LDURATION;
  87                         U16 GDURATION;
  88                         U32  * BUF0_BASE_ADDR;
  89                         U32 BUF0_SIZE;
  90                         U32 *BUF1_BASE_ADDR;
  91                         U32 BUF1_SIZE;
  92                         U16 WAVE_NUM;
  93                         U32 VALID;
  94                 }PWM_MODE_RANDOM_REGS;
  95
  96                 //for seq mode
  97                 struct _PWM_MODE_DELAY_REGS {
  98                         //U32 ENABLE_DELAY_VALUE;
  99                         U16 PWM3_DELAY_DUR;
 100                         U32 PWM3_DELAY_CLK;   //0: block clock source, 1: block/1625 clock source
 101                         U16 PWM4_DELAY_DUR;
 102                         U32 PWM4_DELAY_CLK;
 103                         U16 PWM5_DELAY_DUR;
 104                         U32 PWM5_DELAY_CLK;
 105                 }PWM_MODE_DELAY_REGS;
 106 */
 107         };
 108 };
 109
 110 S32 pwm_set_easy_config(struct pwm_easy_config *conf);
 111 S32 pwm_set_spec_config(struct pwm_spec_config *conf);
 112
 113 void mt_pwm_dump_regs(void);
 114 void mt_pwm_disable(U32 pwm_no, BOOL pmic_pad);
 115
 116 /*----------3dLCM support-----------*/
 117 void mt_set_pwm_3dlcm_enable(BOOL enable);
 118 /*
 119  set "pwm_no" inversion of pwm base or not
 120  */
 121 void mt_set_pwm_3dlcm_inv(U32 pwm_no, BOOL inv);
 122 //void mt_set_pwm_3dlcm_base(U32 pwm_no);
 123
 124 //void mt_pwm_26M_clk_enable(U32 enable);
 125 #endif