include/linux/pmic6326_sw.h

   1 /*****************************************************************************
   2  *
   3  * Filename:
   4  * ---------
   5  *    pmic6326_sw.h
   6  *
   7  * Project:
   8  * --------
   9  *   Maui_Software
  10  *
  11  * Description:
  12  * ------------
  13  *   This file is intended for PMIC 6326 driver.
  14  *
  15  * Author:
  16  * -------
  17  *  mtk01845
  18  *
  19  *============================================================================
  20  *             HISTORY
  21  * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
  22  *------------------------------------------------------------------------------
  23  * $Revision$
  24  * $Modtime:   20 Jun 2005 20:03:54  $
  25  * $Log:   //mtkvs01/vmdata/Maui_sw/archives/mcu/drv/src/gpt.c-arc  $
  26  *
  27  * 08 09 2010 chipeng.chang
  28  * [ALPS00003297] [Need Patch] [Volunteer Patch] android 2.2 migration
  29  * remove .o and add header file.
  30  *
  31  * Feb 5 2009 mtk01845
  32  * [MAUI_01624867] [Drv] PMIC6326 ECO version compatible support
  33  *
  34  *
  35  * Jan 19 2009 mtk01845
  36  * [MAUI_01314361] [Drv]MT6268 check to MAUI
  37  *
  38  *
  39  * Sep 12 2008 mtk01845
  40  * [MAUI_00803843] [Drv][PMIC6326] Check-in to MAUI
  41  *
  42  *
  43  * Sep 2 2008 mtk01845
  44  * [MAUI_01231139] [Drv][PMIC6326] Redundent custom APIs cause MoDIS link error
  45  *
  46  *
  47  * Aug 29 2008 mtk01845
  48  * [MAUI_00803843] [Drv][PMIC6326] Check-in to MAUI
  49  *
  50  *
  51  * Aug 6 2008 mtk01845
  52  * [MAUI_00803843] [Drv][PMIC6326] Check-in to MAUI
  53  *
  54  *
  55  * Aug 5 2008 mtk01845
  56  * [MAUI_00803843] [Drv][PMIC6326] Check-in to MAUI
  57  *
  58  *
  59  * Jul 13 2008 mtk01845
  60  * [MAUI_00803843] [Drv][PMIC6326] Check-in to MAUI
  61  *
  62  *
  63  * Jun 23 2008 mtk01845
  64  * [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
  65  *
  66  *
  67  * Jun 23 2008 mtk01845
  68  * [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
  69  *
  70  *
  71  * Jun 23 2008 mtk01845
  72  * [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
  73  *
  74  *
  75  * Jun 20 2008 mtk01845
  76  * [MAUI_00791553] [Drv] MT6268A merge DVT code back to MAUI
  77  *
  78 *------------------------------------------------------------------------------
  79  * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
  80  *============================================================================
  81  ****************************************************************************/
  82
  83 #ifndef __PMIC6326_SW_H__
  84 #define __PMIC6326_SW_H__
  85 /* #include "pmic_features.h" */
  86
  87
  88 #ifndef __PRODUCTION_RELEASE__
  89 /* Define to keep chaging when assert */
  90 /* This flag is only for debug purpose */
  91 /* #define DRV_MISC_PMIC_ASSERT_KEEP_CHARGING */
  92 #endif                          /* #ifndef __PRODUCTION_RELEASE__ */
  93
  94
  95 #ifdef __PRODUCTION_RELEASE__
  96 /* Define to enable PMIC6326 charger watch dog timer kick */
  97 /* When enable charger, PMIC6326 will enable a watch dog timer */
  98 /* We need to kick the timer periodically, to ontify PMIC6326 that BB is alive */
  99 /* If timeout, PMIC6326 will disable charge automatically */
 100 /* #### If this is NOT enabled, we will disable the watch dog timer function at boot time */
 101 #define ENABLE_KICK_PMIC6326_CHARGER_WATCHDOG_TIMER
 102 #endif                          /* #ifdef __PRODUCTION_RELEASE__ */
 103
 104
 105
 106 #define PMIC6326_ECO_1_VERSION          0x01
 107 #define PMIC6326_ECO_2_VERSION          0x02
 108 #define PMIC6326_ECO_3_VERSION          0x03
 109 #define PMIC6326_ECO_4_VERSION          0x04
 110
 111
 112 typedef struct {
 113         void (*pmic_ac_det) (void);
 114         void (*pmic_usb_det) (void);
 115 } pmic6326_chrdect_callbac_struct;
 116
 117
 118
 119 /* TTTTTTTTTTTTTTTTT */
 120 /* Implemented functions */
 121
 122
 123
 124 /* (0x0D) INT STATUS 3 (RO) */
 125 typedef enum {
 126         VSDIO_OC_STAT = 0x01,   /* BIT0 */
 127         VGP_OC_STAT = 0x02,     /* BIT1 */
 128         VUSB_OC_STAT = 0x04,    /* BIT2 */
 129         OVP_INT_STAT = 0x08,    /* BIT3 */
 130         CHRDET_INT_STAT = 0x10, /* BIT4 */
 131         PWRKEY_INT_STAT = 0x20  /* BIT5 */
 132 } int_state_3_enum;
 133
 134
 135 /* (0x1B) LDO CTRL 2 VRF */
 136 typedef enum {
 137         VRF_BIAS_CURRENT_TIMES_1_0 = 0,
 138         VRF_BIAS_CURRENT_TIMES_0_5,
 139         VRF_BIAS_CURRENT_TIMES_2_0,
 140         VRF_BIAS_CURRENT_TIMES_3_0
 141 } vrf_ical_en_enum;
 142
 143 /* (0x1C) LDO CTRL 3 VRF */
 144 typedef enum {
 145         VRF_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 146         VRF_MAX_SLEW_RATE_TIMES_1_OVER_21,
 147         VRF_MAX_SLEW_RATE,
 148         VRF_MAX_SLEW_RATE_TIMES_1_OVER_5
 149 } vrf_calst_enum;
 150 typedef enum {
 151         VRF_OC_THRESHOLD_685MA = 0,
 152         VRF_OC_THRESHOLD_635MA,
 153         VRF_OC_THRESHOLD_785MA,
 154         VRF_OC_THRESHOLD_735MA
 155 } vrf_caloc_enum;
 156
 157 typedef enum {
 158         VRF_DEFAULT_MILLER_CAPACITOR = 0,
 159         VRF_INCREASE_MILLER_CAPACITOR
 160 } vrf_cm_enum;
 161
 162 typedef enum {
 163         VRF_ENABLE_WITH_SRCLKEN = 0,
 164         VRF_ENABLE_WITH_VRF_EN
 165 } vrf_on_sel_enum;
 166
 167
 168 /* (0x1E) LDO CTRL 5 VTCXO */
 169 typedef enum {
 170         VTCXO_BIAS_CURRENT_TIMES_1_0 = 0,
 171         VTCXO_BIAS_CURRENT_TIMES_0_5,
 172         VTCXO_BIAS_CURRENT_TIMES_2_0,
 173         VTCXO_BIAS_CURRENT_TIMES_3_0
 174 } vtcxo_ical_en_enum;
 175
 176
 177 /* (0x1F) LDO CTRL 6 VTCXO */
 178 typedef enum {
 179         VTCXO_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 180         VTCXO_MAX_SLEW_RATE_TIMES_1_OVER_21,
 181         VTCXO_MAX_SLEW_RATE,
 182         VTCXO_MAX_SLEW_RATE_TIMES_1_OVER_5
 183 } vtcxo_calst_enum;
 184 typedef enum {
 185         VTCXO_OC_THRESHOLD_100MA = 0,
 186         VTCXO_OC_THRESHOLD_109MA,
 187         VTCXO_OC_THRESHOLD_82MA,
 188         VTCXO_OC_THRESHOLD_91MA
 189 } vtcxo_caloc_enum;
 190
 191 typedef enum {
 192         VTCXO_ENABLE_WITH_SRCLKEN = 0,
 193         VTCXO_ENABLE_WITH_VTCXO_EN
 194 } vtcxo_on_sel_enum;
 195
 196 typedef enum {
 197         VTCXO_DEFAULT_MILLER_CAPACITOR = 0,
 198         VTCXO_INCREASE_MILLER_CAPACITOR
 199 } vtcxo_cm_enum;
 200
 201 /* (0x21) LDO CTRL 8 V3GTX */
 202 typedef enum {
 203         V3GTX_BIAS_CURRENT_TIMES_1_0 = 0,
 204         V3GTX_BIAS_CURRENT_TIMES_0_5,
 205         V3GTX_BIAS_CURRENT_TIMES_2_0,
 206         V3GTX_BIAS_CURRENT_TIMES_3_0
 207 } v3gtx_ical_en_enum;
 208
 209 typedef enum {
 210         V3GTX_2_8 = 0,
 211         V3GTX_3_0,
 212         V3GTX_3_3,
 213         V3GTX_2_5
 214 } v3gtx_vol;
 215
 216
 217 /* (0x22) LDO CTRL 9 V3GTX */
 218 typedef enum {
 219         V3GTX_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 220         V3GTX_MAX_SLEW_RATE_TIMES_1_OVER_21,
 221         V3GTX_MAX_SLEW_RATE,
 222         V3GTX_MAX_SLEW_RATE_TIMES_1_OVER_5
 223 } v3gtx_calst_enum;
 224
 225 typedef enum {
 226         V3GTX_OC_THRESHOLD_400MA = 0,
 227         V3GTX_OC_THRESHOLD_438MA,
 228         V3GTX_OC_THRESHOLD_324MA,
 229         V3GTX_OC_THRESHOLD_362MA
 230 } v3gtx_caloc_enum;
 231
 232 typedef enum {
 233         V3GTX_ENABLE_WITH_SRCLKEN = 0,
 234         V3GTX_ENABLE_WITH_V3GTX_EN
 235 } v3gtx_on_sel_enum;
 236
 237
 238 /* (0x24) LDO CTRL 11 V3GRX */
 239 typedef enum {
 240         V3GRX_2_8 = 0,
 241         V3GRX_3_0,
 242         V3GRX_3_3,
 243         V3GRX_2_5
 244 } v3grx_vol;
 245
 246 typedef enum {
 247         V3GRX_BIAS_CURRENT_TIMES_1_0 = 0,
 248         V3GRX_BIAS_CURRENT_TIMES_0_5,
 249         V3GRX_BIAS_CURRENT_TIMES_2_0,
 250         V3GRX_BIAS_CURRENT_TIMES_3_0
 251 } v3grx_ical_en_enum;
 252
 253
 254 /* (0x25) LDO CTRL 12 V3GRX */
 255 typedef enum {
 256         V3GRX_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 257         V3GRX_MAX_SLEW_RATE_TIMES_1_OVER_21,
 258         V3GRX_MAX_SLEW_RATE,
 259         V3GRX_MAX_SLEW_RATE_TIMES_1_OVER_5
 260 } v3grx_calst_enum;
 261
 262 typedef enum {
 263         V3GRX_OC_THRESHOLD_200MA = 0,
 264         V3GRX_OC_THRESHOLD_219MA,
 265         V3GRX_OC_THRESHOLD_162MA,
 266         V3GRX_OC_THRESHOLD_181MA
 267 } v3grx_caloc_enum;
 268
 269
 270 typedef enum {
 271         V3GRX_ENABLE_WITH_SRCLKEN = 0,
 272         V3GRX_ENABLE_WITH_V3GRX_EN
 273 } v3grx_on_sel_enum;
 274
 275
 276 /* (0x2E) LDO CTRL 21 VCAMA */
 277 typedef enum {
 278         VCAMA_2_8 = 0,
 279         VCAMA_2_5,
 280         VCAMA_1_8,
 281         VCAMA_1_5
 282 } vcama_sel_enum;
 283 typedef enum {
 284         VCAMA_BIAS_CURRENT_X_1_0 = 0,
 285         VCAMA_BIAS_CURRENT_X_0_5,
 286         VCAMA_BIAS_CURRENT_X_2_0,
 287         VCAMA_BIAS_CURRENT_X_3_0
 288 } vcama_ical_en_enum;
 289
 290 /* (0x2F) LDO CTRL 22 VCAMA */
 291 typedef enum {
 292         VCAMA_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 293         VCAMA_MAX_SLEW_RATE_TIMES_1_OVER_21,
 294         VCAMA_MAX_SLEW_RATE,
 295         VCAMA_MAX_SLEW_RATE_TIMES_1_OVER_5
 296 } vcama_calst_enum;
 297 typedef enum {
 298         VCAMA_OC_THRESHOLD_500MA = 0,
 299         VCAMA_OC_THRESHOLD_548MA,
 300         VCAMA_OC_THRESHOLD_405MA,
 301         VCAMA_OC_THRESHOLD_452MA
 302 } vcama_caloc_enum;
 303
 304 typedef enum {
 305         VCAMA_DEFAULT_MILLER_CAPACITOR = 0,
 306         VCAMA_INCREASE_MILLER_CAPACITOR
 307 } vcama_cm_enum;
 308
 309 /* (0x31) LDO CTRL 24 VWIFI3V3 */
 310 typedef enum {
 311         VWIFI3V3_2_8 = 0,
 312         VWIFI3V3_3_0,
 313         VWIFI3V3_3_3,
 314         VWIFI3V3_2_5
 315 } vwifi3v3_sel_enum;
 316 typedef enum {
 317         VWIFI3V3_BIAS_CURRENT_X_1_0 = 0,
 318         VWIFI3V3_BIAS_CURRENT_X_0_5,
 319         VWIFI3V3_BIAS_CURRENT_X_2_0,
 320         VWIFI3V3_BIAS_CURRENT_X_3_0
 321 } vwifi3v3_ical_en_enum;
 322
 323 /* (0x32) LDO CTRL 25 VWIFI3V3 */
 324 typedef enum {
 325         VWIFI3V3_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 326         VWIFI3V3_MAX_SLEW_RATE_TIMES_1_OVER_21,
 327         VWIFI3V3_MAX_SLEW_RATE,
 328         VWIFI3V3_MAX_SLEW_RATE_TIMES_1_OVER_5
 329 } vwifi3v3_calst_enum;
 330 typedef enum {
 331         VWIFI3V3_OC_THRESHOLD_600MA = 0,
 332         VWIFI3V3_OC_THRESHOLD_657MA,
 333         VWIFI3V3_OC_THRESHOLD_486MA,
 334         VWIFI3V3_OC_THRESHOLD_543MA
 335 } vwifi3v3_caloc_enum;
 336
 337 typedef enum {
 338         VWIFI3V3_DEFAULT_MILLER_CAPACITOR = 0,
 339         VWIFI3V3_INCREASE_MILLER_CAPACITOR
 340 } vwifi3v3_cm_enum;
 341
 342 /* (0x34) LDO CTRL 27 VWIFI2V8 */
 343 typedef enum {
 344         VWIFI2V8_2_8 = 0,
 345         VWIFI2V8_3_0,
 346         VWIFI2V8_3_3,
 347         VWIFI2V8_2_5
 348 } vwifi2v8_sel_enum;
 349 typedef enum {
 350         VWIFI2V8_BIAS_CURRENT_X_1_0 = 0,
 351         VWIFI2V8_BIAS_CURRENT_X_0_5,
 352         VWIFI2V8_BIAS_CURRENT_X_2_0,
 353         VWIFI2V8_BIAS_CURRENT_X_3_0
 354 } vwifi2v8_ical_en_enum;
 355
 356 /* (0x35) LDO CTRL 28 VWIFI2V8 */
 357 typedef enum {
 358         VWIFI2V8_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 359         VWIFI2V8_MAX_SLEW_RATE_TIMES_1_OVER_21,
 360         VWIFI2V8_MAX_SLEW_RATE,
 361         VWIFI2V8_MAX_SLEW_RATE_TIMES_1_OVER_5
 362 } vwifi2v8_calst_enum;
 363 typedef enum {
 364         VWIFI2V8_OC_THRESHOLD_300MA = 0,
 365         VWIFI2V8_OC_THRESHOLD_329MA,
 366         VWIFI2V8_OC_THRESHOLD_243MA,
 367         VWIFI2V8_OC_THRESHOLD_271MA
 368 } vwifi2v8_caloc_enum;
 369
 370 typedef enum {
 371         VWIFI2V8_DEFAULT_MILLER_CAPACITOR = 0,
 372         VWIFI2V8_INCREASE_MILLER_CAPACITOR
 373 } vwifi2v8_cm_enum;
 374
 375 /* (0x37) LDO CTRL 30 VSIM */
 376 typedef enum {
 377         VSIM_1_3V = 0,
 378         VSIM_1_5V,
 379         VSIM_1_8V,
 380         VSIM_2_5V,
 381         VSIM_2_8V,
 382         VSIM_3_0V,
 383         VSIM_3_3V,
 384         VSIM_1_2V
 385 } vsim_sel_enum;
 386 typedef enum {
 387         VSIM_BIAS_CURRENT_X_1_0 = 0,
 388         VSIM_BIAS_CURRENT_X_0_5,
 389         VSIM_BIAS_CURRENT_X_2_0,
 390         VSIM_BIAS_CURRENT_X_3_0
 391 } vsim_ical_en_enum;
 392
 393 /* (0x3A) LDO CTRL 33 VUSB */
 394 typedef enum {
 395         VUSB_1_3 = 0,
 396         VUSB_1_5,
 397         VUSB_1_8,
 398         VUSB_2_5,
 399         VUSB_2_8,
 400         VUSB_3_0,
 401         VUSB_3_3,
 402         VUSB_1_2                /* TTTTTTTTTTTTTT */
 403 } vusb_sel_enum;
 404 typedef enum {
 405         VUSB_BIAS_CURRENT_X_1_0 = 0,
 406         VUSB_BIAS_CURRENT_X_0_5,
 407         VUSB_BIAS_CURRENT_X_2_0,
 408         VUSB_BIAS_CURRENT_X_3_0
 409 } vusb_ical_en_enum;
 410
 411 /* (0x3B) LDO CTRL 34 VUSB */
 412 typedef enum {
 413         VUSB_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 414         VUSB_MAX_SLEW_RATE_TIMES_1_OVER_21,
 415         VUSB_MAX_SLEW_RATE,
 416         VUSB_MAX_SLEW_RATE_TIMES_1_OVER_5
 417 } vusb_calst_enum;
 418 typedef enum {
 419         VUSB_OC_THRESHOLD_200MA = 0,
 420         VUSB_OC_THRESHOLD_218MA,
 421         VUSB_OC_THRESHOLD_164MA,
 422         VUSB_OC_THRESHOLD_182MA
 423 } vusb_caloc_enum;
 424
 425 /* (0x3D) LDO CTRL 36 VBT */
 426 typedef enum {
 427         VBT_1_3 = 0,
 428         VBT_1_5,
 429         VBT_1_8,
 430         VBT_2_5,
 431         VBT_2_8,
 432         VBT_3_0,
 433         VBT_3_3,
 434         VBT_1_2                 /* TTTTTTTTTTTTTT */
 435 } vbt_sel_enum;
 436
 437 typedef enum {
 438         VBT_E3_1_5 = 0,
 439         VBT_E3_1_3,
 440         VBT_E3_2_5,
 441         VBT_E3_1_8,
 442         VBT_E3_3_0,
 443         VBT_E3_2_8,
 444         VBT_E3_3_3
 445             /* VBT_E3_3_3 */
 446 } vbt_e3_sel_enum;
 447
 448 typedef enum {
 449         VBT_BIAS_CURRENT_X_1_0 = 0,
 450         VBT_BIAS_CURRENT_X_0_5,
 451         VBT_BIAS_CURRENT_X_2_0,
 452         VBT_BIAS_CURRENT_X_3_0
 453 } vbt_ical_en_enum;
 454
 455 /* (0x3E) LDO CTRL 37 VBT */
 456 typedef enum {
 457         VBT_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 458         VBT_MAX_SLEW_RATE_TIMES_1_OVER_21,
 459         VBT_MAX_SLEW_RATE,
 460         VBT_MAX_SLEW_RATE_TIMES_1_OVER_5
 461 } vbt_calst_enum;
 462 typedef enum {
 463         VBT_OC_THRESHOLD_200MA = 0,
 464         VBT_OC_THRESHOLD_218MA,
 465         VBT_OC_THRESHOLD_164MA,
 466         VBT_OC_THRESHOLD_182MA
 467 } vbt_caloc_enum;
 468
 469 /* (0x40) LDO CTRL 39 VCAMD */
 470 typedef enum {
 471         VCAMD_1_3 = 0,
 472         VCAMD_1_5,
 473         VCAMD_1_8,
 474         VCAMD_2_5,
 475         VCAMD_2_8,
 476         VCAMD_3_0,
 477         VCAMD_3_3,
 478         VCAMD_1_2               /* TTTTTTTTTTTTTT */
 479 } vcamd_sel_enum;
 480 typedef enum {
 481         VCAMD_BIAS_CURRENT_X_1_0 = 0,
 482         VCAMD_BIAS_CURRENT_X_0_5,
 483         VCAMD_BIAS_CURRENT_X_2_0,
 484         VCAMD_BIAS_CURRENT_X_3_0
 485 } vcamd_ical_en_enum;
 486
 487 /* (0x41) LDO CTRL 40 VCAMD */
 488 typedef enum {
 489         VCAMD_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 490         VCAMD_MAX_SLEW_RATE_TIMES_1_OVER_21,
 491         VCAMD_MAX_SLEW_RATE,
 492         VCAMD_MAX_SLEW_RATE_TIMES_1_OVER_5
 493 } vcamd_calst_enum;
 494 typedef enum {
 495         VCAMD_OC_THRESHOLD_200MA = 0,
 496         VCAMD_OC_THRESHOLD_218MA,
 497         VCAMD_OC_THRESHOLD_164MA,
 498         VCAMD_OC_THRESHOLD_182MA
 499 } vcamd_caloc_enum;
 500
 501 /* (0x43) LDO CTRL 42 VGP */
 502 typedef enum {
 503         VGP_1_3 = 0,
 504         VGP_1_5,
 505         VGP_1_8,
 506         VGP_2_5,
 507         VGP_2_8,
 508         VGP_3_0,
 509         VGP_3_3
 510 } vgp_sel_enum;
 511
 512 /* (0x46) LDO CTRL 45 VSDIO */
 513 typedef enum {
 514         VSDIO_BIAS_CURRENT_X_1_0 = 0,
 515         VSDIO_BIAS_CURRENT_X_0_5,
 516         VSDIO_BIAS_CURRENT_X_2_0,
 517         VSDIO_BIAS_CURRENT_X_3_0
 518 } vsdio_ical_en_enum;
 519
 520 /* (0x47) LDO CTRL 46 VSDIO */
 521 typedef enum {
 522         VSDIO_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
 523         VSDIO_MAX_SLEW_RATE_TIMES_1_OVER_21,
 524         VSDIO_MAX_SLEW_RATE,
 525         VSDIO_MAX_SLEW_RATE_TIMES_1_OVER_5
 526 } vsdio_calst_enum;
 527 typedef enum {
 528         VSDIO_OC_THRESHOLD_700MA = 0,
 529         VSDIO_OC_THRESHOLD_767MA,
 530         VSDIO_OC_THRESHOLD_567MA,
 531         VSDIO_OC_THRESHOLD_633MA
 532 } vsdio_caloc_enum;
 533 typedef enum {
 534         VSDIO_2_8 = 0,
 535         VSDIO_3_0
 536 } vsdio_sel_enum;
 537 typedef enum {
 538         VSDIO_DEFAULT_MILLER_CAPACITOR = 0,
 539         VSDIO_INCREASE_MILLER_CAPACITOR
 540 } vsdio_cm_enum;
 541
 542
 543 /* (0x53) BUCK CTRL 11 VCORE2 */
 544 typedef enum {
 545         VCORE2_ENABLE_WITH_EN_PASS = 0,
 546         VCORE2_ENABLE_WITH_VCORE2_EN
 547 } vcore2_on_sel_enum;
 548
 549 /* (0x5C) BOOST CTRL 1 BOOST1 */
 550 typedef enum {
 551         VBOOST1_VOL_3_20_V = 0,
 552         VBOOST1_VOL_3_35_V,
 553         VBOOST1_VOL_3_50_V,
 554         VBOOST1_VOL_3_65_V,
 555         VBOOST1_VOL_3_80_V,
 556         VBOOST1_VOL_3_95_V,
 557         VBOOST1_VOL_4_10_V,
 558         VBOOST1_VOL_4_25_V,
 559         VBOOST1_VOL_4_40_V,
 560         VBOOST1_VOL_4_55_V,
 561         VBOOST1_VOL_4_70_V,
 562         VBOOST1_VOL_4_85_V,
 563         VBOOST1_VOL_5_00_V,
 564         VBOOST1_VOL_5_15_V,
 565         VBOOST1_VOL_5_30_V,
 566         VBOOST1_VOL_5_45_V
 567 } vboost1_tune_enum;
 568
 569 /* (0x5D) BOOST CTRL 2 BOOST1 */
 570 typedef enum {
 571         BOOST1_SOFT_START_SPEED = 0,
 572         BOOST1_SOFT_START_SPEED_TIMES_2_OVER_3
 573 } boost1_soft_st_speed_enum;
 574
 575 /* (0x5F) BOOST CTRL 4 BOOST2 */
 576 typedef enum {
 577         VBOOST2_VOL_6_00_V = 0,
 578         VBOOST2_VOL_6_75_V,
 579         VBOOST2_VOL_7_50_V,
 580         VBOOST2_VOL_8_25_V,
 581         VBOOST2_VOL_9_00_V,
 582         VBOOST2_VOL_9_75_V,
 583         VBOOST2_VOL_10_05_V,
 584         VBOOST2_VOL_11_25_V,
 585         VBOOST2_VOL_12_00_V,
 586         VBOOST2_VOL_12_75_V,
 587         VBOOST2_VOL_13_50_V,
 588         VBOOST2_VOL_14_25_V,
 589         VBOOST2_VOL_15_00_V,
 590         VBOOST2_VOL_15_75_V,
 591         VBOOST2_VOL_16_50_V,
 592         VBOOST2_VOL_17_25_V
 593 } vboost2_tune_enum;
 594
 595 typedef enum {
 596         BOOST2_OC_THRESHOLD_5UA = 0,
 597         BOOST2_OC_THRESHOLD_2UA,
 598         BOOST2_OC_THRESHOLD_10UA,
 599         BOOST2_OC_THRESHOLD_7UA
 600 } boost2_oc_th_enum;
 601
 602 typedef enum {
 603         BOOST2_DIGITAL_DIMING = 0,
 604         BOOST2_ANALOG_DIMING
 605 } boost2_dim_source_enum;
 606
 607 /* (0x61) BOOST CTRL 6 BOOST2 and BOOST */
 608 typedef enum {
 609         BOOST_MODE_TYPE_I = 0,
 610         BOOST_MODE_TYPE_II,
 611         BOOST_MODE_TYPE_III,
 612         BOOST_MODE_TYPE_IV
 613 } boost_mode_sel_enum;
 614
 615 /* (0x65) DRIVER CTRL 4 FLASH */
 616 /* typedef enum */
 617 /* { */
 618 /* FLASH_CURRENT_0MA=0, */
 619 /* FLASH_CURRENT_50MA, */
 620 /* FLASH_CURRENT_100MA, */
 621 /* FLASH_CURRENT_150MA, */
 622 /* FLASH_CURRENT_200MA, */
 623 /* FLASH_CURRENT_250MA, */
 624 /* FLASH_CURRENT_300MA, */
 625 /* FLASH_CURRENT_350MA, */
 626 /* FLASH_CURRENT_400MA, */
 627 /* FLASH_CURRENT_450MA, */
 628 /* FLASH_CURRENT_500MA, */
 629 /* FLASH_CURRENT_550MA */
 630 /* }flash_i_tune_enum; */
 631
 632 /* (0x68) DRIVER CTRL 7 BL */
 633 typedef enum {
 634         BL_I_CORSE_TUNE_4MA = 0,
 635         BL_I_CORSE_TUNE_8MA,
 636         BL_I_CORSE_TUNE_12MA,
 637         BL_I_CORSE_TUNE_16MA,
 638         BL_I_CORSE_TUNE_20MA,
 639         BL_I_CORSE_TUNE_24MA,
 640         BL_I_CORSE_TUNE_28MA,
 641         BL_I_CORSE_TUNE_32MA
 642 } bl_i_corse_tune_enum;
 643
 644 typedef enum {
 645         BL_I_FINE_TUNE_0MA = 0,
 646         BL_I_FINE_TUNE_MINUS_1MA,
 647         BL_I_FINE_TUNE_MINUS_2MA,
 648         BL_I_FINE_TUNE_MINUS_3MA,
 649         BL_I_FINE_TUNE_PLUS_4MA,
 650         BL_I_FINE_TUNE_PLUS_3MA,
 651         BL_I_FINE_TUNE_PLUS_2MA,
 652         BL_I_FINE_TUNE_PLUS_1MA
 653 } bl_i_fine_tune_enum;
 654
 655 /* (0x6D) DRIVER CTRL 12 BL */
 656 typedef enum {
 657         BL_NUM_1 = 0,
 658         BL_NUM_2,
 659         BL_NUM_3,
 660         BL_NUM_4,
 661         BL_NUM_5,
 662         BL_NUM_6,
 663         BL_NUM_7,
 664         BL_NUM_8
 665 } bl_number_enum;
 666
 667 /* (0x74) CLASS_D CTRL 4 SPKL */
 668 typedef enum {
 669         SPKL_FB_FORCED_DTIN_DTIP = 0,
 670         SPKL_FF_FORCED_DTIN_DTIP,
 671         SPKL_FB_AUTO_CAL_DTCN_DTCP,
 672         SPKL_FF_AUTO_CAL_DTCN_DTCP
 673 } spkl_dmode_enum;
 674
 675 typedef enum {
 676         SPKL_DTCAL_ENABLE_CLASS_D_R_READ_TIME_CAL = 0,
 677         SPKL_DTCAL_DISABLE_CLASS_D_R_READ_TIME_CAL
 678 } spkl_dtcal_enum;
 679
 680 /* (0x79) CLASS_D CTRL 9 SPKR */
 681 typedef enum {
 682         SPKR_FB_FORCED_DTIN_DTIP = 0,
 683         SPKR_FF_FORCED_DTIN_DTIP,
 684         SPKR_FB_AUTO_CAL_DTCN_DTCP,
 685         SPKR_FF_AUTO_CAL_DTCN_DTCP
 686 } spkr_dmode_enum;
 687
 688 typedef enum {
 689         SPKR_DTCAL_ENABLE_CLASS_D_R_READ_TIME_CAL = 0,
 690         SPKR_DTCAL_DISABLE_CLASS_D_R_READ_TIME_CAL
 691 } spkr_dtcal_enum;
 692
 693 /* (0x81) CHARGER CTRL 1 */
 694 typedef enum {
 695         CHR_CURRENT_OFFSET_NO = 0,
 696         CHR_CURRENT_OFFSET_PLUS_1_STEP = 1,
 697         CHR_CURRENT_OFFSET_PLUS_2_STEP = 2,
 698         CHR_CURRENT_OFFSET_MINUS_2_STEP = 6,
 699         CHR_CURRENT_OFFSET_MINUS_1_STEP = 7
 700 } cht_chr_offset_enum;
 701
 702 typedef enum {
 703         CHR_CURRENT_50MA = 0,
 704         CHR_CURRENT_90MA,
 705         CHR_CURRENT_150MA,
 706         CHR_CURRENT_225MA,
 707         CHR_CURRENT_300MA,
 708         CHR_CURRENT_450MA,
 709         CHR_CURRENT_650MA,
 710         CHR_CURRENT_800MA
 711 } chr_chr_current_enum;
 712
 713 /* (0x83) TESTMODE CTRL 3 Analog Switch */
 714 /* typedef enum */
 715 /* { */
 716 /* ASW_ASEL_ASW_2_SETS = 0, */
 717 /* ASW_ASEL_SIMLS, */
 718 /* ASW_ASEL_ASW_1_SET, */
 719 /* ASW_ASEL_BL_CURRENT_SOURCE */
 720 /* }asw_asel_enum; */
 721 typedef enum {
 722         ASW_ASEL_ISINK_6_8_AS = 0,      /* ISINK 6~8 used as Analog Switch, others for BL */
 723         ASW_ASEL_ALL_ISINK_BL = 3       /* All ISINK used for BL */
 724 } asw_asel_enum;
 725
 726
 727 typedef enum {
 728         HI_Z = 0,
 729         RECEIVER,
 730         TWO_OF_RGB_DRIVER
 731             /* TODO, the last item value */
 732 } asw_bsel_enum;
 733
 734 /* (0x84) TESTMODE CTRL 4 Testmode */
 735 typedef enum {
 736         VGP2_ENABLE_WITH_SRCLKEN = 0,
 737         VGP2_ENABLE_WITH_VGP2_EN
 738 } vgp2_on_sel_enum;
 739
 740
 741 /* (0x89) INT CTRL 1 */
 742 typedef enum {
 743         INT_EN_VCORE2_OC = 0x01,
 744         INT_EN_VPA_OC = 0x02,
 745         INT_EN_BOOST1_OC = 0x04,
 746         INT_EN_BOOST2_OC = 0x08,
 747         INT_EN_SPKL_OC = 0x10,
 748         INT_EN_SPKR_OC = 0x20,
 749         INT_EN_V3GTX_OC = 0x40,
 750         INT_EN_V3GRX_OC = 0x80,
 751         INT_EN_0X89_ALL = 0xFF,
 752         INT1_EN_ALL = 0xFF
 753 } int_ctrl_1_enum;
 754
 755 /* (0x8A) INT CTRL 2 */
 756 typedef enum {
 757         INT_EN_RF_OC = 0x01,
 758         INT_EN_VTCXO_OC = 0x02,
 759         INT_EN_VCAMA_OC = 0x04,
 760         INT_EN_VWIFI3V3_OC = 0x08,
 761         INT_EN_VWIFI2V8_OC = 0x10,
 762         INT_EN_VSIM_OC = 0x20,
 763         INT_EN_VBT_OC = 0x40,
 764         INT_EN_VCAMD_OC = 0x80,
 765         INT_EN_0X8A_ALL = 0xFF,
 766         INT2_EN_ALL = 0xFF
 767 } int_ctrl_2_enum;
 768
 769 /* (0x8B) INT CTRL 3 */
 770 typedef enum {
 771         INT_EN_VSDIO_OC = 0x01,
 772         INT_EN_VGP_OC = 0x02,
 773         INT_EN_VUSB_OC = 0x04,
 774         INT_EN_CHRDET = 0x08,
 775         INT_EN_OVP = 0x10,
 776         INT_EN_WATCHDOG = 0x20,
 777         INT_EN_PWRKEY = 0x40,
 778         INT_EN_0X8B_ALL = 0x7F,
 779         INT3_EN_ALL = 0x7F
 780 } int_ctrl_3_enum;
 781
 782
 783 /* (0x96) WATCHDOG CTRL and INT CTRL 4 */
 784 typedef enum {
 785         WDT_TIMEOUT_4_SEC = 0,
 786         WDT_TIMEOUT_8_SEC,
 787         WDT_TIMEOUT_16_SEC,
 788         WDT_TIMEOUT_32_SEC
 789 } wdt_timout_enum;
 790
 791
 792 /* Combinational functions structures */
 793 typedef enum {
 794         VGP2_1_3 = 0,
 795         VGP2_1_5,
 796         VGP2_1_8,
 797         VGP2_2_5,
 798         VGP2_2_8,
 799         VGP2_3_0,
 800         VGP2_3_3
 801 } vgp2_sel_enum;
 802
 803
 804 #if 0
 805 void pmic_init(void);
 806
 807
 808 /* (0x09) STATUS 6 (RO) */
 809 extern kal_bool pmic_boost2_oc_status(void);
 810 extern kal_bool pmic_spkr_oc_det_status(void);
 811 extern kal_bool pmic_spkl_oc_det_status(void);
 812 extern kal_bool pmic_pwrkey_deb_status(void);
 813 extern kal_bool pmic_ovp_status(void);
 814 extern kal_bool pmic_chrdet_status(void);
 815 extern kal_bool pmic_bat_on_status(void);
 816 extern kal_bool pmic_cv_status(void);
 817
 818 /* (0x0D) INT STATUS 3 (RO) */
 819 extern kal_uint8 pmic_int_status_3(void);
 820 extern kal_bool pmic_vsdio_oc_int_status(void);
 821 extern kal_bool pmic_vgp_oc_int_status(void);
 822 extern kal_bool pmic_vusb_oc_int_status(void);
 823 extern kal_bool pmic_ovp_int_status(void);
 824 extern kal_bool pmic_chrdet_int_status(void);
 825
 826
 827 /* (0x0E) INT STATUS 4 (RO) */
 828 extern kal_uint8 pmic_int_status_4(void);
 829 extern kal_bool pmic_watchdog_int_status(void);
 830 extern void pmic_watchdog_clear(void);
 831
 832 /* (0x1B) LDO CTRL 2 VRF */
 833 extern void pmic_vrf_ical_en(vrf_ical_en_enum sel);
 834 extern void pmic_vrf_oc_auto_off(kal_bool auto_off);
 835 extern void pmic_vrf_enable(kal_bool enable);
 836 extern void pmic_vrf_cal(kal_uint8 val);
 837
 838 /* (0x1C) LDO CTRL 3 VRF */
 839 extern void pmic_vrf_calst(vrf_calst_enum sel);
 840 extern void pmic_vrf_caloc(vrf_caloc_enum sel);
 841 extern void pmic_vrf_on_sel(vrf_on_sel_enum sel);
 842 extern void pmic_vrf_en_force(kal_bool enable);
 843 extern void pmic_vrf_plnmos_dis(kal_bool disable);
 844 extern void pmic_vrf_cm(vrf_cm_enum sel);
 845
 846 /* (0x1E) LDO CTRL 5 VTCXO */
 847 extern void pmic_vtcxo_ical_en(vtcxo_ical_en_enum sel);
 848 extern void pmic_vtcxo_oc_auto_off(kal_bool auto_off);
 849 extern void pmic_vtcxo_enable(kal_bool enable);
 850 extern void pmic_vtcxo_cal(kal_uint8 val);
 851
 852 /* (0x1F) LDO CTRL 6 VTCXO */
 853 extern void pmic_vtcxo_calst(vtcxo_calst_enum sel);
 854 extern void pmic_vtcxo_caloc(vtcxo_caloc_enum sel);
 855 extern void pmic_vtcxo_on_sel(vtcxo_on_sel_enum sel);
 856 extern void pmic_vtcxo_en_force(kal_bool enable);
 857 extern void pmic_vtcxo_plnmos_dis(kal_bool disable);
 858 extern void pmic_vtcxo_cm(vtcxo_cm_enum sel);
 859
 860 /* (0x21) LDO CTRL 8 V3GTX */
 861 extern void pmic_v3gtx_sel(v3gtx_vol vol);
 862 extern void pmic_v3gtx_ical_en(v3gtx_ical_en_enum sel);
 863 extern void pmic_v3gtx_cal(kal_uint8 val);
 864
 865 /* (0x22) LDO CTRL 9 V3GTX */
 866 extern void pmic_v3gtx_calst(v3gtx_calst_enum sel);
 867 extern void pmic_v3gtx_caloc(v3gtx_caloc_enum sel);
 868 extern void pmic_v3gtx_oc_auto_off(kal_bool auto_off);
 869 extern void pmic_v3gtx_enable(kal_bool enable);
 870 extern void pmic_v3gtx_on_sel(v3gtx_on_sel_enum sel);
 871 extern void pmic_v3gtx_en_force(kal_bool enable);
 872
 873 /* (0x24) LDO CTRL 11 V3GRX */
 874 extern void pmic_v3grx_sel(v3grx_vol vol);
 875 extern void pmic_3grx_ical_en(v3grx_ical_en_enum sel);
 876 extern void pmic_v3grx_cal(kal_uint8 val);
 877
 878 /* (0x25) LDO CTRL 12 V3GRX */
 879 extern void pmic_v3grx_calst(v3grx_calst_enum sel);
 880 extern void pmic_v3grx_caloc(v3grx_caloc_enum sel);
 881 extern void pmic_v3grx_oc_auto_off(kal_bool auto_off);
 882 extern void pmic_v3grx_enable(kal_bool enable);
 883 extern void pmic_v3grx_on_sel(v3grx_on_sel_enum sel);
 884 extern void pmic_v3grx_en_force(kal_bool enable);
 885
 886 /* (0x2E) LDO CTRL 21 VCAMA */
 887 extern void pmic_vcama_sel(vcama_sel_enum sel);
 888 extern void pmic_vcama_ical_en(vcama_ical_en_enum sel);
 889 extern void pmic_vcama_cal(kal_uint8 val);
 890
 891 /* (0x2F) LDO CTRL 22 VCAMA */
 892 extern void pmic_vcama_calst(vcama_calst_enum sel);
 893 extern void pmic_vcama_caloc(vcama_caloc_enum sel);
 894 extern void pmic_vcama_enable(kal_bool enable);
 895 extern void pmic_vcama_en_force(kal_bool enable);
 896 extern void pmic_vcama_plnmos_dis(kal_bool disable);
 897 extern void pmic_vcama_cm(vcama_cm_enum sel);
 898
 899 /* (0x31) LDO CTRL 24 VWIFI3V3 */
 900 extern void pmic_vwifi3v3_sel(vwifi3v3_sel_enum sel);
 901 extern void pmic_vwifi3v3_ical_en(vwifi3v3_ical_en_enum sel);
 902 extern void pmic_vwifi3v3_cal(kal_uint8 val);
 903
 904 /* (0x32) LDO CTRL 25 VWIFI3V3 */
 905 extern void pmic_vwifi3v3_calst(vwifi3v3_calst_enum sel);
 906 extern void pmic_vwifi3v3_caloc(vwifi3v3_caloc_enum sel);
 907 extern void pmic_vwifi3v3_enable(kal_bool enable);
 908 extern void pmic_vwifi3v3_en_force(kal_bool enable);
 909 extern void pmic_vwifi3v3_plnmos_dis(kal_bool disable);
 910 extern void pmic_vwifi3v3_cm(vwifi3v3_cm_enum sel);
 911
 912 /* (0x34) LDO CTRL 27 VWIFI2V8 */
 913 extern void pmic_vwifi2v8_sel(vwifi2v8_sel_enum sel);
 914 extern void pmic_vwifi2v8_ical_en(vwifi2v8_ical_en_enum sel);
 915 extern void pmic_vwifi2v8_cal(kal_uint8 val);
 916
 917 /* (0x35) LDO CTRL 28 VWIFI2V8 */
 918 extern void pmic_vwifi2v8_calst(vwifi2v8_calst_enum sel);
 919 extern void pmic_vwifi2v8_caloc(vwifi2v8_caloc_enum sel);
 920 extern void pmic_vwifi2v8_enable(kal_bool enable);
 921 extern void pmic_vwifi2v8_en_force(kal_bool enable);
 922 extern void pmic_vwifi2v8_plnmos_dis(kal_bool disable);
 923 extern void pmic_vwifi2v8_cm(vwifi2v8_cm_enum sel);
 924
 925 /* (0x37) LDO CTRL 30 VSIM */
 926 /* void pmic_vsim_sel(vsim_sel_enum sel); */
 927 extern void pmic6326_vsim_sel(vsim_sel_enum sel);
 928 extern void pmic6326_vsim_sel(vsim_sel_enum sel);
 929 extern void pmic_vsim_enable(kal_bool enable);
 930 extern void pmic_vsim_ical_en(vsim_ical_en_enum sel);
 931 extern void pmic_vsim_en_force(kal_bool enable);
 932 extern void pmic_vsim_plnmos_dis(kal_bool disable);
 933
 934 /* (0x38) LDO CTRL 31 VSIM */
 935 extern void pmic_vsim_cal(kal_uint8 val);
 936
 937 /* (0x3A) LDO CTRL 33 VUSB */
 938 /* USB voltage is NOT opened for change */
 939 /* extern void pmic_vusb_sel(vusb_sel_enum sel); */
 940 extern void pmic_vusb_enable(kal_bool enable);
 941 extern void pmic_vusb_ical_en(vusb_ical_en_enum sel);
 942 extern void pmic_vusb_en_force(kal_bool enable);
 943 extern void pmic_vusb_plnmos_dis(kal_bool disable);
 944
 945 /* (0x3B) LDO CTRL 34 VUSB */
 946 extern void pmic_vusb_cal(kal_uint8 val);
 947 extern void pmic_vusb_calst(vusb_calst_enum sel);
 948 extern void pmic_vusb_caloc(vusb_caloc_enum sel);
 949
 950 /* (0x3D) LDO CTRL 36 VBT */
 951 extern void pmic_vbt_sel(vbt_sel_enum sel);
 952 extern void pmic_vbt_enable(kal_bool enable);
 953 extern void pmic_vbt_ical_en(vbt_ical_en_enum sel);
 954 extern void pmic_vbt_en_force(kal_bool enable);
 955 extern void pmic_vbt_plnmos_dis(kal_bool disable);
 956
 957 /* (0x3E) LDO CTRL 37 VBT */
 958 extern void pmic_vbt_cal(kal_uint8 val);
 959 extern void pmic_vbt_calst(vbt_calst_enum sel);
 960 extern void pmic_vbt_caloc(vbt_caloc_enum sel);
 961
 962 /* (0x40) LDO CTRL 39 VCAMD */
 963 extern void pmic_vcamd_sel(vcamd_sel_enum sel);
 964 extern void pmic_vcamd_enable(kal_bool enable);
 965 extern void pmic_vcamd_ical_en(vcamd_ical_en_enum sel);
 966 extern void pmic_vcamd_en_force(kal_bool enable);
 967 extern void pmic_vcamd_plnmos_dis(kal_bool disable);
 968
 969 /* (0x41) LDO CTRL 40 VCAMD */
 970 extern void pmic_vcamd_cal(kal_uint8 val);
 971 extern void pmic_vcamd_calst(vcamd_calst_enum sel);
 972 extern void pmic_vcamd_caloc(vcamd_caloc_enum sel);
 973
 974 /* (0x43) LDO CTRL 42 VGP */
 975 extern void pmic_vgp_sel(vgp_sel_enum sel);
 976 extern void pmic_vgp_enable(kal_bool enable);
 977
 978 /* (0x44) LDO CTRL 43 VGP */
 979 extern void pmic_vgp_cal(kal_uint8 val);
 980
 981 /* (0x46) LDO CTRL 45 VSDIO */
 982 extern void pmic_vsdio_ical_en(vsdio_ical_en_enum sel);
 983 extern void pmic_vsdio_enable(kal_bool enable);
 984 extern void pmic_vsdio_en_force(kal_bool enable);
 985 extern void pmic_vsdio_cal(kal_uint8 val);
 986
 987 /* (0x47) LDO CTRL 46 VSDIO */
 988 extern void pmic_vsdio_calst(vsdio_calst_enum sel);
 989 extern void pmic_vsdio_caloc(vsdio_caloc_enum sel);
 990 extern void pmic_vsdio_plnmos_dis(kal_bool disable);
 991 extern void pmic_vsdio_sel(vsdio_sel_enum sel);
 992 extern void pmic_vsdio_cm(vsdio_cm_enum sel);
 993
 994 /* (0x48) LDO CTRL 47 VSDIO */
 995 extern void pmic_vcore1_dvfs_step_inc(kal_uint8 val);
 996
 997 /* (0x4E) BUCK CTRL 6 VCORE1 */
 998 extern void pmic_vcore1_dvfs_0_eco3(kal_uint8 val);
 999
1000 /* (0x4F) BUCK CTRL 7 VCORE1 */
1001 extern void pmic_vcore1_sleep_0_eco3(kal_uint8 val);
1002 extern void pmic_vcore1_dvfs_ramp_enable(kal_bool enable);
1003 extern void pmic_vcore1_dvfs_target_update(kal_bool update);
1004
1005 /* (0x51) BUCK CTRL 9 VCORE2 */
1006 extern void pmic_vcore2_dvfs_0_eco3(kal_uint8 val);
1007
1008
1009 /* (0x52) BUCK CTRL 10 VCORE2 */
1010 extern void pmic_vcore2_enable(kal_bool enable);
1011 extern void pmic_vcore2_sleep_0_eco3(kal_uint8 val);
1012
1013 /* (0x53) BUCK CTRL 11 VCORE2 */
1014 extern void pmic_vcore2_on_sel(vcore2_on_sel_enum sel);
1015
1016 /* (0x57) BUCK CTRL 15 VMEM */
1017 extern void pmic_vcore1_sleep_1_eco3(kal_uint8 val);
1018 extern void pmic_vcore1_dvfs_1_eco3(kal_uint8 val);
1019
1020 /* (0x58) BUCK CTRL 16 VPA */
1021 extern void pmic_vpa_tuneh(kal_uint8 value);
1022 extern void pmic_vpa_en_force(kal_bool enable);
1023 extern void pmic_vpa_plnmos_dis(kal_bool disable);
1024 extern void pmic_vpa_enable(kal_bool enable);
1025
1026 /* (0x59) BUCK CTRL 17 VPA */
1027 extern void pmic_vpa_tunel(kal_uint8 value);
1028
1029 /* (0x5A) BUCK CTRL 18 VPA */
1030 extern void pmic_vpa_oc_tune(kal_uint8 val);
1031
1032 /* (0x5C) BOOST CTRL 1 BOOST1 */
1033 extern void pmic_vboost1_tune(vboost1_tune_enum sel);
1034 extern void pmic_vboost1_tatt(kal_uint8 val);
1035
1036 /* (0x5D) BOOST CTRL 2 BOOST1 */
1037 extern void pmic_boost1_oc_th(kal_uint8 val);
1038 extern void pmic_boost1_enable(kal_bool enable);
1039 extern void pmic_boost1_pre_sr_con(kal_uint8 val);
1040 extern void pmic_boost1_soft_st_speed(boost1_soft_st_speed_enum sel);
1041
1042 /* (0x5E) BOOST CTRL 3 BOOST1 */
1043 extern void pmic_boost1_dio_sr_con(kal_uint8 val);
1044 extern void pmic_boost1_sync_enable(kal_bool enable);
1045
1046
1047 /* (0x5F) BOOST CTRL 4 BOOST2 */
1048 extern void pmic_boost2_tune(vboost2_tune_enum sel);
1049 extern void pmic_boots2_oc_th(boost2_oc_th_enum sel);
1050 extern void pmic_boost2_dim_source(boost2_dim_source_enum sel);
1051
1052 /* (0x60) BOOST CTRL 5 BOOST2 */
1053 extern void pmic_boost2_pre_sr_con(kal_uint8 val);
1054 extern void pmic_boost2_enable(kal_bool enable);
1055
1056 /* (0x61) BOOST CTRL 6 BOOST2 and BOOST */
1057 extern void pmic_boost_mode(boost_mode_sel_enum sel);
1058
1059 /* (0x64) DRIVER CTRL 3 GEN */
1060 extern void pmic_igen_drv_isel(kal_uint8 sel);
1061 extern void pmic_igen_drv_force(kal_bool force);
1062 extern void pmic_vgen_drv_bgsel(kal_uint8 sel);
1063
1064 /* (0x65) DRIVER CTRL 4 FLASH */
1065 extern void pmic_flash_i_tune(kal_uint8 val);
1066 extern void pmic_flash_dim_div(kal_uint8 val);
1067
1068 /* (0x66) DRIVER CTRL 5 FLASH */
1069 extern void pmic_flash_dim_duty(kal_uint8 duty);
1070 extern void pmic_flash_enable(kal_bool enable);
1071 extern void pmic_flash_bypass(kal_bool bypass);
1072
1073 /* (0x67) DRIVER CTRL 6 BL */
1074 extern void pmic_bl_dim_duty(kal_uint8 duty);
1075 extern void pmic_bl_enable(kal_bool enable);
1076 extern void pmic_bl_i_cal_enable(kal_bool enable);
1077 extern void pmic_bl_bypass(kal_bool bypass);
1078
1079 /* (0x68) DRIVER CTRL 7 BL */
1080 extern void pmic_bl_i_corse_tune(bl_i_corse_tune_enum sel);
1081 extern void pmic_bl_i_fine_tune(bl_i_fine_tune_enum sel);
1082
1083 /* (0x6D) DRIVER CTRL 12 BL */
1084 extern void pmic_bl_dim_div(kal_uint8 val);
1085 extern void pmic_bl_number(bl_number_enum num);
1086
1087 /* (0x6E) DRIVER CTRL 13 KP */
1088 extern void pmic_kp_dim_div(kal_uint8 val);
1089 extern void pmic_kp_enable(kal_bool enable);
1090
1091 /* (0x6F) DRIVER CTRL 14 KP */
1092 extern void pmic_kp_dim_duty(kal_uint8 duty);
1093
1094 /* (0x70) DRIVER CTRL 15 VIBR */
1095 extern void pmic_vibr_dim_div(kal_uint8 val);
1096 extern void pmic_vibr_enable(kal_bool enable);
1097
1098 /* (0x71) DRIVER CTRL 16 VIBR */
1099 extern void pmic_vibr_dim_duty(kal_uint8 duty);
1100
1101 /* (0x73) CLASS_D CTRL 3 SPKL */
1102 extern void pmic_spkl_dtin(kal_uint8 val);
1103 extern void pmic_spkl_dtip(kal_uint8 val);
1104
1105 /* (0x74) CLASS_D CTRL 4 SPKL */
1106 extern void pmic_spkl_dmode(spkl_dmode_enum sel);
1107 extern void pmic_spkl_enable(kal_bool enable);
1108 extern void pmic_spkl_dtcal(spkl_dtcal_enum sel);
1109
1110 /* (0x78) CLASS_D CTRL 8 SPKR */
1111 extern void pmic_spkr_dtin(kal_uint8 val);
1112 extern void pmic_spkr_dtip(kal_uint8 val);
1113
1114 /* (0x79) CLASS_D CTRL 9 SPKR */
1115 extern void pmic_spkr_dmode(spkr_dmode_enum sel);
1116 extern void pmic_spkr_enable(kal_bool enable);
1117 extern void pmic_spkr_dtcal(spkr_dtcal_enum sel);
1118
1119
1120 /* (0x81) CHARGER CTRL 1 */
1121 extern void pmic_chr_offset(cht_chr_offset_enum sel);
1122 extern void pmic_chr_ov_th_high(void);
1123 extern void pmic_chr_current(chr_chr_current_enum current);
1124
1125 /* (0x82) CHARGER CTRL 2 */
1126 extern void pmic_chr_cv_rt(void);
1127 extern void pmic_chr_force(kal_bool force);
1128 extern void pmic_chr_chr_enable(kal_bool enable);
1129 extern void pmic_chr_cv_tune(void);
1130 /* (0x83) TESTMODE CTRL 3 Analog Switch */
1131 extern void pmic_asw_asel(asw_asel_enum sel);
1132 extern void pmic_asw_bsel(asw_bsel_enum sel);
1133 extern void pmic_asw_a1sel(kal_uint8 sel);
1134 extern void pmic_asw_a2sel(kal_uint8 sel);
1135 /* (0x86) TESTMODE CTRL 6 BB AUXADC Related */
1136 extern void pmic_adc_isense_enable(kal_bool enable);
1137 extern void pmic_adc_vbat_enable(kal_bool enable);
1138 extern void pmic6326_adc_meas_on(kal_bool on);  /* exported for controling vbat, isense adc measure at same time */
1139
1140 /* (0x89) INT CTRL 1 */
1141 extern void pmic_int_ctrl_1_enable(int_ctrl_1_enum sel, kal_bool enable);
1142 /* (0x8A) INT CTRL 2 */
1143 extern void pmic_int_ctrl_2_enable(int_ctrl_2_enum sel, kal_bool enable);
1144 /* (0x8B) INT CTRL 2 */
1145 extern void pmic_int_ctrl_3_enable(int_ctrl_3_enum sel, kal_bool enable);
1146
1147 /* (0x96) WATCHDOG CTRL and INT CTRL 4 */
1148 extern void pmic_wdt_timeout(wdt_timout_enum sel);
1149 extern void pmic_intr_polarity(kal_bool assert);
1150 extern void pmic_wdt_enable(kal_bool enable);
1151
1152
1153 /* Combinational functions */
1154 extern void pmic_vgp2_enable(kal_bool enable);
1155 extern void pmic_vgp2_sel(vgp2_sel_enum sel);
1156 extern void pmic_vgp2_on_sel(vgp2_on_sel_enum sel);
1157 extern void pmic_vgp2_sell(kal_uint8 value);
1158 extern void pmic_vgp2_selh(kal_uint8 value);
1159 extern void pmic_vsim2_enable(kal_bool enable);
1160 extern void pmic_vsim2_sel(vsim_sel_enum sel);
1161 extern void pmic_spk_enable(kal_bool enable);
1162
1163 extern void pmic6326_EM_reg_write(kal_uint8 reg, kal_uint8 val);
1164 extern kal_uint8 pmic6326_EM_reg_read(kal_uint8 reg);
1165
1166 #if defined(DRV_MISC_PMIC_ASSERT_KEEP_CHARGING)
1167 extern void pmic6326_assert_chaging_kick(void);
1168 #endif                          /* #if defined(DRV_MISC_PMIC_ASSERT_KEEP_CHARGING) */
1169
1170 /* The following are implemented in custom files */
1171 /* MoDIS parser skip start */
1172 extern void pmic6326_customization_init(void);
1173 extern void pmic6326_cust_vspk_enable(kal_bool enable);
1174 extern void pmic6326_csut_vsim_enable(kal_bool enable);
1175 extern void pmic6326_csut_vsim_sel(pmic_adpt_vsim_volt volt);
1176 extern void pmic6326_csut_vsim2_enable(kal_bool enable);
1177 extern void pmic6326_csut_vsim2_sel(pmic_adpt_vsim_volt sel);
1178 extern void pmic6326_csut_vusb_enable(kal_bool enable);
1179 extern void pmic6326_csut_vcama_enable(kal_bool enable);
1180 extern void pmic6326_csut_vcama_sel(pmic_adpt_vcama_volt vol);
1181 extern void pmic6326_csut_vcamd_enable(kal_bool enable);
1182 extern void pmic6326_csut_vcamd_sel(pmic_adpt_vcamd_volt volt);
1183 /* MoDIS parser skip end */
1184
1185 #endif
1186
1187 /* ======================================================================================= */
1188
1189 #endif                          /* #ifndef __PMIC6326_SW_H__ */