include/linux/mu3phy/mtk-phy-asic.h

   1 #ifdef CONFIG_PROJECT_PHY
   2 #ifndef __MTK_PROJECT_PHY__H
   3 #define __MTK_PROJECT_PHY__H
   4
   5 //referenecd from ssusb_USB20_PHY_regmap_com_T28HPM.xls
   6 #define U3D_USBPHYACR0      (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x0000) /*2:30 SIV_B*/
   7 #define U3D_USBPHYACR1      (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x0004) /*0:23 SIV_B*/
   8 #define U3D_USBPHYACR2      (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x0008) /*0:15 SIV_B*/
   9 #define U3D_USBPHYACR4      (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x0010) /*0:31 SIV_B*/
  10 #define U3D_USBPHYACR5      (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x0014) /*0:28 SIV_B*/
  11 #define U3D_USBPHYACR6      (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x0018) /*0:31 SIV_B*/
  12 #define U3D_U2PHYACR3       (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x001c) /*0:31 SIV_B*/
  13 #define U3D_U2PHYACR4_0     (SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE+0x0020) /*0:5 SIV_B*/
  14
  15 #define U3D_U2PHYACR4       (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0020) /*8:18*/
  16 #define U3D_U2PHYAMON0      (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0024) /*0:1*/
  17 #define U3D_U2PHYDCR0       (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0060) /*0:31*/
  18 #define U3D_U2PHYDCR1       (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0064) /*0:31*/
  19 #define U3D_U2PHYDTM0       (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0068) /*0:31*/
  20 #define U3D_U2PHYDTM1       (SSUSB_SIFSLV_U2PHY_COM_BASE+0x006C) /*0:31*/
  21 #define U3D_U2PHYDMON0      (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0070) /*0:7*/
  22 #define U3D_U2PHYDMON1      (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0074) /*0:31*/
  23 #define U3D_U2PHYDMON2      (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0078) /*0:31*/
  24 #define U3D_U2PHYDMON3      (SSUSB_SIFSLV_U2PHY_COM_BASE+0x007C) /*0:31*/
  25 #define U3D_U2PHYBC12C      (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0080) /*0:31*/
  26 #define U3D_U2PHYBC12C1     (SSUSB_SIFSLV_U2PHY_COM_BASE+0x0084) /*0:7*/
  27 #define U3D_U2PHYREGFPPC    (SSUSB_SIFSLV_U2PHY_COM_BASE+0x00e0) /*0:4*/
  28 #define U3D_U2PHYVERSIONC   (SSUSB_SIFSLV_U2PHY_COM_BASE+0x00f0) /*0:31*/
  29 #define U3D_U2PHYREGFCOM    (SSUSB_SIFSLV_U2PHY_COM_BASE+0x00fc) /*16:31*/
  30
  31 #define U3D_USB30_PHYA_REG0 (SSUSB_USB30_PHYA_SIV_B_BASE+0x0000)
  32 #define U3D_USB30_PHYA_REG6 (SSUSB_USB30_PHYA_SIV_B_BASE+0x0018)
  33
  34 #define U3D_PHYD_CDR1 (SSUSB_SIFSLV_U3PHYD_BASE+0x5c)
  35
  36 #define U3D_U3PHYA_DA_REG0 (SSUSB_SIFSLV_U3PHYA_DA_BASE+0x0)
  37
  38 #define U3D_SPLLC_XTALCTL3 (SSUSB_SIFSLV_SPLLC_BASE+0x18)
  39
  40 #define U2_SR_COEF_E60802 28
  41
  42 ///////////////////////////////////////////////////////////////////////////////
  43
  44 struct u2phy_reg_e {
  45         //0x0
  46         PHY_LE32 usbphyacr0;
  47         PHY_LE32 usbphyacr1;
  48         PHY_LE32 usbphyacr2;
  49         PHY_LE32 reserve0;
  50         //0x10
  51         PHY_LE32 usbphyacr4;
  52         PHY_LE32 usbphyacr5;
  53         PHY_LE32 usbphyacr6;
  54         PHY_LE32 u2phyacr3;
  55         //0x20
  56         PHY_LE32 u2phyacr4;
  57         PHY_LE32 u2phyamon0;
  58         PHY_LE32 reserve1[2];
  59         //0x30~0x50
  60         PHY_LE32 reserve2[12];
  61         //0x60
  62         PHY_LE32 u2phydcr0;
  63         PHY_LE32 u2phydcr1;
  64         PHY_LE32 u2phydtm0;
  65         PHY_LE32 u2phydtm1;
  66         //0x70
  67         PHY_LE32 u2phydmon0;
  68         PHY_LE32 u2phydmon1;
  69         PHY_LE32 u2phydmon2;
  70         PHY_LE32 u2phydmon3;
  71         //0x80
  72         PHY_LE32 u2phybc12c;
  73         PHY_LE32 u2phybc12c1;
  74         PHY_LE32 reserve3[2];
  75         //0x90~0xd0
  76         PHY_LE32 reserve4[20];
  77         //0xe0
  78         PHY_LE32 regfppc;
  79         PHY_LE32 reserve5[3];
  80         //0xf0
  81         PHY_LE32 versionc;
  82         PHY_LE32 reserve6[2];
  83         PHY_LE32 regfcom;
  84 };
  85
  86 //U3D_USBPHYACR0
  87 #define E60802_RG_USB20_MPX_OUT_SEL               (0x7<<28) //30:28
  88 #define E60802_RG_USB20_TX_PH_ROT_SEL             (0x7<<24) //26:24
  89 #define E60802_RG_USB20_PLL_DIVEN                 (0x7<<20) //22:20
  90 #define E60802_RG_USB20_PLL_BR                    (0x1<<18) //18:18
  91 #define E60802_RG_USB20_PLL_BP                    (0x1<<17) //17:17
  92 #define E60802_RG_USB20_PLL_BLP                   (0x1<<16) //16:16
  93 #define E60802_RG_USB20_USBPLL_FORCE_ON           (0x1<<15) //15:15
  94 #define E60802_RG_USB20_PLL_FBDIV                 (0x7f<<8) //14:8
  95 #define E60802_RG_USB20_PLL_PREDIV                (0x3<<6) //7:6
  96 #define E60802_RG_USB20_INTR_EN                   (0x1<<5) //5:5
  97 #define E60802_RG_USB20_REF_EN                    (0x1<<4) //4:4
  98 #define E60802_RG_USB20_BGR_DIV                   (0x3<<2) //3:2
  99 #define E60802_RG_SIFSLV_CHP_EN                   (0x1<<1) //1:1
 100 #define E60802_RG_SIFSLV_BGR_EN                   (0x1<<0) //0:0
 101
 102 //U3D_USBPHYACR1
 103 #define E60802_RG_USB20_INTR_CAL                  (0x1f<<19) //23:19
 104 #define E60802_RG_USB20_OTG_VBUSTH                (0x7<<16) //18:16
 105 #define E60802_RG_USB20_VRT_VREF_SEL              (0x7<<12) //14:12
 106 #define E60802_RG_USB20_TERM_VREF_SEL             (0x7<<8) //10:8
 107 #define E60802_RG_USB20_MPX_SEL                   (0xff<<0) //7:0
 108
 109 //U3D_USBPHYACR2
 110 #define E60802_RG_SIFSLV_MAC_BANDGAP_EN           (0x1<<17) //17:17
 111 #define E60802_RG_SIFSLV_MAC_CHOPPER_EN           (0x1<<16) //16:16
 112 #define E60802_RG_USB20_CLKREF_REV                (0xffff<<0) //15:0
 113
 114 //U3D_USBPHYACR4
 115 #define E60802_RG_USB20_DP_ABIST_SOURCE_EN        (0x1<<31) //31:31
 116 #define E60802_RG_USB20_DP_ABIST_SELE             (0xf<<24) //27:24
 117 #define E60802_RG_USB20_ICUSB_EN                  (0x1<<16) //16:16
 118 #define E60802_RG_USB20_LS_CR                     (0x7<<12) //14:12
 119 #define E60802_RG_USB20_FS_CR                     (0x7<<8) //10:8
 120 #define E60802_RG_USB20_LS_SR                     (0x7<<4) //6:4
 121 #define E60802_RG_USB20_FS_SR                     (0x7<<0) //2:0
 122
 123 //U3D_USBPHYACR5
 124 #define E60802_RG_USB20_DISC_FIT_EN               (0x1<<28) //28:28
 125 #define E60802_RG_USB20_INIT_SQ_EN_DG             (0x3<<26) //27:26
 126 #define E60802_RG_USB20_HSTX_TMODE_SEL            (0x3<<24) //25:24
 127 #define E60802_RG_USB20_SQD                       (0x3<<22) //23:22
 128 #define E60802_RG_USB20_DISCD                     (0x3<<20) //21:20
 129 #define E60802_RG_USB20_HSTX_TMODE_EN             (0x1<<19) //19:19
 130 #define E60802_RG_USB20_PHYD_MONEN                (0x1<<18) //18:18
 131 #define E60802_RG_USB20_INLPBK_EN                 (0x1<<17) //17:17
 132 #define E60802_RG_USB20_CHIRP_EN                  (0x1<<16) //16:16
 133 #define E60802_RG_USB20_HSTX_SRCAL_EN             (0x1<<15) //15:15
 134 #define E60802_RG_USB20_HSTX_SRCTRL               (0x7<<12) //14:12
 135 #define E60802_RG_USB20_HS_100U_U3_EN             (0x1<<11) //11:11
 136 #define E60802_RG_USB20_GBIAS_ENB                 (0x1<<10) //10:10
 137 #define E60802_RG_USB20_DM_ABIST_SOURCE_EN        (0x1<<7) //7:7
 138 #define E60802_RG_USB20_DM_ABIST_SELE             (0xf<<0) //3:0
 139
 140 //U3D_USBPHYACR6
 141 #define E60802_RG_USB20_ISO_EN                    (0x1U<<31) //31:31
 142 #define E60802_RG_USB20_PHY_REV                   (0xef<<24) //31:24
 143 #define E60802_RG_USB20_BC11_SW_EN                (0x1<<23) //23:23
 144 #define E60802_RG_USB20_SR_CLK_SEL                (0x1<<22) //22:22
 145 #define E60802_RG_USB20_OTG_VBUSCMP_EN            (0x1<<20) //20:20
 146 #define E60802_RG_USB20_OTG_ABIST_EN              (0x1<<19) //19:19
 147 #define E60802_RG_USB20_OTG_ABIST_SELE            (0x7<<16) //18:16
 148 #define E60802_RG_USB20_HSRX_MMODE_SELE           (0x3<<12) //13:12
 149 #define E60802_RG_USB20_HSRX_BIAS_EN_SEL          (0x3<<9) //10:9
 150 #define E60802_RG_USB20_HSRX_TMODE_EN             (0x1<<8) //8:8
 151 #define E60802_RG_USB20_DISCTH                    (0xf<<4) //7:4
 152 #define E60802_RG_USB20_SQTH                      (0xf<<0) //3:0
 153
 154 //U3D_U2PHYACR3
 155 #define E60802_RG_USB20_HSTX_DBIST                (0xf<<28) //31:28
 156 #define E60802_RG_USB20_HSTX_BIST_EN              (0x1<<26) //26:26
 157 #define E60802_RG_USB20_HSTX_I_EN_MODE            (0x3<<24) //25:24
 158 #define E60802_RG_USB20_USB11_TMODE_EN            (0x1<<19) //19:19
 159 #define E60802_RG_USB20_TMODE_FS_LS_TX_EN         (0x1<<18) //18:18
 160 #define E60802_RG_USB20_TMODE_FS_LS_RCV_EN        (0x1<<17) //17:17
 161 #define E60802_RG_USB20_TMODE_FS_LS_MODE          (0x1<<16) //16:16
 162 #define E60802_RG_USB20_HS_TERM_EN_MODE           (0x3<<13) //14:13
 163 #define E60802_RG_USB20_PUPD_BIST_EN              (0x1<<12) //12:12
 164 #define E60802_RG_USB20_EN_PU_DM                  (0x1<<11) //11:11
 165 #define E60802_RG_USB20_EN_PD_DM                  (0x1<<10) //10:10
 166 #define E60802_RG_USB20_EN_PU_DP                  (0x1<<9) //9:9
 167 #define E60802_RG_USB20_EN_PD_DP                  (0x1<<8) //8:8
 168
 169 //U3D_U2PHYACR4
 170 #define E60802_RG_USB20_DP_100K_MODE              (0x1<<18) //18:18
 171 #define E60802_RG_USB20_DM_100K_EN                (0x1<<17) //17:17
 172 #define E60802_USB20_DP_100K_EN                   (0x1<<16) //16:16
 173 #define E60802_USB20_GPIO_DM_I                    (0x1<<15) //15:15
 174 #define E60802_USB20_GPIO_DP_I                    (0x1<<14) //14:14
 175 #define E60802_USB20_GPIO_DM_OE                   (0x1<<13) //13:13
 176 #define E60802_USB20_GPIO_DP_OE                   (0x1<<12) //12:12
 177 #define E60802_RG_USB20_GPIO_CTL                  (0x1<<9) //9:9
 178 #define E60802_USB20_GPIO_MODE                    (0x1<<8) //8:8
 179 #define E60802_RG_USB20_TX_BIAS_EN                (0x1<<5) //5:5
 180 #define E60802_RG_USB20_TX_VCMPDN_EN              (0x1<<4) //4:4
 181 #define E60802_RG_USB20_HS_SQ_EN_MODE             (0x3<<2) //3:2
 182 #define E60802_RG_USB20_HS_RCV_EN_MODE            (0x3<<0) //1:0
 183
 184 //U3D_U2PHYAMON0
 185 #define E60802_RGO_USB20_GPIO_DM_O                (0x1<<1) //1:1
 186 #define E60802_RGO_USB20_GPIO_DP_O                (0x1<<0) //0:0
 187
 188 //U3D_U2PHYDCR0
 189 #define E60802_RG_USB20_CDR_TST                   (0x3<<30) //31:30
 190 #define E60802_RG_USB20_GATED_ENB                 (0x1<<29) //29:29
 191 #define E60802_RG_USB20_TESTMODE                  (0x3<<26) //27:26
 192 #define E60802_RG_SIFSLV_USB20_PLL_STABLE         (0x1<<25) //25:25
 193 #define E60802_RG_SIFSLV_USB20_PLL_FORCE_ON       (0x1<<24) //24:24
 194 #define E60802_RG_USB20_PHYD_RESERVE              (0xffff<<8) //23:8
 195 #define E60802_RG_USB20_EBTHRLD                   (0x1<<7) //7:7
 196 #define E60802_RG_USB20_EARLY_HSTX_I              (0x1<<6) //6:6
 197 #define E60802_RG_USB20_TX_TST                    (0x1<<5) //5:5
 198 #define E60802_RG_USB20_NEGEDGE_ENB               (0x1<<4) //4:4
 199 #define E60802_RG_USB20_CDR_FILT                  (0xf<<0) //3:0
 200
 201 //U3D_U2PHYDCR1
 202 #define E60802_RG_USB20_PROBE_SEL                 (0xff<<24) //31:24
 203 #define E60802_RG_USB20_DRVVBUS                   (0x1<<23) //23:23
 204 #define E60802_RG_DEBUG_EN                        (0x1<<22) //22:22
 205 #define E60802_RG_USB20_OTG_PROBE                 (0x3<<20) //21:20
 206 #define E60802_RG_USB20_SW_PLLMODE                (0x3<<18) //19:18
 207 #define E60802_RG_USB20_BERTH                     (0x3<<16) //17:16
 208 #define E60802_RG_USB20_LBMODE                    (0x3<<13) //14:13
 209 #define E60802_RG_USB20_FORCE_TAP                 (0x1<<12) //12:12
 210 #define E60802_RG_USB20_TAPSEL                    (0xfff<<0) //11:0
 211
 212 //U3D_U2PHYDTM0
 213 #define E60802_RG_UART_MODE                       (0x3<<30) //31:30
 214 #define E60802_FORCE_UART_I                       (0x1<<29) //29:29
 215 #define E60802_FORCE_UART_BIAS_EN                 (0x1<<28) //28:28
 216 #define E60802_FORCE_UART_TX_OE                   (0x1<<27) //27:27
 217 #define E60802_FORCE_UART_EN                      (0x1<<26) //26:26
 218 #define E60802_FORCE_USB_CLKEN                    (0x1<<25) //25:25
 219 #define E60802_FORCE_DRVVBUS                      (0x1<<24) //24:24
 220 #define E60802_FORCE_DATAIN                       (0x1<<23) //23:23
 221 #define E60802_FORCE_TXVALID                      (0x1<<22) //22:22
 222 #define E60802_FORCE_DM_PULLDOWN                  (0x1<<21) //21:21
 223 #define E60802_FORCE_DP_PULLDOWN                  (0x1<<20) //20:20
 224 #define E60802_FORCE_XCVRSEL                      (0x1<<19) //19:19
 225 #define E60802_FORCE_SUSPENDM                     (0x1<<18) //18:18
 226 #define E60802_FORCE_TERMSEL                      (0x1<<17) //17:17
 227 #define E60802_FORCE_OPMODE                       (0x1<<16) //16:16
 228 #define E60802_UTMI_MUXSEL                        (0x1<<15) //15:15
 229 #define E60802_RG_RESET                           (0x1<<14) //14:14
 230 #define E60802_RG_DATAIN                          (0xf<<10) //13:10
 231 #define E60802_RG_TXVALIDH                        (0x1<<9) //9:9
 232 #define E60802_RG_TXVALID                         (0x1<<8) //8:8
 233 #define E60802_RG_DMPULLDOWN                      (0x1<<7) //7:7
 234 #define E60802_RG_DPPULLDOWN                      (0x1<<6) //6:6
 235 #define E60802_RG_XCVRSEL                         (0x3<<4) //5:4
 236 #define E60802_RG_SUSPENDM                        (0x1<<3) //3:3
 237 #define E60802_RG_TERMSEL                         (0x1<<2) //2:2
 238 #define E60802_RG_OPMODE                          (0x3<<0) //1:0
 239
 240 //U3D_U2PHYDTM1
 241 #define E60802_RG_USB20_PRBS7_EN                  (0x1<<31) //31:31
 242 #define E60802_RG_USB20_PRBS7_BITCNT              (0x3f<<24) //29:24
 243 #define E60802_RG_USB20_CLK48M_EN                 (0x1<<23) //23:23
 244 #define E60802_RG_USB20_CLK60M_EN                 (0x1<<22) //22:22
 245 #define E60802_RG_UART_I                          (0x1<<19) //19:19
 246 #define E60802_RG_UART_BIAS_EN                    (0x1<<18) //18:18
 247 #define E60802_RG_UART_TX_OE                      (0x1<<17) //17:17
 248 #define E60802_RG_UART_EN                         (0x1<<16) //16:16
 249 #define E60802_RG_IP_U2_PORT_POWER                (0x1<<15) //15:15
 250 #define E60802_FORCE_IP_U2_PORT_POWER             (0x1<<14) //14:14
 251 #define E60802_FORCE_VBUSVALID                    (0x1<<13) //13:13
 252 #define E60802_FORCE_SESSEND                      (0x1<<12) //12:12
 253 #define E60802_FORCE_BVALID                       (0x1<<11) //11:11
 254 #define E60802_FORCE_AVALID                       (0x1<<10) //10:10
 255 #define E60802_FORCE_IDDIG                        (0x1<<9) //9:9
 256 #define E60802_FORCE_IDPULLUP                     (0x1<<8) //8:8
 257 #define E60802_RG_VBUSVALID                       (0x1<<5) //5:5
 258 #define E60802_RG_SESSEND                         (0x1<<4) //4:4
 259 #define E60802_RG_BVALID                          (0x1<<3) //3:3
 260 #define E60802_RG_AVALID                          (0x1<<2) //2:2
 261 #define E60802_RG_IDDIG                           (0x1<<1) //1:1
 262 #define E60802_RG_IDPULLUP                        (0x1<<0) //0:0
 263
 264 //U3D_U2PHYDMON0
 265 #define E60802_RG_USB20_PRBS7_BERTH               (0xff<<0) //7:0
 266
 267 //U3D_U2PHYDMON1
 268 #define E60802_USB20_UART_O                       (0x1<<31) //31:31
 269 #define E60802_RGO_USB20_LB_PASS                  (0x1<<30) //30:30
 270 #define E60802_RGO_USB20_LB_DONE                  (0x1<<29) //29:29
 271 #define E60802_AD_USB20_BVALID                    (0x1<<28) //28:28
 272 #define E60802_USB20_IDDIG                        (0x1<<27) //27:27
 273 #define E60802_AD_USB20_VBUSVALID                 (0x1<<26) //26:26
 274 #define E60802_AD_USB20_SESSEND                   (0x1<<25) //25:25
 275 #define E60802_AD_USB20_AVALID                    (0x1<<24) //24:24
 276 #define E60802_USB20_LINE_STATE                   (0x3<<22) //23:22
 277 #define E60802_USB20_HST_DISCON                   (0x1<<21) //21:21
 278 #define E60802_USB20_TX_READY                     (0x1<<20) //20:20
 279 #define E60802_USB20_RX_ERROR                     (0x1<<19) //19:19
 280 #define E60802_USB20_RX_ACTIVE                    (0x1<<18) //18:18
 281 #define E60802_USB20_RX_VALIDH                    (0x1<<17) //17:17
 282 #define E60802_USB20_RX_VALID                     (0x1<<16) //16:16
 283 #define E60802_USB20_DATA_OUT                     (0xffff<<0) //15:0
 284
 285 //U3D_U2PHYDMON2
 286 #define E60802_RGO_TXVALID_CNT                    (0xff<<24) //31:24
 287 #define E60802_RGO_RXACTIVE_CNT                   (0xff<<16) //23:16
 288 #define E60802_RGO_USB20_LB_BERCNT                (0xff<<8) //15:8
 289 #define E60802_USB20_PROBE_OUT                    (0xff<<0) //7:0
 290
 291 //U3D_U2PHYDMON3
 292 #define E60802_RGO_USB20_PRBS7_ERRCNT             (0xffff<<16) //31:16
 293 #define E60802_RGO_USB20_PRBS7_DONE               (0x1<<3) //3:3
 294 #define E60802_RGO_USB20_PRBS7_LOCK               (0x1<<2) //2:2
 295 #define E60802_RGO_USB20_PRBS7_PASS               (0x1<<1) //1:1
 296 #define E60802_RGO_USB20_PRBS7_PASSTH             (0x1<<0) //0:0
 297
 298 //U3D_U2PHYBC12C
 299 #define E60802_RG_SIFSLV_CHGDT_DEGLCH_CNT         (0xf<<28) //31:28
 300 #define E60802_RG_SIFSLV_CHGDT_CTRL_CNT           (0xf<<24) //27:24
 301 #define E60802_RG_SIFSLV_CHGDT_FORCE_MODE         (0x1<<16) //16:16
 302 #define E60802_RG_CHGDT_ISRC_LEV                  (0x3<<14) //15:14
 303 #define E60802_RG_CHGDT_VDATSRC                   (0x1<<13) //13:13
 304 #define E60802_RG_CHGDT_BGVREF_SEL                (0x7<<10) //12:10
 305 #define E60802_RG_CHGDT_RDVREF_SEL                (0x3<<8) //9:8
 306 #define E60802_RG_CHGDT_ISRC_DP                   (0x1<<7) //7:7
 307 #define E60802_RG_SIFSLV_CHGDT_OPOUT_DM           (0x1<<6) //6:6
 308 #define E60802_RG_CHGDT_VDAT_DM                   (0x1<<5) //5:5
 309 #define E60802_RG_CHGDT_OPOUT_DP                  (0x1<<4) //4:4
 310 #define E60802_RG_SIFSLV_CHGDT_VDAT_DP            (0x1<<3) //3:3
 311 #define E60802_RG_SIFSLV_CHGDT_COMP_EN            (0x1<<2) //2:2
 312 #define E60802_RG_SIFSLV_CHGDT_OPDRV_EN           (0x1<<1) //1:1
 313 #define E60802_RG_CHGDT_EN                        (0x1<<0) //0:0
 314
 315 //U3D_U2PHYBC12C1
 316 #define E60802_RG_CHGDT_REV                       (0xff<<0) //7:0
 317
 318 //U3D_REGFPPC
 319 #define E60802_USB11_OTG_REG                      (0x1<<4) //4:4
 320 #define E60802_USB20_OTG_REG                      (0x1<<3) //3:3
 321 #define E60802_CHGDT_REG                          (0x1<<2) //2:2
 322 #define E60802_USB11_REG                          (0x1<<1) //1:1
 323 #define E60802_USB20_REG                          (0x1<<0) //0:0
 324
 325 //U3D_VERSIONC
 326 #define E60802_VERSION_CODE_REGFILE               (0xff<<24) //31:24
 327 #define E60802_USB11_VERSION_CODE                 (0xff<<16) //23:16
 328 #define E60802_VERSION_CODE_ANA                   (0xff<<8) //15:8
 329 #define E60802_VERSION_CODE_DIG                   (0xff<<0) //7:0
 330
 331 //U3D_REGFCOM
 332 #define E60802_RG_PAGE                            (0xff<<24) //31:24
 333 #define E60802_I2C_MODE                           (0x1<<16) //16:16
 334
 335 /* OFFSET */
 336
 337 //U3D_USBPHYACR0
 338 #define E60802_RG_USB20_MPX_OUT_SEL_OFST          (28)
 339 #define E60802_RG_USB20_TX_PH_ROT_SEL_OFST        (24)
 340 #define E60802_RG_USB20_PLL_DIVEN_OFST            (20)
 341 #define E60802_RG_USB20_PLL_BR_OFST               (18)
 342 #define E60802_RG_USB20_PLL_BP_OFST               (17)
 343 #define E60802_RG_USB20_PLL_BLP_OFST              (16)
 344 #define E60802_RG_USB20_USBPLL_FORCE_ON_OFST      (15)
 345 #define E60802_RG_USB20_PLL_FBDIV_OFST            (8)
 346 #define E60802_RG_USB20_PLL_PREDIV_OFST           (6)
 347 #define E60802_RG_USB20_INTR_EN_OFST              (5)
 348 #define E60802_RG_USB20_REF_EN_OFST               (4)
 349 #define E60802_RG_USB20_BGR_DIV_OFST              (2)
 350 #define E60802_RG_SIFSLV_CHP_EN_OFST              (1)
 351 #define E60802_RG_SIFSLV_BGR_EN_OFST              (0)
 352
 353 //U3D_USBPHYACR1
 354 #define E60802_RG_USB20_INTR_CAL_OFST             (19)
 355 #define E60802_RG_USB20_OTG_VBUSTH_OFST           (16)
 356 #define E60802_RG_USB20_VRT_VREF_SEL_OFST         (12)
 357 #define E60802_RG_USB20_TERM_VREF_SEL_OFST        (8)
 358 #define E60802_RG_USB20_MPX_SEL_OFST              (0)
 359
 360 //U3D_USBPHYACR2
 361 #define E60802_RG_SIFSLV_MAC_BANDGAP_EN_OFST      (17)
 362 #define E60802_RG_SIFSLV_MAC_CHOPPER_EN_OFST      (16)
 363 #define E60802_RG_USB20_CLKREF_REV_OFST           (0)
 364
 365 //U3D_USBPHYACR4
 366 #define E60802_RG_USB20_DP_ABIST_SOURCE_EN_OFST   (31)
 367 #define E60802_RG_USB20_DP_ABIST_SELE_OFST        (24)
 368 #define E60802_RG_USB20_ICUSB_EN_OFST             (16)
 369 #define E60802_RG_USB20_LS_CR_OFST                (12)
 370 #define E60802_RG_USB20_FS_CR_OFST                (8)
 371 #define E60802_RG_USB20_LS_SR_OFST                (4)
 372 #define E60802_RG_USB20_FS_SR_OFST                (0)
 373
 374 //U3D_USBPHYACR5
 375 #define E60802_RG_USB20_DISC_FIT_EN_OFST          (28)
 376 #define E60802_RG_USB20_INIT_SQ_EN_DG_OFST        (26)
 377 #define E60802_RG_USB20_HSTX_TMODE_SEL_OFST       (24)
 378 #define E60802_RG_USB20_SQD_OFST                  (22)
 379 #define E60802_RG_USB20_DISCD_OFST                (20)
 380 #define E60802_RG_USB20_HSTX_TMODE_EN_OFST        (19)
 381 #define E60802_RG_USB20_PHYD_MONEN_OFST           (18)
 382 #define E60802_RG_USB20_INLPBK_EN_OFST            (17)
 383 #define E60802_RG_USB20_CHIRP_EN_OFST             (16)
 384 #define E60802_RG_USB20_HSTX_SRCAL_EN_OFST        (15)
 385 #define E60802_RG_USB20_HSTX_SRCTRL_OFST          (12)
 386 #define E60802_RG_USB20_HS_100U_U3_EN_OFST        (11)
 387 #define E60802_RG_USB20_GBIAS_ENB_OFST            (10)
 388 #define E60802_RG_USB20_DM_ABIST_SOURCE_EN_OFST   (7)
 389 #define E60802_RG_USB20_DM_ABIST_SELE_OFST        (0)
 390
 391 //U3D_USBPHYACR6
 392 #define E60802_RG_USB20_ISO_EN_OFST               (31)
 393 #define E60802_RG_USB20_PHY_REV_OFST              (24)
 394 #define E60802_RG_USB20_BC11_SW_EN_OFST           (23)
 395 #define E60802_RG_USB20_SR_CLK_SEL_OFST           (22)
 396 #define E60802_RG_USB20_OTG_VBUSCMP_EN_OFST       (20)
 397 #define E60802_RG_USB20_OTG_ABIST_EN_OFST         (19)
 398 #define E60802_RG_USB20_OTG_ABIST_SELE_OFST       (16)
 399 #define E60802_RG_USB20_HSRX_MMODE_SELE_OFST      (12)
 400 #define E60802_RG_USB20_HSRX_BIAS_EN_SEL_OFST     (9)
 401 #define E60802_RG_USB20_HSRX_TMODE_EN_OFST        (8)
 402 #define E60802_RG_USB20_DISCTH_OFST               (4)
 403 #define E60802_RG_USB20_SQTH_OFST                 (0)
 404
 405 //U3D_U2PHYACR3
 406 #define E60802_RG_USB20_HSTX_DBIST_OFST           (28)
 407 #define E60802_RG_USB20_HSTX_BIST_EN_OFST         (26)
 408 #define E60802_RG_USB20_HSTX_I_EN_MODE_OFST       (24)
 409 #define E60802_RG_USB20_USB11_TMODE_EN_OFST       (19)
 410 #define E60802_RG_USB20_TMODE_FS_LS_TX_EN_OFST    (18)
 411 #define E60802_RG_USB20_TMODE_FS_LS_RCV_EN_OFST   (17)
 412 #define E60802_RG_USB20_TMODE_FS_LS_MODE_OFST     (16)
 413 #define E60802_RG_USB20_HS_TERM_EN_MODE_OFST      (13)
 414 #define E60802_RG_USB20_PUPD_BIST_EN_OFST         (12)
 415 #define E60802_RG_USB20_EN_PU_DM_OFST             (11)
 416 #define E60802_RG_USB20_EN_PD_DM_OFST             (10)
 417 #define E60802_RG_USB20_EN_PU_DP_OFST             (9)
 418 #define E60802_RG_USB20_EN_PD_DP_OFST             (8)
 419
 420 //U3D_U2PHYACR4
 421 #define E60802_RG_USB20_DP_100K_MODE_OFST         (18)
 422 #define E60802_RG_USB20_DM_100K_EN_OFST           (17)
 423 #define E60802_USB20_DP_100K_EN_OFST              (16)
 424 #define E60802_USB20_GPIO_DM_I_OFST               (15)
 425 #define E60802_USB20_GPIO_DP_I_OFST               (14)
 426 #define E60802_USB20_GPIO_DM_OE_OFST              (13)
 427 #define E60802_USB20_GPIO_DP_OE_OFST              (12)
 428 #define E60802_RG_USB20_GPIO_CTL_OFST             (9)
 429 #define E60802_USB20_GPIO_MODE_OFST               (8)
 430 #define E60802_RG_USB20_TX_BIAS_EN_OFST           (5)
 431 #define E60802_RG_USB20_TX_VCMPDN_EN_OFST         (4)
 432 #define E60802_RG_USB20_HS_SQ_EN_MODE_OFST        (2)
 433 #define E60802_RG_USB20_HS_RCV_EN_MODE_OFST       (0)
 434
 435 //U3D_U2PHYAMON0
 436 #define E60802_RGO_USB20_GPIO_DM_O_OFST           (1)
 437 #define E60802_RGO_USB20_GPIO_DP_O_OFST           (0)
 438
 439 //U3D_U2PHYDCR0
 440 #define E60802_RG_USB20_CDR_TST_OFST              (30)
 441 #define E60802_RG_USB20_GATED_ENB_OFST            (29)
 442 #define E60802_RG_USB20_TESTMODE_OFST             (26)
 443 #define E60802_RG_SIFSLV_USB20_PLL_STABLE_OFST    (25)
 444 #define E60802_RG_SIFSLV_USB20_PLL_FORCE_ON_OFST  (24)
 445 #define E60802_RG_USB20_PHYD_RESERVE_OFST         (8)
 446 #define E60802_RG_USB20_EBTHRLD_OFST              (7)
 447 #define E60802_RG_USB20_EARLY_HSTX_I_OFST         (6)
 448 #define E60802_RG_USB20_TX_TST_OFST               (5)
 449 #define E60802_RG_USB20_NEGEDGE_ENB_OFST          (4)
 450 #define E60802_RG_USB20_CDR_FILT_OFST             (0)
 451
 452 //U3D_U2PHYDCR1
 453 #define E60802_RG_USB20_PROBE_SEL_OFST            (24)
 454 #define E60802_RG_USB20_DRVVBUS_OFST              (23)
 455 #define E60802_RG_DEBUG_EN_OFST                   (22)
 456 #define E60802_RG_USB20_OTG_PROBE_OFST            (20)
 457 #define E60802_RG_USB20_SW_PLLMODE_OFST           (18)
 458 #define E60802_RG_USB20_BERTH_OFST                (16)
 459 #define E60802_RG_USB20_LBMODE_OFST               (13)
 460 #define E60802_RG_USB20_FORCE_TAP_OFST            (12)
 461 #define E60802_RG_USB20_TAPSEL_OFST               (0)
 462
 463 //U3D_U2PHYDTM0
 464 #define E60802_RG_UART_MODE_OFST                  (30)
 465 #define E60802_FORCE_UART_I_OFST                  (29)
 466 #define E60802_FORCE_UART_BIAS_EN_OFST            (28)
 467 #define E60802_FORCE_UART_TX_OE_OFST              (27)
 468 #define E60802_FORCE_UART_EN_OFST                 (26)
 469 #define E60802_FORCE_USB_CLKEN_OFST               (25)
 470 #define E60802_FORCE_DRVVBUS_OFST                 (24)
 471 #define E60802_FORCE_DATAIN_OFST                  (23)
 472 #define E60802_FORCE_TXVALID_OFST                 (22)
 473 #define E60802_FORCE_DM_PULLDOWN_OFST             (21)
 474 #define E60802_FORCE_DP_PULLDOWN_OFST             (20)
 475 #define E60802_FORCE_XCVRSEL_OFST                 (19)
 476 #define E60802_FORCE_SUSPENDM_OFST                (18)
 477 #define E60802_FORCE_TERMSEL_OFST                 (17)
 478 #define E60802_FORCE_OPMODE_OFST                  (16)
 479 #define E60802_UTMI_MUXSEL_OFST                   (15)
 480 #define E60802_RG_RESET_OFST                      (14)
 481 #define E60802_RG_DATAIN_OFST                     (10)
 482 #define E60802_RG_TXVALIDH_OFST                   (9)
 483 #define E60802_RG_TXVALID_OFST                    (8)
 484 #define E60802_RG_DMPULLDOWN_OFST                 (7)
 485 #define E60802_RG_DPPULLDOWN_OFST                 (6)
 486 #define E60802_RG_XCVRSEL_OFST                    (4)
 487 #define E60802_RG_SUSPENDM_OFST                   (3)
 488 #define E60802_RG_TERMSEL_OFST                    (2)
 489 #define E60802_RG_OPMODE_OFST                     (0)
 490
 491 //U3D_U2PHYDTM1
 492 #define E60802_RG_USB20_PRBS7_EN_OFST             (31)
 493 #define E60802_RG_USB20_PRBS7_BITCNT_OFST         (24)
 494 #define E60802_RG_USB20_CLK48M_EN_OFST            (23)
 495 #define E60802_RG_USB20_CLK60M_EN_OFST            (22)
 496 #define E60802_RG_UART_I_OFST                     (19)
 497 #define E60802_RG_UART_BIAS_EN_OFST               (18)
 498 #define E60802_RG_UART_TX_OE_OFST                 (17)
 499 #define E60802_RG_UART_EN_OFST                    (16)
 500 #define E60802_RG_IP_U2_PORT_POWER_OFST           (15)
 501 #define E60802_FORCE_IP_U2_PORT_POWER_OFST        (14)
 502 #define E60802_FORCE_VBUSVALID_OFST               (13)
 503 #define E60802_FORCE_SESSEND_OFST                 (12)
 504 #define E60802_FORCE_BVALID_OFST                  (11)
 505 #define E60802_FORCE_AVALID_OFST                  (10)
 506 #define E60802_FORCE_IDDIG_OFST                   (9)
 507 #define E60802_FORCE_IDPULLUP_OFST                (8)
 508 #define E60802_RG_VBUSVALID_OFST                  (5)
 509 #define E60802_RG_SESSEND_OFST                    (4)
 510 #define E60802_RG_BVALID_OFST                     (3)
 511 #define E60802_RG_AVALID_OFST                     (2)
 512 #define E60802_RG_IDDIG_OFST                      (1)
 513 #define E60802_RG_IDPULLUP_OFST                   (0)
 514
 515 //U3D_U2PHYDMON0
 516 #define E60802_RG_USB20_PRBS7_BERTH_OFST          (0)
 517
 518 //U3D_U2PHYDMON1
 519 #define E60802_USB20_UART_O_OFST                  (31)
 520 #define E60802_RGO_USB20_LB_PASS_OFST             (30)
 521 #define E60802_RGO_USB20_LB_DONE_OFST             (29)
 522 #define E60802_AD_USB20_BVALID_OFST               (28)
 523 #define E60802_USB20_IDDIG_OFST                   (27)
 524 #define E60802_AD_USB20_VBUSVALID_OFST            (26)
 525 #define E60802_AD_USB20_SESSEND_OFST              (25)
 526 #define E60802_AD_USB20_AVALID_OFST               (24)
 527 #define E60802_USB20_LINE_STATE_OFST              (22)
 528 #define E60802_USB20_HST_DISCON_OFST              (21)
 529 #define E60802_USB20_TX_READY_OFST                (20)
 530 #define E60802_USB20_RX_ERROR_OFST                (19)
 531 #define E60802_USB20_RX_ACTIVE_OFST               (18)
 532 #define E60802_USB20_RX_VALIDH_OFST               (17)
 533 #define E60802_USB20_RX_VALID_OFST                (16)
 534 #define E60802_USB20_DATA_OUT_OFST                (0)
 535
 536 //U3D_U2PHYDMON2
 537 #define E60802_RGO_TXVALID_CNT_OFST               (24)
 538 #define E60802_RGO_RXACTIVE_CNT_OFST              (16)
 539 #define E60802_RGO_USB20_LB_BERCNT_OFST           (8)
 540 #define E60802_USB20_PROBE_OUT_OFST               (0)
 541
 542 //U3D_U2PHYDMON3
 543 #define E60802_RGO_USB20_PRBS7_ERRCNT_OFST        (16)
 544 #define E60802_RGO_USB20_PRBS7_DONE_OFST          (3)
 545 #define E60802_RGO_USB20_PRBS7_LOCK_OFST          (2)
 546 #define E60802_RGO_USB20_PRBS7_PASS_OFST          (1)
 547 #define E60802_RGO_USB20_PRBS7_PASSTH_OFST        (0)
 548
 549 //U3D_U2PHYBC12C
 550 #define E60802_RG_SIFSLV_CHGDT_DEGLCH_CNT_OFST    (28)
 551 #define E60802_RG_SIFSLV_CHGDT_CTRL_CNT_OFST      (24)
 552 #define E60802_RG_SIFSLV_CHGDT_FORCE_MODE_OFST    (16)
 553 #define E60802_RG_CHGDT_ISRC_LEV_OFST             (14)
 554 #define E60802_RG_CHGDT_VDATSRC_OFST              (13)
 555 #define E60802_RG_CHGDT_BGVREF_SEL_OFST           (10)
 556 #define E60802_RG_CHGDT_RDVREF_SEL_OFST           (8)
 557 #define E60802_RG_CHGDT_ISRC_DP_OFST              (7)
 558 #define E60802_RG_SIFSLV_CHGDT_OPOUT_DM_OFST      (6)
 559 #define E60802_RG_CHGDT_VDAT_DM_OFST              (5)
 560 #define E60802_RG_CHGDT_OPOUT_DP_OFST             (4)
 561 #define E60802_RG_SIFSLV_CHGDT_VDAT_DP_OFST       (3)
 562 #define E60802_RG_SIFSLV_CHGDT_COMP_EN_OFST       (2)
 563 #define E60802_RG_SIFSLV_CHGDT_OPDRV_EN_OFST      (1)
 564 #define E60802_RG_CHGDT_EN_OFST                   (0)
 565
 566 //U3D_U2PHYBC12C1
 567 #define E60802_RG_CHGDT_REV_OFST                  (0)
 568
 569 //U3D_REGFPPC
 570 #define E60802_USB11_OTG_REG_OFST                 (4)
 571 #define E60802_USB20_OTG_REG_OFST                 (3)
 572 #define E60802_CHGDT_REG_OFST                     (2)
 573 #define E60802_USB11_REG_OFST                     (1)
 574 #define E60802_USB20_REG_OFST                     (0)
 575
 576 //U3D_VERSIONC
 577 #define E60802_VERSION_CODE_REGFILE_OFST          (24)
 578 #define E60802_USB11_VERSION_CODE_OFST            (16)
 579 #define E60802_VERSION_CODE_ANA_OFST              (8)
 580 #define E60802_VERSION_CODE_DIG_OFST              (0)
 581
 582 //U3D_REGFCOM
 583 #define E60802_RG_PAGE_OFST                       (24)
 584 #define E60802_I2C_MODE_OFST                      (16)
 585
 586 ///////////////////////////////////////////////////////////////////////////////
 587
 588 struct u3phya_reg_e {
 589         //0x0
 590         PHY_LE32 reg0;
 591         PHY_LE32 reg1;
 592         PHY_LE32 reg2;
 593         PHY_LE32 reg3;
 594         //0x10
 595         PHY_LE32 reg4;
 596         PHY_LE32 reg5;
 597         PHY_LE32 reg6;
 598         PHY_LE32 reg7;
 599         //0x20
 600         PHY_LE32 reg8;
 601         PHY_LE32 reg9;
 602         PHY_LE32 rega;
 603         PHY_LE32 regb;
 604         //0x30
 605         PHY_LE32 regc;
 606 };
 607
 608 //U3D_reg0
 609 #define E60802_RG_SSUSB_BGR_EN                    (0x1<<31) //31:31
 610 #define E60802_RG_SSUSB_CHPEN                     (0x1<<30) //30:30
 611 #define E60802_RG_SSUSB_BG_DIV                    (0x3<<28) //29:28
 612 #define E60802_RG_SSUSB_INTR_EN                   (0x1<<26) //26:26
 613 #define E60802_RG_SSUSB_MPX_EN                    (0x1<<24) //24:24
 614 #define E60802_RG_SSUSB_MPX_SEL                   (0xff<<16) //23:16
 615 #define E60802_RG_SSUSB_REF_EN                    (0x1<<15) //15:15
 616 #define E60802_RG_SSUSB_VRT_VREF_SEL              (0xf<<11) //14:11
 617 #define E60802_RG_SSUSB_BG_MONEN                  (0x1<<8) //8:8
 618 #define E60802_RG_SSUSB_INT_BIAS_SEL              (0x1<<7) //7:7
 619 #define E60802_RG_SSUSB_EXT_BIAS_SEL              (0x1<<6) //6:6
 620 #define E60802_RG_PCIE_CLKDRV_OFFSET              (0x3<<2) //3:2
 621 #define E60802_RG_PCIE_CLKDRV_SLEW                (0x3<<0) //1:0
 622
 623 //U3D_reg1
 624 #define E60802_RG_PCIE_CLKDRV_AMP                 (0x7<<29) //31:29
 625 #define E60802_RG_SSUSB_XTAL_TST_A2DCK_EN         (0x1<<28) //28:28
 626 #define E60802_RG_SSUSB_XTAL_MON_EN               (0x1<<27) //27:27
 627 #define E60802_RG_SSUSB_XTAL_HYS                  (0x1<<26) //26:26
 628 #define E60802_RG_SSUSB_XTAL_TOP_RESERVE          (0xffff<<10) //25:10
 629 #define E60802_RG_SSUSB_SYSPLL_PREDIV             (0x3<<8) //9:8
 630 #define E60802_RG_SSUSB_SYSPLL_POSDIV             (0x3<<6) //7:6
 631 #define E60802_RG_SSUSB_SYSPLL_VCO_DIV_SEL        (0x1<<5) //5:5
 632 #define E60802_RG_SSUSB_SYSPLL_VOD_EN             (0x1<<4) //4:4
 633 #define E60802_RG_SSUSB_SYSPLL_RST_DLY            (0x3<<2) //3:2
 634 #define E60802_RG_SSUSB_SYSPLL_BLP                (0x1<<1) //1:1
 635 #define E60802_RG_SSUSB_SYSPLL_BP                 (0x1<<0) //0:0
 636
 637 //U3D_reg2
 638 #define E60802_RG_SSUSB_SYSPLL_BR                 (0x1<<31) //31:31
 639 #define E60802_RG_SSUSB_SYSPLL_BC                 (0x1<<30) //30:30
 640 #define E60802_RG_SSUSB_SYSPLL_MONCK_EN           (0x1<<29) //29:29
 641 #define E60802_RG_SSUSB_SYSPLL_MONVC_EN           (0x1<<28) //28:28
 642 #define E60802_RG_SSUSB_SYSPLL_MONREF_EN          (0x1<<27) //27:27
 643 #define E60802_RG_SSUSB_SYSPLL_SDM_IFM            (0x1<<26) //26:26
 644 #define E60802_RG_SSUSB_SYSPLL_SDM_OUT            (0x1<<25) //25:25
 645 #define E60802_RG_SSUSB_SYSPLL_BACK_EN            (0x1<<24) //24:24
 646
 647 //U3D_reg3
 648 #define E60802_RG_SSUSB_SYSPLL_FBDIV              (0x7fffffff<<1) //31:1
 649 #define E60802_RG_SSUSB_SYSPLL_HR_EN              (0x1<<0) //0:0
 650
 651 //U3D_reg4
 652 #define E60802_RG_SSUSB_SYSPLL_SDM_DI_EN          (0x1<<31) //31:31
 653 #define E60802_RG_SSUSB_SYSPLL_SDM_DI_LS          (0x3<<29) //30:29
 654 #define E60802_RG_SSUSB_SYSPLL_SDM_ORD            (0x3<<27) //28:27
 655 #define E60802_RG_SSUSB_SYSPLL_SDM_MODE           (0x3<<25) //26:25
 656 #define E60802_RG_SSUSB_SYSPLL_RESERVE            (0xff<<17) //24:17
 657 #define E60802_RG_SSUSB_SYSPLL_TOP_RESERVE        (0xffff<<1) //16:1
 658
 659 //U3D_reg5
 660 #define E60802_RG_SSUSB_TX250MCK_INVB             (0x1<<31) //31:31
 661 #define E60802_RG_SSUSB_IDRV_ITAILOP_EN           (0x1<<30) //30:30
 662 #define E60802_RG_SSUSB_IDRV_CALIB                (0x3f<<24) //29:24
 663 #define E60802_RG_SSUSB_IDEM_BIAS                 (0xf<<20) //23:20
 664 #define E60802_RG_SSUSB_TX_R50_FON                (0x1<<19) //19:19
 665 #define E60802_RG_SSUSB_TX_SR                     (0x7<<16) //18:16
 666 #define E60802_RG_SSUSB_RXDET_RSEL                (0x3<<14) //15:14
 667 #define E60802_RG_SSUSB_RXDET_UPDN_FORCE          (0x1<<13) //13:13
 668 #define E60802_RG_SSUSB_RXDET_UPDN_SEL            (0x1<<12) //12:12
 669 #define E60802_RG_SSUSB_RXDET_VTHSEL_L            (0x3<<10) //11:10
 670 #define E60802_RG_SSUSB_RXDET_VTHSEL_H            (0x3<<8) //9:8
 671 #define E60802_RG_SSUSB_CKMON_EN                  (0x1<<7) //7:7
 672 #define E60802_RG_SSUSB_TX_VLMON_EN               (0x1<<6) //6:6
 673 #define E60802_RG_SSUSB_TX_VLMON_SEL              (0x3<<4) //5:4
 674 #define E60802_RG_SSUSB_CKMON_SEL                 (0xf<<0) //3:0
 675
 676 //U3D_reg6
 677 #define E60802_RG_SSUSB_TX_EIDLE_CM               (0xf<<28) //31:28
 678 #define E60802_RG_SSUSB_RXLBTX_EN                 (0x1<<27) //27:27
 679 #define E60802_RG_SSUSB_TXLBRX_EN                 (0x1<<26) //26:26
 680 #define E60802_RG_SSUSB_RESERVE                   (0x3ff<<16) //25:16
 681 #define E60802_RG_SSUSB_PLL_POSDIV                (0x3<<14) //15:14
 682 #define E60802_RG_SSUSB_PLL_AUTOK_LOAD            (0x1<<13) //13:13
 683 #define E60802_RG_SSUSB_PLL_VOD_EN                (0x1<<12) //12:12
 684 #define E60802_RG_SSUSB_PLL_MONREF_EN             (0x1<<11) //11:11
 685 #define E60802_RG_SSUSB_PLL_MONCK_EN              (0x1<<10) //10:10
 686 #define E60802_RG_SSUSB_PLL_MONVC_EN              (0x1<<9) //9:9
 687 #define E60802_RG_SSUSB_PLL_RLH_EN                (0x1<<8) //8:8
 688 #define E60802_RG_SSUSB_PLL_AUTOK_KS              (0x3<<6) //7:6
 689 #define E60802_RG_SSUSB_PLL_AUTOK_KF              (0x3<<4) //5:4
 690 #define E60802_RG_SSUSB_PLL_RST_DLY               (0x3<<2) //3:2
 691
 692 //U3D_reg7
 693 #define E60802_RG_SSUSB_PLL_RESERVE               (0xffff<<16) //31:16
 694 #define E60802_RG_SSUSB_PLL_SSC_PRD               (0xffff<<0) //15:0
 695
 696 //U3D_reg8
 697 #define E60802_RG_SSUSB_PLL_SSC_PHASE_INI         (0x1<<31) //31:31
 698 #define E60802_RG_SSUSB_PLL_SSC_TRI_EN            (0x1<<30) //30:30
 699 #define E60802_RG_SSUSB_PLL_CLK_PH_INV            (0x1<<29) //29:29
 700 #define E60802_RG_SSUSB_PLL_DDS_LPF_EN            (0x1<<28) //28:28
 701 #define E60802_RG_SSUSB_PLL_DDS_RST_SEL           (0x1<<27) //27:27
 702 #define E60802_RG_SSUSB_PLL_DDS_VADJ              (0x1<<26) //26:26
 703 #define E60802_RG_SSUSB_PLL_DDS_MONEN             (0x1<<25) //25:25
 704 #define E60802_RG_SSUSB_PLL_DDS_SEL_EXT           (0x1<<24) //24:24
 705 #define E60802_RG_SSUSB_PLL_DDS_PI_PL_EN          (0x1<<23) //23:23
 706 #define E60802_RG_SSUSB_PLL_DDS_FRAC_MUTE         (0x7<<20) //22:20
 707 #define E60802_RG_SSUSB_PLL_DDS_HF_EN             (0x1<<19) //19:19
 708 #define E60802_RG_SSUSB_PLL_DDS_C                 (0x7<<16) //18:16
 709 #define E60802_RG_SSUSB_PLL_DDS_PREDIV2           (0x1<<15) //15:15
 710 #define E60802_RG_SSUSB_LFPS_LPF                  (0x3<<13) //14:13
 711
 712 //U3D_reg9
 713 #define E60802_RG_SSUSB_CDR_PD_DIV_BYPASS         (0x1<<31) //31:31
 714 #define E60802_RG_SSUSB_CDR_PD_DIV_SEL            (0x1<<30) //30:30
 715 #define E60802_RG_SSUSB_CDR_CPBIAS_SEL            (0x1<<29) //29:29
 716 #define E60802_RG_SSUSB_CDR_OSCDET_EN             (0x1<<28) //28:28
 717 #define E60802_RG_SSUSB_CDR_MONMUX                (0x1<<27) //27:27
 718 #define E60802_RG_SSUSB_CDR_RST_DLY               (0x3<<25) //26:25
 719 #define E60802_RG_SSUSB_CDR_RSTB_MANUAL           (0x1<<24) //24:24
 720 #define E60802_RG_SSUSB_CDR_BYPASS                (0x3<<22) //23:22
 721 #define E60802_RG_SSUSB_CDR_PI_SLEW               (0x3<<20) //21:20
 722 #define E60802_RG_SSUSB_CDR_EPEN                  (0x1<<19) //19:19
 723 #define E60802_RG_SSUSB_CDR_AUTOK_LOAD            (0x1<<18) //18:18
 724 #define E60802_RG_SSUSB_CDR_MONEN                 (0x1<<16) //16:16
 725 #define E60802_RG_SSUSB_CDR_MONEN_DIG             (0x1<<15) //15:15
 726 #define E60802_RG_SSUSB_CDR_REGOD                 (0x3<<13) //14:13
 727 #define E60802_RG_SSUSB_CDR_AUTOK_KS              (0x3<<11) //12:11
 728 #define E60802_RG_SSUSB_CDR_AUTOK_KF              (0x3<<9) //10:9
 729 #define E60802_RG_SSUSB_RX_DAC_EN                 (0x1<<8) //8:8
 730 #define E60802_RG_SSUSB_RX_DAC_PWD                (0x1<<7) //7:7
 731 #define E60802_RG_SSUSB_EQ_CURSEL                 (0x1<<6) //6:6
 732 #define E60802_RG_SSUSB_RX_DAC_MUX                (0x1f<<1) //5:1
 733 #define E60802_RG_SSUSB_RX_R2T_EN                 (0x1<<0) //0:0
 734
 735 //U3D_regA
 736 #define E60802_RG_SSUSB_RX_T2R_EN                 (0x1<<31) //31:31
 737 #define E60802_RG_SSUSB_RX_50_LOWER               (0x7<<28) //30:28
 738 #define E60802_RG_SSUSB_RX_50_TAR                 (0x3<<26) //27:26
 739 #define E60802_RG_SSUSB_RX_SW_CTRL                (0xf<<21) //24:21
 740 #define E60802_RG_PCIE_SIGDET_VTH                 (0x3<<19) //20:19
 741 #define E60802_RG_PCIE_SIGDET_LPF                 (0x3<<17) //18:17
 742 #define E60802_RG_SSUSB_LFPS_MON_EN               (0x1<<16) //16:16
 743 #define E60802_RG_SSUSB_RXAFE_DCMON_SEL           (0xf<<12) //15:12
 744 #define E60802_RG_SSUSB_RX_P1_ENTRY_PASS          (0x1<<11) //11:11
 745 #define E60802_RG_SSUSB_RX_PD_RST                 (0x1<<10) //10:10
 746 #define E60802_RG_SSUSB_RX_PD_RST_PASS            (0x1<<9) //9:9
 747
 748 //U3D_regB
 749 #define E60802_RG_SSUSB_CDR_RESERVE               (0xff<<24) //31:24
 750 #define E60802_RG_SSUSB_RXAFE_RESERVE             (0xff<<16) //23:16
 751 #define E60802_RG_PCIE_RX_RESERVE                 (0xff<<8) //15:8
 752 #define E60802_RG_SSUSB_VRT_25M_EN                (0x1<<7) //7:7
 753 #define E60802_RG_SSUSB_RX_PD_PICAL_SWAP          (0x1<<6) //6:6
 754 #define E60802_RG_SSUSB_RX_DAC_MEAS_EN            (0x1<<5) //5:5
 755 #define E60802_RG_SSUSB_MPX_SEL_L0                (0x1<<4) //4:4
 756 #define E60802_RG_SSUSB_LFPS_SLCOUT_SEL           (0x1<<3) //3:3
 757 #define E60802_RG_SSUSB_LFPS_CMPOUT_SEL           (0x1<<2) //2:2
 758 #define E60802_RG_PCIE_SIGDET_HF                  (0x3<<0) //1:0
 759
 760 //U3D_regC
 761 #define E60802_RGS_SSUSB_RX_DEBUG_RESERVE         (0xff<<0) //7:0
 762
 763 /* OFFSET */
 764
 765 //U3D_reg0
 766 #define E60802_RG_SSUSB_BGR_EN_OFST               (31)
 767 #define E60802_RG_SSUSB_CHPEN_OFST                (30)
 768 #define E60802_RG_SSUSB_BG_DIV_OFST               (28)
 769 #define E60802_RG_SSUSB_INTR_EN_OFST              (26)
 770 #define E60802_RG_SSUSB_MPX_EN_OFST               (24)
 771 #define E60802_RG_SSUSB_MPX_SEL_OFST              (16)
 772 #define E60802_RG_SSUSB_REF_EN_OFST               (15)
 773 #define E60802_RG_SSUSB_VRT_VREF_SEL_OFST         (11)
 774 #define E60802_RG_SSUSB_BG_MONEN_OFST             (8)
 775 #define E60802_RG_SSUSB_INT_BIAS_SEL_OFST         (7)
 776 #define E60802_RG_SSUSB_EXT_BIAS_SEL_OFST         (6)
 777 #define E60802_RG_PCIE_CLKDRV_OFFSET_OFST         (2)
 778 #define E60802_RG_PCIE_CLKDRV_SLEW_OFST           (0)
 779
 780 //U3D_reg1
 781 #define E60802_RG_PCIE_CLKDRV_AMP_OFST            (29)
 782 #define E60802_RG_SSUSB_XTAL_TST_A2DCK_EN_OFST    (28)
 783 #define E60802_RG_SSUSB_XTAL_MON_EN_OFST          (27)
 784 #define E60802_RG_SSUSB_XTAL_HYS_OFST             (26)
 785 #define E60802_RG_SSUSB_XTAL_TOP_RESERVE_OFST     (10)
 786 #define E60802_RG_SSUSB_SYSPLL_PREDIV_OFST        (8)
 787 #define E60802_RG_SSUSB_SYSPLL_POSDIV_OFST        (6)
 788 #define E60802_RG_SSUSB_SYSPLL_VCO_DIV_SEL_OFST   (5)
 789 #define E60802_RG_SSUSB_SYSPLL_VOD_EN_OFST        (4)
 790 #define E60802_RG_SSUSB_SYSPLL_RST_DLY_OFST       (2)
 791 #define E60802_RG_SSUSB_SYSPLL_BLP_OFST           (1)
 792 #define E60802_RG_SSUSB_SYSPLL_BP_OFST            (0)
 793
 794 //U3D_reg2
 795 #define E60802_RG_SSUSB_SYSPLL_BR_OFST            (31)
 796 #define E60802_RG_SSUSB_SYSPLL_BC_OFST            (30)
 797 #define E60802_RG_SSUSB_SYSPLL_MONCK_EN_OFST      (29)
 798 #define E60802_RG_SSUSB_SYSPLL_MONVC_EN_OFST      (28)
 799 #define E60802_RG_SSUSB_SYSPLL_MONREF_EN_OFST     (27)
 800 #define E60802_RG_SSUSB_SYSPLL_SDM_IFM_OFST       (26)
 801 #define E60802_RG_SSUSB_SYSPLL_SDM_OUT_OFST       (25)
 802 #define E60802_RG_SSUSB_SYSPLL_BACK_EN_OFST       (24)
 803
 804 //U3D_reg3
 805 #define E60802_RG_SSUSB_SYSPLL_FBDIV_OFST         (1)
 806 #define E60802_RG_SSUSB_SYSPLL_HR_EN_OFST         (0)
 807
 808 //U3D_reg4
 809 #define E60802_RG_SSUSB_SYSPLL_SDM_DI_EN_OFST     (31)
 810 #define E60802_RG_SSUSB_SYSPLL_SDM_DI_LS_OFST     (29)
 811 #define E60802_RG_SSUSB_SYSPLL_SDM_ORD_OFST       (27)
 812 #define E60802_RG_SSUSB_SYSPLL_SDM_MODE_OFST      (25)
 813 #define E60802_RG_SSUSB_SYSPLL_RESERVE_OFST       (17)
 814 #define E60802_RG_SSUSB_SYSPLL_TOP_RESERVE_OFST   (1)
 815
 816 //U3D_reg5
 817 #define E60802_RG_SSUSB_TX250MCK_INVB_OFST        (31)
 818 #define E60802_RG_SSUSB_IDRV_ITAILOP_EN_OFST      (30)
 819 #define E60802_RG_SSUSB_IDRV_CALIB_OFST           (24)
 820 #define E60802_RG_SSUSB_IDEM_BIAS_OFST            (20)
 821 #define E60802_RG_SSUSB_TX_R50_FON_OFST           (19)
 822 #define E60802_RG_SSUSB_TX_SR_OFST                (16)
 823 #define E60802_RG_SSUSB_RXDET_RSEL_OFST           (14)
 824 #define E60802_RG_SSUSB_RXDET_UPDN_FORCE_OFST     (13)
 825 #define E60802_RG_SSUSB_RXDET_UPDN_SEL_OFST       (12)
 826 #define E60802_RG_SSUSB_RXDET_VTHSEL_L_OFST       (10)
 827 #define E60802_RG_SSUSB_RXDET_VTHSEL_H_OFST       (8)
 828 #define E60802_RG_SSUSB_CKMON_EN_OFST             (7)
 829 #define E60802_RG_SSUSB_TX_VLMON_EN_OFST          (6)
 830 #define E60802_RG_SSUSB_TX_VLMON_SEL_OFST         (4)
 831 #define E60802_RG_SSUSB_CKMON_SEL_OFST            (0)
 832
 833 //U3D_reg6
 834 #define E60802_RG_SSUSB_TX_EIDLE_CM_OFST          (28)
 835 #define E60802_RG_SSUSB_RXLBTX_EN_OFST            (27)
 836 #define E60802_RG_SSUSB_TXLBRX_EN_OFST            (26)
 837 #define E60802_RG_SSUSB_RESERVE_OFST              (16)
 838 #define E60802_RG_SSUSB_PLL_POSDIV_OFST           (14)
 839 #define E60802_RG_SSUSB_PLL_AUTOK_LOAD_OFST       (13)
 840 #define E60802_RG_SSUSB_PLL_VOD_EN_OFST           (12)
 841 #define E60802_RG_SSUSB_PLL_MONREF_EN_OFST        (11)
 842 #define E60802_RG_SSUSB_PLL_MONCK_EN_OFST         (10)
 843 #define E60802_RG_SSUSB_PLL_MONVC_EN_OFST         (9)
 844 #define E60802_RG_SSUSB_PLL_RLH_EN_OFST           (8)
 845 #define E60802_RG_SSUSB_PLL_AUTOK_KS_OFST         (6)
 846 #define E60802_RG_SSUSB_PLL_AUTOK_KF_OFST         (4)
 847 #define E60802_RG_SSUSB_PLL_RST_DLY_OFST          (2)
 848
 849 //U3D_reg7
 850 #define E60802_RG_SSUSB_PLL_RESERVE_OFST          (16)
 851 #define E60802_RG_SSUSB_PLL_SSC_PRD_OFST          (0)
 852
 853 //U3D_reg8
 854 #define E60802_RG_SSUSB_PLL_SSC_PHASE_INI_OFST    (31)
 855 #define E60802_RG_SSUSB_PLL_SSC_TRI_EN_OFST       (30)
 856 #define E60802_RG_SSUSB_PLL_CLK_PH_INV_OFST       (29)
 857 #define E60802_RG_SSUSB_PLL_DDS_LPF_EN_OFST       (28)
 858 #define E60802_RG_SSUSB_PLL_DDS_RST_SEL_OFST      (27)
 859 #define E60802_RG_SSUSB_PLL_DDS_VADJ_OFST         (26)
 860 #define E60802_RG_SSUSB_PLL_DDS_MONEN_OFST        (25)
 861 #define E60802_RG_SSUSB_PLL_DDS_SEL_EXT_OFST      (24)
 862 #define E60802_RG_SSUSB_PLL_DDS_PI_PL_EN_OFST     (23)
 863 #define E60802_RG_SSUSB_PLL_DDS_FRAC_MUTE_OFST    (20)
 864 #define E60802_RG_SSUSB_PLL_DDS_HF_EN_OFST        (19)
 865 #define E60802_RG_SSUSB_PLL_DDS_C_OFST            (16)
 866 #define E60802_RG_SSUSB_PLL_DDS_PREDIV2_OFST      (15)
 867 #define E60802_RG_SSUSB_LFPS_LPF_OFST             (13)
 868
 869 //U3D_reg9
 870 #define E60802_RG_SSUSB_CDR_PD_DIV_BYPASS_OFST    (31)
 871 #define E60802_RG_SSUSB_CDR_PD_DIV_SEL_OFST       (30)
 872 #define E60802_RG_SSUSB_CDR_CPBIAS_SEL_OFST       (29)
 873 #define E60802_RG_SSUSB_CDR_OSCDET_EN_OFST        (28)
 874 #define E60802_RG_SSUSB_CDR_MONMUX_OFST           (27)
 875 #define E60802_RG_SSUSB_CDR_RST_DLY_OFST          (25)
 876 #define E60802_RG_SSUSB_CDR_RSTB_MANUAL_OFST      (24)
 877 #define E60802_RG_SSUSB_CDR_BYPASS_OFST           (22)
 878 #define E60802_RG_SSUSB_CDR_PI_SLEW_OFST          (20)
 879 #define E60802_RG_SSUSB_CDR_EPEN_OFST             (19)
 880 #define E60802_RG_SSUSB_CDR_AUTOK_LOAD_OFST       (18)
 881 #define E60802_RG_SSUSB_CDR_MONEN_OFST            (16)
 882 #define E60802_RG_SSUSB_CDR_MONEN_DIG_OFST        (15)
 883 #define E60802_RG_SSUSB_CDR_REGOD_OFST            (13)
 884 #define E60802_RG_SSUSB_CDR_AUTOK_KS_OFST         (11)
 885 #define E60802_RG_SSUSB_CDR_AUTOK_KF_OFST         (9)
 886 #define E60802_RG_SSUSB_RX_DAC_EN_OFST            (8)
 887 #define E60802_RG_SSUSB_RX_DAC_PWD_OFST           (7)
 888 #define E60802_RG_SSUSB_EQ_CURSEL_OFST            (6)
 889 #define E60802_RG_SSUSB_RX_DAC_MUX_OFST           (1)
 890 #define E60802_RG_SSUSB_RX_R2T_EN_OFST            (0)
 891
 892 //U3D_regA
 893 #define E60802_RG_SSUSB_RX_T2R_EN_OFST            (31)
 894 #define E60802_RG_SSUSB_RX_50_LOWER_OFST          (28)
 895 #define E60802_RG_SSUSB_RX_50_TAR_OFST            (26)
 896 #define E60802_RG_SSUSB_RX_SW_CTRL_OFST           (21)
 897 #define E60802_RG_PCIE_SIGDET_VTH_OFST            (19)
 898 #define E60802_RG_PCIE_SIGDET_LPF_OFST            (17)
 899 #define E60802_RG_SSUSB_LFPS_MON_EN_OFST          (16)
 900 #define E60802_RG_SSUSB_RXAFE_DCMON_SEL_OFST      (12)
 901 #define E60802_RG_SSUSB_RX_P1_ENTRY_PASS_OFST     (11)
 902 #define E60802_RG_SSUSB_RX_PD_RST_OFST            (10)
 903 #define E60802_RG_SSUSB_RX_PD_RST_PASS_OFST       (9)
 904
 905 //U3D_regB
 906 #define E60802_RG_SSUSB_CDR_RESERVE_OFST          (24)
 907 #define E60802_RG_SSUSB_RXAFE_RESERVE_OFST        (16)
 908 #define E60802_RG_PCIE_RX_RESERVE_OFST            (8)
 909 #define E60802_RG_SSUSB_VRT_25M_EN_OFST           (7)
 910 #define E60802_RG_SSUSB_RX_PD_PICAL_SWAP_OFST     (6)
 911 #define E60802_RG_SSUSB_RX_DAC_MEAS_EN_OFST       (5)
 912 #define E60802_RG_SSUSB_MPX_SEL_L0_OFST           (4)
 913 #define E60802_RG_SSUSB_LFPS_SLCOUT_SEL_OFST      (3)
 914 #define E60802_RG_SSUSB_LFPS_CMPOUT_SEL_OFST      (2)
 915 #define E60802_RG_PCIE_SIGDET_HF_OFST             (0)
 916
 917 //U3D_regC
 918 #define E60802_RGS_SSUSB_RX_DEBUG_RESERVE_OFST    (0)
 919
 920 ///////////////////////////////////////////////////////////////////////////////
 921
 922 struct u3phya_da_reg_e {
 923         //0x0
 924         PHY_LE32 reg0;
 925         PHY_LE32 reg1;
 926         PHY_LE32 reg4;
 927         PHY_LE32 reg5;
 928         //0x10
 929         PHY_LE32 reg6;
 930         PHY_LE32 reg7;
 931         PHY_LE32 reg8;
 932         PHY_LE32 reg9;
 933         //0x20
 934         PHY_LE32 reg10;
 935         PHY_LE32 reg12;
 936         PHY_LE32 reg13;
 937         PHY_LE32 reg14;
 938         //0x30
 939         PHY_LE32 reg15;
 940         PHY_LE32 reg16;
 941         PHY_LE32 reg19;
 942         PHY_LE32 reg20;
 943         //0x40
 944         PHY_LE32 reg21;
 945         PHY_LE32 reg23;
 946         PHY_LE32 reg25;
 947         PHY_LE32 reg26;
 948         //0x50
 949         PHY_LE32 reg28;
 950         PHY_LE32 reg29;
 951         PHY_LE32 reg30;
 952         PHY_LE32 reg31;
 953         //0x60
 954         PHY_LE32 reg32;
 955         PHY_LE32 reg33;
 956 };
 957
 958 //U3D_reg0
 959 #define E60802_RG_PCIE_SPEED_PE2D                 (0x1<<24) //24:24
 960 #define E60802_RG_PCIE_SPEED_PE2H                 (0x1<<23) //23:23
 961 #define E60802_RG_PCIE_SPEED_PE1D                 (0x1<<22) //22:22
 962 #define E60802_RG_PCIE_SPEED_PE1H                 (0x1<<21) //21:21
 963 #define E60802_RG_PCIE_SPEED_U3                   (0x1<<20) //20:20
 964 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE2D          (0x3<<18) //19:18
 965 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE2H          (0x3<<16) //17:16
 966 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE1D          (0x3<<14) //15:14
 967 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE1H          (0x3<<12) //13:12
 968 #define E60802_RG_SSUSB_XTAL_EXT_EN_U3            (0x3<<10) //11:10
 969 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE2D        (0x3<<8) //9:8
 970 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE2H        (0x3<<6) //7:6
 971 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE1D        (0x3<<4) //5:4
 972 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE1H        (0x3<<2) //3:2
 973 #define E60802_RG_SSUSB_CDR_REFCK_SEL_U3          (0x3<<0) //1:0
 974
 975 //U3D_reg1
 976 #define E60802_RG_USB20_REFCK_SEL_PE2D            (0x1<<30) //30:30
 977 #define E60802_RG_USB20_REFCK_SEL_PE2H            (0x1<<29) //29:29
 978 #define E60802_RG_USB20_REFCK_SEL_PE1D            (0x1<<28) //28:28
 979 #define E60802_RG_USB20_REFCK_SEL_PE1H            (0x1<<27) //27:27
 980 #define E60802_RG_USB20_REFCK_SEL_U3              (0x1<<26) //26:26
 981 #define E60802_RG_PCIE_REFCK_DIV4_PE2D            (0x1<<25) //25:25
 982 #define E60802_RG_PCIE_REFCK_DIV4_PE2H            (0x1<<24) //24:24
 983 #define E60802_RG_PCIE_REFCK_DIV4_PE1D            (0x1<<18) //18:18
 984 #define E60802_RG_PCIE_REFCK_DIV4_PE1H            (0x1<<17) //17:17
 985 #define E60802_RG_PCIE_REFCK_DIV4_U3              (0x1<<16) //16:16
 986 #define E60802_RG_PCIE_MODE_PE2D                  (0x1<<8) //8:8
 987 #define E60802_RG_PCIE_MODE_PE2H                  (0x1<<3) //3:3
 988 #define E60802_RG_PCIE_MODE_PE1D                  (0x1<<2) //2:2
 989 #define E60802_RG_PCIE_MODE_PE1H                  (0x1<<1) //1:1
 990 #define E60802_RG_PCIE_MODE_U3                    (0x1<<0) //0:0
 991
 992 //U3D_reg4
 993 #define E60802_RG_SSUSB_PLL_DIVEN_PE2D            (0x7<<22) //24:22
 994 #define E60802_RG_SSUSB_PLL_DIVEN_PE2H            (0x7<<19) //21:19
 995 #define E60802_RG_SSUSB_PLL_DIVEN_PE1D            (0x7<<16) //18:16
 996 #define E60802_RG_SSUSB_PLL_DIVEN_PE1H            (0x7<<13) //15:13
 997 #define E60802_RG_SSUSB_PLL_DIVEN_U3              (0x7<<10) //12:10
 998 #define E60802_RG_SSUSB_PLL_BC_PE2D               (0x3<<8) //9:8
 999 #define E60802_RG_SSUSB_PLL_BC_PE2H               (0x3<<6) //7:6
1000 #define E60802_RG_SSUSB_PLL_BC_PE1D               (0x3<<4) //5:4
1001 #define E60802_RG_SSUSB_PLL_BC_PE1H               (0x3<<2) //3:2
1002 #define E60802_RG_SSUSB_PLL_BC_U3                 (0x3<<0) //1:0
1003
1004 //U3D_reg5
1005 #define E60802_RG_SSUSB_PLL_BR_PE2D               (0x3<<30) //31:30
1006 #define E60802_RG_SSUSB_PLL_BR_PE2H               (0x3<<28) //29:28
1007 #define E60802_RG_SSUSB_PLL_BR_PE1D               (0x3<<26) //27:26
1008 #define E60802_RG_SSUSB_PLL_BR_PE1H               (0x3<<24) //25:24
1009 #define E60802_RG_SSUSB_PLL_BR_U3                 (0x3<<22) //23:22
1010 #define E60802_RG_SSUSB_PLL_IC_PE2D               (0xf<<16) //19:16
1011 #define E60802_RG_SSUSB_PLL_IC_PE2H               (0xf<<12) //15:12
1012 #define E60802_RG_SSUSB_PLL_IC_PE1D               (0xf<<8) //11:8
1013 #define E60802_RG_SSUSB_PLL_IC_PE1H               (0xf<<4) //7:4
1014 #define E60802_RG_SSUSB_PLL_IC_U3                 (0xf<<0) //3:0
1015
1016 //U3D_reg6
1017 #define E60802_RG_SSUSB_PLL_IR_PE2D               (0xf<<24) //27:24
1018 #define E60802_RG_SSUSB_PLL_IR_PE2H               (0xf<<16) //19:16
1019 #define E60802_RG_SSUSB_PLL_IR_PE1D               (0xf<<8) //11:8
1020 #define E60802_RG_SSUSB_PLL_IR_PE1H               (0xf<<4) //7:4
1021 #define E60802_RG_SSUSB_PLL_IR_U3                 (0xf<<0) //3:0
1022
1023 //U3D_reg7
1024 #define E60802_RG_SSUSB_PLL_BP_PE2D               (0xf<<24) //27:24
1025 #define E60802_RG_SSUSB_PLL_BP_PE2H               (0xf<<16) //19:16
1026 #define E60802_RG_SSUSB_PLL_BP_PE1D               (0xf<<8) //11:8
1027 #define E60802_RG_SSUSB_PLL_BP_PE1H               (0xf<<4) //7:4
1028 #define E60802_RG_SSUSB_PLL_BP_U3                 (0xf<<0) //3:0
1029
1030 //U3D_reg8
1031 #define E60802_RG_SSUSB_PLL_FBKSEL_PE2D           (0x3<<24) //25:24
1032 #define E60802_RG_SSUSB_PLL_FBKSEL_PE2H           (0x3<<16) //17:16
1033 #define E60802_RG_SSUSB_PLL_FBKSEL_PE1D           (0x3<<8) //9:8
1034 #define E60802_RG_SSUSB_PLL_FBKSEL_PE1H           (0x3<<2) //3:2
1035 #define E60802_RG_SSUSB_PLL_FBKSEL_U3             (0x3<<0) //1:0
1036
1037 //U3D_reg9
1038 #define E60802_RG_SSUSB_PLL_FBKDIV_PE2H           (0x7f<<24) //30:24
1039 #define E60802_RG_SSUSB_PLL_FBKDIV_PE1D           (0x7f<<16) //22:16
1040 #define E60802_RG_SSUSB_PLL_FBKDIV_PE1H           (0x7f<<8) //14:8
1041 #define E60802_RG_SSUSB_PLL_FBKDIV_U3             (0x7f<<0) //6:0
1042
1043 //U3D_reg10
1044 #define E60802_RG_SSUSB_PLL_PREDIV_PE2D           (0x3<<26) //27:26
1045 #define E60802_RG_SSUSB_PLL_PREDIV_PE2H           (0x3<<24) //25:24
1046 #define E60802_RG_SSUSB_PLL_PREDIV_PE1D           (0x3<<18) //19:18
1047 #define E60802_RG_SSUSB_PLL_PREDIV_PE1H           (0x3<<16) //17:16
1048 #define E60802_RG_SSUSB_PLL_PREDIV_U3             (0x3<<8) //9:8
1049 #define E60802_RG_SSUSB_PLL_FBKDIV_PE2D           (0x7f<<0) //6:0
1050
1051 //U3D_reg12
1052 #define E60802_RG_SSUSB_PLL_PCW_NCPO_U3           (0x7fffffff<<0) //30:0
1053
1054 //U3D_reg13
1055 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE1H         (0x7fffffff<<0) //30:0
1056
1057 //U3D_reg14
1058 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE1D         (0x7fffffff<<0) //30:0
1059
1060 //U3D_reg15
1061 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE2H         (0x7fffffff<<0) //30:0
1062
1063 //U3D_reg16
1064 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE2D         (0x7fffffff<<0) //30:0
1065
1066 //U3D_reg19
1067 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE1H       (0xffff<<16) //31:16
1068 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_U3         (0xffff<<0) //15:0
1069
1070 //U3D_reg20
1071 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE2H       (0xffff<<16) //31:16
1072 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE1D       (0xffff<<0) //15:0
1073
1074 //U3D_reg21
1075 #define E60802_RG_SSUSB_PLL_SSC_DELTA_U3          (0xffffU<<16) //31:16
1076 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE2D       (0xffff<<0) //15:0
1077
1078 //U3D_reg23
1079 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE1D        (0xffff<<16) //31:16
1080 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE1H        (0xffff<<0) //15:0
1081
1082 //U3D_reg25
1083 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE2D        (0xffff<<16) //31:16
1084 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE2H        (0xffff<<0) //15:0
1085
1086 //U3D_reg26
1087 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE2D         (0x1<<25) //25:25
1088 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE2H         (0x1<<24) //24:24
1089 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE1D         (0x1<<16) //16:16
1090 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE1H         (0x1<<8) //8:8
1091 #define E60802_RG_SSUSB_PLL_REFCKDIV_U3           (0x1<<0) //0:0
1092
1093 //U3D_reg28
1094 #define E60802_RG_SSUSB_CDR_BPA_PE2D              (0x3<<24) //25:24
1095 #define E60802_RG_SSUSB_CDR_BPA_PE2H              (0x3<<16) //17:16
1096 #define E60802_RG_SSUSB_CDR_BPA_PE1D              (0x3<<10) //11:10
1097 #define E60802_RG_SSUSB_CDR_BPA_PE1H              (0x3<<8) //9:8
1098 #define E60802_RG_SSUSB_CDR_BPA_U3                (0x3<<0) //1:0
1099
1100 //U3D_reg29
1101 #define E60802_RG_SSUSB_CDR_BPB_PE2D              (0x7<<24) //26:24
1102 #define E60802_RG_SSUSB_CDR_BPB_PE2H              (0x7<<16) //18:16
1103 #define E60802_RG_SSUSB_CDR_BPB_PE1D              (0x7<<6) //8:6
1104 #define E60802_RG_SSUSB_CDR_BPB_PE1H              (0x7<<3) //5:3
1105 #define E60802_RG_SSUSB_CDR_BPB_U3                (0x7<<0) //2:0
1106
1107 //U3D_reg30
1108 #define E60802_RG_SSUSB_CDR_BR_PE2D               (0x7<<24) //26:24
1109 #define E60802_RG_SSUSB_CDR_BR_PE2H               (0x7<<16) //18:16
1110 #define E60802_RG_SSUSB_CDR_BR_PE1D               (0x7<<6) //8:6
1111 #define E60802_RG_SSUSB_CDR_BR_PE1H               (0x7<<3) //5:3
1112 #define E60802_RG_SSUSB_CDR_BR_U3                 (0x7<<0) //2:0
1113
1114 //U3D_reg31
1115 #define E60802_RG_SSUSB_CDR_FBDIV_PE2H            (0x7f<<24) //30:24
1116 #define E60802_RG_SSUSB_CDR_FBDIV_PE1D            (0x7f<<16) //22:16
1117 #define E60802_RG_SSUSB_CDR_FBDIV_PE1H            (0x7f<<8) //14:8
1118 #define E60802_RG_SSUSB_CDR_FBDIV_U3              (0x7f<<0) //6:0
1119
1120 //U3D_reg32
1121 #define E60802_RG_SSUSB_EQ_RSTEP1_PE2D            (0x3<<30) //31:30
1122 #define E60802_RG_SSUSB_EQ_RSTEP1_PE2H            (0x3<<28) //29:28
1123 #define E60802_RG_SSUSB_EQ_RSTEP1_PE1D            (0x3<<26) //27:26
1124 #define E60802_RG_SSUSB_EQ_RSTEP1_PE1H            (0x3<<24) //25:24
1125 #define E60802_RG_SSUSB_EQ_RSTEP1_U3              (0x3<<22) //23:22
1126 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE2D        (0x3<<20) //21:20
1127 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE2H        (0x3<<18) //19:18
1128 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE1D        (0x3<<16) //17:16
1129 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE1H        (0x3<<14) //15:14
1130 #define E60802_RG_SSUSB_LFPS_DEGLITCH_U3          (0x3<<12) //13:12
1131 #define E60802_RG_SSUSB_CDR_KVSEL_PE2D            (0x1<<11) //11:11
1132 #define E60802_RG_SSUSB_CDR_KVSEL_PE2H            (0x1<<10) //10:10
1133 #define E60802_RG_SSUSB_CDR_KVSEL_PE1D            (0x1<<9) //9:9
1134 #define E60802_RG_SSUSB_CDR_KVSEL_PE1H            (0x1<<8) //8:8
1135 #define E60802_RG_SSUSB_CDR_KVSEL_U3              (0x1<<7) //7:7
1136 #define E60802_RG_SSUSB_CDR_FBDIV_PE2D            (0x7f<<0) //6:0
1137
1138 //U3D_reg33
1139 #define E60802_RG_SSUSB_RX_CMPWD_PE2D             (0x1<<26) //26:26
1140 #define E60802_RG_SSUSB_RX_CMPWD_PE2H             (0x1<<25) //25:25
1141 #define E60802_RG_SSUSB_RX_CMPWD_PE1D             (0x1<<24) //24:24
1142 #define E60802_RG_SSUSB_RX_CMPWD_PE1H             (0x1<<23) //23:23
1143 #define E60802_RG_SSUSB_RX_CMPWD_U3               (0x1<<16) //16:16
1144 #define E60802_RG_SSUSB_EQ_RSTEP2_PE2D            (0x3<<8) //9:8
1145 #define E60802_RG_SSUSB_EQ_RSTEP2_PE2H            (0x3<<6) //7:6
1146 #define E60802_RG_SSUSB_EQ_RSTEP2_PE1D            (0x3<<4) //5:4
1147 #define E60802_RG_SSUSB_EQ_RSTEP2_PE1H            (0x3<<2) //3:2
1148 #define E60802_RG_SSUSB_EQ_RSTEP2_U3              (0x3<<0) //1:0
1149
1150 /* OFFSET DEFINITION */
1151
1152 //U3D_reg0
1153 #define E60802_RG_PCIE_SPEED_PE2D_OFST            (24)
1154 #define E60802_RG_PCIE_SPEED_PE2H_OFST            (23)
1155 #define E60802_RG_PCIE_SPEED_PE1D_OFST            (22)
1156 #define E60802_RG_PCIE_SPEED_PE1H_OFST            (21)
1157 #define E60802_RG_PCIE_SPEED_U3_OFST              (20)
1158 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE2D_OFST     (18)
1159 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE2H_OFST     (16)
1160 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE1D_OFST     (14)
1161 #define E60802_RG_SSUSB_XTAL_EXT_EN_PE1H_OFST     (12)
1162 #define E60802_RG_SSUSB_XTAL_EXT_EN_U3_OFST       (10)
1163 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE2D_OFST   (8)
1164 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE2H_OFST   (6)
1165 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE1D_OFST   (4)
1166 #define E60802_RG_SSUSB_CDR_REFCK_SEL_PE1H_OFST   (2)
1167 #define E60802_RG_SSUSB_CDR_REFCK_SEL_U3_OFST     (0)
1168
1169 //U3D_reg1
1170 #define E60802_RG_USB20_REFCK_SEL_PE2D_OFST       (30)
1171 #define E60802_RG_USB20_REFCK_SEL_PE2H_OFST       (29)
1172 #define E60802_RG_USB20_REFCK_SEL_PE1D_OFST       (28)
1173 #define E60802_RG_USB20_REFCK_SEL_PE1H_OFST       (27)
1174 #define E60802_RG_USB20_REFCK_SEL_U3_OFST         (26)
1175 #define E60802_RG_PCIE_REFCK_DIV4_PE2D_OFST       (25)
1176 #define E60802_RG_PCIE_REFCK_DIV4_PE2H_OFST       (24)
1177 #define E60802_RG_PCIE_REFCK_DIV4_PE1D_OFST       (18)
1178 #define E60802_RG_PCIE_REFCK_DIV4_PE1H_OFST       (17)
1179 #define E60802_RG_PCIE_REFCK_DIV4_U3_OFST         (16)
1180 #define E60802_RG_PCIE_MODE_PE2D_OFST             (8)
1181 #define E60802_RG_PCIE_MODE_PE2H_OFST             (3)
1182 #define E60802_RG_PCIE_MODE_PE1D_OFST             (2)
1183 #define E60802_RG_PCIE_MODE_PE1H_OFST             (1)
1184 #define E60802_RG_PCIE_MODE_U3_OFST               (0)
1185
1186 //U3D_reg4
1187 #define E60802_RG_SSUSB_PLL_DIVEN_PE2D_OFST       (22)
1188 #define E60802_RG_SSUSB_PLL_DIVEN_PE2H_OFST       (19)
1189 #define E60802_RG_SSUSB_PLL_DIVEN_PE1D_OFST       (16)
1190 #define E60802_RG_SSUSB_PLL_DIVEN_PE1H_OFST       (13)
1191 #define E60802_RG_SSUSB_PLL_DIVEN_U3_OFST         (10)
1192 #define E60802_RG_SSUSB_PLL_BC_PE2D_OFST          (8)
1193 #define E60802_RG_SSUSB_PLL_BC_PE2H_OFST          (6)
1194 #define E60802_RG_SSUSB_PLL_BC_PE1D_OFST          (4)
1195 #define E60802_RG_SSUSB_PLL_BC_PE1H_OFST          (2)
1196 #define E60802_RG_SSUSB_PLL_BC_U3_OFST            (0)
1197
1198 //U3D_reg5
1199 #define E60802_RG_SSUSB_PLL_BR_PE2D_OFST          (30)
1200 #define E60802_RG_SSUSB_PLL_BR_PE2H_OFST          (28)
1201 #define E60802_RG_SSUSB_PLL_BR_PE1D_OFST          (26)
1202 #define E60802_RG_SSUSB_PLL_BR_PE1H_OFST          (24)
1203 #define E60802_RG_SSUSB_PLL_BR_U3_OFST            (22)
1204 #define E60802_RG_SSUSB_PLL_IC_PE2D_OFST          (16)
1205 #define E60802_RG_SSUSB_PLL_IC_PE2H_OFST          (12)
1206 #define E60802_RG_SSUSB_PLL_IC_PE1D_OFST          (8)
1207 #define E60802_RG_SSUSB_PLL_IC_PE1H_OFST          (4)
1208 #define E60802_RG_SSUSB_PLL_IC_U3_OFST            (0)
1209
1210 //U3D_reg6
1211 #define E60802_RG_SSUSB_PLL_IR_PE2D_OFST          (24)
1212 #define E60802_RG_SSUSB_PLL_IR_PE2H_OFST          (16)
1213 #define E60802_RG_SSUSB_PLL_IR_PE1D_OFST          (8)
1214 #define E60802_RG_SSUSB_PLL_IR_PE1H_OFST          (4)
1215 #define E60802_RG_SSUSB_PLL_IR_U3_OFST            (0)
1216
1217 //U3D_reg7
1218 #define E60802_RG_SSUSB_PLL_BP_PE2D_OFST          (24)
1219 #define E60802_RG_SSUSB_PLL_BP_PE2H_OFST          (16)
1220 #define E60802_RG_SSUSB_PLL_BP_PE1D_OFST          (8)
1221 #define E60802_RG_SSUSB_PLL_BP_PE1H_OFST          (4)
1222 #define E60802_RG_SSUSB_PLL_BP_U3_OFST            (0)
1223
1224 //U3D_reg8
1225 #define E60802_RG_SSUSB_PLL_FBKSEL_PE2D_OFST      (24)
1226 #define E60802_RG_SSUSB_PLL_FBKSEL_PE2H_OFST      (16)
1227 #define E60802_RG_SSUSB_PLL_FBKSEL_PE1D_OFST      (8)
1228 #define E60802_RG_SSUSB_PLL_FBKSEL_PE1H_OFST      (2)
1229 #define E60802_RG_SSUSB_PLL_FBKSEL_U3_OFST        (0)
1230
1231 //U3D_reg9
1232 #define E60802_RG_SSUSB_PLL_FBKDIV_PE2H_OFST      (24)
1233 #define E60802_RG_SSUSB_PLL_FBKDIV_PE1D_OFST      (16)
1234 #define E60802_RG_SSUSB_PLL_FBKDIV_PE1H_OFST      (8)
1235 #define E60802_RG_SSUSB_PLL_FBKDIV_U3_OFST        (0)
1236
1237 //U3D_reg10
1238 #define E60802_RG_SSUSB_PLL_PREDIV_PE2D_OFST      (26)
1239 #define E60802_RG_SSUSB_PLL_PREDIV_PE2H_OFST      (24)
1240 #define E60802_RG_SSUSB_PLL_PREDIV_PE1D_OFST      (18)
1241 #define E60802_RG_SSUSB_PLL_PREDIV_PE1H_OFST      (16)
1242 #define E60802_RG_SSUSB_PLL_PREDIV_U3_OFST        (8)
1243 #define E60802_RG_SSUSB_PLL_FBKDIV_PE2D_OFST      (0)
1244
1245 //U3D_reg12
1246 #define E60802_RG_SSUSB_PLL_PCW_NCPO_U3_OFST      (0)
1247
1248 //U3D_reg13
1249 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE1H_OFST    (0)
1250
1251 //U3D_reg14
1252 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE1D_OFST    (0)
1253
1254 //U3D_reg15
1255 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE2H_OFST    (0)
1256
1257 //U3D_reg16
1258 #define E60802_RG_SSUSB_PLL_PCW_NCPO_PE2D_OFST    (0)
1259
1260 //U3D_reg19
1261 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE1H_OFST  (16)
1262 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_U3_OFST    (0)
1263
1264 //U3D_reg20
1265 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE2H_OFST  (16)
1266 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE1D_OFST  (0)
1267
1268 //U3D_reg21
1269 #define E60802_RG_SSUSB_PLL_SSC_DELTA_U3_OFST     (16)
1270 #define E60802_RG_SSUSB_PLL_SSC_DELTA1_PE2D_OFST  (0)
1271
1272 //U3D_reg23
1273 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE1D_OFST   (16)
1274 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE1H_OFST   (0)
1275
1276 //U3D_reg25
1277 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE2D_OFST   (16)
1278 #define E60802_RG_SSUSB_PLL_SSC_DELTA_PE2H_OFST   (0)
1279
1280 //U3D_reg26
1281 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE2D_OFST    (25)
1282 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE2H_OFST    (24)
1283 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE1D_OFST    (16)
1284 #define E60802_RG_SSUSB_PLL_REFCKDIV_PE1H_OFST    (8)
1285 #define E60802_RG_SSUSB_PLL_REFCKDIV_U3_OFST      (0)
1286
1287 //U3D_reg28
1288 #define E60802_RG_SSUSB_CDR_BPA_PE2D_OFST         (24)
1289 #define E60802_RG_SSUSB_CDR_BPA_PE2H_OFST         (16)
1290 #define E60802_RG_SSUSB_CDR_BPA_PE1D_OFST         (10)
1291 #define E60802_RG_SSUSB_CDR_BPA_PE1H_OFST         (8)
1292 #define E60802_RG_SSUSB_CDR_BPA_U3_OFST           (0)
1293
1294 //U3D_reg29
1295 #define E60802_RG_SSUSB_CDR_BPB_PE2D_OFST         (24)
1296 #define E60802_RG_SSUSB_CDR_BPB_PE2H_OFST         (16)
1297 #define E60802_RG_SSUSB_CDR_BPB_PE1D_OFST         (6)
1298 #define E60802_RG_SSUSB_CDR_BPB_PE1H_OFST         (3)
1299 #define E60802_RG_SSUSB_CDR_BPB_U3_OFST           (0)
1300
1301 //U3D_reg30
1302 #define E60802_RG_SSUSB_CDR_BR_PE2D_OFST          (24)
1303 #define E60802_RG_SSUSB_CDR_BR_PE2H_OFST          (16)
1304 #define E60802_RG_SSUSB_CDR_BR_PE1D_OFST          (6)
1305 #define E60802_RG_SSUSB_CDR_BR_PE1H_OFST          (3)
1306 #define E60802_RG_SSUSB_CDR_BR_U3_OFST            (0)
1307
1308 //U3D_reg31
1309 #define E60802_RG_SSUSB_CDR_FBDIV_PE2H_OFST       (24)
1310 #define E60802_RG_SSUSB_CDR_FBDIV_PE1D_OFST       (16)
1311 #define E60802_RG_SSUSB_CDR_FBDIV_PE1H_OFST       (8)
1312 #define E60802_RG_SSUSB_CDR_FBDIV_U3_OFST         (0)
1313
1314 //U3D_reg32
1315 #define E60802_RG_SSUSB_EQ_RSTEP1_PE2D_OFST       (30)
1316 #define E60802_RG_SSUSB_EQ_RSTEP1_PE2H_OFST       (28)
1317 #define E60802_RG_SSUSB_EQ_RSTEP1_PE1D_OFST       (26)
1318 #define E60802_RG_SSUSB_EQ_RSTEP1_PE1H_OFST       (24)
1319 #define E60802_RG_SSUSB_EQ_RSTEP1_U3_OFST         (22)
1320 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE2D_OFST   (20)
1321 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE2H_OFST   (18)
1322 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE1D_OFST   (16)
1323 #define E60802_RG_SSUSB_LFPS_DEGLITCH_PE1H_OFST   (14)
1324 #define E60802_RG_SSUSB_LFPS_DEGLITCH_U3_OFST     (12)
1325 #define E60802_RG_SSUSB_CDR_KVSEL_PE2D_OFST       (11)
1326 #define E60802_RG_SSUSB_CDR_KVSEL_PE2H_OFST       (10)
1327 #define E60802_RG_SSUSB_CDR_KVSEL_PE1D_OFST       (9)
1328 #define E60802_RG_SSUSB_CDR_KVSEL_PE1H_OFST       (8)
1329 #define E60802_RG_SSUSB_CDR_KVSEL_U3_OFST         (7)
1330 #define E60802_RG_SSUSB_CDR_FBDIV_PE2D_OFST       (0)
1331
1332 //U3D_reg33
1333 #define E60802_RG_SSUSB_RX_CMPWD_PE2D_OFST        (26)
1334 #define E60802_RG_SSUSB_RX_CMPWD_PE2H_OFST        (25)
1335 #define E60802_RG_SSUSB_RX_CMPWD_PE1D_OFST        (24)
1336 #define E60802_RG_SSUSB_RX_CMPWD_PE1H_OFST        (23)
1337 #define E60802_RG_SSUSB_RX_CMPWD_U3_OFST          (16)
1338 #define E60802_RG_SSUSB_EQ_RSTEP2_PE2D_OFST       (8)
1339 #define E60802_RG_SSUSB_EQ_RSTEP2_PE2H_OFST       (6)
1340 #define E60802_RG_SSUSB_EQ_RSTEP2_PE1D_OFST       (4)
1341 #define E60802_RG_SSUSB_EQ_RSTEP2_PE1H_OFST       (2)
1342 #define E60802_RG_SSUSB_EQ_RSTEP2_U3_OFST         (0)
1343
1344 ///////////////////////////////////////////////////////////////////////////////
1345
1346 struct u3phyd_reg_e {
1347         //0x0
1348         PHY_LE32 phyd_mix0;
1349         PHY_LE32 phyd_mix1;
1350         PHY_LE32 phyd_lfps0;
1351         PHY_LE32 phyd_lfps1;
1352         //0x10
1353         PHY_LE32 phyd_impcal0;
1354         PHY_LE32 phyd_impcal1;
1355         PHY_LE32 phyd_txpll0;
1356         PHY_LE32 phyd_txpll1;
1357         //0x20
1358         PHY_LE32 phyd_txpll2;
1359         PHY_LE32 phyd_fl0;
1360         PHY_LE32 phyd_mix2;
1361         PHY_LE32 phyd_rx0;
1362         //0x30
1363         PHY_LE32 phyd_t2rlb;
1364         PHY_LE32 phyd_cppat;
1365         PHY_LE32 phyd_mix3;
1366         PHY_LE32 phyd_ebufctl;
1367         //0x40
1368         PHY_LE32 phyd_pipe0;
1369         PHY_LE32 phyd_pipe1;
1370         PHY_LE32 phyd_mix4;
1371         PHY_LE32 phyd_ckgen0;
1372         //0x50
1373         PHY_LE32 phyd_mix5;
1374         PHY_LE32 phyd_reserved;
1375         PHY_LE32 phyd_cdr0;
1376         PHY_LE32 phyd_cdr1;
1377         //0x60
1378         PHY_LE32 phyd_pll_0;
1379         PHY_LE32 phyd_pll_1;
1380         PHY_LE32 phyd_bcn_det_1;
1381         PHY_LE32 phyd_bcn_det_2;
1382         //0x70
1383         PHY_LE32 eq0;
1384         PHY_LE32 eq1;
1385         PHY_LE32 eq2;
1386         PHY_LE32 eq3;
1387         //0x80
1388         PHY_LE32 eq_eye0;
1389         PHY_LE32 eq_eye1;
1390         PHY_LE32 eq_eye2;
1391         PHY_LE32 eq_dfe0;
1392         //0x90
1393         PHY_LE32 eq_dfe1;
1394         PHY_LE32 eq_dfe2;
1395         PHY_LE32 eq_dfe3;
1396         PHY_LE32 reserve0;
1397         //0xa0
1398         PHY_LE32 phyd_mon0;
1399         PHY_LE32 phyd_mon1;
1400         PHY_LE32 phyd_mon2;
1401         PHY_LE32 phyd_mon3;
1402         //0xb0
1403         PHY_LE32 phyd_mon4;
1404         PHY_LE32 phyd_mon5;
1405         PHY_LE32 phyd_mon6;
1406         PHY_LE32 phyd_mon7;
1407         //0xc0
1408         PHY_LE32 phya_rx_mon0;
1409         PHY_LE32 phya_rx_mon1;
1410         PHY_LE32 phya_rx_mon2;
1411         PHY_LE32 phya_rx_mon3;
1412         //0xd0
1413         PHY_LE32 phya_rx_mon4;
1414         PHY_LE32 phya_rx_mon5;
1415         PHY_LE32 phyd_cppat2;
1416         PHY_LE32 eq_eye3;
1417         //0xe0
1418         PHY_LE32 kband_out;
1419         PHY_LE32 kband_out1;
1420 };
1421
1422 //U3D_PHYD_MIX0
1423 #define E60802_RG_SSUSB_P_P3_TX_NG                (0x1<<31) //31:31
1424 #define E60802_RG_SSUSB_TSEQ_EN                   (0x1<<30) //30:30
1425 #define E60802_RG_SSUSB_TSEQ_POLEN                (0x1<<29) //29:29
1426 #define E60802_RG_SSUSB_TSEQ_POL                  (0x1<<28) //28:28
1427 #define E60802_RG_SSUSB_P_P3_PCLK_NG              (0x1<<27) //27:27
1428 #define E60802_RG_SSUSB_TSEQ_TH                   (0x7<<24) //26:24
1429 #define E60802_RG_SSUSB_PRBS_BERTH                (0xff<<16) //23:16
1430 #define E60802_RG_SSUSB_DISABLE_PHY_U2_ON         (0x1<<15) //15:15
1431 #define E60802_RG_SSUSB_DISABLE_PHY_U2_OFF        (0x1<<14) //14:14
1432 #define E60802_RG_SSUSB_PRBS_EN                   (0x1<<13) //13:13
1433 #define E60802_RG_SSUSB_BPSLOCK                   (0x1<<12) //12:12
1434 #define E60802_RG_SSUSB_RTCOMCNT                  (0xf<<8) //11:8
1435 #define E60802_RG_SSUSB_COMCNT                    (0xf<<4) //7:4
1436 #define E60802_RG_SSUSB_PRBSEL_CALIB              (0xf<<0) //3:0
1437
1438 //U3D_PHYD_MIX1
1439 #define E60802_RG_SSUSB_SLEEP_EN                  (0x1<<31) //31:31
1440 #define E60802_RG_SSUSB_PRBSEL_PCS                (0x7<<28) //30:28
1441 #define E60802_RG_SSUSB_TXLFPS_PRD                (0xf<<24) //27:24
1442 #define E60802_RG_SSUSB_P_RX_P0S_CK               (0x1<<23) //23:23
1443 #define E60802_RG_SSUSB_P_TX_P0S_CK               (0x1<<22) //22:22
1444 #define E60802_RG_SSUSB_PDNCTL                    (0x3f<<16) //21:16
1445 #define E60802_RG_SSUSB_TX_DRV_EN                 (0x1<<15) //15:15
1446 #define E60802_RG_SSUSB_TX_DRV_SEL                (0x1<<14) //14:14
1447 #define E60802_RG_SSUSB_TX_DRV_DLY                (0x3f<<8) //13:8
1448 #define E60802_RG_SSUSB_BERT_EN                   (0x1<<7) //7:7
1449 #define E60802_RG_SSUSB_SCP_TH                    (0x7<<4) //6:4
1450 #define E60802_RG_SSUSB_SCP_EN                    (0x1<<3) //3:3
1451 #define E60802_RG_SSUSB_RXANSIDEC_TEST            (0x7<<0) //2:0
1452
1453 //U3D_PHYD_LFPS0
1454 #define E60802_RG_SSUSB_LFPS_PWD                  (0x1<<30) //30:30
1455 #define E60802_RG_SSUSB_FORCE_LFPS_PWD            (0x1<<29) //29:29
1456 #define E60802_RG_SSUSB_RXLFPS_OVF                (0x1f<<24) //28:24
1457 #define E60802_RG_SSUSB_P3_ENTRY_SEL              (0x1<<23) //23:23
1458 #define E60802_RG_SSUSB_P3_ENTRY                  (0x1<<22) //22:22
1459 #define E60802_RG_SSUSB_RXLFPS_CDRSEL             (0x3<<20) //21:20
1460 #define E60802_RG_SSUSB_RXLFPS_CDRTH              (0xf<<16) //19:16
1461 #define E60802_RG_SSUSB_LOCK5G_BLOCK              (0x1<<15) //15:15
1462 #define E60802_RG_SSUSB_TFIFO_EXT_D_SEL           (0x1<<14) //14:14
1463 #define E60802_RG_SSUSB_TFIFO_NO_EXTEND           (0x1<<13) //13:13
1464 #define E60802_RG_SSUSB_RXLFPS_LOB                (0x1f<<8) //12:8
1465 #define E60802_RG_SSUSB_TXLFPS_EN                 (0x1<<7) //7:7
1466 #define E60802_RG_SSUSB_TXLFPS_SEL                (0x1<<6) //6:6
1467 #define E60802_RG_SSUSB_RXLFPS_CDRLOCK            (0x1<<5) //5:5
1468 #define E60802_RG_SSUSB_RXLFPS_UPB                (0x1f<<0) //4:0
1469
1470 //U3D_PHYD_LFPS1
1471 #define E60802_RG_SSUSB_RX_IMP_BIAS               (0xf<<28) //31:28
1472 #define E60802_RG_SSUSB_TX_IMP_BIAS               (0xf<<24) //27:24
1473 #define E60802_RG_SSUSB_FWAKE_TH                  (0x3f<<16) //21:16
1474 #define E60802_RG_SSUSB_P1_ENTRY_SEL              (0x1<<14) //14:14
1475 #define E60802_RG_SSUSB_P1_ENTRY                  (0x1<<13) //13:13
1476 #define E60802_RG_SSUSB_RXLFPS_UDF                (0x1f<<8) //12:8
1477 #define E60802_RG_SSUSB_RXLFPS_P0IDLETH           (0xff<<0) //7:0
1478
1479 //U3D_PHYD_IMPCAL0
1480 #define E60802_RG_SSUSB_FORCE_TX_IMPSEL           (0x1<<31) //31:31
1481 #define E60802_RG_SSUSB_TX_IMPCAL_EN              (0x1<<30) //30:30
1482 #define E60802_RG_SSUSB_FORCE_TX_IMPCAL_EN        (0x1<<29) //29:29
1483 #define E60802_RG_SSUSB_TX_IMPSEL                 (0x1f<<24) //28:24
1484 #define E60802_RG_SSUSB_TX_IMPCAL_CALCYC          (0x3f<<16) //21:16
1485 #define E60802_RG_SSUSB_TX_IMPCAL_STBCYC          (0x1f<<10) //14:10
1486 #define E60802_RG_SSUSB_TX_IMPCAL_CYCCNT          (0x3ff<<0) //9:0
1487
1488 //U3D_PHYD_IMPCAL1
1489 #define E60802_RG_SSUSB_FORCE_RX_IMPSEL           (0x1<<31) //31:31
1490 #define E60802_RG_SSUSB_RX_IMPCAL_EN              (0x1<<30) //30:30
1491 #define E60802_RG_SSUSB_FORCE_RX_IMPCAL_EN        (0x1<<29) //29:29
1492 #define E60802_RG_SSUSB_RX_IMPSEL                 (0x1f<<24) //28:24
1493 #define E60802_RG_SSUSB_RX_IMPCAL_CALCYC          (0x3f<<16) //21:16
1494 #define E60802_RG_SSUSB_RX_IMPCAL_STBCYC          (0x1f<<10) //14:10
1495 #define E60802_RG_SSUSB_RX_IMPCAL_CYCCNT          (0x3ff<<0) //9:0
1496
1497 //U3D_PHYD_TXPLL0
1498 #define E60802_RG_SSUSB_TXPLL_DDSEN_CYC           (0x1f<<27) //31:27
1499 #define E60802_RG_SSUSB_TXPLL_ON                  (0x1<<26) //26:26
1500 #define E60802_RG_SSUSB_FORCE_TXPLLON             (0x1<<25) //25:25
1501 #define E60802_RG_SSUSB_TXPLL_STBCYC              (0x1ff<<16) //24:16
1502 #define E60802_RG_SSUSB_TXPLL_NCPOCHG_CYC         (0xf<<12) //15:12
1503 #define E60802_RG_SSUSB_TXPLL_NCPOEN_CYC          (0x3<<10) //11:10
1504 #define E60802_RG_SSUSB_TXPLL_DDSRSTB_CYC         (0x7<<0) //2:0
1505
1506 //U3D_PHYD_TXPLL1
1507 #define E60802_RG_SSUSB_PLL_NCPO_EN               (0x1<<31) //31:31
1508 #define E60802_RG_SSUSB_PLL_FIFO_START_MAN        (0x1<<30) //30:30
1509 #define E60802_RG_SSUSB_PLL_NCPO_CHG              (0x1<<28) //28:28
1510 #define E60802_RG_SSUSB_PLL_DDS_RSTB              (0x1<<27) //27:27
1511 #define E60802_RG_SSUSB_PLL_DDS_PWDB              (0x1<<26) //26:26
1512 #define E60802_RG_SSUSB_PLL_DDSEN                 (0x1<<25) //25:25
1513 #define E60802_RG_SSUSB_PLL_AUTOK_VCO             (0x1<<24) //24:24
1514 #define E60802_RG_SSUSB_PLL_PWD                   (0x1<<23) //23:23
1515 #define E60802_RG_SSUSB_RX_AFE_PWD                (0x1<<22) //22:22
1516 #define E60802_RG_SSUSB_PLL_TCADJ                 (0x3f<<16) //21:16
1517 #define E60802_RG_SSUSB_FORCE_CDR_TCADJ           (0x1<<15) //15:15
1518 #define E60802_RG_SSUSB_FORCE_CDR_AUTOK_VCO       (0x1<<14) //14:14
1519 #define E60802_RG_SSUSB_FORCE_CDR_PWD             (0x1<<13) //13:13
1520 #define E60802_RG_SSUSB_FORCE_PLL_NCPO_EN         (0x1<<12) //12:12
1521 #define E60802_RG_SSUSB_FORCE_PLL_FIFO_START_MAN  (0x1<<11) //11:11
1522 #define E60802_RG_SSUSB_FORCE_PLL_NCPO_CHG        (0x1<<9) //9:9
1523 #define E60802_RG_SSUSB_FORCE_PLL_DDS_RSTB        (0x1<<8) //8:8
1524 #define E60802_RG_SSUSB_FORCE_PLL_DDS_PWDB        (0x1<<7) //7:7
1525 #define E60802_RG_SSUSB_FORCE_PLL_DDSEN           (0x1<<6) //6:6
1526 #define E60802_RG_SSUSB_FORCE_PLL_TCADJ           (0x1<<5) //5:5
1527 #define E60802_RG_SSUSB_FORCE_PLL_AUTOK_VCO       (0x1<<4) //4:4
1528 #define E60802_RG_SSUSB_FORCE_PLL_PWD             (0x1<<3) //3:3
1529 #define E60802_RG_SSUSB_FLT_1_DISPERR_B           (0x1<<2) //2:2
1530
1531 //U3D_PHYD_TXPLL2
1532 #define E60802_RG_SSUSB_TX_LFPS_EN                (0x1<<31) //31:31
1533 #define E60802_RG_SSUSB_FORCE_TX_LFPS_EN          (0x1<<30) //30:30
1534 #define E60802_RG_SSUSB_TX_LFPS                   (0x1<<29) //29:29
1535 #define E60802_RG_SSUSB_FORCE_TX_LFPS             (0x1<<28) //28:28
1536 #define E60802_RG_SSUSB_RXPLL_STB                 (0x1<<27) //27:27
1537 #define E60802_RG_SSUSB_TXPLL_STB                 (0x1<<26) //26:26
1538 #define E60802_RG_SSUSB_FORCE_RXPLL_STB           (0x1<<25) //25:25
1539 #define E60802_RG_SSUSB_FORCE_TXPLL_STB           (0x1<<24) //24:24
1540 #define E60802_RG_SSUSB_RXPLL_REFCKSEL            (0x1<<16) //16:16
1541 #define E60802_RG_SSUSB_RXPLL_STBMODE             (0x1<<11) //11:11
1542 #define E60802_RG_SSUSB_RXPLL_ON                  (0x1<<10) //10:10
1543 #define E60802_RG_SSUSB_FORCE_RXPLLON             (0x1<<9) //9:9
1544 #define E60802_RG_SSUSB_FORCE_RX_AFE_PWD          (0x1<<8) //8:8
1545 #define E60802_RG_SSUSB_CDR_AUTOK_VCO             (0x1<<7) //7:7
1546 #define E60802_RG_SSUSB_CDR_PWD                   (0x1<<6) //6:6
1547 #define E60802_RG_SSUSB_CDR_TCADJ                 (0x3f<<0) //5:0
1548
1549 //U3D_PHYD_FL0
1550 #define E60802_RG_SSUSB_RX_FL_TARGET              (0xffff<<16) //31:16
1551 #define E60802_RG_SSUSB_RX_FL_CYCLECNT            (0xffff<<0) //15:0
1552
1553 //U3D_PHYD_MIX2
1554 #define E60802_RG_SSUSB_RX_EQ_RST                 (0x1<<31) //31:31
1555 #define E60802_RG_SSUSB_RX_EQ_RST_SEL             (0x1<<30) //30:30
1556 #define E60802_RG_SSUSB_RXVAL_RST                 (0x1<<29) //29:29
1557 #define E60802_RG_SSUSB_RXVAL_CNT                 (0x1f<<24) //28:24
1558 #define E60802_RG_SSUSB_CDROS_EN                  (0x1<<18) //18:18
1559 #define E60802_RG_SSUSB_CDR_LCKOP                 (0x3<<16) //17:16
1560 #define E60802_RG_SSUSB_RX_FL_LOCKTH              (0xf<<8) //11:8
1561 #define E60802_RG_SSUSB_RX_FL_OFFSET              (0xff<<0) //7:0
1562
1563 //U3D_PHYD_RX0
1564 #define E60802_RG_SSUSB_T2RLB_BERTH               (0xff<<24) //31:24
1565 #define E60802_RG_SSUSB_T2RLB_PAT                 (0xff<<16) //23:16
1566 #define E60802_RG_SSUSB_T2RLB_EN                  (0x1<<15) //15:15
1567 #define E60802_RG_SSUSB_T2RLB_BPSCRAMB            (0x1<<14) //14:14
1568 #define E60802_RG_SSUSB_T2RLB_SERIAL              (0x1<<13) //13:13
1569 #define E60802_RG_SSUSB_T2RLB_MODE                (0x3<<11) //12:11
1570 #define E60802_RG_SSUSB_RX_SAOSC_EN               (0x1<<10) //10:10
1571 #define E60802_RG_SSUSB_RX_SAOSC_EN_SEL           (0x1<<9) //9:9
1572 #define E60802_RG_SSUSB_RX_DFE_OPTION             (0x1<<8) //8:8
1573 #define E60802_RG_SSUSB_RX_DFE_EN                 (0x1<<7) //7:7
1574 #define E60802_RG_SSUSB_RX_DFE_EN_SEL             (0x1<<6) //6:6
1575 #define E60802_RG_SSUSB_RX_EQ_EN                  (0x1<<5) //5:5
1576 #define E60802_RG_SSUSB_RX_EQ_EN_SEL              (0x1<<4) //4:4
1577 #define E60802_RG_SSUSB_RX_SAOSC_RST              (0x1<<3) //3:3
1578 #define E60802_RG_SSUSB_RX_SAOSC_RST_SEL          (0x1<<2) //2:2
1579 #define E60802_RG_SSUSB_RX_DFE_RST                (0x1<<1) //1:1
1580 #define E60802_RG_SSUSB_RX_DFE_RST_SEL            (0x1<<0) //0:0
1581
1582 //U3D_PHYD_T2RLB
1583 #define E60802_RG_SSUSB_EQTRAIN_CH_MODE           (0x1<<28) //28:28
1584 #define E60802_RG_SSUSB_PRB_OUT_CPPAT             (0x1<<27) //27:27
1585 #define E60802_RG_SSUSB_BPANSIENC                 (0x1<<26) //26:26
1586 #define E60802_RG_SSUSB_VALID_EN                  (0x1<<25) //25:25
1587 #define E60802_RG_SSUSB_EBUF_SRST                 (0x1<<24) //24:24
1588 #define E60802_RG_SSUSB_K_EMP                     (0xf<<20) //23:20
1589 #define E60802_RG_SSUSB_K_FUL                     (0xf<<16) //19:16
1590 #define E60802_RG_SSUSB_T2RLB_BDATRST             (0xf<<12) //15:12
1591 #define E60802_RG_SSUSB_P_T2RLB_SKP_EN            (0x1<<10) //10:10
1592 #define E60802_RG_SSUSB_T2RLB_PATMODE             (0x3<<8) //9:8
1593 #define E60802_RG_SSUSB_T2RLB_TSEQCNT             (0xff<<0) //7:0
1594
1595 //U3D_PHYD_CPPAT
1596 #define E60802_RG_SSUSB_CPPAT_PROGRAM_EN          (0x1<<24) //24:24
1597 #define E60802_RG_SSUSB_CPPAT_TOZ                 (0x3<<21) //22:21
1598 #define E60802_RG_SSUSB_CPPAT_PRBS_EN             (0x1<<20) //20:20
1599 #define E60802_RG_SSUSB_CPPAT_OUT_TMP2            (0xf<<16) //19:16
1600 #define E60802_RG_SSUSB_CPPAT_OUT_TMP1            (0xff<<8) //15:8
1601 #define E60802_RG_SSUSB_CPPAT_OUT_TMP0            (0xff<<0) //7:0
1602
1603 //U3D_PHYD_MIX3
1604 #define E60802_RG_SSUSB_CDR_TCADJ_MINUS           (0x1<<31) //31:31
1605 #define E60802_RG_SSUSB_P_CDROS_EN                (0x1<<30) //30:30
1606 #define E60802_RG_SSUSB_P_P2_TX_DRV_DIS           (0x1<<28) //28:28
1607 #define E60802_RG_SSUSB_CDR_TCADJ_OFFSET          (0x7<<24) //26:24
1608 #define E60802_RG_SSUSB_PLL_TCADJ_MINUS           (0x1<<23) //23:23
1609 #define E60802_RG_SSUSB_FORCE_PLL_BIAS_LPF_EN     (0x1<<20) //20:20
1610 #define E60802_RG_SSUSB_PLL_BIAS_LPF_EN           (0x1<<19) //19:19
1611 #define E60802_RG_SSUSB_PLL_TCADJ_OFFSET          (0x7<<16) //18:16
1612 #define E60802_RG_SSUSB_FORCE_PLL_SSCEN           (0x1<<15) //15:15
1613 #define E60802_RG_SSUSB_PLL_SSCEN                 (0x1<<14) //14:14
1614 #define E60802_RG_SSUSB_FORCE_CDR_PI_PWD          (0x1<<13) //13:13
1615 #define E60802_RG_SSUSB_CDR_PI_PWD                (0x1<<12) //12:12
1616 #define E60802_RG_SSUSB_CDR_PI_MODE               (0x1<<11) //11:11
1617 #define E60802_RG_SSUSB_TXPLL_SSCEN_CYC           (0x3ff<<0) //9:0
1618
1619 //U3D_PHYD_EBUFCTL
1620 #define E60802_RG_SSUSB_EBUFCTL                   (0xffffffff<<0) //31:0
1621
1622 //U3D_PHYD_PIPE0
1623 #define E60802_RG_SSUSB_RXTERMINATION             (0x1<<30) //30:30
1624 #define E60802_RG_SSUSB_RXEQTRAINING              (0x1<<29) //29:29
1625 #define E60802_RG_SSUSB_RXPOLARITY                (0x1<<28) //28:28
1626 #define E60802_RG_SSUSB_TXDEEMPH                  (0x3<<26) //27:26
1627 #define E60802_RG_SSUSB_POWERDOWN                 (0x3<<24) //25:24
1628 #define E60802_RG_SSUSB_TXONESZEROS               (0x1<<23) //23:23
1629 #define E60802_RG_SSUSB_TXELECIDLE                (0x1<<22) //22:22
1630 #define E60802_RG_SSUSB_TXDETECTRX                (0x1<<21) //21:21
1631 #define E60802_RG_SSUSB_PIPE_SEL                  (0x1<<20) //20:20
1632 #define E60802_RG_SSUSB_TXDATAK                   (0xf<<16) //19:16
1633 #define E60802_RG_SSUSB_CDR_STABLE_SEL            (0x1<<15) //15:15
1634 #define E60802_RG_SSUSB_CDR_STABLE                (0x1<<14) //14:14
1635 #define E60802_RG_SSUSB_CDR_RSTB_SEL              (0x1<<13) //13:13
1636 #define E60802_RG_SSUSB_CDR_RSTB                  (0x1<<12) //12:12
1637 #define E60802_RG_SSUSB_FRC_PIPE_POWERDOWN        (0x1<<11) //11:11
1638 #define E60802_RG_SSUSB_P_TXBCN_DIS               (0x1<<6) //6:6
1639 #define E60802_RG_SSUSB_P_ERROR_SEL               (0x3<<4) //5:4
1640 #define E60802_RG_SSUSB_TXMARGIN                  (0x7<<1) //3:1
1641 #define E60802_RG_SSUSB_TXCOMPLIANCE              (0x1<<0) //0:0
1642
1643 //U3D_PHYD_PIPE1
1644 #define E60802_RG_SSUSB_TXDATA                    (0xffffffff<<0) //31:0
1645
1646 //U3D_PHYD_MIX4
1647 #define E60802_RG_SSUSB_CDROS_CNT                 (0x3f<<24) //29:24
1648 #define E60802_RG_SSUSB_T2RLB_BER_EN              (0x1<<16) //16:16
1649 #define E60802_RG_SSUSB_T2RLB_BER_RATE            (0xffff<<0) //15:0
1650
1651 //U3D_PHYD_CKGEN0
1652 #define E60802_RG_SSUSB_RFIFO_IMPLAT              (0x1<<27) //27:27
1653 #define E60802_RG_SSUSB_TFIFO_PSEL                (0x7<<24) //26:24
1654 #define E60802_RG_SSUSB_CKGEN_PSEL                (0x3<<8) //9:8
1655 #define E60802_RG_SSUSB_RXCK_INV                  (0x1<<0) //0:0
1656
1657 //U3D_PHYD_MIX5
1658 #define E60802_RG_SSUSB_PRB_SEL                   (0xffff<<16) //31:16
1659 #define E60802_RG_SSUSB_RXPLL_STBCYC              (0x7ff<<0) //10:0
1660
1661 //U3D_PHYD_RESERVED
1662 #define E60802_RG_SSUSB_PHYD_RESERVE              (0xffffffff<<0) //31:0
1663
1664 //U3D_PHYD_CDR0
1665 #define E60802_RG_SSUSB_CDR_BIC_LTR               (0xf<<28) //31:28
1666 #define E60802_RG_SSUSB_CDR_BIC_LTD0              (0xf<<24) //27:24
1667 #define E60802_RG_SSUSB_CDR_BC_LTD1               (0x1f<<16) //20:16
1668 #define E60802_RG_SSUSB_CDR_BC_LTR                (0x1f<<8) //12:8
1669 #define E60802_RG_SSUSB_CDR_BC_LTD0               (0x1f<<0) //4:0
1670
1671 //U3D_PHYD_CDR1
1672 #define E60802_RG_SSUSB_CDR_BIR_LTD1              (0x1f<<24) //28:24
1673 #define E60802_RG_SSUSB_CDR_BIR_LTR               (0x1f<<16) //20:16
1674 #define E60802_RG_SSUSB_CDR_BIR_LTD0              (0x1f<<8) //12:8
1675 #define E60802_RG_SSUSB_CDR_BW_SEL                (0x3<<6) //7:6
1676 #define E60802_RG_SSUSB_CDR_BIC_LTD1              (0xf<<0) //3:0
1677
1678 //U3D_PHYD_PLL_0
1679 #define E60802_RG_SSUSB_FORCE_CDR_BAND_5G         (0x1<<28) //28:28
1680 #define E60802_RG_SSUSB_FORCE_CDR_BAND_2P5G       (0x1<<27) //27:27
1681 #define E60802_RG_SSUSB_FORCE_PLL_BAND_5G         (0x1<<26) //26:26
1682 #define E60802_RG_SSUSB_FORCE_PLL_BAND_2P5G       (0x1<<25) //25:25
1683 #define E60802_RG_SSUSB_P_EQ_T_SEL                (0x3ff<<15) //24:15
1684 #define E60802_RG_SSUSB_PLL_ISO_EN_CYC            (0x3ff<<5) //14:5
1685 #define E60802_RG_SSUSB_PLLBAND_RECAL             (0x1<<4) //4:4
1686 #define E60802_RG_SSUSB_PLL_DDS_ISO_EN            (0x1<<3) //3:3
1687 #define E60802_RG_SSUSB_FORCE_PLL_DDS_ISO_EN      (0x1<<2) //2:2
1688 #define E60802_RG_SSUSB_PLL_DDS_PWR_ON            (0x1<<1) //1:1
1689 #define E60802_RG_SSUSB_FORCE_PLL_DDS_PWR_ON      (0x1<<0) //0:0
1690
1691 //U3D_PHYD_PLL_1
1692 #define E60802_RG_SSUSB_CDR_BAND_5G               (0xff<<24) //31:24
1693 #define E60802_RG_SSUSB_CDR_BAND_2P5G             (0xff<<16) //23:16
1694 #define E60802_RG_SSUSB_PLL_BAND_5G               (0xff<<8) //15:8
1695 #define E60802_RG_SSUSB_PLL_BAND_2P5G             (0xff<<0) //7:0
1696
1697 //U3D_PHYD_BCN_DET_1
1698 #define E60802_RG_SSUSB_P_BCN_OBS_PRD             (0xffff<<16) //31:16
1699 #define E60802_RG_SSUSB_U_BCN_OBS_PRD             (0xffff<<0) //15:0
1700
1701 //U3D_PHYD_BCN_DET_2
1702 #define E60802_RG_SSUSB_P_BCN_OBS_SEL             (0xfff<<16) //27:16
1703 #define E60802_RG_SSUSB_BCN_DET_DIS               (0x1<<12) //12:12
1704 #define E60802_RG_SSUSB_U_BCN_OBS_SEL             (0xfff<<0) //11:0
1705
1706 //U3D_EQ0
1707 #define E60802_RG_SSUSB_EQ_DLHL_LFI               (0x7f<<24) //30:24
1708 #define E60802_RG_SSUSB_EQ_DHHL_LFI               (0x7f<<16) //22:16
1709 #define E60802_RG_SSUSB_EQ_DD0HOS_LFI             (0x7f<<8) //14:8
1710 #define E60802_RG_SSUSB_EQ_DD0LOS_LFI             (0x7f<<0) //6:0
1711
1712 //U3D_EQ1
1713 #define E60802_RG_SSUSB_EQ_DD1HOS_LFI             (0x7f<<24) //30:24
1714 #define E60802_RG_SSUSB_EQ_DD1LOS_LFI             (0x7f<<16) //22:16
1715 #define E60802_RG_SSUSB_EQ_DE0OS_LFI              (0x7f<<8) //14:8
1716 #define E60802_RG_SSUSB_EQ_DE1OS_LFI              (0x7f<<0) //6:0
1717
1718 //U3D_EQ2
1719 #define E60802_RG_SSUSB_EQ_DLHLOS_LFI             (0x7f<<24) //30:24
1720 #define E60802_RG_SSUSB_EQ_DHHLOS_LFI             (0x7f<<16) //22:16
1721 #define E60802_RG_SSUSB_EQ_STOPTIME               (0x1<<14) //14:14
1722 #define E60802_RG_SSUSB_EQ_DHHL_LF_SEL            (0x7<<11) //13:11
1723 #define E60802_RG_SSUSB_EQ_DSAOS_LF_SEL           (0x7<<8) //10:8
1724 #define E60802_RG_SSUSB_EQ_STARTTIME              (0x3<<6) //7:6
1725 #define E60802_RG_SSUSB_EQ_DLEQ_LF_SEL            (0x7<<3) //5:3
1726 #define E60802_RG_SSUSB_EQ_DLHL_LF_SEL            (0x7<<0) //2:0
1727
1728 //U3D_EQ3
1729 #define E60802_RG_SSUSB_EQ_DLEQ_LFI_GEN2          (0xf<<28) //31:28
1730 #define E60802_RG_SSUSB_EQ_DLEQ_LFI_GEN1          (0xf<<24) //27:24
1731 #define E60802_RG_SSUSB_EQ_DEYE0OS_LFI            (0x7f<<16) //22:16
1732 #define E60802_RG_SSUSB_EQ_DEYE1OS_LFI            (0x7f<<8) //14:8
1733 #define E60802_RG_SSUSB_EQ_TRI_DET_EN             (0x1<<7) //7:7
1734 #define E60802_RG_SSUSB_EQ_TRI_DET_TH             (0x7f<<0) //6:0
1735
1736 //U3D_EQ_EYE0
1737 #define E60802_RG_SSUSB_EQ_EYE_XOFFSET            (0x7f<<25) //31:25
1738 #define E60802_RG_SSUSB_EQ_EYE_MON_EN             (0x1<<24) //24:24
1739 #define E60802_RG_SSUSB_EQ_EYE0_Y                 (0x7f<<16) //22:16
1740 #define E60802_RG_SSUSB_EQ_EYE1_Y                 (0x7f<<8) //14:8
1741 #define E60802_RG_SSUSB_EQ_PILPO_ROUT             (0x1<<7) //7:7
1742 #define E60802_RG_SSUSB_EQ_PI_KPGAIN              (0x7<<4) //6:4
1743 #define E60802_RG_SSUSB_EQ_EYE_CNT_EN             (0x1<<3) //3:3
1744
1745 //U3D_EQ_EYE1
1746 #define E60802_RG_SSUSB_EQ_SIGDET                 (0x7f<<24) //30:24
1747 #define E60802_RG_SSUSB_EQ_EYE_MASK               (0x3ff<<7) //16:7
1748
1749 //U3D_EQ_EYE2
1750 #define E60802_RG_SSUSB_EQ_RX500M_CK_SEL          (0x1<<31) //31:31
1751 #define E60802_RG_SSUSB_EQ_SD_CNT1                (0x3f<<24) //29:24
1752 #define E60802_RG_SSUSB_EQ_ISIFLAG_SEL            (0x3<<22) //23:22
1753 #define E60802_RG_SSUSB_EQ_SD_CNT0                (0x3f<<16) //21:16
1754
1755 //U3D_EQ_DFE0
1756 #define E60802_RG_SSUSB_EQ_LEQMAX                 (0xf<<28) //31:28
1757 #define E60802_RG_SSUSB_EQ_DFEX_EN                (0x1<<27) //27:27
1758 #define E60802_RG_SSUSB_EQ_DFEX_LF_SEL            (0x7<<24) //26:24
1759 #define E60802_RG_SSUSB_EQ_CHK_EYE_H              (0x1<<23) //23:23
1760 #define E60802_RG_SSUSB_EQ_PIEYE_INI              (0x7f<<16) //22:16
1761 #define E60802_RG_SSUSB_EQ_PI90_INI               (0x7f<<8) //14:8
1762 #define E60802_RG_SSUSB_EQ_PI0_INI                (0x7f<<0) //6:0
1763
1764 //U3D_EQ_DFE1
1765 #define E60802_RG_SSUSB_EQ_REV                    (0xffff<<16) //31:16
1766 #define E60802_RG_SSUSB_EQ_DFEYEN_DUR             (0x7<<12) //14:12
1767 #define E60802_RG_SSUSB_EQ_DFEXEN_DUR             (0x7<<8) //10:8
1768 #define E60802_RG_SSUSB_EQ_DFEX_RST               (0x1<<7) //7:7
1769 #define E60802_RG_SSUSB_EQ_GATED_RXD_B            (0x1<<6) //6:6
1770 #define E60802_RG_SSUSB_EQ_PI90CK_SEL             (0x3<<4) //5:4
1771 #define E60802_RG_SSUSB_EQ_DFEX_DIS               (0x1<<2) //2:2
1772 #define E60802_RG_SSUSB_EQ_DFEYEN_STOP_DIS        (0x1<<1) //1:1
1773 #define E60802_RG_SSUSB_EQ_DFEXEN_SEL             (0x1<<0) //0:0
1774
1775 //U3D_EQ_DFE2
1776 #define E60802_RG_SSUSB_EQ_MON_SEL                (0x1f<<24) //28:24
1777 #define E60802_RG_SSUSB_EQ_LEQOSC_DLYCNT          (0x7<<16) //18:16
1778 #define E60802_RG_SSUSB_EQ_DLEQOS_LFI             (0x1f<<8) //12:8
1779 #define E60802_RG_SSUSB_EQ_DFE_TOG                (0x1<<2) //2:2
1780 #define E60802_RG_SSUSB_EQ_LEQ_STOP_TO            (0x3<<0) //1:0
1781
1782 //U3D_EQ_DFE3
1783 #define E60802_RG_SSUSB_EQ_RESERVED               (0xffffffff<<0) //31:0
1784
1785 //U3D_PHYD_MON0
1786 #define E60802_RGS_SSUSB_BERT_BERC                (0xffff<<16) //31:16
1787 #define E60802_RGS_SSUSB_LFPS                     (0xf<<12) //15:12
1788 #define E60802_RGS_SSUSB_TRAINDEC                 (0x7<<8) //10:8
1789 #define E60802_RGS_SSUSB_SCP_PAT                  (0xff<<0) //7:0
1790
1791 //U3D_PHYD_MON1
1792 #define E60802_RGS_SSUSB_RX_FL_OUT                (0xffff<<0) //15:0
1793
1794 //U3D_PHYD_MON2
1795 #define E60802_RGS_SSUSB_T2RLB_ERRCNT             (0xffff<<16) //31:16
1796 #define E60802_RGS_SSUSB_RETRACK                  (0xf<<12) //15:12
1797 #define E60802_RGS_SSUSB_RXPLL_LOCK               (0x1<<10) //10:10
1798 #define E60802_RGS_SSUSB_CDR_VCOCAL_CPLT_D        (0x1<<9) //9:9
1799 #define E60802_RGS_SSUSB_PLL_VCOCAL_CPLT_D        (0x1<<8) //8:8
1800 #define E60802_RGS_SSUSB_PDNCTL                   (0xff<<0) //7:0
1801
1802 //U3D_PHYD_MON3
1803 #define E60802_RGS_SSUSB_TSEQ_ERRCNT              (0xffff<<16) //31:16
1804 #define E60802_RGS_SSUSB_PRBS_ERRCNT              (0xffff<<0) //15:0
1805
1806 //U3D_PHYD_MON4
1807 #define E60802_RGS_SSUSB_RX_LSLOCK_CNT            (0xf<<24) //27:24
1808 #define E60802_RGS_SSUSB_SCP_DETCNT               (0xff<<16) //23:16
1809 #define E60802_RGS_SSUSB_TSEQ_DETCNT              (0xffff<<0) //15:0
1810
1811 //U3D_PHYD_MON5
1812 #define E60802_RGS_SSUSB_EBUFMSG                  (0xffff<<16) //31:16
1813 #define E60802_RGS_SSUSB_BERT_LOCK                (0x1<<15) //15:15
1814 #define E60802_RGS_SSUSB_SCP_DET                  (0x1<<14) //14:14
1815 #define E60802_RGS_SSUSB_TSEQ_DET                 (0x1<<13) //13:13
1816 #define E60802_RGS_SSUSB_EBUF_UDF                 (0x1<<12) //12:12
1817 #define E60802_RGS_SSUSB_EBUF_OVF                 (0x1<<11) //11:11
1818 #define E60802_RGS_SSUSB_PRBS_PASSTH              (0x1<<10) //10:10
1819 #define E60802_RGS_SSUSB_PRBS_PASS                (0x1<<9) //9:9
1820 #define E60802_RGS_SSUSB_PRBS_LOCK                (0x1<<8) //8:8
1821 #define E60802_RGS_SSUSB_T2RLB_ERR                (0x1<<6) //6:6
1822 #define E60802_RGS_SSUSB_T2RLB_PASSTH             (0x1<<5) //5:5
1823 #define E60802_RGS_SSUSB_T2RLB_PASS               (0x1<<4) //4:4
1824 #define E60802_RGS_SSUSB_T2RLB_LOCK               (0x1<<3) //3:3
1825 #define E60802_RGS_SSUSB_RX_IMPCAL_DONE           (0x1<<2) //2:2
1826 #define E60802_RGS_SSUSB_TX_IMPCAL_DONE           (0x1<<1) //1:1
1827 #define E60802_RGS_SSUSB_RXDETECTED               (0x1<<0) //0:0
1828
1829 //U3D_PHYD_MON6
1830 #define E60802_RGS_SSUSB_SIGCAL_DONE              (0x1<<30) //30:30
1831 #define E60802_RGS_SSUSB_SIGCAL_CAL_OUT           (0x1<<29) //29:29
1832 #define E60802_RGS_SSUSB_SIGCAL_OFFSET            (0x1f<<24) //28:24
1833 #define E60802_RGS_SSUSB_RX_IMP_SEL               (0x1f<<16) //20:16
1834 #define E60802_RGS_SSUSB_TX_IMP_SEL               (0x1f<<8) //12:8
1835 #define E60802_RGS_SSUSB_TFIFO_MSG                (0xf<<4) //7:4
1836 #define E60802_RGS_SSUSB_RFIFO_MSG                (0xf<<0) //3:0
1837
1838 //U3D_PHYD_MON7
1839 #define E60802_RGS_SSUSB_FT_OUT                   (0xff<<8) //15:8
1840 #define E60802_RGS_SSUSB_PRB_OUT                  (0xff<<0) //7:0
1841
1842 //U3D_PHYA_RX_MON0
1843 #define E60802_RGS_SSUSB_EQ_DCLEQ                 (0xf<<24) //27:24
1844 #define E60802_RGS_SSUSB_EQ_DCD0H                 (0x7f<<16) //22:16
1845 #define E60802_RGS_SSUSB_EQ_DCD0L                 (0x7f<<8) //14:8
1846 #define E60802_RGS_SSUSB_EQ_DCD1H                 (0x7f<<0) //6:0
1847
1848 //U3D_PHYA_RX_MON1
1849 #define E60802_RGS_SSUSB_EQ_DCD1L                 (0x7f<<24) //30:24
1850 #define E60802_RGS_SSUSB_EQ_DCE0                  (0x7f<<16) //22:16
1851 #define E60802_RGS_SSUSB_EQ_DCE1                  (0x7f<<8) //14:8
1852 #define E60802_RGS_SSUSB_EQ_DCHHL                 (0x7f<<0) //6:0
1853
1854 //U3D_PHYA_RX_MON2
1855 #define E60802_RGS_SSUSB_EQ_LEQ_STOP              (0x1<<31) //31:31
1856 #define E60802_RGS_SSUSB_EQ_DCLHL                 (0x7f<<24) //30:24
1857 #define E60802_RGS_SSUSB_EQ_STATUS                (0xff<<16) //23:16
1858 #define E60802_RGS_SSUSB_EQ_DCEYE0                (0x7f<<8) //14:8
1859 #define E60802_RGS_SSUSB_EQ_DCEYE1                (0x7f<<0) //6:0
1860
1861 //U3D_PHYA_RX_MON3
1862 #define E60802_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0  (0xfffff<<0) //19:0
1863
1864 //U3D_PHYA_RX_MON4
1865 #define E60802_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1  (0xfffff<<0) //19:0
1866
1867 //U3D_PHYA_RX_MON5
1868 #define E60802_RGS_SSUSB_EQ_DCLEQOS               (0x1f<<8) //12:8
1869 #define E60802_RGS_SSUSB_EQ_EYE_CNT_RDY           (0x1<<7) //7:7
1870 #define E60802_RGS_SSUSB_EQ_PILPO                 (0x7f<<0) //6:0
1871
1872 //U3D_PHYD_CPPAT2
1873 #define E60802_RG_SSUSB_CPPAT_OUT_H_TMP2          (0xf<<16) //19:16
1874 #define E60802_RG_SSUSB_CPPAT_OUT_H_TMP1          (0xff<<8) //15:8
1875 #define E60802_RG_SSUSB_CPPAT_OUT_H_TMP0          (0xff<<0) //7:0
1876
1877 //U3D_EQ_EYE3
1878 #define E60802_RG_SSUSB_EQ_LEQ_SHIFT              (0x7<<24) //26:24
1879 #define E60802_RG_SSUSB_EQ_EYE_CNT                (0xfffff<<0) //19:0
1880
1881 //U3D_KBAND_OUT
1882 #define E60802_RGS_SSUSB_CDR_BAND_5G              (0xff<<24) //31:24
1883 #define E60802_RGS_SSUSB_CDR_BAND_2P5G            (0xff<<16) //23:16
1884 #define E60802_RGS_SSUSB_PLL_BAND_5G              (0xff<<8) //15:8
1885 #define E60802_RGS_SSUSB_PLL_BAND_2P5G            (0xff<<0) //7:0
1886
1887 //U3D_KBAND_OUT1
1888 #define E60802_RGS_SSUSB_CDR_VCOCAL_FAIL          (0x1<<24) //24:24
1889 #define E60802_RGS_SSUSB_CDR_VCOCAL_STATE         (0xff<<16) //23:16
1890 #define E60802_RGS_SSUSB_PLL_VCOCAL_FAIL          (0x1<<8) //8:8
1891 #define E60802_RGS_SSUSB_PLL_VCOCAL_STATE         (0xff<<0) //7:0
1892
1893 /* OFFSET */
1894
1895 //U3D_PHYD_MIX0
1896 #define E60802_RG_SSUSB_P_P3_TX_NG_OFST           (31)
1897 #define E60802_RG_SSUSB_TSEQ_EN_OFST              (30)
1898 #define E60802_RG_SSUSB_TSEQ_POLEN_OFST           (29)
1899 #define E60802_RG_SSUSB_TSEQ_POL_OFST             (28)
1900 #define E60802_RG_SSUSB_P_P3_PCLK_NG_OFST         (27)
1901 #define E60802_RG_SSUSB_TSEQ_TH_OFST              (24)
1902 #define E60802_RG_SSUSB_PRBS_BERTH_OFST           (16)
1903 #define E60802_RG_SSUSB_DISABLE_PHY_U2_ON_OFST    (15)
1904 #define E60802_RG_SSUSB_DISABLE_PHY_U2_OFF_OFST   (14)
1905 #define E60802_RG_SSUSB_PRBS_EN_OFST              (13)
1906 #define E60802_RG_SSUSB_BPSLOCK_OFST              (12)
1907 #define E60802_RG_SSUSB_RTCOMCNT_OFST             (8)
1908 #define E60802_RG_SSUSB_COMCNT_OFST               (4)
1909 #define E60802_RG_SSUSB_PRBSEL_CALIB_OFST         (0)
1910
1911 //U3D_PHYD_MIX1
1912 #define E60802_RG_SSUSB_SLEEP_EN_OFST             (31)
1913 #define E60802_RG_SSUSB_PRBSEL_PCS_OFST           (28)
1914 #define E60802_RG_SSUSB_TXLFPS_PRD_OFST           (24)
1915 #define E60802_RG_SSUSB_P_RX_P0S_CK_OFST          (23)
1916 #define E60802_RG_SSUSB_P_TX_P0S_CK_OFST          (22)
1917 #define E60802_RG_SSUSB_PDNCTL_OFST               (16)
1918 #define E60802_RG_SSUSB_TX_DRV_EN_OFST            (15)
1919 #define E60802_RG_SSUSB_TX_DRV_SEL_OFST           (14)
1920 #define E60802_RG_SSUSB_TX_DRV_DLY_OFST           (8)
1921 #define E60802_RG_SSUSB_BERT_EN_OFST              (7)
1922 #define E60802_RG_SSUSB_SCP_TH_OFST               (4)
1923 #define E60802_RG_SSUSB_SCP_EN_OFST               (3)
1924 #define E60802_RG_SSUSB_RXANSIDEC_TEST_OFST       (0)
1925
1926 //U3D_PHYD_LFPS0
1927 #define E60802_RG_SSUSB_LFPS_PWD_OFST             (30)
1928 #define E60802_RG_SSUSB_FORCE_LFPS_PWD_OFST       (29)
1929 #define E60802_RG_SSUSB_RXLFPS_OVF_OFST           (24)
1930 #define E60802_RG_SSUSB_P3_ENTRY_SEL_OFST         (23)
1931 #define E60802_RG_SSUSB_P3_ENTRY_OFST             (22)
1932 #define E60802_RG_SSUSB_RXLFPS_CDRSEL_OFST        (20)
1933 #define E60802_RG_SSUSB_RXLFPS_CDRTH_OFST         (16)
1934 #define E60802_RG_SSUSB_LOCK5G_BLOCK_OFST         (15)
1935 #define E60802_RG_SSUSB_TFIFO_EXT_D_SEL_OFST      (14)
1936 #define E60802_RG_SSUSB_TFIFO_NO_EXTEND_OFST      (13)
1937 #define E60802_RG_SSUSB_RXLFPS_LOB_OFST           (8)
1938 #define E60802_RG_SSUSB_TXLFPS_EN_OFST            (7)
1939 #define E60802_RG_SSUSB_TXLFPS_SEL_OFST           (6)
1940 #define E60802_RG_SSUSB_RXLFPS_CDRLOCK_OFST       (5)
1941 #define E60802_RG_SSUSB_RXLFPS_UPB_OFST           (0)
1942
1943 //U3D_PHYD_LFPS1
1944 #define E60802_RG_SSUSB_RX_IMP_BIAS_OFST          (28)
1945 #define E60802_RG_SSUSB_TX_IMP_BIAS_OFST          (24)
1946 #define E60802_RG_SSUSB_FWAKE_TH_OFST             (16)
1947 #define E60802_RG_SSUSB_P1_ENTRY_SEL_OFST         (14)
1948 #define E60802_RG_SSUSB_P1_ENTRY_OFST             (13)
1949 #define E60802_RG_SSUSB_RXLFPS_UDF_OFST           (8)
1950 #define E60802_RG_SSUSB_RXLFPS_P0IDLETH_OFST      (0)
1951
1952 //U3D_PHYD_IMPCAL0
1953 #define E60802_RG_SSUSB_FORCE_TX_IMPSEL_OFST      (31)
1954 #define E60802_RG_SSUSB_TX_IMPCAL_EN_OFST         (30)
1955 #define E60802_RG_SSUSB_FORCE_TX_IMPCAL_EN_OFST   (29)
1956 #define E60802_RG_SSUSB_TX_IMPSEL_OFST            (24)
1957 #define E60802_RG_SSUSB_TX_IMPCAL_CALCYC_OFST     (16)
1958 #define E60802_RG_SSUSB_TX_IMPCAL_STBCYC_OFST     (10)
1959 #define E60802_RG_SSUSB_TX_IMPCAL_CYCCNT_OFST     (0)
1960
1961 //U3D_PHYD_IMPCAL1
1962 #define E60802_RG_SSUSB_FORCE_RX_IMPSEL_OFST      (31)
1963 #define E60802_RG_SSUSB_RX_IMPCAL_EN_OFST         (30)
1964 #define E60802_RG_SSUSB_FORCE_RX_IMPCAL_EN_OFST   (29)
1965 #define E60802_RG_SSUSB_RX_IMPSEL_OFST            (24)
1966 #define E60802_RG_SSUSB_RX_IMPCAL_CALCYC_OFST     (16)
1967 #define E60802_RG_SSUSB_RX_IMPCAL_STBCYC_OFST     (10)
1968 #define E60802_RG_SSUSB_RX_IMPCAL_CYCCNT_OFST     (0)
1969
1970 //U3D_PHYD_TXPLL0
1971 #define E60802_RG_SSUSB_TXPLL_DDSEN_CYC_OFST      (27)
1972 #define E60802_RG_SSUSB_TXPLL_ON_OFST             (26)
1973 #define E60802_RG_SSUSB_FORCE_TXPLLON_OFST        (25)
1974 #define E60802_RG_SSUSB_TXPLL_STBCYC_OFST         (16)
1975 #define E60802_RG_SSUSB_TXPLL_NCPOCHG_CYC_OFST    (12)
1976 #define E60802_RG_SSUSB_TXPLL_NCPOEN_CYC_OFST     (10)
1977 #define E60802_RG_SSUSB_TXPLL_DDSRSTB_CYC_OFST    (0)
1978
1979 //U3D_PHYD_TXPLL1
1980 #define E60802_RG_SSUSB_PLL_NCPO_EN_OFST          (31)
1981 #define E60802_RG_SSUSB_PLL_FIFO_START_MAN_OFST   (30)
1982 #define E60802_RG_SSUSB_PLL_NCPO_CHG_OFST         (28)
1983 #define E60802_RG_SSUSB_PLL_DDS_RSTB_OFST         (27)
1984 #define E60802_RG_SSUSB_PLL_DDS_PWDB_OFST         (26)
1985 #define E60802_RG_SSUSB_PLL_DDSEN_OFST            (25)
1986 #define E60802_RG_SSUSB_PLL_AUTOK_VCO_OFST        (24)
1987 #define E60802_RG_SSUSB_PLL_PWD_OFST              (23)
1988 #define E60802_RG_SSUSB_RX_AFE_PWD_OFST           (22)
1989 #define E60802_RG_SSUSB_PLL_TCADJ_OFST            (16)
1990 #define E60802_RG_SSUSB_FORCE_CDR_TCADJ_OFST      (15)
1991 #define E60802_RG_SSUSB_FORCE_CDR_AUTOK_VCO_OFST  (14)
1992 #define E60802_RG_SSUSB_FORCE_CDR_PWD_OFST        (13)
1993 #define E60802_RG_SSUSB_FORCE_PLL_NCPO_EN_OFST    (12)
1994 #define E60802_RG_SSUSB_FORCE_PLL_FIFO_START_MAN_OFST (11)
1995 #define E60802_RG_SSUSB_FORCE_PLL_NCPO_CHG_OFST   (9)
1996 #define E60802_RG_SSUSB_FORCE_PLL_DDS_RSTB_OFST   (8)
1997 #define E60802_RG_SSUSB_FORCE_PLL_DDS_PWDB_OFST   (7)
1998 #define E60802_RG_SSUSB_FORCE_PLL_DDSEN_OFST      (6)
1999 #define E60802_RG_SSUSB_FORCE_PLL_TCADJ_OFST      (5)
2000 #define E60802_RG_SSUSB_FORCE_PLL_AUTOK_VCO_OFST  (4)
2001 #define E60802_RG_SSUSB_FORCE_PLL_PWD_OFST        (3)
2002 #define E60802_RG_SSUSB_FLT_1_DISPERR_B_OFST      (2)
2003
2004 //U3D_PHYD_TXPLL2
2005 #define E60802_RG_SSUSB_TX_LFPS_EN_OFST           (31)
2006 #define E60802_RG_SSUSB_FORCE_TX_LFPS_EN_OFST     (30)
2007 #define E60802_RG_SSUSB_TX_LFPS_OFST              (29)
2008 #define E60802_RG_SSUSB_FORCE_TX_LFPS_OFST        (28)
2009 #define E60802_RG_SSUSB_RXPLL_STB_OFST            (27)
2010 #define E60802_RG_SSUSB_TXPLL_STB_OFST            (26)
2011 #define E60802_RG_SSUSB_FORCE_RXPLL_STB_OFST      (25)
2012 #define E60802_RG_SSUSB_FORCE_TXPLL_STB_OFST      (24)
2013 #define E60802_RG_SSUSB_RXPLL_REFCKSEL_OFST       (16)
2014 #define E60802_RG_SSUSB_RXPLL_STBMODE_OFST        (11)
2015 #define E60802_RG_SSUSB_RXPLL_ON_OFST             (10)
2016 #define E60802_RG_SSUSB_FORCE_RXPLLON_OFST        (9)
2017 #define E60802_RG_SSUSB_FORCE_RX_AFE_PWD_OFST     (8)
2018 #define E60802_RG_SSUSB_CDR_AUTOK_VCO_OFST        (7)
2019 #define E60802_RG_SSUSB_CDR_PWD_OFST              (6)
2020 #define E60802_RG_SSUSB_CDR_TCADJ_OFST            (0)
2021
2022 //U3D_PHYD_FL0
2023 #define E60802_RG_SSUSB_RX_FL_TARGET_OFST         (16)
2024 #define E60802_RG_SSUSB_RX_FL_CYCLECNT_OFST       (0)
2025
2026 //U3D_PHYD_MIX2
2027 #define E60802_RG_SSUSB_RX_EQ_RST_OFST            (31)
2028 #define E60802_RG_SSUSB_RX_EQ_RST_SEL_OFST        (30)
2029 #define E60802_RG_SSUSB_RXVAL_RST_OFST            (29)
2030 #define E60802_RG_SSUSB_RXVAL_CNT_OFST            (24)
2031 #define E60802_RG_SSUSB_CDROS_EN_OFST             (18)
2032 #define E60802_RG_SSUSB_CDR_LCKOP_OFST            (16)
2033 #define E60802_RG_SSUSB_RX_FL_LOCKTH_OFST         (8)
2034 #define E60802_RG_SSUSB_RX_FL_OFFSET_OFST         (0)
2035
2036 //U3D_PHYD_RX0
2037 #define E60802_RG_SSUSB_T2RLB_BERTH_OFST          (24)
2038 #define E60802_RG_SSUSB_T2RLB_PAT_OFST            (16)
2039 #define E60802_RG_SSUSB_T2RLB_EN_OFST             (15)
2040 #define E60802_RG_SSUSB_T2RLB_BPSCRAMB_OFST       (14)
2041 #define E60802_RG_SSUSB_T2RLB_SERIAL_OFST         (13)
2042 #define E60802_RG_SSUSB_T2RLB_MODE_OFST           (11)
2043 #define E60802_RG_SSUSB_RX_SAOSC_EN_OFST          (10)
2044 #define E60802_RG_SSUSB_RX_SAOSC_EN_SEL_OFST      (9)
2045 #define E60802_RG_SSUSB_RX_DFE_OPTION_OFST        (8)
2046 #define E60802_RG_SSUSB_RX_DFE_EN_OFST            (7)
2047 #define E60802_RG_SSUSB_RX_DFE_EN_SEL_OFST        (6)
2048 #define E60802_RG_SSUSB_RX_EQ_EN_OFST             (5)
2049 #define E60802_RG_SSUSB_RX_EQ_EN_SEL_OFST         (4)
2050 #define E60802_RG_SSUSB_RX_SAOSC_RST_OFST         (3)
2051 #define E60802_RG_SSUSB_RX_SAOSC_RST_SEL_OFST     (2)
2052 #define E60802_RG_SSUSB_RX_DFE_RST_OFST           (1)
2053 #define E60802_RG_SSUSB_RX_DFE_RST_SEL_OFST       (0)
2054
2055 //U3D_PHYD_T2RLB
2056 #define E60802_RG_SSUSB_EQTRAIN_CH_MODE_OFST      (28)
2057 #define E60802_RG_SSUSB_PRB_OUT_CPPAT_OFST        (27)
2058 #define E60802_RG_SSUSB_BPANSIENC_OFST            (26)
2059 #define E60802_RG_SSUSB_VALID_EN_OFST             (25)
2060 #define E60802_RG_SSUSB_EBUF_SRST_OFST            (24)
2061 #define E60802_RG_SSUSB_K_EMP_OFST                (20)
2062 #define E60802_RG_SSUSB_K_FUL_OFST                (16)
2063 #define E60802_RG_SSUSB_T2RLB_BDATRST_OFST        (12)
2064 #define E60802_RG_SSUSB_P_T2RLB_SKP_EN_OFST       (10)
2065 #define E60802_RG_SSUSB_T2RLB_PATMODE_OFST        (8)
2066 #define E60802_RG_SSUSB_T2RLB_TSEQCNT_OFST        (0)
2067
2068 //U3D_PHYD_CPPAT
2069 #define E60802_RG_SSUSB_CPPAT_PROGRAM_EN_OFST     (24)
2070 #define E60802_RG_SSUSB_CPPAT_TOZ_OFST            (21)
2071 #define E60802_RG_SSUSB_CPPAT_PRBS_EN_OFST        (20)
2072 #define E60802_RG_SSUSB_CPPAT_OUT_TMP2_OFST       (16)
2073 #define E60802_RG_SSUSB_CPPAT_OUT_TMP1_OFST       (8)
2074 #define E60802_RG_SSUSB_CPPAT_OUT_TMP0_OFST       (0)
2075
2076 //U3D_PHYD_MIX3
2077 #define E60802_RG_SSUSB_CDR_TCADJ_MINUS_OFST      (31)
2078 #define E60802_RG_SSUSB_P_CDROS_EN_OFST           (30)
2079 #define E60802_RG_SSUSB_P_P2_TX_DRV_DIS_OFST      (28)
2080 #define E60802_RG_SSUSB_CDR_TCADJ_OFFSET_OFST     (24)
2081 #define E60802_RG_SSUSB_PLL_TCADJ_MINUS_OFST      (23)
2082 #define E60802_RG_SSUSB_FORCE_PLL_BIAS_LPF_EN_OFST (20)
2083 #define E60802_RG_SSUSB_PLL_BIAS_LPF_EN_OFST      (19)
2084 #define E60802_RG_SSUSB_PLL_TCADJ_OFFSET_OFST     (16)
2085 #define E60802_RG_SSUSB_FORCE_PLL_SSCEN_OFST      (15)
2086 #define E60802_RG_SSUSB_PLL_SSCEN_OFST            (14)
2087 #define E60802_RG_SSUSB_FORCE_CDR_PI_PWD_OFST     (13)
2088 #define E60802_RG_SSUSB_CDR_PI_PWD_OFST           (12)
2089 #define E60802_RG_SSUSB_CDR_PI_MODE_OFST          (11)
2090 #define E60802_RG_SSUSB_TXPLL_SSCEN_CYC_OFST      (0)
2091
2092 //U3D_PHYD_EBUFCTL
2093 #define E60802_RG_SSUSB_EBUFCTL_OFST              (0)
2094
2095 //U3D_PHYD_PIPE0
2096 #define E60802_RG_SSUSB_RXTERMINATION_OFST        (30)
2097 #define E60802_RG_SSUSB_RXEQTRAINING_OFST         (29)
2098 #define E60802_RG_SSUSB_RXPOLARITY_OFST           (28)
2099 #define E60802_RG_SSUSB_TXDEEMPH_OFST             (26)
2100 #define E60802_RG_SSUSB_POWERDOWN_OFST            (24)
2101 #define E60802_RG_SSUSB_TXONESZEROS_OFST          (23)
2102 #define E60802_RG_SSUSB_TXELECIDLE_OFST           (22)
2103 #define E60802_RG_SSUSB_TXDETECTRX_OFST           (21)
2104 #define E60802_RG_SSUSB_PIPE_SEL_OFST             (20)
2105 #define E60802_RG_SSUSB_TXDATAK_OFST              (16)
2106 #define E60802_RG_SSUSB_CDR_STABLE_SEL_OFST       (15)
2107 #define E60802_RG_SSUSB_CDR_STABLE_OFST           (14)
2108 #define E60802_RG_SSUSB_CDR_RSTB_SEL_OFST         (13)
2109 #define E60802_RG_SSUSB_CDR_RSTB_OFST             (12)
2110 #define E60802_RG_SSUSB_FRC_PIPE_POWERDOWN_OFST   (11)
2111 #define E60802_RG_SSUSB_P_TXBCN_DIS_OFST          (6)
2112 #define E60802_RG_SSUSB_P_ERROR_SEL_OFST          (4)
2113 #define E60802_RG_SSUSB_TXMARGIN_OFST             (1)
2114 #define E60802_RG_SSUSB_TXCOMPLIANCE_OFST         (0)
2115
2116 //U3D_PHYD_PIPE1
2117 #define E60802_RG_SSUSB_TXDATA_OFST               (0)
2118
2119 //U3D_PHYD_MIX4
2120 #define E60802_RG_SSUSB_CDROS_CNT_OFST            (24)
2121 #define E60802_RG_SSUSB_T2RLB_BER_EN_OFST         (16)
2122 #define E60802_RG_SSUSB_T2RLB_BER_RATE_OFST       (0)
2123
2124 //U3D_PHYD_CKGEN0
2125 #define E60802_RG_SSUSB_RFIFO_IMPLAT_OFST         (27)
2126 #define E60802_RG_SSUSB_TFIFO_PSEL_OFST           (24)
2127 #define E60802_RG_SSUSB_CKGEN_PSEL_OFST           (8)
2128 #define E60802_RG_SSUSB_RXCK_INV_OFST             (0)
2129
2130 //U3D_PHYD_MIX5
2131 #define E60802_RG_SSUSB_PRB_SEL_OFST              (16)
2132 #define E60802_RG_SSUSB_RXPLL_STBCYC_OFST         (0)
2133
2134 //U3D_PHYD_RESERVED
2135 #define E60802_RG_SSUSB_PHYD_RESERVE_OFST         (0)
2136
2137 //U3D_PHYD_CDR0
2138 #define E60802_RG_SSUSB_CDR_BIC_LTR_OFST          (28)
2139 #define E60802_RG_SSUSB_CDR_BIC_LTD0_OFST         (24)
2140 #define E60802_RG_SSUSB_CDR_BC_LTD1_OFST          (16)
2141 #define E60802_RG_SSUSB_CDR_BC_LTR_OFST           (8)
2142 #define E60802_RG_SSUSB_CDR_BC_LTD0_OFST          (0)
2143
2144 //U3D_PHYD_CDR1
2145 #define E60802_RG_SSUSB_CDR_BIR_LTD1_OFST         (24)
2146 #define E60802_RG_SSUSB_CDR_BIR_LTR_OFST          (16)
2147 #define E60802_RG_SSUSB_CDR_BIR_LTD0_OFST         (8)
2148 #define E60802_RG_SSUSB_CDR_BW_SEL_OFST           (6)
2149 #define E60802_RG_SSUSB_CDR_BIC_LTD1_OFST         (0)
2150
2151 //U3D_PHYD_PLL_0
2152 #define E60802_RG_SSUSB_FORCE_CDR_BAND_5G_OFST    (28)
2153 #define E60802_RG_SSUSB_FORCE_CDR_BAND_2P5G_OFST  (27)
2154 #define E60802_RG_SSUSB_FORCE_PLL_BAND_5G_OFST    (26)
2155 #define E60802_RG_SSUSB_FORCE_PLL_BAND_2P5G_OFST  (25)
2156 #define E60802_RG_SSUSB_P_EQ_T_SEL_OFST           (15)
2157 #define E60802_RG_SSUSB_PLL_ISO_EN_CYC_OFST       (5)
2158 #define E60802_RG_SSUSB_PLLBAND_RECAL_OFST        (4)
2159 #define E60802_RG_SSUSB_PLL_DDS_ISO_EN_OFST       (3)
2160 #define E60802_RG_SSUSB_FORCE_PLL_DDS_ISO_EN_OFST (2)
2161 #define E60802_RG_SSUSB_PLL_DDS_PWR_ON_OFST       (1)
2162 #define E60802_RG_SSUSB_FORCE_PLL_DDS_PWR_ON_OFST (0)
2163
2164 //U3D_PHYD_PLL_1
2165 #define E60802_RG_SSUSB_CDR_BAND_5G_OFST          (24)
2166 #define E60802_RG_SSUSB_CDR_BAND_2P5G_OFST        (16)
2167 #define E60802_RG_SSUSB_PLL_BAND_5G_OFST          (8)
2168 #define E60802_RG_SSUSB_PLL_BAND_2P5G_OFST        (0)
2169
2170 //U3D_PHYD_BCN_DET_1
2171 #define E60802_RG_SSUSB_P_BCN_OBS_PRD_OFST        (16)
2172 #define E60802_RG_SSUSB_U_BCN_OBS_PRD_OFST        (0)
2173
2174 //U3D_PHYD_BCN_DET_2
2175 #define E60802_RG_SSUSB_P_BCN_OBS_SEL_OFST        (16)
2176 #define E60802_RG_SSUSB_BCN_DET_DIS_OFST          (12)
2177 #define E60802_RG_SSUSB_U_BCN_OBS_SEL_OFST        (0)
2178
2179 //U3D_EQ0
2180 #define E60802_RG_SSUSB_EQ_DLHL_LFI_OFST          (24)
2181 #define E60802_RG_SSUSB_EQ_DHHL_LFI_OFST          (16)
2182 #define E60802_RG_SSUSB_EQ_DD0HOS_LFI_OFST        (8)
2183 #define E60802_RG_SSUSB_EQ_DD0LOS_LFI_OFST        (0)
2184
2185 //U3D_EQ1
2186 #define E60802_RG_SSUSB_EQ_DD1HOS_LFI_OFST        (24)
2187 #define E60802_RG_SSUSB_EQ_DD1LOS_LFI_OFST        (16)
2188 #define E60802_RG_SSUSB_EQ_DE0OS_LFI_OFST         (8)
2189 #define E60802_RG_SSUSB_EQ_DE1OS_LFI_OFST         (0)
2190
2191 //U3D_EQ2
2192 #define E60802_RG_SSUSB_EQ_DLHLOS_LFI_OFST        (24)
2193 #define E60802_RG_SSUSB_EQ_DHHLOS_LFI_OFST        (16)
2194 #define E60802_RG_SSUSB_EQ_STOPTIME_OFST          (14)
2195 #define E60802_RG_SSUSB_EQ_DHHL_LF_SEL_OFST       (11)
2196 #define E60802_RG_SSUSB_EQ_DSAOS_LF_SEL_OFST      (8)
2197 #define E60802_RG_SSUSB_EQ_STARTTIME_OFST         (6)
2198 #define E60802_RG_SSUSB_EQ_DLEQ_LF_SEL_OFST       (3)
2199 #define E60802_RG_SSUSB_EQ_DLHL_LF_SEL_OFST       (0)
2200
2201 //U3D_EQ3
2202 #define E60802_RG_SSUSB_EQ_DLEQ_LFI_GEN2_OFST     (28)
2203 #define E60802_RG_SSUSB_EQ_DLEQ_LFI_GEN1_OFST     (24)
2204 #define E60802_RG_SSUSB_EQ_DEYE0OS_LFI_OFST       (16)
2205 #define E60802_RG_SSUSB_EQ_DEYE1OS_LFI_OFST       (8)
2206 #define E60802_RG_SSUSB_EQ_TRI_DET_EN_OFST        (7)
2207 #define E60802_RG_SSUSB_EQ_TRI_DET_TH_OFST        (0)
2208
2209 //U3D_EQ_EYE0
2210 #define E60802_RG_SSUSB_EQ_EYE_XOFFSET_OFST       (25)
2211 #define E60802_RG_SSUSB_EQ_EYE_MON_EN_OFST        (24)
2212 #define E60802_RG_SSUSB_EQ_EYE0_Y_OFST            (16)
2213 #define E60802_RG_SSUSB_EQ_EYE1_Y_OFST            (8)
2214 #define E60802_RG_SSUSB_EQ_PILPO_ROUT_OFST        (7)
2215 #define E60802_RG_SSUSB_EQ_PI_KPGAIN_OFST         (4)
2216 #define E60802_RG_SSUSB_EQ_EYE_CNT_EN_OFST        (3)
2217
2218 //U3D_EQ_EYE1
2219 #define E60802_RG_SSUSB_EQ_SIGDET_OFST            (24)
2220 #define E60802_RG_SSUSB_EQ_EYE_MASK_OFST          (7)
2221
2222 //U3D_EQ_EYE2
2223 #define E60802_RG_SSUSB_EQ_RX500M_CK_SEL_OFST     (31)
2224 #define E60802_RG_SSUSB_EQ_SD_CNT1_OFST           (24)
2225 #define E60802_RG_SSUSB_EQ_ISIFLAG_SEL_OFST       (22)
2226 #define E60802_RG_SSUSB_EQ_SD_CNT0_OFST           (16)
2227
2228 //U3D_EQ_DFE0
2229 #define E60802_RG_SSUSB_EQ_LEQMAX_OFST            (28)
2230 #define E60802_RG_SSUSB_EQ_DFEX_EN_OFST           (27)
2231 #define E60802_RG_SSUSB_EQ_DFEX_LF_SEL_OFST       (24)
2232 #define E60802_RG_SSUSB_EQ_CHK_EYE_H_OFST         (23)
2233 #define E60802_RG_SSUSB_EQ_PIEYE_INI_OFST         (16)
2234 #define E60802_RG_SSUSB_EQ_PI90_INI_OFST          (8)
2235 #define E60802_RG_SSUSB_EQ_PI0_INI_OFST           (0)
2236
2237 //U3D_EQ_DFE1
2238 #define E60802_RG_SSUSB_EQ_REV_OFST               (16)
2239 #define E60802_RG_SSUSB_EQ_DFEYEN_DUR_OFST        (12)
2240 #define E60802_RG_SSUSB_EQ_DFEXEN_DUR_OFST        (8)
2241 #define E60802_RG_SSUSB_EQ_DFEX_RST_OFST          (7)
2242 #define E60802_RG_SSUSB_EQ_GATED_RXD_B_OFST       (6)
2243 #define E60802_RG_SSUSB_EQ_PI90CK_SEL_OFST        (4)
2244 #define E60802_RG_SSUSB_EQ_DFEX_DIS_OFST          (2)
2245 #define E60802_RG_SSUSB_EQ_DFEYEN_STOP_DIS_OFST   (1)
2246 #define E60802_RG_SSUSB_EQ_DFEXEN_SEL_OFST        (0)
2247
2248 //U3D_EQ_DFE2
2249 #define E60802_RG_SSUSB_EQ_MON_SEL_OFST           (24)
2250 #define E60802_RG_SSUSB_EQ_LEQOSC_DLYCNT_OFST     (16)
2251 #define E60802_RG_SSUSB_EQ_DLEQOS_LFI_OFST        (8)
2252 #define E60802_RG_SSUSB_EQ_DFE_TOG_OFST           (2)
2253 #define E60802_RG_SSUSB_EQ_LEQ_STOP_TO_OFST       (0)
2254
2255 //U3D_EQ_DFE3
2256 #define E60802_RG_SSUSB_EQ_RESERVED_OFST          (0)
2257
2258 //U3D_PHYD_MON0
2259 #define E60802_RGS_SSUSB_BERT_BERC_OFST           (16)
2260 #define E60802_RGS_SSUSB_LFPS_OFST                (12)
2261 #define E60802_RGS_SSUSB_TRAINDEC_OFST            (8)
2262 #define E60802_RGS_SSUSB_SCP_PAT_OFST             (0)
2263
2264 //U3D_PHYD_MON1
2265 #define E60802_RGS_SSUSB_RX_FL_OUT_OFST           (0)
2266
2267 //U3D_PHYD_MON2
2268 #define E60802_RGS_SSUSB_T2RLB_ERRCNT_OFST        (16)
2269 #define E60802_RGS_SSUSB_RETRACK_OFST             (12)
2270 #define E60802_RGS_SSUSB_RXPLL_LOCK_OFST          (10)
2271 #define E60802_RGS_SSUSB_CDR_VCOCAL_CPLT_D_OFST   (9)
2272 #define E60802_RGS_SSUSB_PLL_VCOCAL_CPLT_D_OFST   (8)
2273 #define E60802_RGS_SSUSB_PDNCTL_OFST              (0)
2274
2275 //U3D_PHYD_MON3
2276 #define E60802_RGS_SSUSB_TSEQ_ERRCNT_OFST         (16)
2277 #define E60802_RGS_SSUSB_PRBS_ERRCNT_OFST         (0)
2278
2279 //U3D_PHYD_MON4
2280 #define E60802_RGS_SSUSB_RX_LSLOCK_CNT_OFST       (24)
2281 #define E60802_RGS_SSUSB_SCP_DETCNT_OFST          (16)
2282 #define E60802_RGS_SSUSB_TSEQ_DETCNT_OFST         (0)
2283
2284 //U3D_PHYD_MON5
2285 #define E60802_RGS_SSUSB_EBUFMSG_OFST             (16)
2286 #define E60802_RGS_SSUSB_BERT_LOCK_OFST           (15)
2287 #define E60802_RGS_SSUSB_SCP_DET_OFST             (14)
2288 #define E60802_RGS_SSUSB_TSEQ_DET_OFST            (13)
2289 #define E60802_RGS_SSUSB_EBUF_UDF_OFST            (12)
2290 #define E60802_RGS_SSUSB_EBUF_OVF_OFST            (11)
2291 #define E60802_RGS_SSUSB_PRBS_PASSTH_OFST         (10)
2292 #define E60802_RGS_SSUSB_PRBS_PASS_OFST           (9)
2293 #define E60802_RGS_SSUSB_PRBS_LOCK_OFST           (8)
2294 #define E60802_RGS_SSUSB_T2RLB_ERR_OFST           (6)
2295 #define E60802_RGS_SSUSB_T2RLB_PASSTH_OFST        (5)
2296 #define E60802_RGS_SSUSB_T2RLB_PASS_OFST          (4)
2297 #define E60802_RGS_SSUSB_T2RLB_LOCK_OFST          (3)
2298 #define E60802_RGS_SSUSB_RX_IMPCAL_DONE_OFST      (2)
2299 #define E60802_RGS_SSUSB_TX_IMPCAL_DONE_OFST      (1)
2300 #define E60802_RGS_SSUSB_RXDETECTED_OFST          (0)
2301
2302 //U3D_PHYD_MON6
2303 #define E60802_RGS_SSUSB_SIGCAL_DONE_OFST         (30)
2304 #define E60802_RGS_SSUSB_SIGCAL_CAL_OUT_OFST      (29)
2305 #define E60802_RGS_SSUSB_SIGCAL_OFFSET_OFST       (24)
2306 #define E60802_RGS_SSUSB_RX_IMP_SEL_OFST          (16)
2307 #define E60802_RGS_SSUSB_TX_IMP_SEL_OFST          (8)
2308 #define E60802_RGS_SSUSB_TFIFO_MSG_OFST           (4)
2309 #define E60802_RGS_SSUSB_RFIFO_MSG_OFST           (0)
2310
2311 //U3D_PHYD_MON7
2312 #define E60802_RGS_SSUSB_FT_OUT_OFST              (8)
2313 #define E60802_RGS_SSUSB_PRB_OUT_OFST             (0)
2314
2315 //U3D_PHYA_RX_MON0
2316 #define E60802_RGS_SSUSB_EQ_DCLEQ_OFST            (24)
2317 #define E60802_RGS_SSUSB_EQ_DCD0H_OFST            (16)
2318 #define E60802_RGS_SSUSB_EQ_DCD0L_OFST            (8)
2319 #define E60802_RGS_SSUSB_EQ_DCD1H_OFST            (0)
2320
2321 //U3D_PHYA_RX_MON1
2322 #define E60802_RGS_SSUSB_EQ_DCD1L_OFST            (24)
2323 #define E60802_RGS_SSUSB_EQ_DCE0_OFST             (16)
2324 #define E60802_RGS_SSUSB_EQ_DCE1_OFST             (8)
2325 #define E60802_RGS_SSUSB_EQ_DCHHL_OFST            (0)
2326
2327 //U3D_PHYA_RX_MON2
2328 #define E60802_RGS_SSUSB_EQ_LEQ_STOP_OFST         (31)
2329 #define E60802_RGS_SSUSB_EQ_DCLHL_OFST            (24)
2330 #define E60802_RGS_SSUSB_EQ_STATUS_OFST           (16)
2331 #define E60802_RGS_SSUSB_EQ_DCEYE0_OFST           (8)
2332 #define E60802_RGS_SSUSB_EQ_DCEYE1_OFST           (0)
2333
2334 //U3D_PHYA_RX_MON3
2335 #define E60802_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST (0)
2336
2337 //U3D_PHYA_RX_MON4
2338 #define E60802_RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST (0)
2339
2340 //U3D_PHYA_RX_MON5
2341 #define E60802_RGS_SSUSB_EQ_DCLEQOS_OFST          (8)
2342 #define E60802_RGS_SSUSB_EQ_EYE_CNT_RDY_OFST      (7)
2343 #define E60802_RGS_SSUSB_EQ_PILPO_OFST            (0)
2344
2345 //U3D_PHYD_CPPAT2
2346 #define E60802_RG_SSUSB_CPPAT_OUT_H_TMP2_OFST     (16)
2347 #define E60802_RG_SSUSB_CPPAT_OUT_H_TMP1_OFST     (8)
2348 #define E60802_RG_SSUSB_CPPAT_OUT_H_TMP0_OFST     (0)
2349
2350 //U3D_EQ_EYE3
2351 #define E60802_RG_SSUSB_EQ_LEQ_SHIFT_OFST         (24)
2352 #define E60802_RG_SSUSB_EQ_EYE_CNT_OFST           (0)
2353
2354 //U3D_KBAND_OUT
2355 #define E60802_RGS_SSUSB_CDR_BAND_5G_OFST         (24)
2356 #define E60802_RGS_SSUSB_CDR_BAND_2P5G_OFST       (16)
2357 #define E60802_RGS_SSUSB_PLL_BAND_5G_OFST         (8)
2358 #define E60802_RGS_SSUSB_PLL_BAND_2P5G_OFST       (0)
2359
2360 //U3D_KBAND_OUT1
2361 #define E60802_RGS_SSUSB_CDR_VCOCAL_FAIL_OFST     (24)
2362 #define E60802_RGS_SSUSB_CDR_VCOCAL_STATE_OFST    (16)
2363 #define E60802_RGS_SSUSB_PLL_VCOCAL_FAIL_OFST     (8)
2364 #define E60802_RGS_SSUSB_PLL_VCOCAL_STATE_OFST    (0)
2365
2366 ///////////////////////////////////////////////////////////////////////////////
2367
2368 struct u3phyd_bank2_reg_e {
2369         //0x0
2370         PHY_LE32 b2_phyd_top1;
2371         PHY_LE32 b2_phyd_top2;
2372         PHY_LE32 b2_phyd_top3;
2373         PHY_LE32 b2_phyd_top4;
2374         //0x10
2375         PHY_LE32 b2_phyd_top5;
2376         PHY_LE32 b2_phyd_top6;
2377         PHY_LE32 b2_phyd_top7;
2378         PHY_LE32 b2_phyd_p_sigdet1;
2379         //0x20
2380         PHY_LE32 b2_phyd_p_sigdet2;
2381         PHY_LE32 b2_phyd_p_sigdet_cal1;
2382         PHY_LE32 b2_phyd_rxdet1;
2383         PHY_LE32 b2_phyd_rxdet2;
2384         //0x30
2385         PHY_LE32 b2_phyd_misc0;
2386         PHY_LE32 b2_phyd_misc2;
2387         PHY_LE32 b2_phyd_misc3;
2388         PHY_LE32 b2_phyd_l1ss;
2389         //0x40
2390         PHY_LE32 b2_rosc_0;
2391         PHY_LE32 b2_rosc_1;
2392         PHY_LE32 b2_rosc_2;
2393         PHY_LE32 b2_rosc_3;
2394         //0x50
2395         PHY_LE32 b2_rosc_4;
2396         PHY_LE32 b2_rosc_5;
2397         PHY_LE32 b2_rosc_6;
2398         PHY_LE32 b2_rosc_7;
2399         //0x60
2400         PHY_LE32 b2_rosc_8;
2401         PHY_LE32 b2_rosc_9;
2402         PHY_LE32 b2_rosc_a;
2403         PHY_LE32 reserve1;
2404         //0x70~0xd0
2405         PHY_LE32 reserve2[28];
2406         //0xe0
2407         PHY_LE32 phyd_version;
2408         PHY_LE32 phyd_model;
2409 };
2410
2411 //U3D_B2_PHYD_TOP1
2412 #define E60802_RG_SSUSB_PCIE2_K_EMP               (0xf<<28) //31:28
2413 #define E60802_RG_SSUSB_PCIE2_K_FUL               (0xf<<24) //27:24
2414 #define E60802_RG_SSUSB_TX_EIDLE_LP_EN            (0x1<<17) //17:17
2415 #define E60802_RG_SSUSB_FORCE_TX_EIDLE_LP_EN      (0x1<<16) //16:16
2416 #define E60802_RG_SSUSB_SIGDET_EN                 (0x1<<15) //15:15
2417 #define E60802_RG_SSUSB_FORCE_SIGDET_EN           (0x1<<14) //14:14
2418 #define E60802_RG_SSUSB_CLKRX_EN                  (0x1<<13) //13:13
2419 #define E60802_RG_SSUSB_FORCE_CLKRX_EN            (0x1<<12) //12:12
2420 #define E60802_RG_SSUSB_CLKTX_EN                  (0x1<<11) //11:11
2421 #define E60802_RG_SSUSB_FORCE_CLKTX_EN            (0x1<<10) //10:10
2422 #define E60802_RG_SSUSB_CLK_REQ_N_I               (0x1<<9) //9:9
2423 #define E60802_RG_SSUSB_FORCE_CLK_REQ_N_I         (0x1<<8) //8:8
2424 #define E60802_RG_SSUSB_RATE                      (0x1<<6) //6:6
2425 #define E60802_RG_SSUSB_FORCE_RATE                (0x1<<5) //5:5
2426 #define E60802_RG_SSUSB_PCIE_MODE_SEL             (0x1<<4) //4:4
2427 #define E60802_RG_SSUSB_FORCE_PCIE_MODE_SEL       (0x1<<3) //3:3
2428 #define E60802_RG_SSUSB_PHY_MODE                  (0x3<<1) //2:1
2429 #define E60802_RG_SSUSB_FORCE_PHY_MODE            (0x1<<0) //0:0
2430
2431 //U3D_B2_PHYD_TOP2
2432 #define E60802_RG_SSUSB_FORCE_IDRV_6DB            (0x1<<30) //30:30
2433 #define E60802_RG_SSUSB_IDRV_6DB                  (0x3f<<24) //29:24
2434 #define E60802_RG_SSUSB_FORCE_IDEM_3P5DB          (0x1<<22) //22:22
2435 #define E60802_RG_SSUSB_IDEM_3P5DB                (0x3f<<16) //21:16
2436 #define E60802_RG_SSUSB_FORCE_IDRV_3P5DB          (0x1<<14) //14:14
2437 #define E60802_RG_SSUSB_IDRV_3P5DB                (0x3f<<8) //13:8
2438 #define E60802_RG_SSUSB_FORCE_IDRV_0DB            (0x1<<6) //6:6
2439 #define E60802_RG_SSUSB_IDRV_0DB                  (0x3f<<0) //5:0
2440
2441 //U3D_B2_PHYD_TOP3
2442 #define E60802_RG_SSUSB_TX_BIASI                  (0x7<<25) //27:25
2443 #define E60802_RG_SSUSB_FORCE_TX_BIASI_EN         (0x1<<24) //24:24
2444 #define E60802_RG_SSUSB_TX_BIASI_EN               (0x1<<16) //16:16
2445 #define E60802_RG_SSUSB_FORCE_TX_BIASI            (0x1<<13) //13:13
2446 #define E60802_RG_SSUSB_FORCE_IDEM_6DB            (0x1<<8) //8:8
2447 #define E60802_RG_SSUSB_IDEM_6DB                  (0x3f<<0) //5:0
2448
2449 //U3D_B2_PHYD_TOP4
2450 #define E60802_RG_SSUSB_G1_CDR_BIC_LTR            (0xf<<28) //31:28
2451 #define E60802_RG_SSUSB_G1_CDR_BIC_LTD0           (0xf<<24) //27:24
2452 #define E60802_RG_SSUSB_G1_CDR_BC_LTD1            (0x1f<<16) //20:16
2453 #define E60802_RG_SSUSB_G1_L1SS_CDR_BW_SEL        (0x3<<13) //14:13
2454 #define E60802_RG_SSUSB_G1_CDR_BC_LTR             (0x1f<<8) //12:8
2455 #define E60802_RG_SSUSB_G1_CDR_BW_SEL             (0x3<<5) //6:5
2456 #define E60802_RG_SSUSB_G1_CDR_BC_LTD0            (0x1f<<0) //4:0
2457
2458 //U3D_B2_PHYD_TOP5
2459 #define E60802_RG_SSUSB_G1_CDR_BIR_LTD1           (0x1f<<24) //28:24
2460 #define E60802_RG_SSUSB_G1_CDR_BIR_LTR            (0x1f<<16) //20:16
2461 #define E60802_RG_SSUSB_G1_CDR_BIR_LTD0           (0x1f<<8) //12:8
2462 #define E60802_RG_SSUSB_G1_CDR_BIC_LTD1           (0xf<<0) //3:0
2463
2464 //U3D_B2_PHYD_TOP6
2465 #define E60802_RG_SSUSB_G2_CDR_BIC_LTR            (0xf<<28) //31:28
2466 #define E60802_RG_SSUSB_G2_CDR_BIC_LTD0           (0xf<<24) //27:24
2467 #define E60802_RG_SSUSB_G2_CDR_BC_LTD1            (0x1f<<16) //20:16
2468 #define E60802_RG_SSUSB_G2_L1SS_CDR_BW_SEL        (0x3<<13) //14:13
2469 #define E60802_RG_SSUSB_G2_CDR_BC_LTR             (0x1f<<8) //12:8
2470 #define E60802_RG_SSUSB_G2_CDR_BW_SEL             (0x3<<5) //6:5
2471 #define E60802_RG_SSUSB_G2_CDR_BC_LTD0            (0x1f<<0) //4:0
2472
2473 //U3D_B2_PHYD_TOP7
2474 #define E60802_RG_SSUSB_G2_CDR_BIR_LTD1           (0x1f<<24) //28:24
2475 #define E60802_RG_SSUSB_G2_CDR_BIR_LTR            (0x1f<<16) //20:16
2476 #define E60802_RG_SSUSB_G2_CDR_BIR_LTD0           (0x1f<<8) //12:8
2477 #define E60802_RG_SSUSB_G2_CDR_BIC_LTD1           (0xf<<0) //3:0
2478
2479 //U3D_B2_PHYD_P_SIGDET1
2480 #define E60802_RG_SSUSB_P_SIGDET_FLT_DIS          (0x1<<31) //31:31
2481 #define E60802_RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL (0x7f<<24) //30:24
2482 #define E60802_RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL (0x7f<<16) //22:16
2483 #define E60802_RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL   (0x7f<<8) //14:8
2484 #define E60802_RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL   (0x7f<<0) //6:0
2485
2486 //U3D_B2_PHYD_P_SIGDET2
2487 #define E60802_RG_SSUSB_P_SIGDET_RX_VAL_S         (0x1<<29) //29:29
2488 #define E60802_RG_SSUSB_P_SIGDET_L0S_DEAS_SEL     (0x1<<28) //28:28
2489 #define E60802_RG_SSUSB_P_SIGDET_L0_EXIT_S        (0x1<<27) //27:27
2490 #define E60802_RG_SSUSB_P_SIGDET_L0S_EXIT_T_S     (0x3<<25) //26:25
2491 #define E60802_RG_SSUSB_P_SIGDET_L0S_EXIT_S       (0x1<<24) //24:24
2492 #define E60802_RG_SSUSB_P_SIGDET_L0S_ENTRY_S      (0x1<<16) //16:16
2493 #define E60802_RG_SSUSB_P_SIGDET_PRB_SEL          (0x1<<10) //10:10
2494 #define E60802_RG_SSUSB_P_SIGDET_BK_SIG_T         (0x3<<8) //9:8
2495 #define E60802_RG_SSUSB_P_SIGDET_P2_RXLFPS        (0x1<<6) //6:6
2496 #define E60802_RG_SSUSB_P_SIGDET_NON_BK_AD        (0x1<<5) //5:5
2497 #define E60802_RG_SSUSB_P_SIGDET_BK_B_RXEQ        (0x1<<4) //4:4
2498 #define E60802_RG_SSUSB_P_SIGDET_G2_KO_SEL        (0x3<<2) //3:2
2499 #define E60802_RG_SSUSB_P_SIGDET_G1_KO_SEL        (0x3<<0) //1:0
2500
2501 //U3D_B2_PHYD_P_SIGDET_CAL1
2502 #define E60802_RG_SSUSB_G2_2EIOS_DET_EN           (0x1<<29) //29:29
2503 #define E60802_RG_SSUSB_P_SIGDET_CAL_OFFSET       (0x1f<<24) //28:24
2504 #define E60802_RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET (0x1<<16) //16:16
2505 #define E60802_RG_SSUSB_P_SIGDET_CAL_EN           (0x1<<8) //8:8
2506 #define E60802_RG_SSUSB_P_FORCE_SIGDET_CAL_EN     (0x1<<3) //3:3
2507 #define E60802_RG_SSUSB_P_SIGDET_FLT_EN           (0x1<<2) //2:2
2508 #define E60802_RG_SSUSB_P_SIGDET_SAMPLE_PRD       (0x1<<1) //1:1
2509 #define E60802_RG_SSUSB_P_SIGDET_REK              (0x1<<0) //0:0
2510
2511 //U3D_B2_PHYD_RXDET1
2512 #define E60802_RG_SSUSB_RXDET_PRB_SEL             (0x1<<31) //31:31
2513 #define E60802_RG_SSUSB_FORCE_CMDET               (0x1<<30) //30:30
2514 #define E60802_RG_SSUSB_RXDET_EN                  (0x1<<29) //29:29
2515 #define E60802_RG_SSUSB_FORCE_RXDET_EN            (0x1<<28) //28:28
2516 #define E60802_RG_SSUSB_RXDET_K_TWICE             (0x1<<27) //27:27
2517 #define E60802_RG_SSUSB_RXDET_STB3_SET            (0x1ff<<18) //26:18
2518 #define E60802_RG_SSUSB_RXDET_STB2_SET            (0x1ff<<9) //17:9
2519 #define E60802_RG_SSUSB_RXDET_STB1_SET            (0x1ff<<0) //8:0
2520
2521 //U3D_B2_PHYD_RXDET2
2522 #define E60802_RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN  (0x1<<31) //31:31
2523 #define E60802_RG_SSUSB_PHYD_BERTLB_FORCE_CGEN    (0x1<<30) //30:30
2524 #define E60802_RG_SSUSB_PHYD_T2RLB_FORCE_CGEN     (0x1<<29) //29:29
2525 #define E60802_RG_SSUSB_LCK2REF_EXT_EN            (0x1<<28) //28:28
2526 #define E60802_RG_SSUSB_G2_LCK2REF_EXT_SEL        (0xf<<24) //27:24
2527 #define E60802_RG_SSUSB_LCK2REF_EXT_SEL           (0xf<<20) //23:20
2528 #define E60802_RG_SSUSB_PDN_T_SEL                 (0x3<<18) //19:18
2529 #define E60802_RG_SSUSB_RXDET_STB3_SET_P3         (0x1ff<<9) //17:9
2530 #define E60802_RG_SSUSB_RXDET_STB2_SET_P3         (0x1ff<<0) //8:0
2531
2532 //U3D_B2_PHYD_MISC0
2533 #define E60802_RG_SSUSB_TX_EIDLE_LP_P0DLYCYC      (0x3f<<26) //31:26
2534 #define E60802_RG_SSUSB_TX_SER_EN                 (0x1<<25) //25:25
2535 #define E60802_RG_SSUSB_FORCE_TX_SER_EN           (0x1<<24) //24:24
2536 #define E60802_RG_SSUSB_TXPLL_REFCKSEL            (0x1<<23) //23:23
2537 #define E60802_RG_SSUSB_FORCE_PLL_DDS_HF_EN       (0x1<<22) //22:22
2538 #define E60802_RG_SSUSB_PLL_DDS_HF_EN_MAN         (0x1<<21) //21:21
2539 #define E60802_RG_SSUSB_RXLFPS_ENTXDRV            (0x1<<20) //20:20
2540 #define E60802_RG_SSUSB_RX_FL_UNLOCKTH            (0xf<<16) //19:16
2541 #define E60802_RG_SSUSB_LFPS_PSEL                 (0x1<<15) //15:15
2542 #define E60802_RG_SSUSB_RX_SIGDET_EN              (0x1<<14) //14:14
2543 #define E60802_RG_SSUSB_RX_SIGDET_EN_SEL          (0x1<<13) //13:13
2544 #define E60802_RG_SSUSB_RX_PI_CAL_EN              (0x1<<12) //12:12
2545 #define E60802_RG_SSUSB_RX_PI_CAL_EN_SEL          (0x1<<11) //11:11
2546 #define E60802_RG_SSUSB_P3_CLS_CK_SEL             (0x1<<10) //10:10
2547 #define E60802_RG_SSUSB_T2RLB_PSEL                (0x3<<8) //9:8
2548 #define E60802_RG_SSUSB_PPCTL_PSEL                (0x7<<5) //7:5
2549 #define E60802_RG_SSUSB_PHYD_TX_DATA_INV          (0x1<<4) //4:4
2550 #define E60802_RG_SSUSB_BERTLB_PSEL               (0x3<<2) //3:2
2551 #define E60802_RG_SSUSB_RETRACK_DIS               (0x1<<1) //1:1
2552 #define E60802_RG_SSUSB_PPERRCNT_CLR              (0x1<<0) //0:0
2553
2554 //U3D_B2_PHYD_MISC2
2555 #define E60802_RG_SSUSB_FRC_PLL_DDS_PREDIV2       (0x1<<31) //31:31
2556 #define E60802_RG_SSUSB_FRC_PLL_DDS_IADJ          (0xf<<27) //30:27
2557 #define E60802_RG_SSUSB_P_SIGDET_125FILTER        (0x1<<26) //26:26
2558 #define E60802_RG_SSUSB_P_SIGDET_RST_FILTER       (0x1<<25) //25:25
2559 #define E60802_RG_SSUSB_P_SIGDET_EID_USE_RAW      (0x1<<24) //24:24
2560 #define E60802_RG_SSUSB_P_SIGDET_LTD_USE_RAW      (0x1<<23) //23:23
2561 #define E60802_RG_SSUSB_EIDLE_BF_RXDET            (0x1<<22) //22:22
2562 #define E60802_RG_SSUSB_EIDLE_LP_STBCYC           (0x1ff<<13) //21:13
2563 #define E60802_RG_SSUSB_TX_EIDLE_LP_POSTDLY       (0x3f<<7) //12:7
2564 #define E60802_RG_SSUSB_TX_EIDLE_LP_PREDLY        (0x3f<<1) //6:1
2565 #define E60802_RG_SSUSB_TX_EIDLE_LP_EN_ADV        (0x1<<0) //0:0
2566
2567 //U3D_B2_PHYD_MISC3
2568 #define E60802_RGS_SSUSB_DDS_CALIB_C_STATE        (0x7<<16) //18:16
2569 #define E60802_RGS_SSUSB_PPERRCNT                 (0xffff<<0) //15:0
2570
2571 //U3D_B2_PHYD_L1SS
2572 #define E60802_RG_SSUSB_L1SS_REV1                 (0xff<<24) //31:24
2573 #define E60802_RG_SSUSB_L1SS_REV0                 (0xff<<16) //23:16
2574 #define E60802_RG_SSUSB_P_LTD1_SLOCK_DIS          (0x1<<11) //11:11
2575 #define E60802_RG_SSUSB_PLL_CNT_CLEAN_DIS         (0x1<<10) //10:10
2576 #define E60802_RG_SSUSB_P_PLL_REK_SEL             (0x1<<9) //9:9
2577 #define E60802_RG_SSUSB_TXDRV_MASKDLY             (0x1<<8) //8:8
2578 #define E60802_RG_SSUSB_RXSTS_VAL                 (0x1<<7) //7:7
2579 #define E60802_RG_PCIE_PHY_CLKREQ_N_EN            (0x1<<6) //6:6
2580 #define E60802_RG_PCIE_FORCE_PHY_CLKREQ_N_EN      (0x1<<5) //5:5
2581 #define E60802_RG_PCIE_PHY_CLKREQ_N_OUT           (0x1<<4) //4:4
2582 #define E60802_RG_PCIE_FORCE_PHY_CLKREQ_N_OUT     (0x1<<3) //3:3
2583 #define E60802_RG_SSUSB_RXPLL_STB_PX0             (0x1<<2) //2:2
2584 #define E60802_RG_PCIE_L1SS_EN                    (0x1<<1) //1:1
2585 #define E60802_RG_PCIE_FORCE_L1SS_EN              (0x1<<0) //0:0
2586
2587 //U3D_B2_ROSC_0
2588 #define E60802_RG_SSUSB_RING_OSC_CNTEND           (0x1ff<<23) //31:23
2589 #define E60802_RG_SSUSB_XTAL_OSC_CNTEND           (0x7f<<16) //22:16
2590 #define E60802_RG_SSUSB_RING_OSC_EN               (0x1<<3) //3:3
2591 #define E60802_RG_SSUSB_RING_OSC_FORCE_EN         (0x1<<2) //2:2
2592 #define E60802_RG_SSUSB_FRC_RING_BYPASS_DET       (0x1<<1) //1:1
2593 #define E60802_RG_SSUSB_RING_BYPASS_DET           (0x1<<0) //0:0
2594
2595 //U3D_B2_ROSC_1
2596 #define E60802_RG_SSUSB_RING_OSC_FRC_P3           (0x1<<20) //20:20
2597 #define E60802_RG_SSUSB_RING_OSC_P3               (0x1<<19) //19:19
2598 #define E60802_RG_SSUSB_RING_OSC_FRC_RECAL        (0x3<<17) //18:17
2599 #define E60802_RG_SSUSB_RING_OSC_RECAL            (0x1<<16) //16:16
2600 #define E60802_RG_SSUSB_RING_OSC_SEL              (0xff<<8) //15:8
2601 #define E60802_RG_SSUSB_RING_OSC_FRC_SEL          (0x1<<0) //0:0
2602
2603 //U3D_B2_ROSC_2
2604 #define E60802_RG_SSUSB_RING_DET_STRCYC2          (0xffff<<16) //31:16
2605 #define E60802_RG_SSUSB_RING_DET_STRCYC1          (0xffff<<0) //15:0
2606
2607 //U3D_B2_ROSC_3
2608 #define E60802_RG_SSUSB_RING_DET_DETWIN1          (0xffff<<16) //31:16
2609 #define E60802_RG_SSUSB_RING_DET_STRCYC3          (0xffff<<0) //15:0
2610
2611 //U3D_B2_ROSC_4
2612 #define E60802_RG_SSUSB_RING_DET_DETWIN3          (0xffff<<16) //31:16
2613 #define E60802_RG_SSUSB_RING_DET_DETWIN2          (0xffff<<0) //15:0
2614
2615 //U3D_B2_ROSC_5
2616 #define E60802_RG_SSUSB_RING_DET_LBOND1           (0xffff<<16) //31:16
2617 #define E60802_RG_SSUSB_RING_DET_UBOND1           (0xffff<<0) //15:0
2618
2619 //U3D_B2_ROSC_6
2620 #define E60802_RG_SSUSB_RING_DET_LBOND2           (0xffff<<16) //31:16
2621 #define E60802_RG_SSUSB_RING_DET_UBOND2           (0xffff<<0) //15:0
2622
2623 //U3D_B2_ROSC_7
2624 #define E60802_RG_SSUSB_RING_DET_LBOND3           (0xffff<<16) //31:16
2625 #define E60802_RG_SSUSB_RING_DET_UBOND3           (0xffff<<0) //15:0
2626
2627 //U3D_B2_ROSC_8
2628 #define E60802_RG_SSUSB_RING_RESERVE              (0xffff<<16) //31:16
2629 #define E60802_RG_SSUSB_ROSC_PROB_SEL             (0xf<<2) //5:2
2630 #define E60802_RG_SSUSB_RING_FREQMETER_EN         (0x1<<1) //1:1
2631 #define E60802_RG_SSUSB_RING_DET_BPS_UBOND        (0x1<<0) //0:0
2632
2633 //U3D_B2_ROSC_9
2634 #define E60802_RGS_FM_RING_CNT                    (0xffff<<16) //31:16
2635 #define E60802_RGS_SSUSB_RING_OSC_STATE           (0x3<<10) //11:10
2636 #define E60802_RGS_SSUSB_RING_OSC_STABLE          (0x1<<9) //9:9
2637 #define E60802_RGS_SSUSB_RING_OSC_CAL_FAIL        (0x1<<8) //8:8
2638 #define E60802_RGS_SSUSB_RING_OSC_CAL             (0xff<<0) //7:0
2639
2640 //U3D_B2_ROSC_A
2641 #define E60802_RGS_SSUSB_ROSC_PROB_OUT            (0xff<<0) //7:0
2642
2643 //U3D_PHYD_VERSION
2644 #define E60802_RGS_SSUSB_PHYD_VERSION             (0xffffffff<<0) //31:0
2645
2646 //U3D_PHYD_MODEL
2647 #define E60802_RGS_SSUSB_PHYD_MODEL               (0xffffffff<<0) //31:0
2648
2649 /* OFFSET */
2650
2651 //U3D_B2_PHYD_TOP1
2652 #define E60802_RG_SSUSB_PCIE2_K_EMP_OFST          (28)
2653 #define E60802_RG_SSUSB_PCIE2_K_FUL_OFST          (24)
2654 #define E60802_RG_SSUSB_TX_EIDLE_LP_EN_OFST       (17)
2655 #define E60802_RG_SSUSB_FORCE_TX_EIDLE_LP_EN_OFST (16)
2656 #define E60802_RG_SSUSB_SIGDET_EN_OFST            (15)
2657 #define E60802_RG_SSUSB_FORCE_SIGDET_EN_OFST      (14)
2658 #define E60802_RG_SSUSB_CLKRX_EN_OFST             (13)
2659 #define E60802_RG_SSUSB_FORCE_CLKRX_EN_OFST       (12)
2660 #define E60802_RG_SSUSB_CLKTX_EN_OFST             (11)
2661 #define E60802_RG_SSUSB_FORCE_CLKTX_EN_OFST       (10)
2662 #define E60802_RG_SSUSB_CLK_REQ_N_I_OFST          (9)
2663 #define E60802_RG_SSUSB_FORCE_CLK_REQ_N_I_OFST    (8)
2664 #define E60802_RG_SSUSB_RATE_OFST                 (6)
2665 #define E60802_RG_SSUSB_FORCE_RATE_OFST           (5)
2666 #define E60802_RG_SSUSB_PCIE_MODE_SEL_OFST        (4)
2667 #define E60802_RG_SSUSB_FORCE_PCIE_MODE_SEL_OFST  (3)
2668 #define E60802_RG_SSUSB_PHY_MODE_OFST             (1)
2669 #define E60802_RG_SSUSB_FORCE_PHY_MODE_OFST       (0)
2670
2671 //U3D_B2_PHYD_TOP2
2672 #define E60802_RG_SSUSB_FORCE_IDRV_6DB_OFST       (30)
2673 #define E60802_RG_SSUSB_IDRV_6DB_OFST             (24)
2674 #define E60802_RG_SSUSB_FORCE_IDEM_3P5DB_OFST     (22)
2675 #define E60802_RG_SSUSB_IDEM_3P5DB_OFST           (16)
2676 #define E60802_RG_SSUSB_FORCE_IDRV_3P5DB_OFST     (14)
2677 #define E60802_RG_SSUSB_IDRV_3P5DB_OFST           (8)
2678 #define E60802_RG_SSUSB_FORCE_IDRV_0DB_OFST       (6)
2679 #define E60802_RG_SSUSB_IDRV_0DB_OFST             (0)
2680
2681 //U3D_B2_PHYD_TOP3
2682 #define E60802_RG_SSUSB_TX_BIASI_OFST             (25)
2683 #define E60802_RG_SSUSB_FORCE_TX_BIASI_EN_OFST    (24)
2684 #define E60802_RG_SSUSB_TX_BIASI_EN_OFST          (16)
2685 #define E60802_RG_SSUSB_FORCE_TX_BIASI_OFST       (13)
2686 #define E60802_RG_SSUSB_FORCE_IDEM_6DB_OFST       (8)
2687 #define E60802_RG_SSUSB_IDEM_6DB_OFST             (0)
2688
2689 //U3D_B2_PHYD_TOP4
2690 #define E60802_RG_SSUSB_G1_CDR_BIC_LTR_OFST       (28)
2691 #define E60802_RG_SSUSB_G1_CDR_BIC_LTD0_OFST      (24)
2692 #define E60802_RG_SSUSB_G1_CDR_BC_LTD1_OFST       (16)
2693 #define E60802_RG_SSUSB_G1_L1SS_CDR_BW_SEL_OFST   (13)
2694 #define E60802_RG_SSUSB_G1_CDR_BC_LTR_OFST        (8)
2695 #define E60802_RG_SSUSB_G1_CDR_BW_SEL_OFST        (5)
2696 #define E60802_RG_SSUSB_G1_CDR_BC_LTD0_OFST       (0)
2697
2698 //U3D_B2_PHYD_TOP5
2699 #define E60802_RG_SSUSB_G1_CDR_BIR_LTD1_OFST      (24)
2700 #define E60802_RG_SSUSB_G1_CDR_BIR_LTR_OFST       (16)
2701 #define E60802_RG_SSUSB_G1_CDR_BIR_LTD0_OFST      (8)
2702 #define E60802_RG_SSUSB_G1_CDR_BIC_LTD1_OFST      (0)
2703
2704 //U3D_B2_PHYD_TOP6
2705 #define E60802_RG_SSUSB_G2_CDR_BIC_LTR_OFST       (28)
2706 #define E60802_RG_SSUSB_G2_CDR_BIC_LTD0_OFST      (24)
2707 #define E60802_RG_SSUSB_G2_CDR_BC_LTD1_OFST       (16)
2708 #define E60802_RG_SSUSB_G2_L1SS_CDR_BW_SEL_OFST   (13)
2709 #define E60802_RG_SSUSB_G2_CDR_BC_LTR_OFST        (8)
2710 #define E60802_RG_SSUSB_G2_CDR_BW_SEL_OFST        (5)
2711 #define E60802_RG_SSUSB_G2_CDR_BC_LTD0_OFST       (0)
2712
2713 //U3D_B2_PHYD_TOP7
2714 #define E60802_RG_SSUSB_G2_CDR_BIR_LTD1_OFST      (24)
2715 #define E60802_RG_SSUSB_G2_CDR_BIR_LTR_OFST       (16)
2716 #define E60802_RG_SSUSB_G2_CDR_BIR_LTD0_OFST      (8)
2717 #define E60802_RG_SSUSB_G2_CDR_BIC_LTD1_OFST      (0)
2718
2719 //U3D_B2_PHYD_P_SIGDET1
2720 #define E60802_RG_SSUSB_P_SIGDET_FLT_DIS_OFST     (31)
2721 #define E60802_RG_SSUSB_P_SIGDET_FLT_G2_DEAST_SEL_OFST (24)
2722 #define E60802_RG_SSUSB_P_SIGDET_FLT_G1_DEAST_SEL_OFST (16)
2723 #define E60802_RG_SSUSB_P_SIGDET_FLT_P2_AST_SEL_OFST (8)
2724 #define E60802_RG_SSUSB_P_SIGDET_FLT_PX_AST_SEL_OFST (0)
2725
2726 //U3D_B2_PHYD_P_SIGDET2
2727 #define E60802_RG_SSUSB_P_SIGDET_RX_VAL_S_OFST    (29)
2728 #define E60802_RG_SSUSB_P_SIGDET_L0S_DEAS_SEL_OFST (28)
2729 #define E60802_RG_SSUSB_P_SIGDET_L0_EXIT_S_OFST   (27)
2730 #define E60802_RG_SSUSB_P_SIGDET_L0S_EXIT_T_S_OFST (25)
2731 #define E60802_RG_SSUSB_P_SIGDET_L0S_EXIT_S_OFST  (24)
2732 #define E60802_RG_SSUSB_P_SIGDET_L0S_ENTRY_S_OFST (16)
2733 #define E60802_RG_SSUSB_P_SIGDET_PRB_SEL_OFST     (10)
2734 #define E60802_RG_SSUSB_P_SIGDET_BK_SIG_T_OFST    (8)
2735 #define E60802_RG_SSUSB_P_SIGDET_P2_RXLFPS_OFST   (6)
2736 #define E60802_RG_SSUSB_P_SIGDET_NON_BK_AD_OFST   (5)
2737 #define E60802_RG_SSUSB_P_SIGDET_BK_B_RXEQ_OFST   (4)
2738 #define E60802_RG_SSUSB_P_SIGDET_G2_KO_SEL_OFST   (2)
2739 #define E60802_RG_SSUSB_P_SIGDET_G1_KO_SEL_OFST   (0)
2740
2741 //U3D_B2_PHYD_P_SIGDET_CAL1
2742 #define E60802_RG_SSUSB_G2_2EIOS_DET_EN_OFST      (29)
2743 #define E60802_RG_SSUSB_P_SIGDET_CAL_OFFSET_OFST  (24)
2744 #define E60802_RG_SSUSB_P_FORCE_SIGDET_CAL_OFFSET_OFST (16)
2745 #define E60802_RG_SSUSB_P_SIGDET_CAL_EN_OFST      (8)
2746 #define E60802_RG_SSUSB_P_FORCE_SIGDET_CAL_EN_OFST (3)
2747 #define E60802_RG_SSUSB_P_SIGDET_FLT_EN_OFST      (2)
2748 #define E60802_RG_SSUSB_P_SIGDET_SAMPLE_PRD_OFST  (1)
2749 #define E60802_RG_SSUSB_P_SIGDET_REK_OFST         (0)
2750
2751 //U3D_B2_PHYD_RXDET1
2752 #define E60802_RG_SSUSB_RXDET_PRB_SEL_OFST        (31)
2753 #define E60802_RG_SSUSB_FORCE_CMDET_OFST          (30)
2754 #define E60802_RG_SSUSB_RXDET_EN_OFST             (29)
2755 #define E60802_RG_SSUSB_FORCE_RXDET_EN_OFST       (28)
2756 #define E60802_RG_SSUSB_RXDET_K_TWICE_OFST        (27)
2757 #define E60802_RG_SSUSB_RXDET_STB3_SET_OFST       (18)
2758 #define E60802_RG_SSUSB_RXDET_STB2_SET_OFST       (9)
2759 #define E60802_RG_SSUSB_RXDET_STB1_SET_OFST       (0)
2760
2761 //U3D_B2_PHYD_RXDET2
2762 #define E60802_RG_SSUSB_PHYD_TRAINDEC_FORCE_CGEN_OFST (31)
2763 #define E60802_RG_SSUSB_PHYD_BERTLB_FORCE_CGEN_OFST (30)
2764 #define E60802_RG_SSUSB_PHYD_T2RLB_FORCE_CGEN_OFST (29)
2765 #define E60802_RG_SSUSB_LCK2REF_EXT_EN_OFST       (28)
2766 #define E60802_RG_SSUSB_G2_LCK2REF_EXT_SEL_OFST   (24)
2767 #define E60802_RG_SSUSB_LCK2REF_EXT_SEL_OFST      (20)
2768 #define E60802_RG_SSUSB_PDN_T_SEL_OFST            (18)
2769 #define E60802_RG_SSUSB_RXDET_STB3_SET_P3_OFST    (9)
2770 #define E60802_RG_SSUSB_RXDET_STB2_SET_P3_OFST    (0)
2771
2772 //U3D_B2_PHYD_MISC0
2773 #define E60802_RG_SSUSB_TX_EIDLE_LP_P0DLYCYC_OFST (26)
2774 #define E60802_RG_SSUSB_TX_SER_EN_OFST            (25)
2775 #define E60802_RG_SSUSB_FORCE_TX_SER_EN_OFST      (24)
2776 #define E60802_RG_SSUSB_TXPLL_REFCKSEL_OFST       (23)
2777 #define E60802_RG_SSUSB_FORCE_PLL_DDS_HF_EN_OFST  (22)
2778 #define E60802_RG_SSUSB_PLL_DDS_HF_EN_MAN_OFST    (21)
2779 #define E60802_RG_SSUSB_RXLFPS_ENTXDRV_OFST       (20)
2780 #define E60802_RG_SSUSB_RX_FL_UNLOCKTH_OFST       (16)
2781 #define E60802_RG_SSUSB_LFPS_PSEL_OFST            (15)
2782 #define E60802_RG_SSUSB_RX_SIGDET_EN_OFST         (14)
2783 #define E60802_RG_SSUSB_RX_SIGDET_EN_SEL_OFST     (13)
2784 #define E60802_RG_SSUSB_RX_PI_CAL_EN_OFST         (12)
2785 #define E60802_RG_SSUSB_RX_PI_CAL_EN_SEL_OFST     (11)
2786 #define E60802_RG_SSUSB_P3_CLS_CK_SEL_OFST        (10)
2787 #define E60802_RG_SSUSB_T2RLB_PSEL_OFST           (8)
2788 #define E60802_RG_SSUSB_PPCTL_PSEL_OFST           (5)
2789 #define E60802_RG_SSUSB_PHYD_TX_DATA_INV_OFST     (4)
2790 #define E60802_RG_SSUSB_BERTLB_PSEL_OFST          (2)
2791 #define E60802_RG_SSUSB_RETRACK_DIS_OFST          (1)
2792 #define E60802_RG_SSUSB_PPERRCNT_CLR_OFST         (0)
2793
2794 //U3D_B2_PHYD_MISC2
2795 #define E60802_RG_SSUSB_FRC_PLL_DDS_PREDIV2_OFST  (31)
2796 #define E60802_RG_SSUSB_FRC_PLL_DDS_IADJ_OFST     (27)
2797 #define E60802_RG_SSUSB_P_SIGDET_125FILTER_OFST   (26)
2798 #define E60802_RG_SSUSB_P_SIGDET_RST_FILTER_OFST  (25)
2799 #define E60802_RG_SSUSB_P_SIGDET_EID_USE_RAW_OFST (24)
2800 #define E60802_RG_SSUSB_P_SIGDET_LTD_USE_RAW_OFST (23)
2801 #define E60802_RG_SSUSB_EIDLE_BF_RXDET_OFST       (22)
2802 #define E60802_RG_SSUSB_EIDLE_LP_STBCYC_OFST      (13)
2803 #define E60802_RG_SSUSB_TX_EIDLE_LP_POSTDLY_OFST  (7)
2804 #define E60802_RG_SSUSB_TX_EIDLE_LP_PREDLY_OFST   (1)
2805 #define E60802_RG_SSUSB_TX_EIDLE_LP_EN_ADV_OFST   (0)
2806
2807 //U3D_B2_PHYD_MISC3
2808 #define E60802_RGS_SSUSB_DDS_CALIB_C_STATE_OFST   (16)
2809 #define E60802_RGS_SSUSB_PPERRCNT_OFST            (0)
2810
2811 //U3D_B2_PHYD_L1SS
2812 #define E60802_RG_SSUSB_L1SS_REV1_OFST            (24)
2813 #define E60802_RG_SSUSB_L1SS_REV0_OFST            (16)
2814 #define E60802_RG_SSUSB_P_LTD1_SLOCK_DIS_OFST     (11)
2815 #define E60802_RG_SSUSB_PLL_CNT_CLEAN_DIS_OFST    (10)
2816 #define E60802_RG_SSUSB_P_PLL_REK_SEL_OFST        (9)
2817 #define E60802_RG_SSUSB_TXDRV_MASKDLY_OFST        (8)
2818 #define E60802_RG_SSUSB_RXSTS_VAL_OFST            (7)
2819 #define E60802_RG_PCIE_PHY_CLKREQ_N_EN_OFST       (6)
2820 #define E60802_RG_PCIE_FORCE_PHY_CLKREQ_N_EN_OFST (5)
2821 #define E60802_RG_PCIE_PHY_CLKREQ_N_OUT_OFST      (4)
2822 #define E60802_RG_PCIE_FORCE_PHY_CLKREQ_N_OUT_OFST (3)
2823 #define E60802_RG_SSUSB_RXPLL_STB_PX0_OFST        (2)
2824 #define E60802_RG_PCIE_L1SS_EN_OFST               (1)
2825 #define E60802_RG_PCIE_FORCE_L1SS_EN_OFST         (0)
2826
2827 //U3D_B2_ROSC_0
2828 #define E60802_RG_SSUSB_RING_OSC_CNTEND_OFST      (23)
2829 #define E60802_RG_SSUSB_XTAL_OSC_CNTEND_OFST      (16)
2830 #define E60802_RG_SSUSB_RING_OSC_EN_OFST          (3)
2831 #define E60802_RG_SSUSB_RING_OSC_FORCE_EN_OFST    (2)
2832 #define E60802_RG_SSUSB_FRC_RING_BYPASS_DET_OFST  (1)
2833 #define E60802_RG_SSUSB_RING_BYPASS_DET_OFST      (0)
2834
2835 //U3D_B2_ROSC_1
2836 #define E60802_RG_SSUSB_RING_OSC_FRC_P3_OFST      (20)
2837 #define E60802_RG_SSUSB_RING_OSC_P3_OFST          (19)
2838 #define E60802_RG_SSUSB_RING_OSC_FRC_RECAL_OFST   (17)
2839 #define E60802_RG_SSUSB_RING_OSC_RECAL_OFST       (16)
2840 #define E60802_RG_SSUSB_RING_OSC_SEL_OFST         (8)
2841 #define E60802_RG_SSUSB_RING_OSC_FRC_SEL_OFST     (0)
2842
2843 //U3D_B2_ROSC_2
2844 #define E60802_RG_SSUSB_RING_DET_STRCYC2_OFST     (16)
2845 #define E60802_RG_SSUSB_RING_DET_STRCYC1_OFST     (0)
2846
2847 //U3D_B2_ROSC_3
2848 #define E60802_RG_SSUSB_RING_DET_DETWIN1_OFST     (16)
2849 #define E60802_RG_SSUSB_RING_DET_STRCYC3_OFST     (0)
2850
2851 //U3D_B2_ROSC_4
2852 #define E60802_RG_SSUSB_RING_DET_DETWIN3_OFST     (16)
2853 #define E60802_RG_SSUSB_RING_DET_DETWIN2_OFST     (0)
2854
2855 //U3D_B2_ROSC_5
2856 #define E60802_RG_SSUSB_RING_DET_LBOND1_OFST      (16)
2857 #define E60802_RG_SSUSB_RING_DET_UBOND1_OFST      (0)
2858
2859 //U3D_B2_ROSC_6
2860 #define E60802_RG_SSUSB_RING_DET_LBOND2_OFST      (16)
2861 #define E60802_RG_SSUSB_RING_DET_UBOND2_OFST      (0)
2862
2863 //U3D_B2_ROSC_7
2864 #define E60802_RG_SSUSB_RING_DET_LBOND3_OFST      (16)
2865 #define E60802_RG_SSUSB_RING_DET_UBOND3_OFST      (0)
2866
2867 //U3D_B2_ROSC_8
2868 #define E60802_RG_SSUSB_RING_RESERVE_OFST         (16)
2869 #define E60802_RG_SSUSB_ROSC_PROB_SEL_OFST        (2)
2870 #define E60802_RG_SSUSB_RING_FREQMETER_EN_OFST    (1)
2871 #define E60802_RG_SSUSB_RING_DET_BPS_UBOND_OFST   (0)
2872
2873 //U3D_B2_ROSC_9
2874 #define E60802_RGS_FM_RING_CNT_OFST               (16)
2875 #define E60802_RGS_SSUSB_RING_OSC_STATE_OFST      (10)
2876 #define E60802_RGS_SSUSB_RING_OSC_STABLE_OFST     (9)
2877 #define E60802_RGS_SSUSB_RING_OSC_CAL_FAIL_OFST   (8)
2878 #define E60802_RGS_SSUSB_RING_OSC_CAL_OFST        (0)
2879
2880 //U3D_B2_ROSC_A
2881 #define E60802_RGS_SSUSB_ROSC_PROB_OUT_OFST       (0)
2882
2883 //U3D_PHYD_VERSION
2884 #define E60802_RGS_SSUSB_PHYD_VERSION_OFST        (0)
2885
2886 //U3D_PHYD_MODEL
2887 #define E60802_RGS_SSUSB_PHYD_MODEL_OFST          (0)
2888
2889 ///////////////////////////////////////////////////////////////////////////////
2890
2891 struct sifslv_chip_reg_e {
2892         //0x0
2893         PHY_LE32 gpio_ctla;
2894         PHY_LE32 gpio_ctlb;
2895         PHY_LE32 gpio_ctlc;
2896 };
2897
2898 ///////////////////////////////////////////////////////////////////////////////
2899
2900 struct sifslv_fm_feg_e {
2901         //0x0
2902         PHY_LE32 fmcr0;
2903         PHY_LE32 fmcr1;
2904         PHY_LE32 fmcr2;
2905         PHY_LE32 fmmonr0;
2906         //0X10
2907         PHY_LE32 fmmonr1;
2908 };
2909
2910 //U3D_FMCR0
2911 #define E60802_RG_LOCKTH                                 (0xf<<28) //31:28
2912 #define E60802_RG_MONCLK_SEL                             (0x3<<26) //27:26
2913 #define E60802_RG_FM_MODE                                (0x1<<25) //25:25
2914 #define E60802_RG_FREQDET_EN                             (0x1<<24) //24:24
2915 #define E60802_RG_CYCLECNT                               (0xffffff<<0) //23:0
2916
2917 //U3D_FMCR1
2918 #define E60802_RG_TARGET                                 (0xffffffff<<0) //31:0
2919
2920 //U3D_FMCR2
2921 #define E60802_RG_OFFSET                                 (0xffffffff<<0) //31:0
2922
2923 //U3D_FMMONR0
2924 #define E60802_USB_FM_OUT                                (0xffffffff<<0) //31:0
2925
2926 //U3D_FMMONR1
2927 #define E60802_RG_MONCLK_SEL_2                           (0x1<<9) //9:9
2928 #define E60802_RG_FRCK_EN                                (0x1<<8) //8:8
2929 #define E60802_USBPLL_LOCK                               (0x1<<1) //1:1
2930 #define E60802_USB_FM_VLD                                (0x1<<0) //0:0
2931
2932 /* OFFSET */
2933
2934 //U3D_FMCR0
2935 #define E60802_RG_LOCKTH_OFST                            (28)
2936 #define E60802_RG_MONCLK_SEL_OFST                        (26)
2937 #define E60802_RG_FM_MODE_OFST                           (25)
2938 #define E60802_RG_FREQDET_EN_OFST                        (24)
2939 #define E60802_RG_CYCLECNT_OFST                          (0)
2940
2941 //U3D_FMCR1
2942 #define E60802_RG_TARGET_OFST                            (0)
2943
2944 //U3D_FMCR2
2945 #define E60802_RG_OFFSET_OFST                            (0)
2946
2947 //U3D_FMMONR0
2948 #define E60802_USB_FM_OUT_OFST                           (0)
2949
2950 //U3D_FMMONR1
2951 #define E60802_RG_MONCLK_SEL_2_OFST                      (9)
2952 #define E60802_RG_FRCK_EN_OFST                           (8)
2953 #define E60802_USBPLL_LOCK_OFST                          (1)
2954 #define E60802_USB_FM_VLD_OFST                           (0)
2955
2956 ///////////////////////////////////////////////////////////////////////////////
2957
2958 struct spllc_reg_e {
2959         //0x0
2960         PHY_LE32 u3d_syspll_0;
2961         PHY_LE32 u3d_syspll_1;
2962         PHY_LE32 u3d_syspll_2;
2963         PHY_LE32 u3d_syspll_sdm;
2964         //0x10
2965         PHY_LE32 u3d_xtalctl_1;
2966         PHY_LE32 u3d_xtalctl_2;
2967         PHY_LE32 u3d_xtalctl3;
2968 };
2969
2970 //U3D_SYSPLL_0
2971 #define E60802_RG_SSUSB_SPLL_DDSEN_CYC                   (0x1f<<27) //31:27
2972 #define E60802_RG_SSUSB_SPLL_NCPOEN_CYC                  (0x3<<25) //26:25
2973 #define E60802_RG_SSUSB_SPLL_STBCYC                      (0x1ff<<16) //24:16
2974 #define E60802_RG_SSUSB_SPLL_NCPOCHG_CYC                 (0xf<<12) //15:12
2975 #define E60802_RG_SSUSB_SYSPLL_ON                        (0x1<<11) //11:11
2976 #define E60802_RG_SSUSB_FORCE_SYSPLLON                   (0x1<<10) //10:10
2977 #define E60802_RG_SSUSB_SPLL_DDSRSTB_CYC                 (0x7<<0) //2:0
2978
2979 //U3D_SYSPLL_1
2980 #define E60802_RG_SSUSB_PLL_BIAS_CYC                     (0xff<<24) //31:24
2981 #define E60802_RG_SSUSB_SYSPLL_STB                       (0x1<<23) //23:23
2982 #define E60802_RG_SSUSB_FORCE_SYSPLL_STB                 (0x1<<22) //22:22
2983 #define E60802_RG_SSUSB_SPLL_DDS_ISO_EN                  (0x1<<21) //21:21
2984 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_ISO_EN            (0x1<<20) //20:20
2985 #define E60802_RG_SSUSB_SPLL_DDS_PWR_ON                  (0x1<<19) //19:19
2986 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_PWR_ON            (0x1<<18) //18:18
2987 #define E60802_RG_SSUSB_PLL_BIAS_PWD                     (0x1<<17) //17:17
2988 #define E60802_RG_SSUSB_FORCE_PLL_BIAS_PWD               (0x1<<16) //16:16
2989 #define E60802_RG_SSUSB_FORCE_SPLL_NCPO_EN               (0x1<<15) //15:15
2990 #define E60802_RG_SSUSB_FORCE_SPLL_FIFO_START_MAN        (0x1<<14) //14:14
2991 #define E60802_RG_SSUSB_FORCE_SPLL_NCPO_CHG              (0x1<<12) //12:12
2992 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_RSTB              (0x1<<11) //11:11
2993 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_PWDB              (0x1<<10) //10:10
2994 #define E60802_RG_SSUSB_FORCE_SPLL_DDSEN                 (0x1<<9) //9:9
2995 #define E60802_RG_SSUSB_FORCE_SPLL_PWD                   (0x1<<8) //8:8
2996 #define E60802_RG_SSUSB_SPLL_NCPO_EN                     (0x1<<7) //7:7
2997 #define E60802_RG_SSUSB_SPLL_FIFO_START_MAN              (0x1<<6) //6:6
2998 #define E60802_RG_SSUSB_SPLL_NCPO_CHG                    (0x1<<4) //4:4
2999 #define E60802_RG_SSUSB_SPLL_DDS_RSTB                    (0x1<<3) //3:3
3000 #define E60802_RG_SSUSB_SPLL_DDS_PWDB                    (0x1<<2) //2:2
3001 #define E60802_RG_SSUSB_SPLL_DDSEN                       (0x1<<1) //1:1
3002 #define E60802_RG_SSUSB_SPLL_PWD                         (0x1<<0) //0:0
3003
3004 //U3D_SYSPLL_2
3005 #define E60802_RG_SSUSB_SPLL_P_ON_SEL                    (0x1<<11) //11:11
3006 #define E60802_RG_SSUSB_SPLL_FBDIV_CHG                   (0x1<<10) //10:10
3007 #define E60802_RG_SSUSB_SPLL_DDS_ISOEN_CYC               (0x3ff<<0) //9:0
3008
3009 //U3D_SYSPLL_SDM
3010 #define E60802_RG_SSUSB_SPLL_SDM_ISO_EN_CYC              (0x3ff<<14) //23:14
3011 #define E60802_RG_SSUSB_SPLL_FORCE_SDM_ISO_EN            (0x1<<13) //13:13
3012 #define E60802_RG_SSUSB_SPLL_SDM_ISO_EN                  (0x1<<12) //12:12
3013 #define E60802_RG_SSUSB_SPLL_SDM_PWR_ON_CYC              (0x3ff<<2) //11:2
3014 #define E60802_RG_SSUSB_SPLL_FORCE_SDM_PWR_ON            (0x1<<1) //1:1
3015 #define E60802_RG_SSUSB_SPLL_SDM_PWR_ON                  (0x1<<0) //0:0
3016
3017 //U3D_XTALCTL_1
3018 #define E60802_RG_SSUSB_BIAS_STBCYC                      (0x3fff<<17) //30:17
3019 #define E60802_RG_SSUSB_XTAL_CLK_REQ_N                   (0x1<<16) //16:16
3020 #define E60802_RG_SSUSB_XTAL_FORCE_CLK_REQ_N             (0x1<<15) //15:15
3021 #define E60802_RG_SSUSB_XTAL_STBCYC                      (0x7fff<<0) //14:0
3022
3023 //U3D_XTALCTL_2
3024 #define E60802_RG_SSUSB_INT_XTAL_SEL                     (0x1<<29) //29:29
3025 #define E60802_RG_SSUSB_BG_LPF_DLY                       (0x3<<27) //28:27
3026 #define E60802_RG_SSUSB_BG_LPF_EN                        (0x1<<26) //26:26
3027 #define E60802_RG_SSUSB_FORCE_BG_LPF_EN                  (0x1<<25) //25:25
3028 #define E60802_RG_SSUSB_P3_BIAS_PWD                      (0x1<<24) //24:24
3029 #define E60802_RG_SSUSB_PCIE_CLKDET_HIT                  (0x1<<20) //20:20
3030 #define E60802_RG_SSUSB_PCIE_CLKDET_EN                   (0x1<<19) //19:19
3031 #define E60802_RG_SSUSB_FRC_PCIE_CLKDET_EN               (0x1<<18) //18:18
3032 #define E60802_RG_SSUSB_USB20_BIAS_EN                    (0x1<<17) //17:17
3033 #define E60802_RG_SSUSB_USB20_SLEEP                      (0x1<<16) //16:16
3034 #define E60802_RG_SSUSB_OSC_ONLY                         (0x1<<9) //9:9
3035 #define E60802_RG_SSUSB_OSC_EN                           (0x1<<8) //8:8
3036 #define E60802_RG_SSUSB_XTALBIAS_STB                     (0x1<<5) //5:5
3037 #define E60802_RG_SSUSB_FORCE_XTALBIAS_STB               (0x1<<4) //4:4
3038 #define E60802_RG_SSUSB_BIAS_PWD                         (0x1<<3) //3:3
3039 #define E60802_RG_SSUSB_XTAL_PWD                         (0x1<<2) //2:2
3040 #define E60802_RG_SSUSB_FORCE_BIAS_PWD                   (0x1<<1) //1:1
3041 #define E60802_RG_SSUSB_FORCE_XTAL_PWD                   (0x1<<0) //0:0
3042
3043 //U3D_XTALCTL3
3044 #define E60802_RG_SSUSB_XTALCTL_REV                      (0xf<<12) //15:12
3045 #define E60802_RG_SSUSB_BIASIMR_EN                       (0x1<<11) //11:11
3046 #define E60802_RG_SSUSB_FORCE_BIASIMR_EN                 (0x1<<10) //10:10
3047 #define E60802_RG_SSUSB_XTAL_RX_PWD                      (0x1<<9) //9:9
3048 #define E60802_RG_SSUSB_FRC_XTAL_RX_PWD                  (0x1<<8) //8:8
3049 #define E60802_RG_SSUSB_CKBG_PROB_SEL                    (0x3<<6) //7:6
3050 #define E60802_RG_SSUSB_XTAL_PROB_SEL                    (0x3<<4) //5:4
3051 #define E60802_RG_SSUSB_XTAL_VREGBIAS_LPF_ENB            (0x1<<3) //3:3
3052 #define E60802_RG_SSUSB_XTAL_FRC_VREGBIAS_LPF_ENB        (0x1<<2) //2:2
3053 #define E60802_RG_SSUSB_XTAL_VREGBIAS_PWD                (0x1<<1) //1:1
3054 #define E60802_RG_SSUSB_XTAL_FRC_VREGBIAS_PWD            (0x1<<0) //0:0
3055
3056
3057 /* SSUSB_SIFSLV_SPLLC FIELD OFFSET DEFINITION */
3058
3059 //U3D_SYSPLL_0
3060 #define E60802_RG_SSUSB_SPLL_DDSEN_CYC_OFST              (27)
3061 #define E60802_RG_SSUSB_SPLL_NCPOEN_CYC_OFST             (25)
3062 #define E60802_RG_SSUSB_SPLL_STBCYC_OFST                 (16)
3063 #define E60802_RG_SSUSB_SPLL_NCPOCHG_CYC_OFST            (12)
3064 #define E60802_RG_SSUSB_SYSPLL_ON_OFST                   (11)
3065 #define E60802_RG_SSUSB_FORCE_SYSPLLON_OFST              (10)
3066 #define E60802_RG_SSUSB_SPLL_DDSRSTB_CYC_OFST            (0)
3067
3068 //U3D_SYE60802_SPLL_1
3069 #define E60802_RG_SSUSB_PLL_BIAS_CYC_OFST                (24)
3070 #define E60802_RG_SSUSB_SYSPLL_STB_OFST                  (23)
3071 #define E60802_RG_SSUSB_FORCE_SYSPLL_STB_OFST            (22)
3072 #define E60802_RG_SSUSB_SPLL_DDS_ISO_EN_OFST             (21)
3073 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_ISO_EN_OFST       (20)
3074 #define E60802_RG_SSUSB_SPLL_DDS_PWR_ON_OFST             (19)
3075 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_PWR_ON_OFST       (18)
3076 #define E60802_RG_SSUSB_PLL_BIAS_PWD_OFST                (17)
3077 #define E60802_RG_SSUSB_FORCE_PLL_BIAS_PWD_OFST          (16)
3078 #define E60802_RG_SSUSB_FORCE_SPLL_NCPO_EN_OFST          (15)
3079 #define E60802_RG_SSUSB_FORCE_SPLL_FIFO_START_MAN_OFST   (14)
3080 #define E60802_RG_SSUSB_FORCE_SPLL_NCPO_CHG_OFST         (12)
3081 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_RSTB_OFST         (11)
3082 #define E60802_RG_SSUSB_FORCE_SPLL_DDS_PWDB_OFST         (10)
3083 #define E60802_RG_SSUSB_FORCE_SPLL_DDSEN_OFST            (9)
3084 #define E60802_RG_SSUSB_FORCE_SPLL_PWD_OFST              (8)
3085 #define E60802_RG_SSUSB_SPLL_NCPO_EN_OFST                (7)
3086 #define E60802_RG_SSUSB_SPLL_FIFO_START_MAN_OFST         (6)
3087 #define E60802_RG_SSUSB_SPLL_NCPO_CHG_OFST               (4)
3088 #define E60802_RG_SSUSB_SPLL_DDS_RSTB_OFST               (3)
3089 #define E60802_RG_SSUSB_SPLL_DDS_PWDB_OFST               (2)
3090 #define E60802_RG_SSUSB_SPLL_DDSEN_OFST                  (1)
3091 #define E60802_RG_SSUSB_SPLL_PWD_OFST                    (0)
3092
3093 //U3D_SYSPLL_2
3094 #define E60802_RG_SSUSB_SPLL_P_ON_SEL_OFST               (11)
3095 #define E60802_RG_SSUSB_SPLL_FBDIV_CHG_OFST              (10)
3096 #define E60802_RG_SSUSB_SPLL_DDS_ISOEN_CYC_OFST          (0)
3097
3098 //U3D_SYSPLL_SDM
3099 #define E60802_RG_SSUSB_SPLL_SDM_ISO_EN_CYC_OFST         (14)
3100 #define E60802_RG_SSUSB_SPLL_FORCE_SDM_ISO_EN_OFST       (13)
3101 #define E60802_RG_SSUSB_SPLL_SDM_ISO_EN_OFST             (12)
3102 #define E60802_RG_SSUSB_SPLL_SDM_PWR_ON_CYC_OFST         (2)
3103 #define E60802_RG_SSUSB_SPLL_FORCE_SDM_PWR_ON_OFST       (1)
3104 #define E60802_RG_SSUSB_SPLL_SDM_PWR_ON_OFST             (0)
3105
3106 //U3D_XTALCTL_1
3107 #define E60802_RG_SSUSB_BIAS_STBCYC_OFST                 (17)
3108 #define E60802_RG_SSUSB_XTAL_CLK_REQ_N_OFST              (16)
3109 #define E60802_RG_SSUSB_XTAL_FORCE_CLK_REQ_N_OFST        (15)
3110 #define E60802_RG_SSUSB_XTAL_STBCYC_OFST                 (0)
3111
3112 //U3D_XTALCTL_2
3113 #define E60802_RG_SSUSB_INT_XTAL_SEL_OFST                (29)
3114 #define E60802_RG_SSUSB_BG_LPF_DLY_OFST                  (27)
3115 #define E60802_RG_SSUSB_BG_LPF_EN_OFST                   (26)
3116 #define E60802_RG_SSUSB_FORCE_BG_LPF_EN_OFST             (25)
3117 #define E60802_RG_SSUSB_P3_BIAS_PWD_OFST                 (24)
3118 #define E60802_RG_SSUSB_PCIE_CLKDET_HIT_OFST             (20)
3119 #define E60802_RG_SSUSB_PCIE_CLKDET_EN_OFST              (19)
3120 #define E60802_RG_SSUSB_FRC_PCIE_CLKDET_EN_OFST          (18)
3121 #define E60802_RG_SSUSB_USB20_BIAS_EN_OFST               (17)
3122 #define E60802_RG_SSUSB_USB20_SLEEP_OFST                 (16)
3123 #define E60802_RG_SSUSB_OSC_ONLY_OFST                    (9)
3124 #define E60802_RG_SSUSB_OSC_EN_OFST                      (8)
3125 #define E60802_RG_SSUSB_XTALBIAS_STB_OFST                (5)
3126 #define E60802_RG_SSUSB_FORCE_XTALBIAS_STB_OFST          (4)
3127 #define E60802_RG_SSUSB_BIAS_PWD_OFST                    (3)
3128 #define E60802_RG_SSUSB_XTAL_PWD_OFST                    (2)
3129 #define E60802_RG_SSUSB_FORCE_BIAS_PWD_OFST              (1)
3130 #define E60802_RG_SSUSB_FORCE_XTAL_PWD_OFST              (0)
3131
3132 //U3D_XTALCTL3
3133 #define E60802_RG_SSUSB_XTALCTL_REV_OFST                 (12)
3134 #define E60802_RG_SSUSB_BIASIMR_EN_OFST                  (11)
3135 #define E60802_RG_SSUSB_FORCE_BIASIMR_EN_OFST            (10)
3136 #define E60802_RG_SSUSB_XTAL_RX_PWD_OFST                 (9)
3137 #define E60802_RG_SSUSB_FRC_XTAL_RX_PWD_OFST             (8)
3138 #define E60802_RG_SSUSB_CKBG_PROB_SEL_OFST               (6)
3139 #define E60802_RG_SSUSB_XTAL_PROB_SEL_OFST               (4)
3140 #define E60802_RG_SSUSB_XTAL_VREGBIAS_LPF_ENB_OFST       (3)
3141 #define E60802_RG_SSUSB_XTAL_FRC_VREGBIAS_LPF_ENB_OFST   (2)
3142 #define E60802_RG_SSUSB_XTAL_VREGBIAS_PWD_OFST           (1)
3143 #define E60802_RG_SSUSB_XTAL_FRC_VREGBIAS_PWD_OFST       (0)
3144
3145 ///////////////////////////////////////////////////////////////////////////////
3146 PHY_INT32 phy_init_soc(struct u3phy_info *info);
3147 PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info);
3148
3149 void usb_phy_savecurrent(unsigned int clk_on);
3150 void usb_phy_recover(unsigned int clk_on);
3151 void usb_fake_powerdown(unsigned int clk_on);
3152
3153 #endif
3154 #endif