include/asm-x86/pgtable_32.h

   1 #ifndef ASM_X86__PGTABLE_32_H
   2 #define ASM_X86__PGTABLE_32_H
   3
   4
   5 /*
   6  * The Linux memory management assumes a three-level page table setup. On
   7  * the i386, we use that, but "fold" the mid level into the top-level page
   8  * table, so that we physically have the same two-level page table as the
   9  * i386 mmu expects.
  10  *
  11  * This file contains the functions and defines necessary to modify and use
  12  * the i386 page table tree.
  13  */
  14 #ifndef __ASSEMBLY__
  15 #include <asm/processor.h>
  16 #include <asm/fixmap.h>
  17 #include <linux/threads.h>
  18 #include <asm/paravirt.h>
  19
  20 #include <linux/bitops.h>
  21 #include <linux/slab.h>
  22 #include <linux/list.h>
  23 #include <linux/spinlock.h>
  24
  25 struct mm_struct;
  26 struct vm_area_struct;
  27
  28 extern pgd_t swapper_pg_dir[1024];
  29
  30 static inline void pgtable_cache_init(void) { }
  31 static inline void check_pgt_cache(void) { }
  32 void paging_init(void);
  33
  34
  35 /*
  36  * The Linux x86 paging architecture is 'compile-time dual-mode', it
  37  * implements both the traditional 2-level x86 page tables and the
  38  * newer 3-level PAE-mode page tables.
  39  */
  40 #ifdef CONFIG_X86_PAE
  41 # include <asm/pgtable-3level-defs.h>
  42 # define PMD_SIZE       (1UL << PMD_SHIFT)
  43 # define PMD_MASK       (~(PMD_SIZE - 1))
  44 #else
  45 # include <asm/pgtable-2level-defs.h>
  46 #endif
  47
  48 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  49 #define PGDIR_MASK      (~(PGDIR_SIZE - 1))
  50
  51 /* Just any arbitrary offset to the start of the vmalloc VM area: the
  52  * current 8MB value just means that there will be a 8MB "hole" after the
  53  * physical memory until the kernel virtual memory starts.  That means that
  54  * any out-of-bounds memory accesses will hopefully be caught.
  55  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  56  * area for the same reason. ;)
  57  */
  58 #define VMALLOC_OFFSET  (8 * 1024 * 1024)
  59 #define VMALLOC_START   (((unsigned long)high_memory + 2 * VMALLOC_OFFSET - 1) \
  60                          & ~(VMALLOC_OFFSET - 1))
  61 #ifdef CONFIG_X86_PAE
  62 #define LAST_PKMAP 512
  63 #else
  64 #define LAST_PKMAP 1024
  65 #endif
  66
  67 #define PKMAP_BASE ((FIXADDR_BOOT_START - PAGE_SIZE * (LAST_PKMAP + 1)) \
  68                     & PMD_MASK)
  69
  70 #ifdef CONFIG_HIGHMEM
  71 # define VMALLOC_END    (PKMAP_BASE - 2 * PAGE_SIZE)
  72 #else
  73 # define VMALLOC_END    (FIXADDR_START - 2 * PAGE_SIZE)
  74 #endif
  75
  76 /*
  77  * Define this if things work differently on an i386 and an i486:
  78  * it will (on an i486) warn about kernel memory accesses that are
  79  * done without a 'access_ok(VERIFY_WRITE,..)'
  80  */
  81 #undef TEST_ACCESS_OK
  82
  83 /* The boot page tables (all created as a single array) */
  84 extern unsigned long pg0[];
  85
  86 #define pte_present(x)  ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
  87
  88 /* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
  89 #define pmd_none(x)     (!(unsigned long)pmd_val((x)))
  90 #define pmd_present(x)  (pmd_val((x)) & _PAGE_PRESENT)
  91 #define pmd_bad(x) ((pmd_val(x) & (~PTE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
  92
  93 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
  94
  95 #ifdef CONFIG_X86_PAE
  96 # include <asm/pgtable-3level.h>
  97 #else
  98 # include <asm/pgtable-2level.h>
  99 #endif
 100
 101 /*
 102  * Macro to mark a page protection value as "uncacheable".
 103  * On processors which do not support it, this is a no-op.
 104  */
 105 #define pgprot_noncached(prot)                                  \
 106         ((boot_cpu_data.x86 > 3)                                \
 107          ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) \
 108          : (prot))
 109
 110 /*
 111  * Conversion functions: convert a page and protection to a page entry,
 112  * and a page entry and page directory to the page they refer to.
 113  */
 114 #define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
 115
 116
 117 static inline int pud_large(pud_t pud) { return 0; }
 118
 119 /*
 120  * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
 121  *
 122  * this macro returns the index of the entry in the pmd page which would
 123  * control the given virtual address
 124  */
 125 #define pmd_index(address)                              \
 126         (((address) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 127
 128 /*
 129  * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
 130  *
 131  * this macro returns the index of the entry in the pte page which would
 132  * control the given virtual address
 133  */
 134 #define pte_index(address)                                      \
 135         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 136 #define pte_offset_kernel(dir, address)                         \
 137         ((pte_t *)pmd_page_vaddr(*(dir)) +  pte_index((address)))
 138
 139 #define pmd_page(pmd) (pfn_to_page(pmd_val((pmd)) >> PAGE_SHIFT))
 140
 141 #define pmd_page_vaddr(pmd)                                     \
 142         ((unsigned long)__va(pmd_val((pmd)) & PTE_MASK))
 143
 144 #if defined(CONFIG_HIGHPTE)
 145 #define pte_offset_map(dir, address)                                    \
 146         ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE0) +          \
 147          pte_index((address)))
 148 #define pte_offset_map_nested(dir, address)                             \
 149         ((pte_t *)kmap_atomic_pte(pmd_page(*(dir)), KM_PTE1) +          \
 150          pte_index((address)))
 151 #define pte_unmap(pte) kunmap_atomic((pte), KM_PTE0)
 152 #define pte_unmap_nested(pte) kunmap_atomic((pte), KM_PTE1)
 153 #else
 154 #define pte_offset_map(dir, address)                                    \
 155         ((pte_t *)page_address(pmd_page(*(dir))) + pte_index((address)))
 156 #define pte_offset_map_nested(dir, address) pte_offset_map((dir), (address))
 157 #define pte_unmap(pte) do { } while (0)
 158 #define pte_unmap_nested(pte) do { } while (0)
 159 #endif
 160
 161 /* Clear a kernel PTE and flush it from the TLB */
 162 #define kpte_clear_flush(ptep, vaddr)           \
 163 do {                                            \
 164         pte_clear(&init_mm, (vaddr), (ptep));   \
 165         __flush_tlb_one((vaddr));               \
 166 } while (0)
 167
 168 /*
 169  * The i386 doesn't have any external MMU info: the kernel page
 170  * tables contain all the necessary information.
 171  */
 172 #define update_mmu_cache(vma, address, pte) do { } while (0)
 173
 174 #endif /* !__ASSEMBLY__ */
 175
 176 /*
 177  * kern_addr_valid() is (1) for FLATMEM and (0) for
 178  * SPARSEMEM and DISCONTIGMEM
 179  */
 180 #ifdef CONFIG_FLATMEM
 181 #define kern_addr_valid(addr)   (1)
 182 #else
 183 #define kern_addr_valid(kaddr)  (0)
 184 #endif
 185
 186 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
 187         remap_pfn_range(vma, vaddr, pfn, size, prot)
 188
 189 #endif /* ASM_X86__PGTABLE_32_H */