x86: consolidate header guards
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-x86 / gart.h
1 #ifndef ASM_X86__GART_H
2 #define ASM_X86__GART_H
3
4 #include <asm/e820.h>
5
6 extern void set_up_gart_resume(u32, u32);
7
8 extern int fallback_aper_order;
9 extern int fallback_aper_force;
10 extern int fix_aperture;
11
12 /* PTE bits. */
13 #define GPTE_VALID 1
14 #define GPTE_COHERENT 2
15
16 /* Aperture control register bits. */
17 #define GARTEN (1<<0)
18 #define DISGARTCPU (1<<4)
19 #define DISGARTIO (1<<5)
20
21 /* GART cache control register bits. */
22 #define INVGART (1<<0)
23 #define GARTPTEERR (1<<1)
24
25 /* K8 On-cpu GART registers */
26 #define AMD64_GARTAPERTURECTL 0x90
27 #define AMD64_GARTAPERTUREBASE 0x94
28 #define AMD64_GARTTABLEBASE 0x98
29 #define AMD64_GARTCACHECTL 0x9c
30 #define AMD64_GARTEN (1<<0)
31
32 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
33 {
34 u32 tmp, ctl;
35
36 /* address of the mappings table */
37 addr >>= 12;
38 tmp = (u32) addr<<4;
39 tmp &= ~0xf;
40 pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
41
42 /* Enable GART translation for this hammer. */
43 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
44 ctl |= GARTEN;
45 ctl &= ~(DISGARTCPU | DISGARTIO);
46 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
47 }
48
49 static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
50 {
51 if (!aper_base)
52 return 0;
53
54 if (aper_base + aper_size > 0x100000000ULL) {
55 printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
56 return 0;
57 }
58 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
59 printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
60 return 0;
61 }
62 if (aper_size < min_size) {
63 printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
64 aper_size>>20, min_size>>20);
65 return 0;
66 }
67
68 return 1;
69 }
70
71 #endif /* ASM_X86__GART_H */