include/asm-blackfin/mach-bf561/anomaly.h

   1
   2 /*
   3  * File:         include/asm-blackfin/mach-bf561/anomaly.h
   4  * Based on:
   5  * Author:
   6  *
   7  * Created:
   8  * Description:
   9  *
  10  * Rev:
  11  *
  12  * Modified:
  13  *
  14  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; see the file COPYING.
  28  * If not, write to the Free Software Foundation,
  29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 /* This file shoule be up to date with:
  33  *  - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
  34  */
  35
  36 #ifndef _MACH_ANOMALY_H_
  37 #define _MACH_ANOMALY_H_
  38
  39 /* We do not support 0.1 or 0.4 silicon - sorry */
  40 #if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
  41 #error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
  42 #endif
  43
  44 /* Issues that are common to 0.5 and  0.3 silicon */
  45 #if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
  46 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
  47                             slot1 and store of a P register in slot 2 is not
  48                             supported */
  49 #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
  50                             updated at the same time. */
  51 #define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
  52                             memory locations */
  53 #define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
  54                             registers */
  55 #define ANOMALY_05000127 /* Signbits instruction not functional under certain
  56                             conditions */
  57 #define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
  58 #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
  59                             upper bits */
  60 #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
  61 #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
  62                             syncs */
  63 #define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
  64                             and higher devices */
  65 #define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
  66 #define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
  67 #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
  68                             functional */
  69 #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
  70                             shadow of a conditional branch */
  71 #define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
  72                             may cause bad instruction fetches */
  73 #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
  74                             external SPORT TX and RX clocks */
  75 #define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
  76 #define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
  77                             voltage regulator (VDDint) to increase */
  78 #define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
  79                             voltage regulator (VDDint) to decrease */
  80 #define ANOMALY_05000272 /* Certain data cache write through modes fail for
  81                             VDDint <=0.9V */
  82 #define ANOMALY_05000274 /* Data cache write back to external synchronous memory
  83                             may be lost */
  84 #define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
  85 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
  86                             registers are interrupted */
  87
  88 #endif /*  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
  89
  90 #if  (defined(CONFIG_BF_REV_0_5))
  91 #define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
  92                             mode with external clock */
  93 #define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
  94                             using IMDMA */
  95 #endif
  96
  97 #if  (defined(CONFIG_BF_REV_0_3))
  98 #define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
  99                             Mode with 0 Frame Syncs */
 100 #define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
 101 #define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
 102                             cache data writes */
 103 #define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
 104 #define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
 105 #define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
 106 #define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
 107                             accumulator saturation */
 108 #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
 109                             Purpose TX or RX modes */
 110 #define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
 111                             registers */
 112 #define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
 113                             External Frame Syncs */
 114 #define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
 115 #define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
 116                             (not a meaningful mode) */
 117 #define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
 118                             Placement in Memory */
 119 #define ANOMALY_05000189 /* False Protection Exception */
 120 #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
 121                             when polarity setting is changed */
 122 #define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
 123                             corruption */
 124 #define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
 125                             memory read */
 126 #define ANOMALY_05000199 /* DMA current address shows wrong value during carry
 127                             fix */
 128 #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
 129                             inactive channels in certain conditions */
 130 #define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
 131                             situation */
 132 #define ANOMALY_05000204 /* Incorrect data read with write-through cache and
 133                             allocate cache lines on reads only mode */
 134 #define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
 135                             stopping */
 136 #define ANOMALY_05000207 /* Recovery from "brown-out" condition */
 137 #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
 138                             instructions */
 139 #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
 140 #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
 141                             state */
 142 #define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
 143                             Non-Cached On-Chip L2 Memory */
 144 #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
 145 #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
 146                             data */
 147 #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
 148                             Differences in certain Conditions */
 149 #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
 150 #define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
 151                             multichannel mode */
 152 #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
 153                             hardware reset */
 154 #define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
 155                             Control causes failures */
 156 #define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
 157 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
 158                             (TDM) mode in certain conditions */
 159 #define ANOMALY_05000251 /* Exception not generated for MMR accesses in
 160                             reserved region */
 161 #define ANOMALY_05000253 /* Maximum external clock speed for Timers */
 162 #define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
 163                             of the ICPLB Data registers differ */
 164 #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
 165 #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
 166 #define ANOMALY_05000262 /* Stores to data cache may be lost */
 167 #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
 168                             exception */
 169 #define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
 170                             to last instruction in hardware loop */
 171 #define ANOMALY_05000276 /* Timing requirements change for External Frame
 172                             Sync PPI Modes with non-zero PPI_DELAY */
 173 #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
 174                             DMA system instability */
 175 #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
 176                             not restored */
 177 #define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
 178                             in a particular stage */
 179 #define ANOMALY_05000287 /* A read will receive incorrect data under certain
 180                             conditions */
 181 #define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
 182 #endif
 183
 184 #endif /* _MACH_ANOMALY_H_ */