include/asm-blackfin/mach-bf533/anomaly.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf533/anomaly.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *
  13  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2, or (at your option)
  18  * any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; see the file COPYING.
  27  * If not, write to the Free Software Foundation,
  28  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 /* This file shoule be up to date with:
  32  *  - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
  33  *  - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
  34  *  - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
  35  */
  36
  37 #ifndef _MACH_ANOMALY_H_
  38 #define _MACH_ANOMALY_H_
  39
  40 /* We do not support 0.1 or 0.2 silicon - sorry */
  41 #if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
  42 #error Kernel will not work on BF533 Version 0.1 or 0.2
  43 #endif
  44
  45 /* Issues that are common to 0.5, 0.4, and 0.3 silicon */
  46 #if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
  47 #define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
  48                             slot1 and store of a P register in slot 2 is not
  49                             supported */
  50 #define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
  51                             every corresponding match */
  52 #define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
  53                             Channel DMA stops */
  54 #define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
  55                             registers. */
  56 #define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
  57                             upper bits*/
  58 #define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
  59 #define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
  60                             syncs */
  61 #define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
  62                             functional */
  63 #define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
  64                             state */
  65 #define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
  66 #define ANOMALY_05000272 /* Certain data cache write through modes fail for
  67                             VDDint <=0.9V */
  68 #define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
  69 #define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
  70                             an edge is detected may clear interrupt */
  71 #define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
  72                             DMA system instability */
  73 #define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
  74                             not restored */
  75 #define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
  76                             control */
  77 #define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
  78                             killed in a particular stage*/
  79 #define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
  80                             registers are interrupted */
  81 #define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
  82
  83 #endif
  84
  85 /* These issues only occur on 0.3 or 0.4 BF533 */
  86 #if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
  87 #define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
  88                             updated at the same time. */
  89 #define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
  90                             Cache Fill can be corrupted after or during
  91                             Instruction DMA if certain core stalls exist */
  92 #define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
  93                             Purpose TX or RX modes */
  94 #define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
  95                             preceding memory read */
  96 #define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
  97                             inactive channels in certain conditions */
  98 #define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
  99                             situation */
 100 #define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
 101 #define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
 102 #define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
 103                             data*/
 104 #define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
 105                             Differences in certain Conditions */
 106 #define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
 107 #define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
 108                             hardware reset */
 109 #define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
 110                             IDLE around a Change of Control causes
 111                             unpredictable results */
 112 #define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
 113                             shadow of a conditional branch */
 114 #define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
 115                             errors */
 116 #define ANOMALY_05000253 /* Maximum external clock speed for Timers */
 117 #define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
 118                             interrupt not functional */
 119 #define ANOMALY_05000257 /* An interrupt or exception during short Hardware
 120                             loops may cause the instruction fetch unit to
 121                             malfunction */
 122 #define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
 123                             the ICPLB Data registers differ */
 124 #define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
 125 #define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
 126 #define ANOMALY_05000262 /* Stores to data cache may be lost */
 127 #define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
 128 #define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
 129                             instruction will cause an infinite stall in the
 130                             second to last instruction in a hardware loop */
 131 #define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
 132                             SPORT external receive and transmit clocks. */
 133 #define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
 134                             internal voltage regulator (VDDint) to increase. */
 135 #define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
 136                             internal voltage regulator (VDDint) to decrease */
 137 #endif
 138
 139 /* These issues are only on 0.4 silicon */
 140 #if (defined(CONFIG_BF_REV_0_4))
 141 #define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
 142 #define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
 143                             (TDM) */
 144 #endif
 145
 146 /* These issues are only on 0.3 silicon */
 147 #if defined(CONFIG_BF_REV_0_3)
 148 #define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
 149                             External Frame Syncs */
 150 #define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
 151                             Instruction or Data Fetches, or by Fetches at the
 152                             boundary of reserved memory space */
 153 #define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
 154                             when polarity setting is changed */
 155 #define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
 156                             corruption */
 157 #define ANOMALY_05000199 /* DMA current address shows wrong value during carry
 158                             fix */
 159 #define ANOMALY_05000201 /* Receive frame sync not ignored during active
 160                             frames in sport MCM */
 161 #define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
 162                             stopping */
 163 #if defined(CONFIG_BF533)
 164 #define ANOMALY_05000204 /* Incorrect data read with write-through cache and
 165                             allocate cache lines on reads only mode */
 166 #endif /* CONFIG_BF533 */
 167 #define ANOMALY_05000207 /* Recovery from "brown-out" condition */
 168 #define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
 169                             instructions */
 170 #define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
 171                             Sync Transmit Mode */
 172 #define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
 173 #endif
 174
 175 #endif /*  _MACH_ANOMALY_H_ */