2 * AVR32 System Registers
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef __ASM_AVR32_SYSREG_H__
11 #define __ASM_AVR32_SYSREG_H__
13 /* sysreg register offsets */
14 #define SYSREG_SR 0x0000
15 #define SYSREG_EVBA 0x0004
16 #define SYSREG_ACBA 0x0008
17 #define SYSREG_CPUCR 0x000c
18 #define SYSREG_ECR 0x0010
19 #define SYSREG_RSR_SUP 0x0014
20 #define SYSREG_RSR_INT0 0x0018
21 #define SYSREG_RSR_INT1 0x001c
22 #define SYSREG_RSR_INT2 0x0020
23 #define SYSREG_RSR_INT3 0x0024
24 #define SYSREG_RSR_EX 0x0028
25 #define SYSREG_RSR_NMI 0x002c
26 #define SYSREG_RSR_DBG 0x0030
27 #define SYSREG_RAR_SUP 0x0034
28 #define SYSREG_RAR_INT0 0x0038
29 #define SYSREG_RAR_INT1 0x003c
30 #define SYSREG_RAR_INT2 0x0040
31 #define SYSREG_RAR_INT3 0x0044
32 #define SYSREG_RAR_EX 0x0048
33 #define SYSREG_RAR_NMI 0x004c
34 #define SYSREG_RAR_DBG 0x0050
35 #define SYSREG_JECR 0x0054
36 #define SYSREG_JOSP 0x0058
37 #define SYSREG_JAVA_LV0 0x005c
38 #define SYSREG_JAVA_LV1 0x0060
39 #define SYSREG_JAVA_LV2 0x0064
40 #define SYSREG_JAVA_LV3 0x0068
41 #define SYSREG_JAVA_LV4 0x006c
42 #define SYSREG_JAVA_LV5 0x0070
43 #define SYSREG_JAVA_LV6 0x0074
44 #define SYSREG_JAVA_LV7 0x0078
45 #define SYSREG_JTBA 0x007c
46 #define SYSREG_JBCR 0x0080
47 #define SYSREG_CONFIG0 0x0100
48 #define SYSREG_CONFIG1 0x0104
49 #define SYSREG_COUNT 0x0108
50 #define SYSREG_COMPARE 0x010c
51 #define SYSREG_TLBEHI 0x0110
52 #define SYSREG_TLBELO 0x0114
53 #define SYSREG_PTBR 0x0118
54 #define SYSREG_TLBEAR 0x011c
55 #define SYSREG_MMUCR 0x0120
56 #define SYSREG_TLBARLO 0x0124
57 #define SYSREG_TLBARHI 0x0128
58 #define SYSREG_PCCNT 0x012c
59 #define SYSREG_PCNT0 0x0130
60 #define SYSREG_PCNT1 0x0134
61 #define SYSREG_PCCR 0x0138
62 #define SYSREG_BEAR 0x013c
65 #define SYSREG_SR_C_OFFSET 0
66 #define SYSREG_SR_C_SIZE 1
67 #define SYSREG_Z_OFFSET 1
68 #define SYSREG_Z_SIZE 1
69 #define SYSREG_SR_N_OFFSET 2
70 #define SYSREG_SR_N_SIZE 1
71 #define SYSREG_SR_V_OFFSET 3
72 #define SYSREG_SR_V_SIZE 1
73 #define SYSREG_Q_OFFSET 4
74 #define SYSREG_Q_SIZE 1
75 #define SYSREG_GM_OFFSET 16
76 #define SYSREG_GM_SIZE 1
77 #define SYSREG_I0M_OFFSET 17
78 #define SYSREG_I0M_SIZE 1
79 #define SYSREG_I1M_OFFSET 18
80 #define SYSREG_I1M_SIZE 1
81 #define SYSREG_I2M_OFFSET 19
82 #define SYSREG_I2M_SIZE 1
83 #define SYSREG_I3M_OFFSET 20
84 #define SYSREG_I3M_SIZE 1
85 #define SYSREG_EM_OFFSET 21
86 #define SYSREG_EM_SIZE 1
87 #define SYSREG_M0_OFFSET 22
88 #define SYSREG_M0_SIZE 1
89 #define SYSREG_M1_OFFSET 23
90 #define SYSREG_M1_SIZE 1
91 #define SYSREG_M2_OFFSET 24
92 #define SYSREG_M2_SIZE 1
93 #define SYSREG_SR_D_OFFSET 26
94 #define SYSREG_SR_D_SIZE 1
95 #define SYSREG_DM_OFFSET 27
96 #define SYSREG_DM_SIZE 1
97 #define SYSREG_SR_J_OFFSET 28
98 #define SYSREG_SR_J_SIZE 1
99 #define SYSREG_R_OFFSET 29
100 #define SYSREG_R_SIZE 1
101 #define SYSREG_H_OFFSET 30
102 #define SYSREG_H_SIZE 1
104 /* Bitfields in EVBA */
106 /* Bitfields in ACBA */
108 /* Bitfields in CPUCR */
109 #define SYSREG_BI_OFFSET 0
110 #define SYSREG_BI_SIZE 1
111 #define SYSREG_BE_OFFSET 1
112 #define SYSREG_BE_SIZE 1
113 #define SYSREG_FE_OFFSET 2
114 #define SYSREG_FE_SIZE 1
115 #define SYSREG_RE_OFFSET 3
116 #define SYSREG_RE_SIZE 1
117 #define SYSREG_IBE_OFFSET 4
118 #define SYSREG_IBE_SIZE 1
119 #define SYSREG_IEE_OFFSET 5
120 #define SYSREG_IEE_SIZE 1
122 /* Bitfields in ECR */
123 #define SYSREG_ECR_OFFSET 0
124 #define SYSREG_ECR_SIZE 32
126 /* Bitfields in RSR_SUP */
128 /* Bitfields in RSR_INT0 */
130 /* Bitfields in RSR_INT1 */
132 /* Bitfields in RSR_INT2 */
134 /* Bitfields in RSR_INT3 */
136 /* Bitfields in RSR_EX */
138 /* Bitfields in RSR_NMI */
140 /* Bitfields in RSR_DBG */
142 /* Bitfields in RAR_SUP */
144 /* Bitfields in RAR_INT0 */
146 /* Bitfields in RAR_INT1 */
148 /* Bitfields in RAR_INT2 */
150 /* Bitfields in RAR_INT3 */
152 /* Bitfields in RAR_EX */
154 /* Bitfields in RAR_NMI */
156 /* Bitfields in RAR_DBG */
158 /* Bitfields in JECR */
160 /* Bitfields in JOSP */
162 /* Bitfields in JAVA_LV0 */
164 /* Bitfields in JAVA_LV1 */
166 /* Bitfields in JAVA_LV2 */
168 /* Bitfields in JAVA_LV3 */
170 /* Bitfields in JAVA_LV4 */
172 /* Bitfields in JAVA_LV5 */
174 /* Bitfields in JAVA_LV6 */
176 /* Bitfields in JAVA_LV7 */
178 /* Bitfields in JTBA */
180 /* Bitfields in JBCR */
182 /* Bitfields in CONFIG0 */
183 #define SYSREG_CONFIG0_D_OFFSET 1
184 #define SYSREG_CONFIG0_D_SIZE 1
185 #define SYSREG_CONFIG0_S_OFFSET 2
186 #define SYSREG_CONFIG0_S_SIZE 1
187 #define SYSREG_O_OFFSET 3
188 #define SYSREG_O_SIZE 1
189 #define SYSREG_P_OFFSET 4
190 #define SYSREG_P_SIZE 1
191 #define SYSREG_CONFIG0_J_OFFSET 5
192 #define SYSREG_CONFIG0_J_SIZE 1
193 #define SYSREG_F_OFFSET 6
194 #define SYSREG_F_SIZE 1
195 #define SYSREG_MMUT_OFFSET 7
196 #define SYSREG_MMUT_SIZE 3
197 #define SYSREG_AR_OFFSET 10
198 #define SYSREG_AR_SIZE 3
199 #define SYSREG_AT_OFFSET 13
200 #define SYSREG_AT_SIZE 3
201 #define SYSREG_PROCESSORREVISION_OFFSET 16
202 #define SYSREG_PROCESSORREVISION_SIZE 8
203 #define SYSREG_PROCESSORID_OFFSET 24
204 #define SYSREG_PROCESSORID_SIZE 8
206 /* Bitfields in CONFIG1 */
207 #define SYSREG_DASS_OFFSET 0
208 #define SYSREG_DASS_SIZE 3
209 #define SYSREG_DLSZ_OFFSET 3
210 #define SYSREG_DLSZ_SIZE 3
211 #define SYSREG_DSET_OFFSET 6
212 #define SYSREG_DSET_SIZE 4
213 #define SYSREG_IASS_OFFSET 10
214 #define SYSREG_IASS_SIZE 2
215 #define SYSREG_ILSZ_OFFSET 13
216 #define SYSREG_ILSZ_SIZE 3
217 #define SYSREG_ISET_OFFSET 16
218 #define SYSREG_ISET_SIZE 4
219 #define SYSREG_DMMUSZ_OFFSET 20
220 #define SYSREG_DMMUSZ_SIZE 6
221 #define SYSREG_IMMUSZ_OFFSET 26
222 #define SYSREG_IMMUSZ_SIZE 6
224 /* Bitfields in COUNT */
226 /* Bitfields in COMPARE */
228 /* Bitfields in TLBEHI */
229 #define SYSREG_ASID_OFFSET 0
230 #define SYSREG_ASID_SIZE 8
231 #define SYSREG_TLBEHI_I_OFFSET 8
232 #define SYSREG_TLBEHI_I_SIZE 1
233 #define SYSREG_TLBEHI_V_OFFSET 9
234 #define SYSREG_TLBEHI_V_SIZE 1
235 #define SYSREG_VPN_OFFSET 10
236 #define SYSREG_VPN_SIZE 22
238 /* Bitfields in TLBELO */
239 #define SYSREG_W_OFFSET 0
240 #define SYSREG_W_SIZE 1
241 #define SYSREG_TLBELO_D_OFFSET 1
242 #define SYSREG_TLBELO_D_SIZE 1
243 #define SYSREG_SZ_OFFSET 2
244 #define SYSREG_SZ_SIZE 2
245 #define SYSREG_AP_OFFSET 4
246 #define SYSREG_AP_SIZE 3
247 #define SYSREG_B_OFFSET 7
248 #define SYSREG_B_SIZE 1
249 #define SYSREG_G_OFFSET 8
250 #define SYSREG_G_SIZE 1
251 #define SYSREG_TLBELO_C_OFFSET 9
252 #define SYSREG_TLBELO_C_SIZE 1
253 #define SYSREG_PFN_OFFSET 10
254 #define SYSREG_PFN_SIZE 22
256 /* Bitfields in PTBR */
258 /* Bitfields in TLBEAR */
260 /* Bitfields in MMUCR */
261 #define SYSREG_E_OFFSET 0
262 #define SYSREG_E_SIZE 1
263 #define SYSREG_M_OFFSET 1
264 #define SYSREG_M_SIZE 1
265 #define SYSREG_MMUCR_I_OFFSET 2
266 #define SYSREG_MMUCR_I_SIZE 1
267 #define SYSREG_MMUCR_N_OFFSET 3
268 #define SYSREG_MMUCR_N_SIZE 1
269 #define SYSREG_MMUCR_S_OFFSET 4
270 #define SYSREG_MMUCR_S_SIZE 1
271 #define SYSREG_DLA_OFFSET 8
272 #define SYSREG_DLA_SIZE 6
273 #define SYSREG_DRP_OFFSET 14
274 #define SYSREG_DRP_SIZE 6
275 #define SYSREG_ILA_OFFSET 20
276 #define SYSREG_ILA_SIZE 6
277 #define SYSREG_IRP_OFFSET 26
278 #define SYSREG_IRP_SIZE 6
280 /* Bitfields in TLBARLO */
282 /* Bitfields in TLBARHI */
284 /* Bitfields in PCCNT */
286 /* Bitfields in PCNT0 */
288 /* Bitfields in PCNT1 */
290 /* Bitfields in PCCR */
292 /* Bitfields in BEAR */
294 /* Constants for ECR */
295 #define ECR_UNRECOVERABLE 0
296 #define ECR_TLB_MULTIPLE 1
297 #define ECR_BUS_ERROR_WRITE 2
298 #define ECR_BUS_ERROR_READ 3
300 #define ECR_ADDR_ALIGN_X 5
301 #define ECR_PROTECTION_X 6
303 #define ECR_ILLEGAL_OPCODE 8
304 #define ECR_UNIMPL_INSTRUCTION 9
305 #define ECR_PRIVILEGE_VIOLATION 10
307 #define ECR_COPROC_ABSENT 12
308 #define ECR_ADDR_ALIGN_R 13
309 #define ECR_ADDR_ALIGN_W 14
310 #define ECR_PROTECTION_R 15
311 #define ECR_PROTECTION_W 16
312 #define ECR_DTLB_MODIFIED 17
313 #define ECR_TLB_MISS_X 20
314 #define ECR_TLB_MISS_R 24
315 #define ECR_TLB_MISS_W 28
317 /* Bit manipulation macros */
318 #define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET)
319 #define SYSREG_BF(name,value) (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) << SYSREG_##name##_OFFSET)
320 #define SYSREG_BFEXT(name,value) (((value) >> SYSREG_##name##_OFFSET) & ((1 << SYSREG_##name##_SIZE) - 1))
321 #define SYSREG_BFINS(name,value,old) (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) << SYSREG_##name##_OFFSET)) | SYSREG_BF(name,value))
324 extern unsigned long __builtin_mfsr(unsigned long reg
);
325 extern void __builtin_mtsr(unsigned long reg
, unsigned long value
);
328 /* Register access macros */
329 #define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg)
330 #define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value)
332 #endif /* __ASM_AVR32_SYSREG_H__ */
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