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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / tgafb.c
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 * Copyright (C) 2006, 2007 Maciej W. Rozycki
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive for
12 * more details.
13 */
14
15 #include <linux/bitrev.h>
16 #include <linux/compiler.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/errno.h>
20 #include <linux/fb.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/selection.h>
28 #include <linux/string.h>
29 #include <linux/tc.h>
30
31 #include <asm/io.h>
32
33 #include <video/tgafb.h>
34
35 #ifdef CONFIG_PCI
36 #define TGA_BUS_PCI(dev) (dev->bus == &pci_bus_type)
37 #else
38 #define TGA_BUS_PCI(dev) 0
39 #endif
40
41 #ifdef CONFIG_TC
42 #define TGA_BUS_TC(dev) (dev->bus == &tc_bus_type)
43 #else
44 #define TGA_BUS_TC(dev) 0
45 #endif
46
47 /*
48 * Local functions.
49 */
50
51 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
52 static int tgafb_set_par(struct fb_info *);
53 static void tgafb_set_pll(struct tga_par *, int);
54 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
55 unsigned, struct fb_info *);
56 static int tgafb_blank(int, struct fb_info *);
57 static void tgafb_init_fix(struct fb_info *);
58
59 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
60 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
61 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
62 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
63
64 static int tgafb_register(struct device *dev);
65 static void tgafb_unregister(struct device *dev);
66
67 static const char *mode_option;
68 static const char *mode_option_pci = "640x480@60";
69 static const char *mode_option_tc = "1280x1024@72";
70
71
72 static struct pci_driver tgafb_pci_driver;
73 static struct tc_driver tgafb_tc_driver;
74
75 /*
76 * Frame buffer operations
77 */
78
79 static struct fb_ops tgafb_ops = {
80 .owner = THIS_MODULE,
81 .fb_check_var = tgafb_check_var,
82 .fb_set_par = tgafb_set_par,
83 .fb_setcolreg = tgafb_setcolreg,
84 .fb_blank = tgafb_blank,
85 .fb_pan_display = tgafb_pan_display,
86 .fb_fillrect = tgafb_fillrect,
87 .fb_copyarea = tgafb_copyarea,
88 .fb_imageblit = tgafb_imageblit,
89 };
90
91
92 #ifdef CONFIG_PCI
93 /*
94 * PCI registration operations
95 */
96 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
97 static void tgafb_pci_unregister(struct pci_dev *);
98
99 static struct pci_device_id const tgafb_pci_table[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA) },
101 { }
102 };
103 MODULE_DEVICE_TABLE(pci, tgafb_pci_table);
104
105 static struct pci_driver tgafb_pci_driver = {
106 .name = "tgafb",
107 .id_table = tgafb_pci_table,
108 .probe = tgafb_pci_register,
109 .remove = tgafb_pci_unregister,
110 };
111
112 static int tgafb_pci_register(struct pci_dev *pdev,
113 const struct pci_device_id *ent)
114 {
115 return tgafb_register(&pdev->dev);
116 }
117
118 static void tgafb_pci_unregister(struct pci_dev *pdev)
119 {
120 tgafb_unregister(&pdev->dev);
121 }
122 #endif /* CONFIG_PCI */
123
124 #ifdef CONFIG_TC
125 /*
126 * TC registration operations
127 */
128 static int tgafb_tc_register(struct device *);
129 static int tgafb_tc_unregister(struct device *);
130
131 static struct tc_device_id const tgafb_tc_table[] = {
132 { "DEC ", "PMAGD-AA" },
133 { "DEC ", "PMAGD " },
134 { }
135 };
136 MODULE_DEVICE_TABLE(tc, tgafb_tc_table);
137
138 static struct tc_driver tgafb_tc_driver = {
139 .id_table = tgafb_tc_table,
140 .driver = {
141 .name = "tgafb",
142 .bus = &tc_bus_type,
143 .probe = tgafb_tc_register,
144 .remove = tgafb_tc_unregister,
145 },
146 };
147
148 static int tgafb_tc_register(struct device *dev)
149 {
150 int status = tgafb_register(dev);
151 if (!status)
152 get_device(dev);
153 return status;
154 }
155
156 static int tgafb_tc_unregister(struct device *dev)
157 {
158 put_device(dev);
159 tgafb_unregister(dev);
160 return 0;
161 }
162 #endif /* CONFIG_TC */
163
164
165 /**
166 * tgafb_check_var - Optional function. Validates a var passed in.
167 * @var: frame buffer variable screen structure
168 * @info: frame buffer structure that represents a single frame buffer
169 */
170 static int
171 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
172 {
173 struct tga_par *par = (struct tga_par *)info->par;
174
175 if (par->tga_type == TGA_TYPE_8PLANE) {
176 if (var->bits_per_pixel != 8)
177 return -EINVAL;
178 } else {
179 if (var->bits_per_pixel != 32)
180 return -EINVAL;
181 }
182 var->red.length = var->green.length = var->blue.length = 8;
183 if (var->bits_per_pixel == 32) {
184 var->red.offset = 16;
185 var->green.offset = 8;
186 var->blue.offset = 0;
187 }
188
189 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
190 return -EINVAL;
191 if (var->xres * var->yres * (var->bits_per_pixel >> 3) > info->fix.smem_len)
192 return -EINVAL;
193 if (var->nonstd)
194 return -EINVAL;
195 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
196 return -EINVAL;
197 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
198 return -EINVAL;
199
200 /* Some of the acceleration routines assume the line width is
201 a multiple of 64 bytes. */
202 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
203 return -EINVAL;
204
205 return 0;
206 }
207
208 /**
209 * tgafb_set_par - Optional function. Alters the hardware state.
210 * @info: frame buffer structure that represents a single frame buffer
211 */
212 static int
213 tgafb_set_par(struct fb_info *info)
214 {
215 static unsigned int const deep_presets[4] = {
216 0x00004000,
217 0x0000440d,
218 0xffffffff,
219 0x0000441d
220 };
221 static unsigned int const rasterop_presets[4] = {
222 0x00000003,
223 0x00000303,
224 0xffffffff,
225 0x00000303
226 };
227 static unsigned int const mode_presets[4] = {
228 0x00000000,
229 0x00000300,
230 0xffffffff,
231 0x00000300
232 };
233 static unsigned int const base_addr_presets[4] = {
234 0x00000000,
235 0x00000001,
236 0xffffffff,
237 0x00000001
238 };
239
240 struct tga_par *par = (struct tga_par *) info->par;
241 int tga_bus_pci = TGA_BUS_PCI(par->dev);
242 int tga_bus_tc = TGA_BUS_TC(par->dev);
243 u32 htimings, vtimings, pll_freq;
244 u8 tga_type;
245 int i;
246
247 /* Encode video timings. */
248 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
249 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
250 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
251 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
252 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
253 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
254 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
255 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
256 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
257
258 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
259 htimings |= TGA_HORIZ_POLARITY;
260 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
261 vtimings |= TGA_VERT_POLARITY;
262
263 par->htimings = htimings;
264 par->vtimings = vtimings;
265
266 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
267
268 /* Store other useful values in par. */
269 par->xres = info->var.xres;
270 par->yres = info->var.yres;
271 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
272 par->bits_per_pixel = info->var.bits_per_pixel;
273 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
274
275 tga_type = par->tga_type;
276
277 /* First, disable video. */
278 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
279
280 /* Write the DEEP register. */
281 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
282 continue;
283 mb();
284 TGA_WRITE_REG(par, deep_presets[tga_type] |
285 (par->sync_on_green ? 0x0 : 0x00010000),
286 TGA_DEEP_REG);
287 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
288 continue;
289 mb();
290
291 /* Write some more registers. */
292 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
293 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
294 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
295
296 /* Calculate & write the PLL. */
297 tgafb_set_pll(par, pll_freq);
298
299 /* Write some more registers. */
300 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
301 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
302
303 /* Init video timing regs. */
304 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
305 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
306
307 /* Initialise RAMDAC. */
308 if (tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
309
310 /* Init BT485 RAMDAC registers. */
311 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
312 BT485_CMD_0);
313 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
314 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
315 BT485_WRITE(par, 0x40, BT485_CMD_1);
316 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
317 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
318
319 /* Fill palette registers. */
320 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
321 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
322
323 for (i = 0; i < 256 * 3; i += 4) {
324 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
325 TGA_RAMDAC_REG);
326 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
327 TGA_RAMDAC_REG);
328 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
329 TGA_RAMDAC_REG);
330 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
331 TGA_RAMDAC_REG);
332 }
333
334 } else if (tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
335
336 /* Init BT459 RAMDAC registers. */
337 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_0, 0x40);
338 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_1, 0x00);
339 BT459_WRITE(par, BT459_REG_ACC, BT459_CMD_REG_2,
340 (par->sync_on_green ? 0xc0 : 0x40));
341
342 BT459_WRITE(par, BT459_REG_ACC, BT459_CUR_CMD_REG, 0x00);
343
344 /* Fill the palette. */
345 BT459_LOAD_ADDR(par, 0x0000);
346 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
347
348 for (i = 0; i < 256 * 3; i += 4) {
349 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
350 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
351 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
352 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
353 }
354
355 } else { /* 24-plane or 24plusZ */
356
357 /* Init BT463 RAMDAC registers. */
358 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
359 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
360 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
361 (par->sync_on_green ? 0xc0 : 0x40));
362
363 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
364 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
365 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
366 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
367
368 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
369 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
370 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
371 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
372
373 /* Fill the palette. */
374 BT463_LOAD_ADDR(par, 0x0000);
375 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
376
377 #ifdef CONFIG_HW_CONSOLE
378 for (i = 0; i < 16; i++) {
379 int j = color_table[i];
380
381 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
382 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
383 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
384 }
385 for (i = 0; i < 512 * 3; i += 4) {
386 #else
387 for (i = 0; i < 528 * 3; i += 4) {
388 #endif
389 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
390 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
391 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
392 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
393 }
394
395 /* Fill window type table after start of vertical retrace. */
396 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
397 continue;
398 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
399 mb();
400 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
401 continue;
402 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
403
404 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
405 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
406
407 for (i = 0; i < 16; i++) {
408 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
409 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
410 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
411 }
412
413 }
414
415 /* Finally, enable video scan (and pray for the monitor... :-) */
416 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
417
418 return 0;
419 }
420
421 #define DIFFCHECK(X) \
422 do { \
423 if (m <= 0x3f) { \
424 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
425 if (delta < 0) \
426 delta = -delta; \
427 if (delta < min_diff) \
428 min_diff = delta, vm = m, va = a, vr = r; \
429 } \
430 } while (0)
431
432 static void
433 tgafb_set_pll(struct tga_par *par, int f)
434 {
435 int n, shift, base, min_diff, target;
436 int r,a,m,vm = 34, va = 1, vr = 30;
437
438 for (r = 0 ; r < 12 ; r++)
439 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
440
441 if (f > TGA_PLL_MAX_FREQ)
442 f = TGA_PLL_MAX_FREQ;
443
444 if (f >= TGA_PLL_MAX_FREQ / 2)
445 shift = 0;
446 else if (f >= TGA_PLL_MAX_FREQ / 4)
447 shift = 1;
448 else
449 shift = 2;
450
451 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
452 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
453
454 for (r = 0 ; r < 10 ; r++)
455 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
456
457 if (f <= 120000) {
458 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
459 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
460 }
461 else if (f <= 200000) {
462 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
463 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
464 }
465 else {
466 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
467 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
468 }
469
470 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
471 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
472 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
473 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
474 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
475 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
476
477 target = (f << shift) / TGA_PLL_BASE_FREQ;
478 min_diff = TGA_PLL_MAX_FREQ;
479
480 r = 7 / target;
481 if (!r) r = 1;
482
483 base = target * r;
484 while (base < 449) {
485 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
486 m = ((n + 3) / 7) - 1;
487 a = 0;
488 DIFFCHECK((m + 1) * 7);
489 m++;
490 DIFFCHECK((m + 1) * 7);
491 m = (n / 6) - 1;
492 if ((a = n % 6))
493 DIFFCHECK(n);
494 }
495 r++;
496 base += target;
497 }
498
499 vr--;
500
501 for (r = 0; r < 8; r++)
502 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
503 for (r = 0; r < 8 ; r++)
504 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
505 for (r = 0; r < 7 ; r++)
506 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
507 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
508 }
509
510
511 /**
512 * tgafb_setcolreg - Optional function. Sets a color register.
513 * @regno: boolean, 0 copy local, 1 get_user() function
514 * @red: frame buffer colormap structure
515 * @green: The green value which can be up to 16 bits wide
516 * @blue: The blue value which can be up to 16 bits wide.
517 * @transp: If supported the alpha value which can be up to 16 bits wide.
518 * @info: frame buffer info structure
519 */
520 static int
521 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
522 unsigned transp, struct fb_info *info)
523 {
524 struct tga_par *par = (struct tga_par *) info->par;
525 int tga_bus_pci = TGA_BUS_PCI(par->dev);
526 int tga_bus_tc = TGA_BUS_TC(par->dev);
527
528 if (regno > 255)
529 return 1;
530 red >>= 8;
531 green >>= 8;
532 blue >>= 8;
533
534 if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_pci) {
535 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
536 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
537 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
538 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
539 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
540 } else if (par->tga_type == TGA_TYPE_8PLANE && tga_bus_tc) {
541 BT459_LOAD_ADDR(par, regno);
542 TGA_WRITE_REG(par, BT459_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
543 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
544 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
545 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
546 } else {
547 if (regno < 16) {
548 u32 value = (regno << 16) | (regno << 8) | regno;
549 ((u32 *)info->pseudo_palette)[regno] = value;
550 }
551 BT463_LOAD_ADDR(par, regno);
552 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
553 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
554 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
555 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
556 }
557
558 return 0;
559 }
560
561
562 /**
563 * tgafb_blank - Optional function. Blanks the display.
564 * @blank_mode: the blank mode we want.
565 * @info: frame buffer structure that represents a single frame buffer
566 */
567 static int
568 tgafb_blank(int blank, struct fb_info *info)
569 {
570 struct tga_par *par = (struct tga_par *) info->par;
571 u32 vhcr, vvcr, vvvr;
572 unsigned long flags;
573
574 local_irq_save(flags);
575
576 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
577 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
578 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
579 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
580
581 switch (blank) {
582 case FB_BLANK_UNBLANK: /* Unblanking */
583 if (par->vesa_blanked) {
584 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
585 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
586 par->vesa_blanked = 0;
587 }
588 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
589 break;
590
591 case FB_BLANK_NORMAL: /* Normal blanking */
592 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
593 TGA_VALID_REG);
594 break;
595
596 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
597 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
598 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
599 par->vesa_blanked = 1;
600 break;
601
602 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
603 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
604 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
605 par->vesa_blanked = 1;
606 break;
607
608 case FB_BLANK_POWERDOWN: /* Poweroff */
609 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
610 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
611 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
612 par->vesa_blanked = 1;
613 break;
614 }
615
616 local_irq_restore(flags);
617 return 0;
618 }
619
620
621 /*
622 * Acceleration.
623 */
624
625 static void
626 tgafb_mono_imageblit(struct fb_info *info, const struct fb_image *image)
627 {
628 struct tga_par *par = (struct tga_par *) info->par;
629 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
630 unsigned long rincr, line_length, shift, pos, is8bpp;
631 unsigned long i, j;
632 const unsigned char *data;
633 void __iomem *regs_base;
634 void __iomem *fb_base;
635
636 is8bpp = info->var.bits_per_pixel == 8;
637
638 dx = image->dx;
639 dy = image->dy;
640 width = image->width;
641 height = image->height;
642 vxres = info->var.xres_virtual;
643 vyres = info->var.yres_virtual;
644 line_length = info->fix.line_length;
645 rincr = (width + 7) / 8;
646
647 /* A shift below cannot cope with. */
648 if (unlikely(width == 0))
649 return;
650 /* Crop the image to the screen. */
651 if (dx > vxres || dy > vyres)
652 return;
653 if (dx + width > vxres)
654 width = vxres - dx;
655 if (dy + height > vyres)
656 height = vyres - dy;
657
658 regs_base = par->tga_regs_base;
659 fb_base = par->tga_fb_base;
660
661 /* Expand the color values to fill 32-bits. */
662 /* ??? Would be nice to notice colour changes elsewhere, so
663 that we can do this only when necessary. */
664 fgcolor = image->fg_color;
665 bgcolor = image->bg_color;
666 if (is8bpp) {
667 fgcolor |= fgcolor << 8;
668 fgcolor |= fgcolor << 16;
669 bgcolor |= bgcolor << 8;
670 bgcolor |= bgcolor << 16;
671 } else {
672 if (fgcolor < 16)
673 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
674 if (bgcolor < 16)
675 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
676 }
677 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
678 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
679
680 /* Acquire proper alignment; set up the PIXELMASK register
681 so that we only write the proper character cell. */
682 pos = dy * line_length;
683 if (is8bpp) {
684 pos += dx;
685 shift = pos & 3;
686 pos &= -4;
687 } else {
688 pos += dx * 4;
689 shift = (pos & 7) >> 2;
690 pos &= -8;
691 }
692
693 data = (const unsigned char *) image->data;
694
695 /* Enable opaque stipple mode. */
696 __raw_writel((is8bpp
697 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
698 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
699 regs_base + TGA_MODE_REG);
700
701 if (width + shift <= 32) {
702 unsigned long bwidth;
703
704 /* Handle common case of imaging a single character, in
705 a font less than or 32 pixels wide. */
706
707 /* Avoid a shift by 32; width > 0 implied. */
708 pixelmask = (2ul << (width - 1)) - 1;
709 pixelmask <<= shift;
710 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
711 wmb();
712
713 bwidth = (width + 7) / 8;
714
715 for (i = 0; i < height; ++i) {
716 u32 mask = 0;
717
718 /* The image data is bit big endian; we need
719 little endian. */
720 for (j = 0; j < bwidth; ++j)
721 mask |= bitrev8(data[j]) << (j * 8);
722
723 __raw_writel(mask << shift, fb_base + pos);
724
725 pos += line_length;
726 data += rincr;
727 }
728 wmb();
729 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
730 } else if (shift == 0) {
731 unsigned long pos0 = pos;
732 const unsigned char *data0 = data;
733 unsigned long bincr = (is8bpp ? 8 : 8*4);
734 unsigned long bwidth;
735
736 /* Handle another common case in which accel_putcs
737 generates a large bitmap, which happens to be aligned.
738 Allow the tail to be misaligned. This case is
739 interesting because we've not got to hold partial
740 bytes across the words being written. */
741
742 wmb();
743
744 bwidth = (width / 8) & -4;
745 for (i = 0; i < height; ++i) {
746 for (j = 0; j < bwidth; j += 4) {
747 u32 mask = 0;
748 mask |= bitrev8(data[j+0]) << (0 * 8);
749 mask |= bitrev8(data[j+1]) << (1 * 8);
750 mask |= bitrev8(data[j+2]) << (2 * 8);
751 mask |= bitrev8(data[j+3]) << (3 * 8);
752 __raw_writel(mask, fb_base + pos + j*bincr);
753 }
754 pos += line_length;
755 data += rincr;
756 }
757 wmb();
758
759 pixelmask = (1ul << (width & 31)) - 1;
760 if (pixelmask) {
761 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
762 wmb();
763
764 pos = pos0 + bwidth*bincr;
765 data = data0 + bwidth;
766 bwidth = ((width & 31) + 7) / 8;
767
768 for (i = 0; i < height; ++i) {
769 u32 mask = 0;
770 for (j = 0; j < bwidth; ++j)
771 mask |= bitrev8(data[j]) << (j * 8);
772 __raw_writel(mask, fb_base + pos);
773 pos += line_length;
774 data += rincr;
775 }
776 wmb();
777 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
778 }
779 } else {
780 unsigned long pos0 = pos;
781 const unsigned char *data0 = data;
782 unsigned long bincr = (is8bpp ? 8 : 8*4);
783 unsigned long bwidth;
784
785 /* Finally, handle the generic case of misaligned start.
786 Here we split the write into 16-bit spans. This allows
787 us to use only one pixel mask, instead of four as would
788 be required by writing 24-bit spans. */
789
790 pixelmask = 0xffff << shift;
791 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
792 wmb();
793
794 bwidth = (width / 8) & -2;
795 for (i = 0; i < height; ++i) {
796 for (j = 0; j < bwidth; j += 2) {
797 u32 mask = 0;
798 mask |= bitrev8(data[j+0]) << (0 * 8);
799 mask |= bitrev8(data[j+1]) << (1 * 8);
800 mask <<= shift;
801 __raw_writel(mask, fb_base + pos + j*bincr);
802 }
803 pos += line_length;
804 data += rincr;
805 }
806 wmb();
807
808 pixelmask = ((1ul << (width & 15)) - 1) << shift;
809 if (pixelmask) {
810 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
811 wmb();
812
813 pos = pos0 + bwidth*bincr;
814 data = data0 + bwidth;
815 bwidth = (width & 15) > 8;
816
817 for (i = 0; i < height; ++i) {
818 u32 mask = bitrev8(data[0]);
819 if (bwidth)
820 mask |= bitrev8(data[1]) << 8;
821 mask <<= shift;
822 __raw_writel(mask, fb_base + pos);
823 pos += line_length;
824 data += rincr;
825 }
826 wmb();
827 }
828 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
829 }
830
831 /* Disable opaque stipple mode. */
832 __raw_writel((is8bpp
833 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
834 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
835 regs_base + TGA_MODE_REG);
836 }
837
838 static void
839 tgafb_clut_imageblit(struct fb_info *info, const struct fb_image *image)
840 {
841 struct tga_par *par = (struct tga_par *) info->par;
842 u32 color, dx, dy, width, height, vxres, vyres;
843 u32 *palette = ((u32 *)info->pseudo_palette);
844 unsigned long pos, line_length, i, j;
845 const unsigned char *data;
846 void __iomem *regs_base, *fb_base;
847
848 dx = image->dx;
849 dy = image->dy;
850 width = image->width;
851 height = image->height;
852 vxres = info->var.xres_virtual;
853 vyres = info->var.yres_virtual;
854 line_length = info->fix.line_length;
855
856 /* Crop the image to the screen. */
857 if (dx > vxres || dy > vyres)
858 return;
859 if (dx + width > vxres)
860 width = vxres - dx;
861 if (dy + height > vyres)
862 height = vyres - dy;
863
864 regs_base = par->tga_regs_base;
865 fb_base = par->tga_fb_base;
866
867 pos = dy * line_length + (dx * 4);
868 data = image->data;
869
870 /* Now copy the image, color_expanding via the palette. */
871 for (i = 0; i < height; i++) {
872 for (j = 0; j < width; j++) {
873 color = palette[*data++];
874 __raw_writel(color, fb_base + pos + j*4);
875 }
876 pos += line_length;
877 }
878 }
879
880 /**
881 * tgafb_imageblit - REQUIRED function. Can use generic routines if
882 * non acclerated hardware and packed pixel based.
883 * Copies a image from system memory to the screen.
884 *
885 * @info: frame buffer structure that represents a single frame buffer
886 * @image: structure defining the image.
887 */
888 static void
889 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
890 {
891 unsigned int is8bpp = info->var.bits_per_pixel == 8;
892
893 /* If a mono image, regardless of FB depth, go do it. */
894 if (image->depth == 1) {
895 tgafb_mono_imageblit(info, image);
896 return;
897 }
898
899 /* For copies that aren't pixel expansion, there's little we
900 can do better than the generic code. */
901 /* ??? There is a DMA write mode; I wonder if that could be
902 made to pull the data from the image buffer... */
903 if (image->depth == info->var.bits_per_pixel) {
904 cfb_imageblit(info, image);
905 return;
906 }
907
908 /* If 24-plane FB and the image is 8-plane with CLUT, we can do it. */
909 if (!is8bpp && image->depth == 8) {
910 tgafb_clut_imageblit(info, image);
911 return;
912 }
913
914 /* Silently return... */
915 }
916
917 /**
918 * tgafb_fillrect - REQUIRED function. Can use generic routines if
919 * non acclerated hardware and packed pixel based.
920 * Draws a rectangle on the screen.
921 *
922 * @info: frame buffer structure that represents a single frame buffer
923 * @rect: structure defining the rectagle and operation.
924 */
925 static void
926 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
927 {
928 struct tga_par *par = (struct tga_par *) info->par;
929 int is8bpp = info->var.bits_per_pixel == 8;
930 u32 dx, dy, width, height, vxres, vyres, color;
931 unsigned long pos, align, line_length, i, j;
932 void __iomem *regs_base;
933 void __iomem *fb_base;
934
935 dx = rect->dx;
936 dy = rect->dy;
937 width = rect->width;
938 height = rect->height;
939 vxres = info->var.xres_virtual;
940 vyres = info->var.yres_virtual;
941 line_length = info->fix.line_length;
942 regs_base = par->tga_regs_base;
943 fb_base = par->tga_fb_base;
944
945 /* Crop the rectangle to the screen. */
946 if (dx > vxres || dy > vyres || !width || !height)
947 return;
948 if (dx + width > vxres)
949 width = vxres - dx;
950 if (dy + height > vyres)
951 height = vyres - dy;
952
953 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
954
955 /* ??? We could implement ROP_XOR with opaque fill mode
956 and a RasterOp setting of GXxor, but as far as I can
957 tell, this mode is not actually used in the kernel.
958 Thus I am ignoring it for now. */
959 if (rect->rop != ROP_COPY) {
960 cfb_fillrect(info, rect);
961 return;
962 }
963
964 /* Expand the color value to fill 8 pixels. */
965 color = rect->color;
966 if (is8bpp) {
967 color |= color << 8;
968 color |= color << 16;
969 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
970 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
971 } else {
972 if (color < 16)
973 color = ((u32 *)info->pseudo_palette)[color];
974 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
975 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
976 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
977 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
978 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
979 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
980 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
981 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
982 }
983
984 /* The DATA register holds the fill mask for block fill mode.
985 Since we're not stippling, this is all ones. */
986 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
987
988 /* Enable block fill mode. */
989 __raw_writel((is8bpp
990 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
991 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
992 regs_base + TGA_MODE_REG);
993 wmb();
994
995 /* We can fill 2k pixels per operation. Notice blocks that fit
996 the width of the screen so that we can take advantage of this
997 and fill more than one line per write. */
998 if (width == line_length)
999 width *= height, height = 1;
1000
1001 /* The write into the frame buffer must be aligned to 4 bytes,
1002 but we are allowed to encode the offset within the word in
1003 the data word written. */
1004 align = (pos & 3) << 16;
1005 pos &= -4;
1006
1007 if (width <= 2048) {
1008 u32 data;
1009
1010 data = (width - 1) | align;
1011
1012 for (i = 0; i < height; ++i) {
1013 __raw_writel(data, fb_base + pos);
1014 pos += line_length;
1015 }
1016 } else {
1017 unsigned long Bpp = (is8bpp ? 1 : 4);
1018 unsigned long nwidth = width & -2048;
1019 u32 fdata, ldata;
1020
1021 fdata = (2048 - 1) | align;
1022 ldata = ((width & 2047) - 1) | align;
1023
1024 for (i = 0; i < height; ++i) {
1025 for (j = 0; j < nwidth; j += 2048)
1026 __raw_writel(fdata, fb_base + pos + j*Bpp);
1027 if (j < width)
1028 __raw_writel(ldata, fb_base + pos + j*Bpp);
1029 pos += line_length;
1030 }
1031 }
1032 wmb();
1033
1034 /* Disable block fill mode. */
1035 __raw_writel((is8bpp
1036 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
1037 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
1038 regs_base + TGA_MODE_REG);
1039 }
1040
1041 /**
1042 * tgafb_copyarea - REQUIRED function. Can use generic routines if
1043 * non acclerated hardware and packed pixel based.
1044 * Copies on area of the screen to another area.
1045 *
1046 * @info: frame buffer structure that represents a single frame buffer
1047 * @area: structure defining the source and destination.
1048 */
1049
1050 /* Handle the special case of copying entire lines, e.g. during scrolling.
1051 We can avoid a lot of needless computation in this case. In the 8bpp
1052 case we need to use the COPY64 registers instead of mask writes into
1053 the frame buffer to achieve maximum performance. */
1054
1055 static inline void
1056 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
1057 u32 height, u32 width)
1058 {
1059 struct tga_par *par = (struct tga_par *) info->par;
1060 void __iomem *tga_regs = par->tga_regs_base;
1061 unsigned long dpos, spos, i, n64;
1062
1063 /* Set up the MODE and PIXELSHIFT registers. */
1064 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1065 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1066 wmb();
1067
1068 n64 = (height * width) / 64;
1069
1070 if (sy < dy) {
1071 spos = (sy + height) * width;
1072 dpos = (dy + height) * width;
1073
1074 for (i = 0; i < n64; ++i) {
1075 spos -= 64;
1076 dpos -= 64;
1077 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1078 wmb();
1079 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1080 wmb();
1081 }
1082 } else {
1083 spos = sy * width;
1084 dpos = dy * width;
1085
1086 for (i = 0; i < n64; ++i) {
1087 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
1088 wmb();
1089 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
1090 wmb();
1091 spos += 64;
1092 dpos += 64;
1093 }
1094 }
1095
1096 /* Reset the MODE register to normal. */
1097 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1098 }
1099
1100 static inline void
1101 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
1102 u32 height, u32 width)
1103 {
1104 struct tga_par *par = (struct tga_par *) info->par;
1105 void __iomem *tga_regs = par->tga_regs_base;
1106 void __iomem *tga_fb = par->tga_fb_base;
1107 void __iomem *src;
1108 void __iomem *dst;
1109 unsigned long i, n16;
1110
1111 /* Set up the MODE and PIXELSHIFT registers. */
1112 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1113 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1114 wmb();
1115
1116 n16 = (height * width) / 16;
1117
1118 if (sy < dy) {
1119 src = tga_fb + (sy + height) * width * 4;
1120 dst = tga_fb + (dy + height) * width * 4;
1121
1122 for (i = 0; i < n16; ++i) {
1123 src -= 64;
1124 dst -= 64;
1125 __raw_writel(0xffff, src);
1126 wmb();
1127 __raw_writel(0xffff, dst);
1128 wmb();
1129 }
1130 } else {
1131 src = tga_fb + sy * width * 4;
1132 dst = tga_fb + dy * width * 4;
1133
1134 for (i = 0; i < n16; ++i) {
1135 __raw_writel(0xffff, src);
1136 wmb();
1137 __raw_writel(0xffff, dst);
1138 wmb();
1139 src += 64;
1140 dst += 64;
1141 }
1142 }
1143
1144 /* Reset the MODE register to normal. */
1145 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1146 }
1147
1148 /* The (almost) general case of backward copy in 8bpp mode. */
1149 static inline void
1150 copyarea_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1151 u32 height, u32 width, u32 line_length,
1152 const struct fb_copyarea *area)
1153 {
1154 struct tga_par *par = (struct tga_par *) info->par;
1155 unsigned i, yincr;
1156 int depos, sepos, backward, last_step, step;
1157 u32 mask_last;
1158 unsigned n32;
1159 void __iomem *tga_regs;
1160 void __iomem *tga_fb;
1161
1162 /* Do acceleration only if we are aligned on 8 pixels */
1163 if ((dx | sx | width) & 7) {
1164 cfb_copyarea(info, area);
1165 return;
1166 }
1167
1168 yincr = line_length;
1169 if (dy > sy) {
1170 dy += height - 1;
1171 sy += height - 1;
1172 yincr = -yincr;
1173 }
1174 backward = dy == sy && dx > sx && dx < sx + width;
1175
1176 /* Compute the offsets and alignments in the frame buffer.
1177 More than anything else, these control how we do copies. */
1178 depos = dy * line_length + dx;
1179 sepos = sy * line_length + sx;
1180 if (backward)
1181 depos += width, sepos += width;
1182
1183 /* Next copy full words at a time. */
1184 n32 = width / 32;
1185 last_step = width % 32;
1186
1187 /* Finally copy the unaligned head of the span. */
1188 mask_last = (1ul << last_step) - 1;
1189
1190 if (!backward) {
1191 step = 32;
1192 last_step = 32;
1193 } else {
1194 step = -32;
1195 last_step = -last_step;
1196 sepos -= 32;
1197 depos -= 32;
1198 }
1199
1200 tga_regs = par->tga_regs_base;
1201 tga_fb = par->tga_fb_base;
1202
1203 /* Set up the MODE and PIXELSHIFT registers. */
1204 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1205 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1206 wmb();
1207
1208 for (i = 0; i < height; ++i) {
1209 unsigned long j;
1210 void __iomem *sfb;
1211 void __iomem *dfb;
1212
1213 sfb = tga_fb + sepos;
1214 dfb = tga_fb + depos;
1215
1216 for (j = 0; j < n32; j++) {
1217 if (j < 2 && j + 1 < n32 && !backward &&
1218 !(((unsigned long)sfb | (unsigned long)dfb) & 63)) {
1219 do {
1220 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1221 wmb();
1222 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1223 wmb();
1224 sfb += 64;
1225 dfb += 64;
1226 j += 2;
1227 } while (j + 1 < n32);
1228 j--;
1229 continue;
1230 }
1231 __raw_writel(0xffffffff, sfb);
1232 wmb();
1233 __raw_writel(0xffffffff, dfb);
1234 wmb();
1235 sfb += step;
1236 dfb += step;
1237 }
1238
1239 if (mask_last) {
1240 sfb += last_step - step;
1241 dfb += last_step - step;
1242 __raw_writel(mask_last, sfb);
1243 wmb();
1244 __raw_writel(mask_last, dfb);
1245 wmb();
1246 }
1247
1248 sepos += yincr;
1249 depos += yincr;
1250 }
1251
1252 /* Reset the MODE register to normal. */
1253 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1254 }
1255
1256 static void
1257 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1258 {
1259 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1260 unsigned long line_length, bpp;
1261
1262 dx = area->dx;
1263 dy = area->dy;
1264 width = area->width;
1265 height = area->height;
1266 sx = area->sx;
1267 sy = area->sy;
1268 vxres = info->var.xres_virtual;
1269 vyres = info->var.yres_virtual;
1270 line_length = info->fix.line_length;
1271
1272 /* The top left corners must be in the virtual screen. */
1273 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1274 return;
1275
1276 /* Clip the destination. */
1277 if (dx + width > vxres)
1278 width = vxres - dx;
1279 if (dy + height > vyres)
1280 height = vyres - dy;
1281
1282 /* The source must be completely inside the virtual screen. */
1283 if (sx + width > vxres || sy + height > vyres)
1284 return;
1285
1286 bpp = info->var.bits_per_pixel;
1287
1288 /* Detect copies of the entire line. */
1289 if (width * (bpp >> 3) == line_length) {
1290 if (bpp == 8)
1291 copyarea_line_8bpp(info, dy, sy, height, width);
1292 else
1293 copyarea_line_32bpp(info, dy, sy, height, width);
1294 }
1295
1296 /* ??? The documentation is unclear to me exactly how the pixelshift
1297 register works in 32bpp mode. Since I don't have hardware to test,
1298 give up for now and fall back on the generic routines. */
1299 else if (bpp == 32)
1300 cfb_copyarea(info, area);
1301
1302 else
1303 copyarea_8bpp(info, dx, dy, sx, sy, height,
1304 width, line_length, area);
1305 }
1306
1307
1308 /*
1309 * Initialisation
1310 */
1311
1312 static void
1313 tgafb_init_fix(struct fb_info *info)
1314 {
1315 struct tga_par *par = (struct tga_par *)info->par;
1316 int tga_bus_pci = TGA_BUS_PCI(par->dev);
1317 int tga_bus_tc = TGA_BUS_TC(par->dev);
1318 u8 tga_type = par->tga_type;
1319 const char *tga_type_name = NULL;
1320 unsigned memory_size;
1321
1322 switch (tga_type) {
1323 case TGA_TYPE_8PLANE:
1324 if (tga_bus_pci)
1325 tga_type_name = "Digital ZLXp-E1";
1326 if (tga_bus_tc)
1327 tga_type_name = "Digital ZLX-E1";
1328 memory_size = 2097152;
1329 break;
1330 case TGA_TYPE_24PLANE:
1331 if (tga_bus_pci)
1332 tga_type_name = "Digital ZLXp-E2";
1333 if (tga_bus_tc)
1334 tga_type_name = "Digital ZLX-E2";
1335 memory_size = 8388608;
1336 break;
1337 case TGA_TYPE_24PLUSZ:
1338 if (tga_bus_pci)
1339 tga_type_name = "Digital ZLXp-E3";
1340 if (tga_bus_tc)
1341 tga_type_name = "Digital ZLX-E3";
1342 memory_size = 16777216;
1343 break;
1344 default:
1345 tga_type_name = "Unknown";
1346 memory_size = 16777216;
1347 break;
1348 }
1349
1350 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1351
1352 info->fix.type = FB_TYPE_PACKED_PIXELS;
1353 info->fix.type_aux = 0;
1354 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1355 ? FB_VISUAL_PSEUDOCOLOR
1356 : FB_VISUAL_DIRECTCOLOR);
1357
1358 info->fix.smem_start = (size_t) par->tga_fb_base;
1359 info->fix.smem_len = memory_size;
1360 info->fix.mmio_start = (size_t) par->tga_regs_base;
1361 info->fix.mmio_len = 512;
1362
1363 info->fix.xpanstep = 0;
1364 info->fix.ypanstep = 0;
1365 info->fix.ywrapstep = 0;
1366
1367 info->fix.accel = FB_ACCEL_DEC_TGA;
1368
1369 /*
1370 * These are needed by fb_set_logo_truepalette(), so we
1371 * set them here for 24-plane cards.
1372 */
1373 if (tga_type != TGA_TYPE_8PLANE) {
1374 info->var.red.length = 8;
1375 info->var.green.length = 8;
1376 info->var.blue.length = 8;
1377 info->var.red.offset = 16;
1378 info->var.green.offset = 8;
1379 info->var.blue.offset = 0;
1380 }
1381 }
1382
1383 static int tgafb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1384 {
1385 /* We just use this to catch switches out of graphics mode. */
1386 tgafb_set_par(info); /* A bit of overkill for BASE_ADDR reset. */
1387 return 0;
1388 }
1389
1390 static int tgafb_register(struct device *dev)
1391 {
1392 static const struct fb_videomode modedb_tc = {
1393 /* 1280x1024 @ 72 Hz, 76.8 kHz hsync */
1394 "1280x1024@72", 0, 1280, 1024, 7645, 224, 28, 33, 3, 160, 3,
1395 FB_SYNC_ON_GREEN, FB_VMODE_NONINTERLACED
1396 };
1397
1398 static unsigned int const fb_offset_presets[4] = {
1399 TGA_8PLANE_FB_OFFSET,
1400 TGA_24PLANE_FB_OFFSET,
1401 0xffffffff,
1402 TGA_24PLUSZ_FB_OFFSET
1403 };
1404
1405 const struct fb_videomode *modedb_tga = NULL;
1406 resource_size_t bar0_start = 0, bar0_len = 0;
1407 const char *mode_option_tga = NULL;
1408 int tga_bus_pci = TGA_BUS_PCI(dev);
1409 int tga_bus_tc = TGA_BUS_TC(dev);
1410 unsigned int modedbsize_tga = 0;
1411 void __iomem *mem_base;
1412 struct fb_info *info;
1413 struct tga_par *par;
1414 u8 tga_type;
1415 int ret = 0;
1416
1417 /* Enable device in PCI config. */
1418 if (tga_bus_pci && pci_enable_device(to_pci_dev(dev))) {
1419 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1420 return -ENODEV;
1421 }
1422
1423 /* Allocate the fb and par structures. */
1424 info = framebuffer_alloc(sizeof(struct tga_par), dev);
1425 if (!info) {
1426 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1427 return -ENOMEM;
1428 }
1429
1430 par = info->par;
1431 dev_set_drvdata(dev, info);
1432
1433 /* Request the mem regions. */
1434 ret = -ENODEV;
1435 if (tga_bus_pci) {
1436 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1437 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1438 }
1439 if (tga_bus_tc) {
1440 bar0_start = to_tc_dev(dev)->resource.start;
1441 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1442 }
1443 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1444 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1445 goto err0;
1446 }
1447
1448 /* Map the framebuffer. */
1449 mem_base = ioremap_nocache(bar0_start, bar0_len);
1450 if (!mem_base) {
1451 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1452 goto err1;
1453 }
1454
1455 /* Grab info about the card. */
1456 tga_type = (readl(mem_base) >> 12) & 0x0f;
1457 par->dev = dev;
1458 par->tga_mem_base = mem_base;
1459 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1460 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1461 par->tga_type = tga_type;
1462 if (tga_bus_pci)
1463 par->tga_chip_rev = (to_pci_dev(dev))->revision;
1464 if (tga_bus_tc)
1465 par->tga_chip_rev = TGA_READ_REG(par, TGA_START_REG) & 0xff;
1466
1467 /* Setup framebuffer. */
1468 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1469 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1470 info->fbops = &tgafb_ops;
1471 info->screen_base = par->tga_fb_base;
1472 info->pseudo_palette = par->palette;
1473
1474 /* This should give a reasonable default video mode. */
1475 if (tga_bus_pci) {
1476 mode_option_tga = mode_option_pci;
1477 }
1478 if (tga_bus_tc) {
1479 mode_option_tga = mode_option_tc;
1480 modedb_tga = &modedb_tc;
1481 modedbsize_tga = 1;
1482 }
1483
1484 tgafb_init_fix(info);
1485
1486 ret = fb_find_mode(&info->var, info,
1487 mode_option ? mode_option : mode_option_tga,
1488 modedb_tga, modedbsize_tga, NULL,
1489 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1490 if (ret == 0 || ret == 4) {
1491 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1492 ret = -EINVAL;
1493 goto err1;
1494 }
1495
1496 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1497 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1498 ret = -ENOMEM;
1499 goto err1;
1500 }
1501
1502 tgafb_set_par(info);
1503
1504 if (register_framebuffer(info) < 0) {
1505 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1506 ret = -EINVAL;
1507 goto err2;
1508 }
1509
1510 if (tga_bus_pci) {
1511 pr_info("tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1512 par->tga_chip_rev);
1513 pr_info("tgafb: at PCI bus %d, device %d, function %d\n",
1514 to_pci_dev(dev)->bus->number,
1515 PCI_SLOT(to_pci_dev(dev)->devfn),
1516 PCI_FUNC(to_pci_dev(dev)->devfn));
1517 }
1518 if (tga_bus_tc)
1519 pr_info("tgafb: SFB+ detected, rev=0x%02x\n",
1520 par->tga_chip_rev);
1521 pr_info("fb%d: %s frame buffer device at 0x%lx\n",
1522 info->node, info->fix.id, (long)bar0_start);
1523
1524 return 0;
1525
1526 err2:
1527 fb_dealloc_cmap(&info->cmap);
1528 err1:
1529 if (mem_base)
1530 iounmap(mem_base);
1531 release_mem_region(bar0_start, bar0_len);
1532 err0:
1533 framebuffer_release(info);
1534 return ret;
1535 }
1536
1537 static void tgafb_unregister(struct device *dev)
1538 {
1539 resource_size_t bar0_start = 0, bar0_len = 0;
1540 int tga_bus_pci = TGA_BUS_PCI(dev);
1541 int tga_bus_tc = TGA_BUS_TC(dev);
1542 struct fb_info *info = NULL;
1543 struct tga_par *par;
1544
1545 info = dev_get_drvdata(dev);
1546 if (!info)
1547 return;
1548
1549 par = info->par;
1550 unregister_framebuffer(info);
1551 fb_dealloc_cmap(&info->cmap);
1552 iounmap(par->tga_mem_base);
1553 if (tga_bus_pci) {
1554 bar0_start = pci_resource_start(to_pci_dev(dev), 0);
1555 bar0_len = pci_resource_len(to_pci_dev(dev), 0);
1556 }
1557 if (tga_bus_tc) {
1558 bar0_start = to_tc_dev(dev)->resource.start;
1559 bar0_len = to_tc_dev(dev)->resource.end - bar0_start + 1;
1560 }
1561 release_mem_region(bar0_start, bar0_len);
1562 framebuffer_release(info);
1563 }
1564
1565 static void tgafb_exit(void)
1566 {
1567 tc_unregister_driver(&tgafb_tc_driver);
1568 pci_unregister_driver(&tgafb_pci_driver);
1569 }
1570
1571 #ifndef MODULE
1572 static int tgafb_setup(char *arg)
1573 {
1574 char *this_opt;
1575
1576 if (arg && *arg) {
1577 while ((this_opt = strsep(&arg, ","))) {
1578 if (!*this_opt)
1579 continue;
1580 if (!strncmp(this_opt, "mode:", 5))
1581 mode_option = this_opt+5;
1582 else
1583 printk(KERN_ERR
1584 "tgafb: unknown parameter %s\n",
1585 this_opt);
1586 }
1587 }
1588
1589 return 0;
1590 }
1591 #endif /* !MODULE */
1592
1593 static int tgafb_init(void)
1594 {
1595 int status;
1596 #ifndef MODULE
1597 char *option = NULL;
1598
1599 if (fb_get_options("tgafb", &option))
1600 return -ENODEV;
1601 tgafb_setup(option);
1602 #endif
1603 status = pci_register_driver(&tgafb_pci_driver);
1604 if (!status)
1605 status = tc_register_driver(&tgafb_tc_driver);
1606 return status;
1607 }
1608
1609 /*
1610 * Modularisation
1611 */
1612
1613 module_init(tgafb_init);
1614 module_exit(tgafb_exit);
1615
1616 MODULE_DESCRIPTION("Framebuffer driver for TGA/SFB+ chipset");
1617 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)