projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge tag 'v3.10.71' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / video / controlfb.c
1 /*
2 * controlfb.c -- frame buffer device for the PowerMac 'control' display
3 *
4 * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org>
5 * Copyright (C) 1998 Dan Jacobowitz
6 * Copyright (C) 2001 Takashi Oe
7 *
8 * Mmap code by Michel Lanners <mlan@cpu.lu>
9 *
10 * Frame buffer structure from:
11 * drivers/video/chipsfb.c -- frame buffer device for
12 * Chips & Technologies 65550 chip.
13 *
14 * Copyright (C) 1998 Paul Mackerras
15 *
16 * This file is derived from the Powermac "chips" driver:
17 * Copyright (C) 1997 Fabio Riccardi.
18 * And from the frame buffer device for Open Firmware-initialized devices:
19 * Copyright (C) 1997 Geert Uytterhoeven.
20 *
21 * Hardware information from:
22 * control.c: Console support for PowerMac "control" display adaptor.
23 * Copyright (C) 1996 Paul Mackerras
24 *
25 * Updated to 2.5 framebuffer API by Ben Herrenschmidt
26 * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>,
27 * and James Simmons <jsimmons@infradead.org>.
28 *
29 * This file is subject to the terms and conditions of the GNU General Public
30 * License. See the file COPYING in the main directory of this archive for
31 * more details.
32 */
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/errno.h>
37 #include <linux/string.h>
38 #include <linux/mm.h>
39 #include <linux/slab.h>
40 #include <linux/vmalloc.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/of.h>
44 #include <linux/of_address.h>
45 #include <linux/fb.h>
46 #include <linux/init.h>
47 #include <linux/pci.h>
48 #include <linux/nvram.h>
49 #include <linux/adb.h>
50 #include <linux/cuda.h>
51 #include <asm/io.h>
52 #include <asm/prom.h>
53 #include <asm/pgtable.h>
54 #include <asm/btext.h>
55
56 #include "macmodes.h"
57 #include "controlfb.h"
58
59 struct fb_par_control {
60 int vmode, cmode;
61 int xres, yres;
62 int vxres, vyres;
63 int xoffset, yoffset;
64 int pitch;
65 struct control_regvals regvals;
66 unsigned long sync;
67 unsigned char ctrl;
68 };
69
70 #define DIRTY(z) ((x)->z != (y)->z)
71 #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
72 static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
73 {
74 int i, results;
75
76 results = 1;
77 for (i = 0; i < 3; i++)
78 results &= !DIRTY(regvals.clock_params[i]);
79 if (!results)
80 return 0;
81 for (i = 0; i < 16; i++)
82 results &= !DIRTY(regvals.regs[i]);
83 if (!results)
84 return 0;
85 return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
86 && !DIRTY(vxres) && !DIRTY(vyres));
87 }
88 static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y)
89 {
90 return (!DIRTY(bits_per_pixel) && !DIRTY(xres)
91 && !DIRTY(yres) && !DIRTY(xres_virtual)
92 && !DIRTY(yres_virtual)
93 && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue));
94 }
95
96 struct fb_info_control {
97 struct fb_info info;
98 struct fb_par_control par;
99 u32 pseudo_palette[16];
100
101 struct cmap_regs __iomem *cmap_regs;
102 unsigned long cmap_regs_phys;
103
104 struct control_regs __iomem *control_regs;
105 unsigned long control_regs_phys;
106 unsigned long control_regs_size;
107
108 __u8 __iomem *frame_buffer;
109 unsigned long frame_buffer_phys;
110 unsigned long fb_orig_base;
111 unsigned long fb_orig_size;
112
113 int control_use_bank2;
114 unsigned long total_vram;
115 unsigned char vram_attr;
116 };
117
118 /* control register access macro */
119 #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
120
121
122 /******************** Prototypes for exported functions ********************/
123 /*
124 * struct fb_ops
125 */
126 static int controlfb_pan_display(struct fb_var_screeninfo *var,
127 struct fb_info *info);
128 static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
129 u_int transp, struct fb_info *info);
130 static int controlfb_blank(int blank_mode, struct fb_info *info);
131 static int controlfb_mmap(struct fb_info *info,
132 struct vm_area_struct *vma);
133 static int controlfb_set_par (struct fb_info *info);
134 static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info);
135
136 /******************** Prototypes for internal functions **********************/
137
138 static void set_control_clock(unsigned char *params);
139 static int init_control(struct fb_info_control *p);
140 static void control_set_hardware(struct fb_info_control *p,
141 struct fb_par_control *par);
142 static int control_of_init(struct device_node *dp);
143 static void find_vram_size(struct fb_info_control *p);
144 static int read_control_sense(struct fb_info_control *p);
145 static int calc_clock_params(unsigned long clk, unsigned char *param);
146 static int control_var_to_par(struct fb_var_screeninfo *var,
147 struct fb_par_control *par, const struct fb_info *fb_info);
148 static inline void control_par_to_var(struct fb_par_control *par,
149 struct fb_var_screeninfo *var);
150 static void control_init_info(struct fb_info *info, struct fb_info_control *p);
151 static void control_cleanup(void);
152
153
154 /************************** Internal variables *******************************/
155
156 static struct fb_info_control *control_fb;
157
158 static int default_vmode __initdata = VMODE_NVRAM;
159 static int default_cmode __initdata = CMODE_NVRAM;
160
161
162 static struct fb_ops controlfb_ops = {
163 .owner = THIS_MODULE,
164 .fb_check_var = controlfb_check_var,
165 .fb_set_par = controlfb_set_par,
166 .fb_setcolreg = controlfb_setcolreg,
167 .fb_pan_display = controlfb_pan_display,
168 .fb_blank = controlfb_blank,
169 .fb_mmap = controlfb_mmap,
170 .fb_fillrect = cfb_fillrect,
171 .fb_copyarea = cfb_copyarea,
172 .fb_imageblit = cfb_imageblit,
173 };
174
175
176 /******************** The functions for controlfb_ops ********************/
177
178 #ifdef MODULE
179 MODULE_LICENSE("GPL");
180
181 int init_module(void)
182 {
183 struct device_node *dp;
184 int ret = -ENXIO;
185
186 dp = of_find_node_by_name(NULL, "control");
187 if (dp != 0 && !control_of_init(dp))
188 ret = 0;
189 of_node_put(dp);
190
191 return ret;
192 }
193
194 void cleanup_module(void)
195 {
196 control_cleanup();
197 }
198 #endif
199
200 /*
201 * Checks a var structure
202 */
203 static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
204 {
205 struct fb_par_control par;
206 int err;
207
208 err = control_var_to_par(var, &par, info);
209 if (err)
210 return err;
211 control_par_to_var(&par, var);
212
213 return 0;
214 }
215
216 /*
217 * Applies current var to display
218 */
219 static int controlfb_set_par (struct fb_info *info)
220 {
221 struct fb_info_control *p = (struct fb_info_control *) info;
222 struct fb_par_control par;
223 int err;
224
225 if((err = control_var_to_par(&info->var, &par, info))) {
226 printk (KERN_ERR "controlfb_set_par: error calling"
227 " control_var_to_par: %d.\n", err);
228 return err;
229 }
230
231 control_set_hardware(p, &par);
232
233 info->fix.visual = (p->par.cmode == CMODE_8) ?
234 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
235 info->fix.line_length = p->par.pitch;
236 info->fix.xpanstep = 32 >> p->par.cmode;
237 info->fix.ypanstep = 1;
238
239 return 0;
240 }
241
242 /*
243 * Set screen start address according to var offset values
244 */
245 static inline void set_screen_start(int xoffset, int yoffset,
246 struct fb_info_control *p)
247 {
248 struct fb_par_control *par = &p->par;
249
250 par->xoffset = xoffset;
251 par->yoffset = yoffset;
252 out_le32(CNTRL_REG(p,start_addr),
253 par->yoffset * par->pitch + (par->xoffset << par->cmode));
254 }
255
256
257 static int controlfb_pan_display(struct fb_var_screeninfo *var,
258 struct fb_info *info)
259 {
260 unsigned int xoffset, hstep;
261 struct fb_info_control *p = (struct fb_info_control *)info;
262 struct fb_par_control *par = &p->par;
263
264 /*
265 * make sure start addr will be 32-byte aligned
266 */
267 hstep = 0x1f >> par->cmode;
268 xoffset = (var->xoffset + hstep) & ~hstep;
269
270 if (xoffset+par->xres > par->vxres ||
271 var->yoffset+par->yres > par->vyres)
272 return -EINVAL;
273
274 set_screen_start(xoffset, var->yoffset, p);
275
276 return 0;
277 }
278
279
280 /*
281 * Private mmap since we want to have a different caching on the framebuffer
282 * for controlfb.
283 * Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
284 */
285 static int controlfb_mmap(struct fb_info *info,
286 struct vm_area_struct *vma)
287 {
288 unsigned long mmio_pgoff;
289 unsigned long start;
290 u32 len;
291
292 start = info->fix.smem_start;
293 len = info->fix.smem_len;
294 mmio_pgoff = PAGE_ALIGN((start & ~PAGE_MASK) + len) >> PAGE_SHIFT;
295 if (vma->vm_pgoff >= mmio_pgoff) {
296 if (info->var.accel_flags)
297 return -EINVAL;
298 vma->vm_pgoff -= mmio_pgoff;
299 start = info->fix.mmio_start;
300 len = info->fix.mmio_len;
301 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
302 } else {
303 /* framebuffer */
304 vma->vm_page_prot = pgprot_cached_wthru(vma->vm_page_prot);
305 }
306
307 return vm_iomap_memory(vma, start, len);
308 }
309
310 static int controlfb_blank(int blank_mode, struct fb_info *info)
311 {
312 struct fb_info_control *p = (struct fb_info_control *) info;
313 unsigned ctrl;
314
315 ctrl = ld_le32(CNTRL_REG(p,ctrl));
316 if (blank_mode > 0)
317 switch (blank_mode) {
318 case FB_BLANK_VSYNC_SUSPEND:
319 ctrl &= ~3;
320 break;
321 case FB_BLANK_HSYNC_SUSPEND:
322 ctrl &= ~0x30;
323 break;
324 case FB_BLANK_POWERDOWN:
325 ctrl &= ~0x33;
326 /* fall through */
327 case FB_BLANK_NORMAL:
328 ctrl |= 0x400;
329 break;
330 default:
331 break;
332 }
333 else {
334 ctrl &= ~0x400;
335 ctrl |= 0x33;
336 }
337 out_le32(CNTRL_REG(p,ctrl), ctrl);
338
339 return 0;
340 }
341
342 static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
343 u_int transp, struct fb_info *info)
344 {
345 struct fb_info_control *p = (struct fb_info_control *) info;
346 __u8 r, g, b;
347
348 if (regno > 255)
349 return 1;
350
351 r = red >> 8;
352 g = green >> 8;
353 b = blue >> 8;
354
355 out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
356 out_8(&p->cmap_regs->lut, r); /* send one color channel at */
357 out_8(&p->cmap_regs->lut, g); /* a time... */
358 out_8(&p->cmap_regs->lut, b);
359
360 if (regno < 16) {
361 int i;
362 switch (p->par.cmode) {
363 case CMODE_16:
364 p->pseudo_palette[regno] =
365 (regno << 10) | (regno << 5) | regno;
366 break;
367 case CMODE_32:
368 i = (regno << 8) | regno;
369 p->pseudo_palette[regno] = (i << 16) | i;
370 break;
371 }
372 }
373
374 return 0;
375 }
376
377
378 /******************** End of controlfb_ops implementation ******************/
379
380
381
382 static void set_control_clock(unsigned char *params)
383 {
384 #ifdef CONFIG_ADB_CUDA
385 struct adb_request req;
386 int i;
387
388 for (i = 0; i < 3; ++i) {
389 cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
390 0x50, i + 1, params[i]);
391 while (!req.complete)
392 cuda_poll();
393 }
394 #endif
395 }
396
397
398 /*
399 * finish off the driver initialization and register
400 */
401 static int __init init_control(struct fb_info_control *p)
402 {
403 int full, sense, vmode, cmode, vyres;
404 struct fb_var_screeninfo var;
405 int rc;
406
407 printk(KERN_INFO "controlfb: ");
408
409 full = p->total_vram == 0x400000;
410
411 /* Try to pick a video mode out of NVRAM if we have one. */
412 #ifdef CONFIG_NVRAM
413 if (default_cmode == CMODE_NVRAM) {
414 cmode = nvram_read_byte(NV_CMODE);
415 if(cmode < CMODE_8 || cmode > CMODE_32)
416 cmode = CMODE_8;
417 } else
418 #endif
419 cmode=default_cmode;
420 #ifdef CONFIG_NVRAM
421 if (default_vmode == VMODE_NVRAM) {
422 vmode = nvram_read_byte(NV_VMODE);
423 if (vmode < 1 || vmode > VMODE_MAX ||
424 control_mac_modes[vmode - 1].m[full] < cmode) {
425 sense = read_control_sense(p);
426 printk("Monitor sense value = 0x%x, ", sense);
427 vmode = mac_map_monitor_sense(sense);
428 if (control_mac_modes[vmode - 1].m[full] < cmode)
429 vmode = VMODE_640_480_60;
430 }
431 } else
432 #endif
433 {
434 vmode=default_vmode;
435 if (control_mac_modes[vmode - 1].m[full] < cmode) {
436 if (cmode > CMODE_8)
437 cmode--;
438 else
439 vmode = VMODE_640_480_60;
440 }
441 }
442
443 /* Initialize info structure */
444 control_init_info(&p->info, p);
445
446 /* Setup default var */
447 if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
448 /* This shouldn't happen! */
449 printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
450 try_again:
451 vmode = VMODE_640_480_60;
452 cmode = CMODE_8;
453 if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
454 printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
455 return -ENXIO;
456 }
457 printk(KERN_INFO "controlfb: ");
458 }
459 printk("using video mode %d and color mode %d.\n", vmode, cmode);
460
461 vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
462 if (vyres > var.yres)
463 var.yres_virtual = vyres;
464
465 /* Apply default var */
466 var.activate = FB_ACTIVATE_NOW;
467 rc = fb_set_var(&p->info, &var);
468 if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
469 goto try_again;
470
471 /* Register with fbdev layer */
472 if (register_framebuffer(&p->info) < 0)
473 return -ENXIO;
474
475 printk(KERN_INFO "fb%d: control display adapter\n", p->info.node);
476
477 return 0;
478 }
479
480 #define RADACAL_WRITE(a,d) \
481 out_8(&p->cmap_regs->addr, (a)); \
482 out_8(&p->cmap_regs->dat, (d))
483
484 /* Now how about actually saying, Make it so! */
485 /* Some things in here probably don't need to be done each time. */
486 static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
487 {
488 struct control_regvals *r;
489 volatile struct preg __iomem *rp;
490 int i, cmode;
491
492 if (PAR_EQUAL(&p->par, par)) {
493 /*
494 * check if only xoffset or yoffset differs.
495 * this prevents flickers in typical VT switch case.
496 */
497 if (p->par.xoffset != par->xoffset ||
498 p->par.yoffset != par->yoffset)
499 set_screen_start(par->xoffset, par->yoffset, p);
500
501 return;
502 }
503
504 p->par = *par;
505 cmode = p->par.cmode;
506 r = &par->regvals;
507
508 /* Turn off display */
509 out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
510
511 set_control_clock(r->clock_params);
512
513 RADACAL_WRITE(0x20, r->radacal_ctrl);
514 RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
515 RADACAL_WRITE(0x10, 0);
516 RADACAL_WRITE(0x11, 0);
517
518 rp = &p->control_regs->vswin;
519 for (i = 0; i < 16; ++i, ++rp)
520 out_le32(&rp->r, r->regs[i]);
521
522 out_le32(CNTRL_REG(p,pitch), par->pitch);
523 out_le32(CNTRL_REG(p,mode), r->mode);
524 out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
525 out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
526 + (par->xoffset << cmode));
527 out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
528 out_le32(CNTRL_REG(p,intr_ena), 0);
529
530 /* Turn on display */
531 out_le32(CNTRL_REG(p,ctrl), par->ctrl);
532
533 #ifdef CONFIG_BOOTX_TEXT
534 btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
535 p->par.xres, p->par.yres,
536 (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
537 p->par.pitch);
538 #endif /* CONFIG_BOOTX_TEXT */
539 }
540
541
542 /*
543 * Parse user specified options (`video=controlfb:')
544 */
545 static void __init control_setup(char *options)
546 {
547 char *this_opt;
548
549 if (!options || !*options)
550 return;
551
552 while ((this_opt = strsep(&options, ",")) != NULL) {
553 if (!strncmp(this_opt, "vmode:", 6)) {
554 int vmode = simple_strtoul(this_opt+6, NULL, 0);
555 if (vmode > 0 && vmode <= VMODE_MAX &&
556 control_mac_modes[vmode - 1].m[1] >= 0)
557 default_vmode = vmode;
558 } else if (!strncmp(this_opt, "cmode:", 6)) {
559 int depth = simple_strtoul(this_opt+6, NULL, 0);
560 switch (depth) {
561 case CMODE_8:
562 case CMODE_16:
563 case CMODE_32:
564 default_cmode = depth;
565 break;
566 case 8:
567 default_cmode = CMODE_8;
568 break;
569 case 15:
570 case 16:
571 default_cmode = CMODE_16;
572 break;
573 case 24:
574 case 32:
575 default_cmode = CMODE_32;
576 break;
577 }
578 }
579 }
580 }
581
582 static int __init control_init(void)
583 {
584 struct device_node *dp;
585 char *option = NULL;
586 int ret = -ENXIO;
587
588 if (fb_get_options("controlfb", &option))
589 return -ENODEV;
590 control_setup(option);
591
592 dp = of_find_node_by_name(NULL, "control");
593 if (dp != 0 && !control_of_init(dp))
594 ret = 0;
595 of_node_put(dp);
596
597 return ret;
598 }
599
600 module_init(control_init);
601
602 /* Work out which banks of VRAM we have installed. */
603 /* danj: I guess the card just ignores writes to nonexistant VRAM... */
604
605 static void __init find_vram_size(struct fb_info_control *p)
606 {
607 int bank1, bank2;
608
609 /*
610 * Set VRAM in 2MB (bank 1) mode
611 * VRAM Bank 2 will be accessible through offset 0x600000 if present
612 * and VRAM Bank 1 will not respond at that offset even if present
613 */
614 out_le32(CNTRL_REG(p,vram_attr), 0x31);
615
616 out_8(&p->frame_buffer[0x600000], 0xb3);
617 out_8(&p->frame_buffer[0x600001], 0x71);
618 asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0x600000])
619 : "memory" );
620 mb();
621 asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0x600000])
622 : "memory" );
623 mb();
624
625 bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
626 && (in_8(&p->frame_buffer[0x600001]) == 0x71);
627
628 /*
629 * Set VRAM in 2MB (bank 2) mode
630 * VRAM Bank 1 will be accessible through offset 0x000000 if present
631 * and VRAM Bank 2 will not respond at that offset even if present
632 */
633 out_le32(CNTRL_REG(p,vram_attr), 0x39);
634
635 out_8(&p->frame_buffer[0], 0x5a);
636 out_8(&p->frame_buffer[1], 0xc7);
637 asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0])
638 : "memory" );
639 mb();
640 asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0])
641 : "memory" );
642 mb();
643
644 bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
645 && (in_8(&p->frame_buffer[1]) == 0xc7);
646
647 if (bank2) {
648 if (!bank1) {
649 /*
650 * vram bank 2 only
651 */
652 p->control_use_bank2 = 1;
653 p->vram_attr = 0x39;
654 p->frame_buffer += 0x600000;
655 p->frame_buffer_phys += 0x600000;
656 } else {
657 /*
658 * 4 MB vram
659 */
660 p->vram_attr = 0x51;
661 }
662 } else {
663 /*
664 * vram bank 1 only
665 */
666 p->vram_attr = 0x31;
667 }
668
669 p->total_vram = (bank1 + bank2) * 0x200000;
670
671 printk(KERN_INFO "controlfb: VRAM Total = %dMB "
672 "(%dMB @ bank 1, %dMB @ bank 2)\n",
673 (bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
674 }
675
676
677 /*
678 * find "control" and initialize
679 */
680 static int __init control_of_init(struct device_node *dp)
681 {
682 struct fb_info_control *p;
683 struct resource fb_res, reg_res;
684
685 if (control_fb) {
686 printk(KERN_ERR "controlfb: only one control is supported\n");
687 return -ENXIO;
688 }
689
690 if (of_pci_address_to_resource(dp, 2, &fb_res) ||
691 of_pci_address_to_resource(dp, 1, &reg_res)) {
692 printk(KERN_ERR "can't get 2 addresses for control\n");
693 return -ENXIO;
694 }
695 p = kzalloc(sizeof(*p), GFP_KERNEL);
696 if (p == 0)
697 return -ENXIO;
698 control_fb = p; /* save it for cleanups */
699
700 /* Map in frame buffer and registers */
701 p->fb_orig_base = fb_res.start;
702 p->fb_orig_size = resource_size(&fb_res);
703 /* use the big-endian aperture (??) */
704 p->frame_buffer_phys = fb_res.start + 0x800000;
705 p->control_regs_phys = reg_res.start;
706 p->control_regs_size = resource_size(&reg_res);
707
708 if (!p->fb_orig_base ||
709 !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
710 p->fb_orig_base = 0;
711 goto error_out;
712 }
713 /* map at most 8MB for the frame buffer */
714 p->frame_buffer = __ioremap(p->frame_buffer_phys, 0x800000,
715 _PAGE_WRITETHRU);
716
717 if (!p->control_regs_phys ||
718 !request_mem_region(p->control_regs_phys, p->control_regs_size,
719 "controlfb regs")) {
720 p->control_regs_phys = 0;
721 goto error_out;
722 }
723 p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
724
725 p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
726 if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
727 p->cmap_regs_phys = 0;
728 goto error_out;
729 }
730 p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
731
732 if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
733 goto error_out;
734
735 find_vram_size(p);
736 if (!p->total_vram)
737 goto error_out;
738
739 if (init_control(p) < 0)
740 goto error_out;
741
742 return 0;
743
744 error_out:
745 control_cleanup();
746 return -ENXIO;
747 }
748
749 /*
750 * Get the monitor sense value.
751 * Note that this can be called before calibrate_delay,
752 * so we can't use udelay.
753 */
754 static int read_control_sense(struct fb_info_control *p)
755 {
756 int sense;
757
758 out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
759 __delay(200);
760 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
761 __delay(2000);
762 sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
763
764 /* drive each sense line low in turn and collect the other 2 */
765 out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
766 __delay(2000);
767 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
768 out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
769 __delay(2000);
770 sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
771 | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
772 out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
773 __delay(2000);
774 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
775
776 out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
777
778 return sense;
779 }
780
781 /********************** Various translation functions **********************/
782
783 #define CONTROL_PIXCLOCK_BASE 256016
784 #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
785
786 /*
787 * calculate the clock paramaters to be sent to CUDA according to given
788 * pixclock in pico second.
789 */
790 static int calc_clock_params(unsigned long clk, unsigned char *param)
791 {
792 unsigned long p0, p1, p2, k, l, m, n, min;
793
794 if (clk > (CONTROL_PIXCLOCK_BASE << 3))
795 return 1;
796
797 p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
798 l = clk << p2;
799 p0 = 0;
800 p1 = 0;
801 for (k = 1, min = l; k < 32; k++) {
802 unsigned long rem;
803
804 m = CONTROL_PIXCLOCK_BASE * k;
805 n = m / l;
806 rem = m % l;
807 if (n && (n < 128) && rem < min) {
808 p0 = k;
809 p1 = n;
810 min = rem;
811 }
812 }
813 if (!p0 || !p1)
814 return 1;
815
816 param[0] = p0;
817 param[1] = p1;
818 param[2] = p2;
819
820 return 0;
821 }
822
823
824 /*
825 * This routine takes a user-supplied var, and picks the best vmode/cmode
826 * from it.
827 */
828
829 static int control_var_to_par(struct fb_var_screeninfo *var,
830 struct fb_par_control *par, const struct fb_info *fb_info)
831 {
832 int cmode, piped_diff, hstep;
833 unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
834 hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
835 unsigned long pixclock;
836 struct fb_info_control *p = (struct fb_info_control *) fb_info;
837 struct control_regvals *r = &par->regvals;
838
839 switch (var->bits_per_pixel) {
840 case 8:
841 par->cmode = CMODE_8;
842 if (p->total_vram > 0x200000) {
843 r->mode = 3;
844 r->radacal_ctrl = 0x20;
845 piped_diff = 13;
846 } else {
847 r->mode = 2;
848 r->radacal_ctrl = 0x10;
849 piped_diff = 9;
850 }
851 break;
852 case 15:
853 case 16:
854 par->cmode = CMODE_16;
855 if (p->total_vram > 0x200000) {
856 r->mode = 2;
857 r->radacal_ctrl = 0x24;
858 piped_diff = 5;
859 } else {
860 r->mode = 1;
861 r->radacal_ctrl = 0x14;
862 piped_diff = 3;
863 }
864 break;
865 case 32:
866 par->cmode = CMODE_32;
867 if (p->total_vram > 0x200000) {
868 r->mode = 1;
869 r->radacal_ctrl = 0x28;
870 } else {
871 r->mode = 0;
872 r->radacal_ctrl = 0x18;
873 }
874 piped_diff = 1;
875 break;
876 default:
877 return -EINVAL;
878 }
879
880 /*
881 * adjust xres and vxres so that the corresponding memory widths are
882 * 32-byte aligned
883 */
884 hstep = 31 >> par->cmode;
885 par->xres = (var->xres + hstep) & ~hstep;
886 par->vxres = (var->xres_virtual + hstep) & ~hstep;
887 par->xoffset = (var->xoffset + hstep) & ~hstep;
888 if (par->vxres < par->xres)
889 par->vxres = par->xres;
890 par->pitch = par->vxres << par->cmode;
891
892 par->yres = var->yres;
893 par->vyres = var->yres_virtual;
894 par->yoffset = var->yoffset;
895 if (par->vyres < par->yres)
896 par->vyres = par->yres;
897
898 par->sync = var->sync;
899
900 if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
901 return -EINVAL;
902
903 if (par->xoffset + par->xres > par->vxres)
904 par->xoffset = par->vxres - par->xres;
905 if (par->yoffset + par->yres > par->vyres)
906 par->yoffset = par->vyres - par->yres;
907
908 pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
909 var->pixclock;
910 if (calc_clock_params(pixclock, r->clock_params))
911 return -EINVAL;
912
913 hperiod = ((var->left_margin + par->xres + var->right_margin
914 + var->hsync_len) >> 1) - 2;
915 hssync = hperiod + 1;
916 hsblank = hssync - (var->right_margin >> 1);
917 hesync = (var->hsync_len >> 1) - 1;
918 heblank = (var->left_margin >> 1) + hesync;
919 piped = heblank - piped_diff;
920 heq = var->hsync_len >> 2;
921 hlfln = (hperiod+2) >> 1;
922 hserr = hssync-hesync;
923 vperiod = (var->vsync_len + var->lower_margin + par->yres
924 + var->upper_margin) << 1;
925 vssync = vperiod - 2;
926 vesync = (var->vsync_len << 1) - vperiod + vssync;
927 veblank = (var->upper_margin << 1) + vesync;
928 vsblank = vssync - (var->lower_margin << 1);
929 vswin = (vsblank+vssync) >> 1;
930 vewin = (vesync+veblank) >> 1;
931
932 r->regs[0] = vswin;
933 r->regs[1] = vsblank;
934 r->regs[2] = veblank;
935 r->regs[3] = vewin;
936 r->regs[4] = vesync;
937 r->regs[5] = vssync;
938 r->regs[6] = vperiod;
939 r->regs[7] = piped;
940 r->regs[8] = hperiod;
941 r->regs[9] = hsblank;
942 r->regs[10] = heblank;
943 r->regs[11] = hesync;
944 r->regs[12] = hssync;
945 r->regs[13] = heq;
946 r->regs[14] = hlfln;
947 r->regs[15] = hserr;
948
949 if (par->xres >= 1280 && par->cmode >= CMODE_16)
950 par->ctrl = 0x7f;
951 else
952 par->ctrl = 0x3b;
953
954 if (mac_var_to_vmode(var, &par->vmode, &cmode))
955 par->vmode = 0;
956
957 return 0;
958 }
959
960
961 /*
962 * Convert hardware data in par to an fb_var_screeninfo
963 */
964
965 static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
966 {
967 struct control_regints *rv;
968
969 rv = (struct control_regints *) par->regvals.regs;
970
971 memset(var, 0, sizeof(*var));
972 var->xres = par->xres;
973 var->yres = par->yres;
974 var->xres_virtual = par->vxres;
975 var->yres_virtual = par->vyres;
976 var->xoffset = par->xoffset;
977 var->yoffset = par->yoffset;
978
979 switch(par->cmode) {
980 default:
981 case CMODE_8:
982 var->bits_per_pixel = 8;
983 var->red.length = 8;
984 var->green.length = 8;
985 var->blue.length = 8;
986 break;
987 case CMODE_16: /* RGB 555 */
988 var->bits_per_pixel = 16;
989 var->red.offset = 10;
990 var->red.length = 5;
991 var->green.offset = 5;
992 var->green.length = 5;
993 var->blue.length = 5;
994 break;
995 case CMODE_32: /* RGB 888 */
996 var->bits_per_pixel = 32;
997 var->red.offset = 16;
998 var->red.length = 8;
999 var->green.offset = 8;
1000 var->green.length = 8;
1001 var->blue.length = 8;
1002 var->transp.offset = 24;
1003 var->transp.length = 8;
1004 break;
1005 }
1006 var->height = -1;
1007 var->width = -1;
1008 var->vmode = FB_VMODE_NONINTERLACED;
1009
1010 var->left_margin = (rv->heblank - rv->hesync) << 1;
1011 var->right_margin = (rv->hssync - rv->hsblank) << 1;
1012 var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
1013
1014 var->upper_margin = (rv->veblank - rv->vesync) >> 1;
1015 var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
1016 var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
1017
1018 var->sync = par->sync;
1019
1020 /*
1021 * 10^12 * clock_params[0] / (3906400 * clock_params[1]
1022 * * 2^clock_params[2])
1023 * (10^12 * clock_params[0] / (3906400 * clock_params[1]))
1024 * >> clock_params[2]
1025 */
1026 /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
1027 var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
1028 var->pixclock /= par->regvals.clock_params[1];
1029 var->pixclock >>= par->regvals.clock_params[2];
1030 }
1031
1032 /*
1033 * Set misc info vars for this driver
1034 */
1035 static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
1036 {
1037 /* Fill fb_info */
1038 info->par = &p->par;
1039 info->fbops = &controlfb_ops;
1040 info->pseudo_palette = p->pseudo_palette;
1041 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1042 info->screen_base = p->frame_buffer + CTRLFB_OFF;
1043
1044 fb_alloc_cmap(&info->cmap, 256, 0);
1045
1046 /* Fill fix common fields */
1047 strcpy(info->fix.id, "control");
1048 info->fix.mmio_start = p->control_regs_phys;
1049 info->fix.mmio_len = sizeof(struct control_regs);
1050 info->fix.type = FB_TYPE_PACKED_PIXELS;
1051 info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
1052 info->fix.smem_len = p->total_vram - CTRLFB_OFF;
1053 info->fix.ywrapstep = 0;
1054 info->fix.type_aux = 0;
1055 info->fix.accel = FB_ACCEL_NONE;
1056 }
1057
1058
1059 static void control_cleanup(void)
1060 {
1061 struct fb_info_control *p = control_fb;
1062
1063 if (!p)
1064 return;
1065
1066 if (p->cmap_regs)
1067 iounmap(p->cmap_regs);
1068 if (p->control_regs)
1069 iounmap(p->control_regs);
1070 if (p->frame_buffer) {
1071 if (p->control_use_bank2)
1072 p->frame_buffer -= 0x600000;
1073 iounmap(p->frame_buffer);
1074 }
1075 if (p->cmap_regs_phys)
1076 release_mem_region(p->cmap_regs_phys, 0x1000);
1077 if (p->control_regs_phys)
1078 release_mem_region(p->control_regs_phys, p->control_regs_size);
1079 if (p->fb_orig_base)
1080 release_mem_region(p->fb_orig_base, p->fb_orig_size);
1081 kfree(p);
1082 }
1083
1084
kernel source for telekom puls (alcatel/mediatek)