2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #ifndef __LINUX_XHCI_HCD_H
24 #define __LINUX_XHCI_HCD_H
26 #include <linux/usb.h>
27 #include <linux/timer.h>
28 #include <linux/kernel.h>
29 #include <linux/usb/hcd.h>
31 /* Code sharing between pci-quirks and xhci hcd */
32 #include "xhci-ext-caps.h"
33 #include "pci-quirks.h"
36 /* xHCI PCI Configuration Registers */
37 #define XHCI_SBRN_OFFSET (0x60)
39 /* Max number of USB devices for any host controller - limit in section 6.1 */
40 #define MAX_HC_SLOTS 256
41 /* Section 5.3.3 - MaxPorts */
42 #define MAX_HC_PORTS 127
45 * xHCI register interface.
46 * This corresponds to the eXtensible Host Controller Interface (xHCI)
47 * Revision 0.95 specification
51 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
52 * @hc_capbase: length of the capabilities register and HC version number
53 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
54 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
55 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
56 * @hcc_params: HCCPARAMS - Capability Parameters
57 * @db_off: DBOFF - Doorbell array offset
58 * @run_regs_off: RTSOFF - Runtime register space offset
60 struct xhci_cap_regs
{
68 /* Reserved up to (CAPLENGTH - 0x1C) */
71 /* hc_capbase bitmasks */
72 /* bits 7:0 - how long is the Capabilities register */
73 #define HC_LENGTH(p) XHCI_HC_LENGTH(p)
75 #define HC_VERSION(p) (((p) >> 16) & 0xffff)
77 /* HCSPARAMS1 - hcs_params1 - bitmasks */
78 /* bits 0:7, Max Device Slots */
79 #define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
80 #define HCS_SLOTS_MASK 0xff
81 /* bits 8:18, Max Interrupters */
82 #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
83 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
84 #define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
86 /* HCSPARAMS2 - hcs_params2 - bitmasks */
87 /* bits 0:3, frames or uframes that SW needs to queue transactions
88 * ahead of the HW to meet periodic deadlines */
89 #define HCS_IST(p) (((p) >> 0) & 0xf)
90 /* bits 4:7, max number of Event Ring segments */
91 #define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
92 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
93 /* bits 27:31 number of Scratchpad buffers SW must allocate for the HW */
94 #define HCS_MAX_SCRATCHPAD(p) (((p) >> 27) & 0x1f)
96 /* HCSPARAMS3 - hcs_params3 - bitmasks */
97 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
98 #define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
99 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
100 #define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
102 /* HCCPARAMS - hcc_params - bitmasks */
103 /* true: HC can use 64-bit address pointers */
104 #define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
105 /* true: HC can do bandwidth negotiation */
106 #define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
107 /* true: HC uses 64-byte Device Context structures
108 * FIXME 64-byte context structures aren't supported yet.
110 #define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
111 /* true: HC has port power switches */
112 #define HCC_PPC(p) ((p) & (1 << 3))
113 /* true: HC has port indicators */
114 #define HCS_INDICATOR(p) ((p) & (1 << 4))
115 /* true: HC has Light HC Reset Capability */
116 #define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
117 /* true: HC supports latency tolerance messaging */
118 #define HCC_LTC(p) ((p) & (1 << 6))
119 /* true: no secondary Stream ID Support */
120 #define HCC_NSS(p) ((p) & (1 << 7))
121 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
122 #define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
123 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
124 #define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
126 /* db_off bitmask - bits 0:1 reserved */
127 #define DBOFF_MASK (~0x3)
129 /* run_regs_off bitmask - bits 0:4 reserved */
130 #define RTSOFF_MASK (~0x1f)
133 /* Number of registers per port */
134 #define NUM_PORT_REGS 4
137 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
138 * @command: USBCMD - xHC command register
139 * @status: USBSTS - xHC status register
140 * @page_size: This indicates the page size that the host controller
141 * supports. If bit n is set, the HC supports a page size
142 * of 2^(n+12), up to a 128MB page size.
143 * 4K is the minimum page size.
144 * @cmd_ring: CRP - 64-bit Command Ring Pointer
145 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
146 * @config_reg: CONFIG - Configure Register
147 * @port_status_base: PORTSCn - base address for Port Status and Control
148 * Each port has a Port Status and Control register,
149 * followed by a Port Power Management Status and Control
150 * register, a Port Link Info register, and a reserved
152 * @port_power_base: PORTPMSCn - base address for
153 * Port Power Management Status and Control
154 * @port_link_base: PORTLIn - base address for Port Link Info (current
155 * Link PM state and control) for USB 2.1 and USB 3.0
158 struct xhci_op_regs
{
164 __le32 dev_notification
;
166 /* rsvd: offset 0x20-2F */
170 /* rsvd: offset 0x3C-3FF */
171 __le32 reserved4
[241];
172 /* port 1 registers, which serve as a base address for other ports */
173 __le32 port_status_base
;
174 __le32 port_power_base
;
175 __le32 port_link_base
;
177 /* registers for ports 2-255 */
178 __le32 reserved6
[NUM_PORT_REGS
*254];
181 /* USBCMD - USB command - command bitmasks */
182 /* start/stop HC execution - do not write unless HC is halted*/
183 #define CMD_RUN XHCI_CMD_RUN
184 /* Reset HC - resets internal HC state machine and all registers (except
185 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
186 * The xHCI driver must reinitialize the xHC after setting this bit.
188 #define CMD_RESET (1 << 1)
189 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
190 #define CMD_EIE XHCI_CMD_EIE
191 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
192 #define CMD_HSEIE XHCI_CMD_HSEIE
193 /* bits 4:6 are reserved (and should be preserved on writes). */
194 /* light reset (port status stays unchanged) - reset completed when this is 0 */
195 #define CMD_LRESET (1 << 7)
196 /* host controller save/restore state. */
197 #define CMD_CSS (1 << 8)
198 #define CMD_CRS (1 << 9)
199 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
200 #define CMD_EWE XHCI_CMD_EWE
201 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
202 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
203 * '0' means the xHC can power it off if all ports are in the disconnect,
204 * disabled, or powered-off state.
206 #define CMD_PM_INDEX (1 << 11)
207 /* bits 12:31 are reserved (and should be preserved on writes). */
209 /* IMAN - Interrupt Management Register */
210 #define IMAN_IE (1 << 1)
211 #define IMAN_IP (1 << 0)
213 /* USBSTS - USB status - status bitmasks */
214 /* HC not running - set to 1 when run/stop bit is cleared. */
215 #define STS_HALT XHCI_STS_HALT
216 /* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
217 #define STS_FATAL (1 << 2)
218 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
219 #define STS_EINT (1 << 3)
220 /* port change detect */
221 #define STS_PORT (1 << 4)
222 /* bits 5:7 reserved and zeroed */
223 /* save state status - '1' means xHC is saving state */
224 #define STS_SAVE (1 << 8)
225 /* restore state status - '1' means xHC is restoring state */
226 #define STS_RESTORE (1 << 9)
227 /* true: save or restore error */
228 #define STS_SRE (1 << 10)
229 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
230 #define STS_CNR XHCI_STS_CNR
231 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
232 #define STS_HCE (1 << 12)
233 /* bits 13:31 reserved and should be preserved */
236 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
237 * Generate a device notification event when the HC sees a transaction with a
238 * notification type that matches a bit set in this bit field.
240 #define DEV_NOTE_MASK (0xffff)
241 #define ENABLE_DEV_NOTE(x) (1 << (x))
242 /* Most of the device notification types should only be used for debug.
243 * SW does need to pay attention to function wake notifications.
245 #define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
247 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
248 /* bit 0 is the command ring cycle state */
249 /* stop ring operation after completion of the currently executing command */
250 #define CMD_RING_PAUSE (1 << 1)
251 /* stop ring immediately - abort the currently executing command */
252 #define CMD_RING_ABORT (1 << 2)
253 /* true: command ring is running */
254 #define CMD_RING_RUNNING (1 << 3)
255 /* bits 4:5 reserved and should be preserved */
256 /* Command Ring pointer - bit mask for the lower 32 bits. */
257 #define CMD_RING_RSVD_BITS (0x3f)
259 /* CONFIG - Configure Register - config_reg bitmasks */
260 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
261 #define MAX_DEVS(p) ((p) & 0xff)
262 /* bits 8:31 - reserved and should be preserved */
264 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
265 /* true: device connected */
266 #define PORT_CONNECT (1 << 0)
267 /* true: port enabled */
268 #define PORT_PE (1 << 1)
269 /* bit 2 reserved and zeroed */
270 /* true: port has an over-current condition */
271 #define PORT_OC (1 << 3)
272 /* true: port reset signaling asserted */
273 #define PORT_RESET (1 << 4)
274 /* Port Link State - bits 5:8
275 * A read gives the current link PM state of the port,
276 * a write with Link State Write Strobe set sets the link state.
278 #define PORT_PLS_MASK (0xf << 5)
279 #define XDEV_U0 (0x0 << 5)
280 #define XDEV_U2 (0x2 << 5)
281 #define XDEV_U3 (0x3 << 5)
282 #define XDEV_RESUME (0xf << 5)
283 /* true: port has power (see HCC_PPC) */
284 #define PORT_POWER (1 << 9)
285 /* bits 10:13 indicate device speed:
286 * 0 - undefined speed - port hasn't be initialized by a reset yet
293 #define DEV_SPEED_MASK (0xf << 10)
294 #define XDEV_FS (0x1 << 10)
295 #define XDEV_LS (0x2 << 10)
296 #define XDEV_HS (0x3 << 10)
297 #define XDEV_SS (0x4 << 10)
298 #define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
299 #define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
300 #define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
301 #define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
302 #define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
303 /* Bits 20:23 in the Slot Context are the speed for the device */
304 #define SLOT_SPEED_FS (XDEV_FS << 10)
305 #define SLOT_SPEED_LS (XDEV_LS << 10)
306 #define SLOT_SPEED_HS (XDEV_HS << 10)
307 #define SLOT_SPEED_SS (XDEV_SS << 10)
308 /* Port Indicator Control */
309 #define PORT_LED_OFF (0 << 14)
310 #define PORT_LED_AMBER (1 << 14)
311 #define PORT_LED_GREEN (2 << 14)
312 #define PORT_LED_MASK (3 << 14)
313 /* Port Link State Write Strobe - set this when changing link state */
314 #define PORT_LINK_STROBE (1 << 16)
315 /* true: connect status change */
316 #define PORT_CSC (1 << 17)
317 /* true: port enable change */
318 #define PORT_PEC (1 << 18)
319 /* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
320 * into an enabled state, and the device into the default state. A "warm" reset
321 * also resets the link, forcing the device through the link training sequence.
322 * SW can also look at the Port Reset register to see when warm reset is done.
324 #define PORT_WRC (1 << 19)
325 /* true: over-current change */
326 #define PORT_OCC (1 << 20)
327 /* true: reset change - 1 to 0 transition of PORT_RESET */
328 #define PORT_RC (1 << 21)
329 /* port link status change - set on some port link state transitions:
331 * ------------------------------------------------------------------------------
332 * - U3 to Resume Wakeup signaling from a device
333 * - Resume to Recovery to U0 USB 3.0 device resume
334 * - Resume to U0 USB 2.0 device resume
335 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
336 * - U3 to U0 Software resume of USB 2.0 device complete
337 * - U2 to U0 L1 resume of USB 2.1 device complete
338 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
339 * - U0 to disabled L1 entry error with USB 2.1 device
340 * - Any state to inactive Error on USB 3.0 port
342 #define PORT_PLC (1 << 22)
343 /* port configure error change - port failed to configure its link partner */
344 #define PORT_CEC (1 << 23)
345 /* Cold Attach Status - xHC can set this bit to report device attached during
346 * Sx state. Warm port reset should be perfomed to clear this bit and move port
347 * to connected state.
349 #define PORT_CAS (1 << 24)
350 /* wake on connect (enable) */
351 #define PORT_WKCONN_E (1 << 25)
352 /* wake on disconnect (enable) */
353 #define PORT_WKDISC_E (1 << 26)
354 /* wake on over-current (enable) */
355 #define PORT_WKOC_E (1 << 27)
356 /* bits 28:29 reserved */
357 /* true: device is removable - for USB 3.0 roothub emulation */
358 #define PORT_DEV_REMOVE (1 << 30)
359 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
360 #define PORT_WR (1 << 31)
362 /* We mark duplicate entries with -1 */
363 #define DUPLICATE_ENTRY ((u8)(-1))
365 /* Port Power Management Status and Control - port_power_base bitmasks */
366 /* Inactivity timer value for transitions into U1, in microseconds.
367 * Timeout can be up to 127us. 0xFF means an infinite timeout.
369 #define PORT_U1_TIMEOUT(p) ((p) & 0xff)
370 #define PORT_U1_TIMEOUT_MASK 0xff
371 /* Inactivity timer value for transitions into U2 */
372 #define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
373 #define PORT_U2_TIMEOUT_MASK (0xff << 8)
374 /* Bits 24:31 for port testing */
376 /* USB2 Protocol PORTSPMSC */
377 #define PORT_L1S_MASK 7
378 #define PORT_L1S_SUCCESS 1
379 #define PORT_RWE (1 << 3)
380 #define PORT_HIRD(p) (((p) & 0xf) << 4)
381 #define PORT_HIRD_MASK (0xf << 4)
382 #define PORT_L1DS(p) (((p) & 0xff) << 8)
383 #define PORT_HLE (1 << 16)
386 * struct xhci_intr_reg - Interrupt Register Set
387 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
388 * interrupts and check for pending interrupts.
389 * @irq_control: IMOD - Interrupt Moderation Register.
390 * Used to throttle interrupts.
391 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
392 * @erst_base: ERST base address.
393 * @erst_dequeue: Event ring dequeue pointer.
395 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
396 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
397 * multiple segments of the same size. The HC places events on the ring and
398 * "updates the Cycle bit in the TRBs to indicate to software the current
399 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
400 * updates the dequeue pointer.
402 struct xhci_intr_reg
{
411 /* irq_pending bitmasks */
412 #define ER_IRQ_PENDING(p) ((p) & 0x1)
413 /* bits 2:31 need to be preserved */
414 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
415 #define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
416 #define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
417 #define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
419 /* irq_control bitmasks */
420 /* Minimum interval between interrupts (in 250ns intervals). The interval
421 * between interrupts will be longer if there are no events on the event ring.
422 * Default is 4000 (1 ms).
424 #define ER_IRQ_INTERVAL_MASK (0xffff)
425 /* Counter used to count down the time to the next interrupt - HW use only */
426 #define ER_IRQ_COUNTER_MASK (0xffff << 16)
428 /* erst_size bitmasks */
429 /* Preserve bits 16:31 of erst_size */
430 #define ERST_SIZE_MASK (0xffff << 16)
432 /* erst_dequeue bitmasks */
433 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
434 * where the current dequeue pointer lies. This is an optional HW hint.
436 #define ERST_DESI_MASK (0x7)
437 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
438 * a work queue (or delayed service routine)?
440 #define ERST_EHB (1 << 3)
441 #define ERST_PTR_MASK (0xf)
444 * struct xhci_run_regs
446 * MFINDEX - current microframe number
448 * Section 5.5 Host Controller Runtime Registers:
449 * "Software should read and write these registers using only Dword (32 bit)
450 * or larger accesses"
452 struct xhci_run_regs
{
453 __le32 microframe_index
;
455 struct xhci_intr_reg ir_set
[128];
459 * struct doorbell_array
461 * Bits 0 - 7: Endpoint target
463 * Bits 16 - 31: Stream ID
467 struct xhci_doorbell_array
{
468 __le32 doorbell
[256];
471 #define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
472 #define DB_VALUE_HOST 0x00000000
475 * struct xhci_protocol_caps
476 * @revision: major revision, minor revision, capability ID,
477 * and next capability pointer.
478 * @name_string: Four ASCII characters to say which spec this xHC
479 * follows, typically "USB ".
480 * @port_info: Port offset, count, and protocol-defined information.
482 struct xhci_protocol_caps
{
488 #define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
489 #define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
490 #define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
493 * struct xhci_container_ctx
494 * @type: Type of context. Used to calculated offsets to contained contexts.
495 * @size: Size of the context data
496 * @bytes: The raw context data given to HW
497 * @dma: dma address of the bytes
499 * Represents either a Device or Input context. Holds a pointer to the raw
500 * memory used for the context (bytes) and dma address of it (dma).
502 struct xhci_container_ctx
{
504 #define XHCI_CTX_TYPE_DEVICE 0x1
505 #define XHCI_CTX_TYPE_INPUT 0x2
514 * struct xhci_slot_ctx
515 * @dev_info: Route string, device speed, hub info, and last valid endpoint
516 * @dev_info2: Max exit latency for device number, root hub port number
517 * @tt_info: tt_info is used to construct split transaction tokens
518 * @dev_state: slot state and device address
520 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
521 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
522 * reserved at the end of the slot context for HC internal use.
524 struct xhci_slot_ctx
{
529 /* offset 0x10 to 0x1f reserved for HC internal use */
533 /* dev_info bitmasks */
534 /* Route String - 0:19 */
535 #define ROUTE_STRING_MASK (0xfffff)
536 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
537 #define DEV_SPEED (0xf << 20)
538 /* bit 24 reserved */
539 /* Is this LS/FS device connected through a HS hub? - bit 25 */
540 #define DEV_MTT (0x1 << 25)
541 /* Set if the device is a hub - bit 26 */
542 #define DEV_HUB (0x1 << 26)
543 /* Index of the last valid endpoint context in this device context - 27:31 */
544 #define LAST_CTX_MASK (0x1f << 27)
545 #define LAST_CTX(p) ((p) << 27)
546 #define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
547 #define SLOT_FLAG (1 << 0)
548 #define EP0_FLAG (1 << 1)
550 /* dev_info2 bitmasks */
551 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
552 #define MAX_EXIT (0xffff)
553 /* Root hub port number that is needed to access the USB device */
554 #define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
555 #define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
556 /* Maximum number of ports under a hub device */
557 #define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
559 /* tt_info bitmasks */
561 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
562 * The Slot ID of the hub that isolates the high speed signaling from
563 * this low or full-speed device. '0' if attached to root hub port.
565 #define TT_SLOT (0xff)
567 * The number of the downstream facing port of the high-speed hub
568 * '0' if the device is not low or full speed.
570 #define TT_PORT (0xff << 8)
571 #define TT_THINK_TIME(p) (((p) & 0x3) << 16)
573 /* dev_state bitmasks */
574 /* USB device address - assigned by the HC */
575 #define DEV_ADDR_MASK (0xff)
576 /* bits 8:26 reserved */
578 #define SLOT_STATE (0x1f << 27)
579 #define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
581 #define SLOT_STATE_DISABLED 0
582 #define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
583 #define SLOT_STATE_DEFAULT 1
584 #define SLOT_STATE_ADDRESSED 2
585 #define SLOT_STATE_CONFIGURED 3
589 * @ep_info: endpoint state, streams, mult, and interval information.
590 * @ep_info2: information on endpoint type, max packet size, max burst size,
591 * error count, and whether the HC will force an event for all
593 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
594 * defines one stream, this points to the endpoint transfer ring.
595 * Otherwise, it points to a stream context array, which has a
596 * ring pointer for each flow.
598 * Average TRB lengths for the endpoint ring and
599 * max payload within an Endpoint Service Interval Time (ESIT).
601 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
602 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
603 * reserved at the end of the endpoint context for HC internal use.
610 /* offset 0x14 - 0x1f reserved for HC internal use */
614 /* ep_info bitmasks */
616 * Endpoint State - bits 0:2
619 * 2 - halted due to halt condition - ok to manipulate endpoint ring
624 #define EP_STATE_MASK (0xf)
625 #define EP_STATE_DISABLED 0
626 #define EP_STATE_RUNNING 1
627 #define EP_STATE_HALTED 2
628 #define EP_STATE_STOPPED 3
629 #define EP_STATE_ERROR 4
630 /* Mult - Max number of burtst within an interval, in EP companion desc. */
631 #define EP_MULT(p) (((p) & 0x3) << 8)
632 #define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
633 /* bits 10:14 are Max Primary Streams */
634 /* bit 15 is Linear Stream Array */
635 /* Interval - period between requests to an endpoint - 125u increments. */
636 #define EP_INTERVAL(p) (((p) & 0xff) << 16)
637 #define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
638 #define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
639 #define EP_MAXPSTREAMS_MASK (0x1f << 10)
640 #define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
641 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
642 #define EP_HAS_LSA (1 << 15)
644 /* ep_info2 bitmasks */
646 * Force Event - generate transfer events for all TRBs for this endpoint
647 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
649 #define FORCE_EVENT (0x1)
650 #define ERROR_COUNT(p) (((p) & 0x3) << 1)
651 #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
652 #define EP_TYPE(p) ((p) << 3)
653 #define ISOC_OUT_EP 1
654 #define BULK_OUT_EP 2
661 /* bit 7 is Host Initiate Disable - for disabling stream selection */
662 #define MAX_BURST(p) (((p)&0xff) << 8)
663 #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
664 #define MAX_PACKET(p) (((p)&0xffff) << 16)
665 #define MAX_PACKET_MASK (0xffff << 16)
666 #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
668 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
671 #define GET_MAX_PACKET(p) ((p) & 0x7ff)
673 /* tx_info bitmasks */
674 #define AVG_TRB_LENGTH_FOR_EP(p) ((p) & 0xffff)
675 #define MAX_ESIT_PAYLOAD_FOR_EP(p) (((p) & 0xffff) << 16)
676 #define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
679 #define EP_CTX_CYCLE_MASK (1 << 0)
681 #ifdef CONFIG_MTK_XHCI
682 /* mtk scheduler bitmasks */
683 #define BPKTS(p) ((p) & 0x3f)
684 #define BCSCOUNT(p) (((p) & 0x7) << 8)
685 #define BBM(p) ((p) << 11)
686 #define BOFFSET(p) ((p) & 0x3fff)
687 #define BREPEAT(p) (((p) & 0x7fff) << 16)
691 * struct xhci_input_control_context
692 * Input control context; see section 6.2.5.
694 * @drop_context: set the bit of the endpoint context you want to disable
695 * @add_context: set the bit of the endpoint context you want to enable
697 struct xhci_input_control_ctx
{
703 #define EP_IS_ADDED(ctrl_ctx, i) \
704 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
705 #define EP_IS_DROPPED(ctrl_ctx, i) \
706 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
708 /* Represents everything that is needed to issue a command on the command ring.
709 * It's useful to pre-allocate these for commands that cannot fail due to
710 * out-of-memory errors, like freeing streams.
712 struct xhci_command
{
713 /* Input context for changing device state */
714 struct xhci_container_ctx
*in_ctx
;
716 /* If completion is null, no one is waiting on this command
717 * and the structure can be freed after the command completes.
719 struct completion
*completion
;
720 union xhci_trb
*command_trb
;
721 struct list_head cmd_list
;
724 /* drop context bitmasks */
725 #define DROP_EP(x) (0x1 << x)
726 /* add context bitmasks */
727 #define ADD_EP(x) (0x1 << x)
729 struct xhci_stream_ctx
{
730 /* 64-bit stream ring address, cycle state, and stream type */
732 /* offset 0x14 - 0x1f reserved for HC internal use */
736 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
737 #define SCT_FOR_CTX(p) (((p) << 1) & 0x7)
738 /* Secondary stream array type, dequeue pointer is to a transfer ring */
740 /* Primary stream array type, dequeue pointer is to a transfer ring */
742 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
747 #define SCT_SSA_128 6
748 #define SCT_SSA_256 7
750 /* Assume no secondary streams for now */
751 struct xhci_stream_info
{
752 struct xhci_ring
**stream_rings
;
753 /* Number of streams, including stream 0 (which drivers can't use) */
754 unsigned int num_streams
;
755 /* The stream context array may be bigger than
756 * the number of streams the driver asked for
758 struct xhci_stream_ctx
*stream_ctx_array
;
759 unsigned int num_stream_ctxs
;
760 dma_addr_t ctx_array_dma
;
761 /* For mapping physical TRB addresses to segments in stream rings */
762 struct radix_tree_root trb_address_map
;
763 struct xhci_command
*free_streams_command
;
766 #define SMALL_STREAM_ARRAY_SIZE 256
767 #define MEDIUM_STREAM_ARRAY_SIZE 1024
769 /* Some Intel xHCI host controllers need software to keep track of the bus
770 * bandwidth. Keep track of endpoint info here. Each root port is allocated
771 * the full bus bandwidth. We must also treat TTs (including each port under a
772 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
773 * (DMI) also limits the total bandwidth (across all domains) that can be used.
775 struct xhci_bw_info
{
776 /* ep_interval is zero-based */
777 unsigned int ep_interval
;
778 /* mult and num_packets are one-based */
780 unsigned int num_packets
;
781 unsigned int max_packet_size
;
782 unsigned int max_esit_payload
;
786 /* "Block" sizes in bytes the hardware uses for different device speeds.
787 * The logic in this part of the hardware limits the number of bits the hardware
788 * can use, so must represent bandwidth in a less precise manner to mimic what
789 * the scheduler hardware computes.
796 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
797 * with each byte transferred. SuperSpeed devices have an initial overhead to
798 * set up bursts. These are in blocks, see above. LS overhead has already been
799 * translated into FS blocks.
801 #define DMI_OVERHEAD 8
802 #define DMI_OVERHEAD_BURST 4
803 #define SS_OVERHEAD 8
804 #define SS_OVERHEAD_BURST 32
805 #define HS_OVERHEAD 26
806 #define FS_OVERHEAD 20
807 #define LS_OVERHEAD 128
808 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
809 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
810 * of overhead associated with split transfers crossing microframe boundaries.
811 * 31 blocks is pure protocol overhead.
813 #define TT_HS_OVERHEAD (31 + 94)
814 #define TT_DMI_OVERHEAD (25 + 12)
816 /* Bandwidth limits in blocks */
817 #define FS_BW_LIMIT 1285
818 #define TT_BW_LIMIT 1320
819 #define HS_BW_LIMIT 1607
820 #define SS_BW_LIMIT_IN 3906
821 #define DMI_BW_LIMIT_IN 3906
822 #define SS_BW_LIMIT_OUT 3906
823 #define DMI_BW_LIMIT_OUT 3906
825 /* Percentage of bus bandwidth reserved for non-periodic transfers */
826 #define FS_BW_RESERVED 10
827 #define HS_BW_RESERVED 20
828 #define SS_BW_RESERVED 10
830 struct xhci_virt_ep
{
831 struct xhci_ring
*ring
;
832 /* Related to endpoints that are configured to use stream IDs only */
833 struct xhci_stream_info
*stream_info
;
834 /* Temporary storage in case the configure endpoint command fails and we
835 * have to restore the device state to the previous state
837 struct xhci_ring
*new_ring
;
838 unsigned int ep_state
;
839 #define SET_DEQ_PENDING (1 << 0)
840 #define EP_HALTED (1 << 1) /* For stall handling */
841 #define EP_HALT_PENDING (1 << 2) /* For URB cancellation */
842 /* Transitioning the endpoint to using streams, don't enqueue URBs */
843 #define EP_GETTING_STREAMS (1 << 3)
844 #define EP_HAS_STREAMS (1 << 4)
845 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
846 #define EP_GETTING_NO_STREAMS (1 << 5)
847 /* ---- Related to URB cancellation ---- */
848 struct list_head cancelled_td_list
;
849 /* The TRB that was last reported in a stopped endpoint ring */
850 union xhci_trb
*stopped_trb
;
851 struct xhci_td
*stopped_td
;
852 unsigned int stopped_stream
;
853 /* Watchdog timer for stop endpoint command to cancel URBs */
854 struct timer_list stop_cmd_timer
;
855 int stop_cmds_pending
;
856 struct xhci_hcd
*xhci
;
857 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
858 * command. We'll need to update the ring's dequeue segment and dequeue
859 * pointer after the command completes.
861 struct xhci_segment
*queued_deq_seg
;
862 union xhci_trb
*queued_deq_ptr
;
864 * Sometimes the xHC can not process isochronous endpoint ring quickly
865 * enough, and it will miss some isoc tds on the ring and generate
866 * a Missed Service Error Event.
867 * Set skip flag when receive a Missed Service Error Event and
868 * process the missed tds on the endpoint ring.
871 /* Bandwidth checking storage */
872 struct xhci_bw_info bw_info
;
873 struct list_head bw_endpoint_list
;
876 enum xhci_overhead_type
{
877 LS_OVERHEAD_TYPE
= 0,
882 struct xhci_interval_bw
{
883 unsigned int num_packets
;
884 /* Sorted by max packet size.
885 * Head of the list is the greatest max packet size.
887 struct list_head endpoints
;
888 /* How many endpoints of each speed are present. */
889 unsigned int overhead
[3];
892 #define XHCI_MAX_INTERVAL 16
894 struct xhci_interval_bw_table
{
895 unsigned int interval0_esit_payload
;
896 struct xhci_interval_bw interval_bw
[XHCI_MAX_INTERVAL
];
897 /* Includes reserved bandwidth for async endpoints */
898 unsigned int bw_used
;
899 unsigned int ss_bw_in
;
900 unsigned int ss_bw_out
;
904 struct xhci_virt_device
{
905 struct usb_device
*udev
;
907 * Commands to the hardware are passed an "input context" that
908 * tells the hardware what to change in its data structures.
909 * The hardware will return changes in an "output context" that
910 * software must allocate for the hardware. We need to keep
911 * track of input and output contexts separately because
912 * these commands might fail and we don't trust the hardware.
914 struct xhci_container_ctx
*out_ctx
;
915 /* Used for addressing devices and configuration changes */
916 struct xhci_container_ctx
*in_ctx
;
917 /* Rings saved to ensure old alt settings can be re-instated */
918 struct xhci_ring
**ring_cache
;
919 int num_rings_cached
;
920 /* Store xHC assigned device address */
922 #define XHCI_MAX_RINGS_CACHED 31
923 struct xhci_virt_ep eps
[31];
924 struct completion cmd_completion
;
925 /* Status of the last command issued for this device */
927 struct list_head cmd_list
;
930 struct xhci_interval_bw_table
*bw_table
;
931 struct xhci_tt_bw_info
*tt_info
;
932 /* The current max exit latency for the enabled USB3 link states. */
937 * For each roothub, keep track of the bandwidth information for each periodic
940 * If a high speed hub is attached to the roothub, each TT associated with that
941 * hub is a separate bandwidth domain. The interval information for the
942 * endpoints on the devices under that TT will appear in the TT structure.
944 struct xhci_root_port_bw_info
{
945 struct list_head tts
;
946 unsigned int num_active_tts
;
947 struct xhci_interval_bw_table bw_table
;
950 struct xhci_tt_bw_info
{
951 struct list_head tt_list
;
954 struct xhci_interval_bw_table bw_table
;
960 * struct xhci_device_context_array
961 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
963 struct xhci_device_context_array
{
964 /* 64-bit device addresses; we only write 32-bit addresses */
965 __le64 dev_context_ptrs
[MAX_HC_SLOTS
];
966 /* private xHCD pointers */
969 /* TODO: write function to set the 64-bit device DMA address */
971 * TODO: change this to be dynamically sized at HC mem init time since the HC
972 * might not be able to handle the maximum number of devices possible.
976 struct xhci_transfer_event
{
977 /* 64-bit buffer address, or immediate data */
980 /* This field is interpreted differently based on the type of TRB */
984 /* Transfer event TRB length bit mask */
986 #define EVENT_TRB_LEN(p) ((p) & 0xffffff)
988 /** Transfer Event bit fields **/
989 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
991 /* Completion Code - only applicable for some types of TRBs */
992 #define COMP_CODE_MASK (0xff << 24)
993 #define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
994 #define COMP_SUCCESS 1
995 /* Data Buffer Error */
996 #define COMP_DB_ERR 2
997 /* Babble Detected Error */
998 #define COMP_BABBLE 3
999 /* USB Transaction Error */
1000 #define COMP_TX_ERR 4
1001 /* TRB Error - some TRB field is invalid */
1002 #define COMP_TRB_ERR 5
1003 /* Stall Error - USB device is stalled */
1004 #define COMP_STALL 6
1005 /* Resource Error - HC doesn't have memory for that device configuration */
1006 #define COMP_ENOMEM 7
1007 /* Bandwidth Error - not enough room in schedule for this dev config */
1008 #define COMP_BW_ERR 8
1009 /* No Slots Available Error - HC ran out of device slots */
1010 #define COMP_ENOSLOTS 9
1011 /* Invalid Stream Type Error */
1012 #define COMP_STREAM_ERR 10
1013 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1014 #define COMP_EBADSLT 11
1015 /* Endpoint Not Enabled Error */
1016 #define COMP_EBADEP 12
1018 #define COMP_SHORT_TX 13
1019 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1020 #define COMP_UNDERRUN 14
1021 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1022 #define COMP_OVERRUN 15
1023 /* Virtual Function Event Ring Full Error */
1024 #define COMP_VF_FULL 16
1025 /* Parameter Error - Context parameter is invalid */
1026 #define COMP_EINVAL 17
1027 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1028 #define COMP_BW_OVER 18
1029 /* Context State Error - illegal context state transition requested */
1030 #define COMP_CTX_STATE 19
1031 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1032 #define COMP_PING_ERR 20
1033 /* Event Ring is full */
1034 #define COMP_ER_FULL 21
1035 /* Incompatible Device Error */
1036 #define COMP_DEV_ERR 22
1037 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1038 #define COMP_MISSED_INT 23
1039 /* Successfully stopped command ring */
1040 #define COMP_CMD_STOP 24
1041 /* Successfully aborted current command and stopped command ring */
1042 #define COMP_CMD_ABORT 25
1043 /* Stopped - transfer was terminated by a stop endpoint command */
1044 #define COMP_STOP 26
1045 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1046 #define COMP_STOP_INVAL 27
1047 /* Control Abort Error - Debug Capability - control pipe aborted */
1048 #define COMP_DBG_ABORT 28
1049 /* Max Exit Latency Too Large Error */
1050 #define COMP_MEL_ERR 29
1051 /* TRB type 30 reserved */
1052 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1053 #define COMP_BUFF_OVER 31
1054 /* Event Lost Error - xHC has an "internal event overrun condition" */
1055 #define COMP_ISSUES 32
1056 /* Undefined Error - reported when other error codes don't apply */
1057 #define COMP_UNKNOWN 33
1058 /* Invalid Stream ID Error */
1059 #define COMP_STRID_ERR 34
1060 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1061 #define COMP_2ND_BW_ERR 35
1062 /* Split Transaction Error */
1063 #define COMP_SPLIT_ERR 36
1065 struct xhci_link_trb
{
1066 /* 64-bit segment pointer*/
1072 /* control bitfields */
1073 #define LINK_TOGGLE (0x1<<1)
1075 /* Command completion event TRB */
1076 struct xhci_event_cmd
{
1077 /* Pointer to command TRB, or the value passed by the event data trb */
1083 /* flags bitmasks */
1084 /* bits 16:23 are the virtual function ID */
1085 /* bits 24:31 are the slot ID */
1086 #define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1087 #define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1089 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1090 #define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1091 #define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1093 #define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1094 #define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1095 #define LAST_EP_INDEX 30
1097 /* Set TR Dequeue Pointer command TRB fields */
1098 #define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1099 #define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1102 /* Port Status Change Event TRB fields */
1103 /* Port ID - bits 31:24 */
1104 #define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1106 /* Normal TRB fields */
1107 /* transfer_len bitmasks - bits 0:16 */
1108 #define TRB_LEN(p) ((p) & 0x1ffff)
1109 /* Interrupter Target - which MSI-X vector to target the completion event at */
1110 #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1111 #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1112 #define TRB_TBC(p) (((p) & 0x3) << 7)
1113 #define TRB_TLBPC(p) (((p) & 0xf) << 16)
1115 /* Cycle bit - indicates TRB ownership by HC or HCD */
1116 #define TRB_CYCLE (1<<0)
1118 * Force next event data TRB to be evaluated before task switch.
1119 * Used to pass OS data back after a TD completes.
1121 #define TRB_ENT (1<<1)
1122 /* Interrupt on short packet */
1123 #define TRB_ISP (1<<2)
1124 /* Set PCIe no snoop attribute */
1125 #define TRB_NO_SNOOP (1<<3)
1126 /* Chain multiple TRBs into a TD */
1127 #define TRB_CHAIN (1<<4)
1128 /* Interrupt on completion */
1129 #define TRB_IOC (1<<5)
1130 /* The buffer pointer contains immediate data */
1131 #define TRB_IDT (1<<6)
1133 /* Block Event Interrupt */
1134 #define TRB_BEI (1<<9)
1136 /* Control transfer TRB specific fields */
1137 #define TRB_DIR_IN (1<<16)
1138 #define TRB_TX_TYPE(p) ((p) << 16)
1139 #define TRB_DATA_OUT 2
1140 #define TRB_DATA_IN 3
1142 /* Isochronous TRB specific fields */
1143 #define TRB_SIA (1<<31)
1145 struct xhci_generic_trb
{
1150 struct xhci_link_trb link
;
1151 struct xhci_transfer_event trans_event
;
1152 struct xhci_event_cmd event_cmd
;
1153 struct xhci_generic_trb generic
;
1157 #define TRB_TYPE_BITMASK (0xfc00)
1158 #define TRB_TYPE(p) ((p) << 10)
1159 #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1161 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1162 #define TRB_NORMAL 1
1163 /* setup stage for control transfers */
1165 /* data stage for control transfers */
1167 /* status stage for control transfers */
1168 #define TRB_STATUS 4
1169 /* isoc transfers */
1171 /* TRB for linking ring segments */
1173 #define TRB_EVENT_DATA 7
1174 /* Transfer Ring No-op (not for the command ring) */
1175 #define TRB_TR_NOOP 8
1177 /* Enable Slot Command */
1178 #define TRB_ENABLE_SLOT 9
1179 /* Disable Slot Command */
1180 #define TRB_DISABLE_SLOT 10
1181 /* Address Device Command */
1182 #define TRB_ADDR_DEV 11
1183 /* Configure Endpoint Command */
1184 #define TRB_CONFIG_EP 12
1185 /* Evaluate Context Command */
1186 #define TRB_EVAL_CONTEXT 13
1187 /* Reset Endpoint Command */
1188 #define TRB_RESET_EP 14
1189 /* Stop Transfer Ring Command */
1190 #define TRB_STOP_RING 15
1191 /* Set Transfer Ring Dequeue Pointer Command */
1192 #define TRB_SET_DEQ 16
1193 /* Reset Device Command */
1194 #define TRB_RESET_DEV 17
1195 /* Force Event Command (opt) */
1196 #define TRB_FORCE_EVENT 18
1197 /* Negotiate Bandwidth Command (opt) */
1198 #define TRB_NEG_BANDWIDTH 19
1199 /* Set Latency Tolerance Value Command (opt) */
1200 #define TRB_SET_LT 20
1201 /* Get port bandwidth Command */
1202 #define TRB_GET_BW 21
1203 /* Force Header Command - generate a transaction or link management packet */
1204 #define TRB_FORCE_HEADER 22
1205 /* No-op Command - not for transfer rings */
1206 #define TRB_CMD_NOOP 23
1207 /* TRB IDs 24-31 reserved */
1209 /* Transfer Event */
1210 #define TRB_TRANSFER 32
1211 /* Command Completion Event */
1212 #define TRB_COMPLETION 33
1213 /* Port Status Change Event */
1214 #define TRB_PORT_STATUS 34
1215 /* Bandwidth Request Event (opt) */
1216 #define TRB_BANDWIDTH_EVENT 35
1217 /* Doorbell Event (opt) */
1218 #define TRB_DOORBELL 36
1219 /* Host Controller Event */
1220 #define TRB_HC_EVENT 37
1221 /* Device Notification Event - device sent function wake notification */
1222 #define TRB_DEV_NOTE 38
1223 /* MFINDEX Wrap Event - microframe counter wrapped */
1224 #define TRB_MFINDEX_WRAP 39
1225 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1227 /* Nec vendor-specific command completion event. */
1228 #define TRB_NEC_CMD_COMP 48
1229 /* Get NEC firmware revision. */
1230 #define TRB_NEC_GET_FW 49
1232 #define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1233 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1234 #define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1235 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1236 #define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1237 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1239 #define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1240 #define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1243 * TRBS_PER_SEGMENT must be a multiple of 4,
1244 * since the command ring is 64-byte aligned.
1245 * It must also be greater than 16.
1247 #define TRBS_PER_SEGMENT 64
1248 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1249 #define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1250 #define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1251 #define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1252 /* TRB buffer pointers can't cross 64KB boundaries */
1253 #define TRB_MAX_BUFF_SHIFT 16
1254 #define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1256 struct xhci_segment
{
1257 union xhci_trb
*trbs
;
1258 /* private to HCD */
1259 struct xhci_segment
*next
;
1264 struct list_head td_list
;
1265 struct list_head cancelled_td_list
;
1267 struct xhci_segment
*start_seg
;
1268 union xhci_trb
*first_trb
;
1269 union xhci_trb
*last_trb
;
1272 /* xHCI command default timeout value */
1273 #define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1275 /* command descriptor */
1277 struct list_head cancel_cmd_list
;
1278 struct xhci_command
*command
;
1279 union xhci_trb
*cmd_trb
;
1282 struct xhci_dequeue_state
{
1283 struct xhci_segment
*new_deq_seg
;
1284 union xhci_trb
*new_deq_ptr
;
1285 int new_cycle_state
;
1288 enum xhci_ring_type
{
1299 struct xhci_segment
*first_seg
;
1300 struct xhci_segment
*last_seg
;
1301 union xhci_trb
*enqueue
;
1302 struct xhci_segment
*enq_seg
;
1303 unsigned int enq_updates
;
1304 union xhci_trb
*dequeue
;
1305 struct xhci_segment
*deq_seg
;
1306 unsigned int deq_updates
;
1307 struct list_head td_list
;
1309 * Write the cycle state into the TRB cycle field to give ownership of
1310 * the TRB to the host controller (if we are the producer), or to check
1311 * if we own the TRB (if we are the consumer). See section 4.9.1.
1314 unsigned int stream_id
;
1315 unsigned int num_segs
;
1316 unsigned int num_trbs_free
;
1317 unsigned int num_trbs_free_temp
;
1318 enum xhci_ring_type type
;
1319 bool last_td_was_short
;
1322 struct xhci_erst_entry
{
1323 /* 64-bit event ring segment address */
1331 struct xhci_erst_entry
*entries
;
1332 unsigned int num_entries
;
1333 /* xhci->event_ring keeps track of segment dma addresses */
1334 dma_addr_t erst_dma_addr
;
1335 /* Num entries the ERST can contain */
1336 unsigned int erst_size
;
1339 struct xhci_scratchpad
{
1343 dma_addr_t
*sp_dma_buffers
;
1349 struct xhci_td
*td
[0];
1353 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1354 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1355 * meaning 64 ring segments.
1356 * Initial allocated size of the ERST, in number of entries */
1357 #define ERST_NUM_SEGS 1
1358 /* Initial allocated size of the ERST, in number of entries */
1359 #define ERST_SIZE 64
1360 /* Initial number of event segment rings allocated */
1361 #define ERST_ENTRIES 1
1362 /* Poll every 60 seconds */
1363 #define POLL_TIMEOUT 60
1364 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1365 #define XHCI_STOP_EP_CMD_TIMEOUT 5
1366 /* XXX: Make these module parameters */
1383 struct list_head list
;
1386 struct xhci_bus_state
{
1387 unsigned long bus_suspended
;
1388 unsigned long next_statechange
;
1390 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1391 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1393 u32 suspended_ports
;
1394 u32 port_remote_wakeup
;
1395 unsigned long resume_done
[USB_MAXCHILDREN
];
1396 /* which ports have started to resume */
1397 unsigned long resuming_ports
;
1400 static inline unsigned int hcd_index(struct usb_hcd
*hcd
)
1402 if (hcd
->speed
== HCD_USB3
)
1408 /* There is one xhci_hcd structure per controller */
1410 struct usb_hcd
*main_hcd
;
1411 struct usb_hcd
*shared_hcd
;
1412 /* glue to PCI and HCD framework */
1413 struct xhci_cap_regs __iomem
*cap_regs
;
1414 struct xhci_op_regs __iomem
*op_regs
;
1415 struct xhci_run_regs __iomem
*run_regs
;
1416 struct xhci_doorbell_array __iomem
*dba
;
1417 /* Our HCD's current interrupter register set */
1418 struct xhci_intr_reg __iomem
*ir_set
;
1420 #ifdef CONFIG_MTK_XHCI
1421 unsigned long base_regs
;
1422 unsigned long sif_regs
;
1423 unsigned long sif2_regs
;
1426 /* Cached register copies of read-only HC data */
1434 /* packed release number */
1438 u8 max_interrupters
;
1443 /* 4KB min, 128MB max */
1445 /* Valid values are 12 to 20, inclusive */
1449 struct msix_entry
*msix_entries
;
1450 /* data structures */
1451 struct xhci_device_context_array
*dcbaa
;
1452 struct xhci_ring
*cmd_ring
;
1453 unsigned int cmd_ring_state
;
1454 #define CMD_RING_STATE_RUNNING (1 << 0)
1455 #define CMD_RING_STATE_ABORTED (1 << 1)
1456 #define CMD_RING_STATE_STOPPED (1 << 2)
1457 struct list_head cancel_cmd_list
;
1458 unsigned int cmd_ring_reserved_trbs
;
1459 struct xhci_ring
*event_ring
;
1460 struct xhci_erst erst
;
1462 struct xhci_scratchpad
*scratchpad
;
1463 /* Store LPM test failed devices' information */
1464 struct list_head lpm_failed_devs
;
1466 /* slot enabling and address device helpers */
1467 struct completion addr_dev
;
1469 /* For USB 3.0 LPM enable/disable. */
1470 struct xhci_command
*lpm_command
;
1471 /* Internal mirror of the HW's dcbaa */
1472 struct xhci_virt_device
*devs
[MAX_HC_SLOTS
];
1473 /* For keeping track of bandwidth domains per roothub. */
1474 struct xhci_root_port_bw_info
*rh_bw
;
1477 struct dma_pool
*device_pool
;
1478 struct dma_pool
*segment_pool
;
1479 struct dma_pool
*small_streams_pool
;
1480 struct dma_pool
*medium_streams_pool
;
1482 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1483 /* Poll the rings - for debugging */
1484 struct timer_list event_ring_timer
;
1487 /* Host controller watchdog timer structures */
1488 unsigned int xhc_state
;
1492 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1494 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1495 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1496 * that sees this status (other than the timer that set it) should stop touching
1497 * hardware immediately. Interrupt handlers should return immediately when
1498 * they see this status (any time they drop and re-acquire xhci->lock).
1499 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1500 * putting the TD on the canceled list, etc.
1502 * There are no reports of xHCI host controllers that display this issue.
1504 #define XHCI_STATE_DYING (1 << 0)
1505 #define XHCI_STATE_HALTED (1 << 1)
1508 unsigned int quirks
;
1509 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1510 #define XHCI_RESET_EP_QUIRK (1 << 1)
1511 #define XHCI_NEC_HOST (1 << 2)
1512 #ifndef CONFIG_MTK_XHCI
1513 #define XHCI_AMD_PLL_FIX (1 << 3)
1515 #define XHCI_SPURIOUS_SUCCESS (1 << 4)
1517 * Certain Intel host controllers have a limit to the number of endpoint
1518 * contexts they can handle. Ideally, they would signal that they can't handle
1519 * anymore endpoint contexts by returning a Resource Error for the Configure
1520 * Endpoint command, but they don't. Instead they expect software to keep track
1521 * of the number of active endpoints for them, across configure endpoint
1522 * commands, reset device commands, disable slot commands, and address device
1525 #define XHCI_EP_LIMIT_QUIRK (1 << 5)
1526 #define XHCI_BROKEN_MSI (1 << 6)
1527 #define XHCI_RESET_ON_RESUME (1 << 7)
1528 #define XHCI_SW_BW_CHECKING (1 << 8)
1529 #ifndef CONFIG_MTK_XHCI
1530 #define XHCI_AMD_0x96_HOST (1 << 9)
1532 #define XHCI_TRUST_TX_LENGTH (1 << 10)
1533 #define XHCI_LPM_SUPPORT (1 << 11)
1534 #define XHCI_INTEL_HOST (1 << 12)
1535 #define XHCI_SPURIOUS_REBOOT (1 << 13)
1536 #define XHCI_COMP_MODE_QUIRK (1 << 14)
1537 #define XHCI_AVOID_BEI (1 << 15)
1538 #define XHCI_PLAT (1 << 16)
1539 unsigned int num_active_eps
;
1540 unsigned int limit_active_eps
;
1541 /* There are two roothubs to keep track of bus suspend info for */
1542 struct xhci_bus_state bus_state
[2];
1543 /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1545 /* Array of pointers to USB 3.0 PORTSC registers */
1546 __le32 __iomem
**usb3_ports
;
1547 unsigned int num_usb3_ports
;
1548 /* Array of pointers to USB 2.0 PORTSC registers */
1549 __le32 __iomem
**usb2_ports
;
1550 unsigned int num_usb2_ports
;
1551 /* support xHCI 0.96 spec USB2 software LPM */
1552 unsigned sw_lpm_support
:1;
1553 /* support xHCI 1.0 spec USB2 hardware LPM */
1554 unsigned hw_lpm_support
:1;
1555 /* Compliance Mode Recovery Data */
1556 struct timer_list comp_mode_recovery_timer
;
1558 /* Compliance Mode Timer Triggered every 2 seconds */
1559 #define COMP_MODE_RCVRY_MSECS 2000
1562 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1563 static inline struct xhci_hcd
*hcd_to_xhci(struct usb_hcd
*hcd
)
1565 return *((struct xhci_hcd
**) (hcd
->hcd_priv
));
1568 static inline struct usb_hcd
*xhci_to_hcd(struct xhci_hcd
*xhci
)
1570 return xhci
->main_hcd
;
1573 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1574 #define XHCI_DEBUG 1
1576 #define XHCI_DEBUG 0
1579 #define xhci_dbg(xhci, fmt, args...) \
1580 do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1581 #define xhci_info(xhci, fmt, args...) \
1582 do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1583 #define xhci_err(xhci, fmt, args...) \
1584 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1585 #define xhci_warn(xhci, fmt, args...) \
1586 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1587 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1588 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1590 /* TODO: copied from ehci.h - can be refactored? */
1591 /* xHCI spec says all registers are little endian */
1592 static inline unsigned int xhci_readl(const struct xhci_hcd
*xhci
,
1597 static inline void xhci_writel(struct xhci_hcd
*xhci
,
1598 const unsigned int val
, void __iomem
*regs
)
1604 * Registers should always be accessed with double word or quad word accesses.
1606 * Some xHCI implementations may support 64-bit address pointers. Registers
1607 * with 64-bit address pointers should be written to with dword accesses by
1608 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1609 * xHCI implementations that do not support 64-bit address pointers will ignore
1610 * the high dword, and write order is irrelevant.
1612 static inline u64
xhci_read_64(const struct xhci_hcd
*xhci
,
1613 __le64 __iomem
*regs
)
1615 __u32 __iomem
*ptr
= (__u32 __iomem
*) regs
;
1616 u64 val_lo
= readl(ptr
);
1617 u64 val_hi
= readl(ptr
+ 1);
1618 return val_lo
+ (val_hi
<< 32);
1620 static inline void xhci_write_64(struct xhci_hcd
*xhci
,
1621 const u64 val
, __le64 __iomem
*regs
)
1623 __u32 __iomem
*ptr
= (__u32 __iomem
*) regs
;
1624 u32 val_lo
= lower_32_bits(val
);
1625 u32 val_hi
= upper_32_bits(val
);
1627 writel(val_lo
, ptr
);
1628 writel(val_hi
, ptr
+ 1);
1631 static inline int xhci_link_trb_quirk(struct xhci_hcd
*xhci
)
1633 return xhci
->quirks
& XHCI_LINK_TRB_QUIRK
;
1636 /* xHCI debugging */
1637 void xhci_print_ir_set(struct xhci_hcd
*xhci
, int set_num
);
1638 void xhci_print_registers(struct xhci_hcd
*xhci
);
1639 void xhci_dbg_regs(struct xhci_hcd
*xhci
);
1640 void xhci_print_run_regs(struct xhci_hcd
*xhci
);
1641 void xhci_print_trb_offsets(struct xhci_hcd
*xhci
, union xhci_trb
*trb
);
1642 void xhci_debug_trb(struct xhci_hcd
*xhci
, union xhci_trb
*trb
);
1643 void xhci_debug_segment(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
);
1644 void xhci_debug_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
);
1645 void xhci_dbg_erst(struct xhci_hcd
*xhci
, struct xhci_erst
*erst
);
1646 void xhci_dbg_cmd_ptrs(struct xhci_hcd
*xhci
);
1647 void xhci_dbg_ring_ptrs(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
);
1648 void xhci_dbg_ctx(struct xhci_hcd
*xhci
, struct xhci_container_ctx
*ctx
, unsigned int last_ep
);
1649 char *xhci_get_slot_state(struct xhci_hcd
*xhci
,
1650 struct xhci_container_ctx
*ctx
);
1651 void xhci_dbg_ep_rings(struct xhci_hcd
*xhci
,
1652 unsigned int slot_id
, unsigned int ep_index
,
1653 struct xhci_virt_ep
*ep
);
1655 /* xHCI memory management */
1656 void xhci_mem_cleanup(struct xhci_hcd
*xhci
);
1657 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
);
1658 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
);
1659 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
, struct usb_device
*udev
, gfp_t flags
);
1660 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
);
1661 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
1662 struct usb_device
*udev
);
1663 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor
*desc
);
1664 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor
*desc
);
1665 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index
);
1666 unsigned int xhci_last_valid_endpoint(u32 added_ctxs
);
1667 void xhci_endpoint_zero(struct xhci_hcd
*xhci
, struct xhci_virt_device
*virt_dev
, struct usb_host_endpoint
*ep
);
1668 void xhci_drop_ep_from_interval_table(struct xhci_hcd
*xhci
,
1669 struct xhci_bw_info
*ep_bw
,
1670 struct xhci_interval_bw_table
*bw_table
,
1671 struct usb_device
*udev
,
1672 struct xhci_virt_ep
*virt_ep
,
1673 struct xhci_tt_bw_info
*tt_info
);
1674 void xhci_update_tt_active_eps(struct xhci_hcd
*xhci
,
1675 struct xhci_virt_device
*virt_dev
,
1676 int old_active_eps
);
1677 void xhci_clear_endpoint_bw_info(struct xhci_bw_info
*bw_info
);
1678 void xhci_update_bw_info(struct xhci_hcd
*xhci
,
1679 struct xhci_container_ctx
*in_ctx
,
1680 struct xhci_input_control_ctx
*ctrl_ctx
,
1681 struct xhci_virt_device
*virt_dev
);
1682 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1683 struct xhci_container_ctx
*in_ctx
,
1684 struct xhci_container_ctx
*out_ctx
,
1685 unsigned int ep_index
);
1686 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1687 struct xhci_container_ctx
*in_ctx
,
1688 struct xhci_container_ctx
*out_ctx
);
1689 int xhci_endpoint_init(struct xhci_hcd
*xhci
, struct xhci_virt_device
*virt_dev
,
1690 struct usb_device
*udev
, struct usb_host_endpoint
*ep
,
1692 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
);
1693 int xhci_ring_expansion(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1694 unsigned int num_trbs
, gfp_t flags
);
1695 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd
*xhci
,
1696 struct xhci_virt_device
*virt_dev
,
1697 unsigned int ep_index
);
1698 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
1699 unsigned int num_stream_ctxs
,
1700 unsigned int num_streams
, gfp_t flags
);
1701 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
1702 struct xhci_stream_info
*stream_info
);
1703 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
1704 struct xhci_ep_ctx
*ep_ctx
,
1705 struct xhci_stream_info
*stream_info
);
1706 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
1707 struct xhci_ep_ctx
*ep_ctx
,
1708 struct xhci_virt_ep
*ep
);
1709 void xhci_free_device_endpoint_resources(struct xhci_hcd
*xhci
,
1710 struct xhci_virt_device
*virt_dev
, bool drop_control_ep
);
1711 struct xhci_ring
*xhci_dma_to_transfer_ring(
1712 struct xhci_virt_ep
*ep
,
1714 struct xhci_ring
*xhci_stream_id_to_ring(
1715 struct xhci_virt_device
*dev
,
1716 unsigned int ep_index
,
1717 unsigned int stream_id
);
1718 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1719 bool allocate_in_ctx
, bool allocate_completion
,
1721 void xhci_urb_free_priv(struct xhci_hcd
*xhci
, struct urb_priv
*urb_priv
);
1722 void xhci_free_command(struct xhci_hcd
*xhci
,
1723 struct xhci_command
*command
);
1727 int xhci_register_pci(void);
1728 void xhci_unregister_pci(void);
1730 static inline int xhci_register_pci(void) { return 0; }
1731 static inline void xhci_unregister_pci(void) {}
1734 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1735 || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1736 int xhci_register_plat(void);
1737 void xhci_unregister_plat(void);
1739 static inline int xhci_register_plat(void)
1741 static inline void xhci_unregister_plat(void)
1745 /* xHCI host controller glue */
1746 typedef void (*xhci_get_quirks_t
)(struct device
*, struct xhci_hcd
*);
1747 int xhci_handshake(struct xhci_hcd
*xhci
, void __iomem
*ptr
,
1748 u32 mask
, u32 done
, int usec
);
1749 void xhci_quiesce(struct xhci_hcd
*xhci
);
1750 int xhci_halt(struct xhci_hcd
*xhci
);
1751 int xhci_reset(struct xhci_hcd
*xhci
);
1752 int xhci_init(struct usb_hcd
*hcd
);
1753 int xhci_run(struct usb_hcd
*hcd
);
1754 void xhci_stop(struct usb_hcd
*hcd
);
1755 void xhci_shutdown(struct usb_hcd
*hcd
);
1756 int xhci_gen_setup(struct usb_hcd
*hcd
, xhci_get_quirks_t get_quirks
);
1759 int xhci_suspend(struct xhci_hcd
*xhci
);
1760 int xhci_resume(struct xhci_hcd
*xhci
, bool hibernated
);
1762 #define xhci_suspend NULL
1763 #define xhci_resume NULL
1766 int xhci_get_frame(struct usb_hcd
*hcd
);
1767 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
);
1768 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
);
1769 int xhci_alloc_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
);
1770 void xhci_free_dev(struct usb_hcd
*hcd
, struct usb_device
*udev
);
1771 int xhci_alloc_tt_info(struct xhci_hcd
*xhci
,
1772 struct xhci_virt_device
*virt_dev
,
1773 struct usb_device
*hdev
,
1774 struct usb_tt
*tt
, gfp_t mem_flags
);
1775 int xhci_alloc_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1776 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
1777 unsigned int num_streams
, gfp_t mem_flags
);
1778 int xhci_free_streams(struct usb_hcd
*hcd
, struct usb_device
*udev
,
1779 struct usb_host_endpoint
**eps
, unsigned int num_eps
,
1781 int xhci_address_device(struct usb_hcd
*hcd
, struct usb_device
*udev
);
1782 int xhci_update_device(struct usb_hcd
*hcd
, struct usb_device
*udev
);
1783 int xhci_set_usb2_hardware_lpm(struct usb_hcd
*hcd
,
1784 struct usb_device
*udev
, int enable
);
1785 int xhci_update_hub_device(struct usb_hcd
*hcd
, struct usb_device
*hdev
,
1786 struct usb_tt
*tt
, gfp_t mem_flags
);
1787 int xhci_urb_enqueue(struct usb_hcd
*hcd
, struct urb
*urb
, gfp_t mem_flags
);
1788 int xhci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
);
1789 int xhci_add_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
, struct usb_host_endpoint
*ep
);
1790 int xhci_drop_endpoint(struct usb_hcd
*hcd
, struct usb_device
*udev
, struct usb_host_endpoint
*ep
);
1791 void xhci_endpoint_reset(struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
);
1792 int xhci_discover_or_reset_device(struct usb_hcd
*hcd
, struct usb_device
*udev
);
1793 int xhci_check_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
);
1794 void xhci_reset_bandwidth(struct usb_hcd
*hcd
, struct usb_device
*udev
);
1796 /* xHCI ring, segment, TRB, and TD functions */
1797 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
, union xhci_trb
*trb
);
1798 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1799 union xhci_trb
*start_trb
, union xhci_trb
*end_trb
,
1800 dma_addr_t suspect_dma
);
1801 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
);
1802 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
);
1803 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
);
1804 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1806 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
1807 u32 field1
, u32 field2
, u32 field3
, u32 field4
);
1808 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1809 unsigned int ep_index
, int suspend
);
1810 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
, struct urb
*urb
,
1811 int slot_id
, unsigned int ep_index
);
1812 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
, struct urb
*urb
,
1813 int slot_id
, unsigned int ep_index
);
1814 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
, struct urb
*urb
,
1815 int slot_id
, unsigned int ep_index
);
1816 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1817 struct urb
*urb
, int slot_id
, unsigned int ep_index
);
1818 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1819 u32 slot_id
, bool command_must_succeed
);
1820 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1821 u32 slot_id
, bool command_must_succeed
);
1822 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1823 unsigned int ep_index
);
1824 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
);
1825 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
1826 unsigned int slot_id
, unsigned int ep_index
,
1827 unsigned int stream_id
, struct xhci_td
*cur_td
,
1828 struct xhci_dequeue_state
*state
);
1829 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
1830 unsigned int slot_id
, unsigned int ep_index
,
1831 unsigned int stream_id
,
1832 struct xhci_dequeue_state
*deq_state
);
1833 void xhci_cleanup_stalled_ring(struct xhci_hcd
*xhci
,
1834 struct usb_device
*udev
, unsigned int ep_index
);
1835 void xhci_queue_config_ep_quirk(struct xhci_hcd
*xhci
,
1836 unsigned int slot_id
, unsigned int ep_index
,
1837 struct xhci_dequeue_state
*deq_state
);
1838 void xhci_stop_endpoint_command_watchdog(unsigned long arg
);
1839 int xhci_cancel_cmd(struct xhci_hcd
*xhci
, struct xhci_command
*command
,
1840 union xhci_trb
*cmd_trb
);
1841 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
, unsigned int slot_id
,
1842 unsigned int ep_index
, unsigned int stream_id
);
1843 union xhci_trb
*xhci_find_next_enqueue(struct xhci_ring
*ring
);
1845 /* xHCI roothub code */
1846 void xhci_set_link_state(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
1847 int port_id
, u32 link_state
);
1848 int xhci_enable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
1849 struct usb_device
*udev
, enum usb3_link_state state
);
1850 int xhci_disable_usb3_lpm_timeout(struct usb_hcd
*hcd
,
1851 struct usb_device
*udev
, enum usb3_link_state state
);
1852 void xhci_test_and_clear_bit(struct xhci_hcd
*xhci
, __le32 __iomem
**port_array
,
1853 int port_id
, u32 port_bit
);
1854 int xhci_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
, u16 wIndex
,
1855 char *buf
, u16 wLength
);
1856 int xhci_hub_status_data(struct usb_hcd
*hcd
, char *buf
);
1857 int xhci_find_raw_port_number(struct usb_hcd
*hcd
, int port1
);
1860 int xhci_bus_suspend(struct usb_hcd
*hcd
);
1861 int xhci_bus_resume(struct usb_hcd
*hcd
);
1863 #define xhci_bus_suspend NULL
1864 #define xhci_bus_resume NULL
1865 #endif /* CONFIG_PM */
1867 u32
xhci_port_state_to_neutral(u32 state
);
1868 int xhci_find_slot_id_by_port(struct usb_hcd
*hcd
, struct xhci_hcd
*xhci
,
1870 void xhci_ring_device(struct xhci_hcd
*xhci
, int slot_id
);
1873 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_hcd
*xhci
, struct xhci_container_ctx
*ctx
);
1874 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
, struct xhci_container_ctx
*ctx
);
1875 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
, struct xhci_container_ctx
*ctx
, unsigned int ep_index
);
1878 bool xhci_compliance_mode_recovery_timer_quirk_check(void);
1880 #endif /* __LINUX_XHCI_HCD_H */