drivers/usb/host/xhci.h

   1
   2 /*
   3  * xHCI host controller driver
   4  *
   5  * Copyright (C) 2008 Intel Corp.
   6  *
   7  * Author: Sarah Sharp
   8  * Some code borrowed from the Linux EHCI driver.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  * for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software Foundation,
  21  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22  */
  23
  24 #ifndef __LINUX_XHCI_HCD_H
  25 #define __LINUX_XHCI_HCD_H
  26
  27 #include <linux/usb.h>
  28 #include <linux/timer.h>
  29 #include <linux/kernel.h>
  30 #include <linux/usb/hcd.h>
  31
  32 /* Code sharing between pci-quirks and xhci hcd */
  33 #include        "xhci-ext-caps.h"
  34 #include "pci-quirks.h"
  35
  36
  37 /* xHCI PCI Configuration Registers */
  38 #define XHCI_SBRN_OFFSET        (0x60)
  39
  40 /* Max number of USB devices for any host controller - limit in section 6.1 */
  41 #define MAX_HC_SLOTS            256
  42 /* Section 5.3.3 - MaxPorts */
  43 #define MAX_HC_PORTS            127
  44
  45 /*
  46  * xHCI register interface.
  47  * This corresponds to the eXtensible Host Controller Interface (xHCI)
  48  * Revision 0.95 specification
  49  */
  50
  51 /**
  52  * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
  53  * @hc_capbase:         length of the capabilities register and HC version number
  54  * @hcs_params1:        HCSPARAMS1 - Structural Parameters 1
  55  * @hcs_params2:        HCSPARAMS2 - Structural Parameters 2
  56  * @hcs_params3:        HCSPARAMS3 - Structural Parameters 3
  57  * @hcc_params:         HCCPARAMS - Capability Parameters
  58  * @db_off:             DBOFF - Doorbell array offset
  59  * @run_regs_off:       RTSOFF - Runtime register space offset
  60  */
  61 struct xhci_cap_regs {
  62         __le32  hc_capbase;
  63         __le32  hcs_params1;
  64         __le32  hcs_params2;
  65         __le32  hcs_params3;
  66         __le32  hcc_params;
  67         __le32  db_off;
  68         __le32  run_regs_off;
  69         /* Reserved up to (CAPLENGTH - 0x1C) */
  70 };
  71
  72 /* hc_capbase bitmasks */
  73 /* bits 7:0 - how long is the Capabilities register */
  74 #define HC_LENGTH(p)            XHCI_HC_LENGTH(p)
  75 /* bits 31:16   */
  76 #define HC_VERSION(p)           (((p) >> 16) & 0xffff)
  77
  78 /* HCSPARAMS1 - hcs_params1 - bitmasks */
  79 /* bits 0:7, Max Device Slots */
  80 #define HCS_MAX_SLOTS(p)        (((p) >> 0) & 0xff)
  81 #define HCS_SLOTS_MASK          0xff
  82 /* bits 8:18, Max Interrupters */
  83 #define HCS_MAX_INTRS(p)        (((p) >> 8) & 0x7ff)
  84 /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
  85 #define HCS_MAX_PORTS(p)        (((p) >> 24) & 0x7f)
  86
  87 /* HCSPARAMS2 - hcs_params2 - bitmasks */
  88 /* bits 0:3, frames or uframes that SW needs to queue transactions
  89  * ahead of the HW to meet periodic deadlines */
  90 #define HCS_IST(p)              (((p) >> 0) & 0xf)
  91 /* bits 4:7, max number of Event Ring segments */
  92 #define HCS_ERST_MAX(p)         (((p) >> 4) & 0xf)
  93 /* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
  94 /* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
  95 /* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
  96 #define HCS_MAX_SCRATCHPAD(p)   ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
  97
  98 /* HCSPARAMS3 - hcs_params3 - bitmasks */
  99 /* bits 0:7, Max U1 to U0 latency for the roothub ports */
 100 #define HCS_U1_LATENCY(p)       (((p) >> 0) & 0xff)
 101 /* bits 16:31, Max U2 to U0 latency for the roothub ports */
 102 #define HCS_U2_LATENCY(p)       (((p) >> 16) & 0xffff)
 103
 104 /* HCCPARAMS - hcc_params - bitmasks */
 105 /* true: HC can use 64-bit address pointers */
 106 #define HCC_64BIT_ADDR(p)       ((p) & (1 << 0))
 107 /* true: HC can do bandwidth negotiation */
 108 #define HCC_BANDWIDTH_NEG(p)    ((p) & (1 << 1))
 109 /* true: HC uses 64-byte Device Context structures
 110  * FIXME 64-byte context structures aren't supported yet.
 111  */
 112 #define HCC_64BYTE_CONTEXT(p)   ((p) & (1 << 2))
 113 /* true: HC has port power switches */
 114 #define HCC_PPC(p)              ((p) & (1 << 3))
 115 /* true: HC has port indicators */
 116 #define HCS_INDICATOR(p)        ((p) & (1 << 4))
 117 /* true: HC has Light HC Reset Capability */
 118 #define HCC_LIGHT_RESET(p)      ((p) & (1 << 5))
 119 /* true: HC supports latency tolerance messaging */
 120 #define HCC_LTC(p)              ((p) & (1 << 6))
 121 /* true: no secondary Stream ID Support */
 122 #define HCC_NSS(p)              ((p) & (1 << 7))
 123 /* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
 124 #define HCC_MAX_PSA(p)          (1 << ((((p) >> 12) & 0xf) + 1))
 125 /* Extended Capabilities pointer from PCI base - section 5.3.6 */
 126 #define HCC_EXT_CAPS(p)         XHCI_HCC_EXT_CAPS(p)
 127
 128 /* db_off bitmask - bits 0:1 reserved */
 129 #define DBOFF_MASK      (~0x3)
 130
 131 /* run_regs_off bitmask - bits 0:4 reserved */
 132 #define RTSOFF_MASK     (~0x1f)
 133
 134
 135 /* Number of registers per port */
 136 #define NUM_PORT_REGS   4
 137
 138 /**
 139  * struct xhci_op_regs - xHCI Host Controller Operational Registers.
 140  * @command:            USBCMD - xHC command register
 141  * @status:             USBSTS - xHC status register
 142  * @page_size:          This indicates the page size that the host controller
 143  *                      supports.  If bit n is set, the HC supports a page size
 144  *                      of 2^(n+12), up to a 128MB page size.
 145  *                      4K is the minimum page size.
 146  * @cmd_ring:           CRP - 64-bit Command Ring Pointer
 147  * @dcbaa_ptr:          DCBAAP - 64-bit Device Context Base Address Array Pointer
 148  * @config_reg:         CONFIG - Configure Register
 149  * @port_status_base:   PORTSCn - base address for Port Status and Control
 150  *                      Each port has a Port Status and Control register,
 151  *                      followed by a Port Power Management Status and Control
 152  *                      register, a Port Link Info register, and a reserved
 153  *                      register.
 154  * @port_power_base:    PORTPMSCn - base address for
 155  *                      Port Power Management Status and Control
 156  * @port_link_base:     PORTLIn - base address for Port Link Info (current
 157  *                      Link PM state and control) for USB 2.1 and USB 3.0
 158  *                      devices.
 159  */
 160 struct xhci_op_regs {
 161         __le32  command;
 162         __le32  status;
 163         __le32  page_size;
 164         __le32  reserved1;
 165         __le32  reserved2;
 166         __le32  dev_notification;
 167         __le64  cmd_ring;
 168         /* rsvd: offset 0x20-2F */
 169         __le32  reserved3[4];
 170         __le64  dcbaa_ptr;
 171         __le32  config_reg;
 172         /* rsvd: offset 0x3C-3FF */
 173         __le32  reserved4[241];
 174         /* port 1 registers, which serve as a base address for other ports */
 175         __le32  port_status_base;
 176         __le32  port_power_base;
 177         __le32  port_link_base;
 178         __le32  reserved5;
 179         /* registers for ports 2-255 */
 180         __le32  reserved6[NUM_PORT_REGS*254];
 181 };
 182
 183 /* USBCMD - USB command - command bitmasks */
 184 /* start/stop HC execution - do not write unless HC is halted*/
 185 #define CMD_RUN         XHCI_CMD_RUN
 186 /* Reset HC - resets internal HC state machine and all registers (except
 187  * PCI config regs).  HC does NOT drive a USB reset on the downstream ports.
 188  * The xHCI driver must reinitialize the xHC after setting this bit.
 189  */
 190 #define CMD_RESET       (1 << 1)
 191 /* Event Interrupt Enable - a '1' allows interrupts from the host controller */
 192 #define CMD_EIE         XHCI_CMD_EIE
 193 /* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
 194 #define CMD_HSEIE       XHCI_CMD_HSEIE
 195 /* bits 4:6 are reserved (and should be preserved on writes). */
 196 /* light reset (port status stays unchanged) - reset completed when this is 0 */
 197 #define CMD_LRESET      (1 << 7)
 198 /* host controller save/restore state. */
 199 #define CMD_CSS         (1 << 8)
 200 #define CMD_CRS         (1 << 9)
 201 /* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
 202 #define CMD_EWE         XHCI_CMD_EWE
 203 /* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
 204  * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
 205  * '0' means the xHC can power it off if all ports are in the disconnect,
 206  * disabled, or powered-off state.
 207  */
 208 #define CMD_PM_INDEX    (1 << 11)
 209 /* bits 12:31 are reserved (and should be preserved on writes). */
 210
 211 /* IMAN - Interrupt Management Register */
 212 #define IMAN_IE         (1 << 1)
 213 #define IMAN_IP         (1 << 0)
 214
 215 /* USBSTS - USB status - status bitmasks */
 216 /* HC not running - set to 1 when run/stop bit is cleared. */
 217 #define STS_HALT        XHCI_STS_HALT
 218 /* serious error, e.g. PCI parity error.  The HC will clear the run/stop bit. */
 219 #define STS_FATAL       (1 << 2)
 220 /* event interrupt - clear this prior to clearing any IP flags in IR set*/
 221 #define STS_EINT        (1 << 3)
 222 /* port change detect */
 223 #define STS_PORT        (1 << 4)
 224 /* bits 5:7 reserved and zeroed */
 225 /* save state status - '1' means xHC is saving state */
 226 #define STS_SAVE        (1 << 8)
 227 /* restore state status - '1' means xHC is restoring state */
 228 #define STS_RESTORE     (1 << 9)
 229 /* true: save or restore error */
 230 #define STS_SRE         (1 << 10)
 231 /* true: Controller Not Ready to accept doorbell or op reg writes after reset */
 232 #define STS_CNR         XHCI_STS_CNR
 233 /* true: internal Host Controller Error - SW needs to reset and reinitialize */
 234 #define STS_HCE         (1 << 12)
 235 /* bits 13:31 reserved and should be preserved */
 236
 237 /*
 238  * DNCTRL - Device Notification Control Register - dev_notification bitmasks
 239  * Generate a device notification event when the HC sees a transaction with a
 240  * notification type that matches a bit set in this bit field.
 241  */
 242 #define DEV_NOTE_MASK           (0xffff)
 243 #define ENABLE_DEV_NOTE(x)      (1 << (x))
 244 /* Most of the device notification types should only be used for debug.
 245  * SW does need to pay attention to function wake notifications.
 246  */
 247 #define DEV_NOTE_FWAKE          ENABLE_DEV_NOTE(1)
 248
 249 /* CRCR - Command Ring Control Register - cmd_ring bitmasks */
 250 /* bit 0 is the command ring cycle state */
 251 /* stop ring operation after completion of the currently executing command */
 252 #define CMD_RING_PAUSE          (1 << 1)
 253 /* stop ring immediately - abort the currently executing command */
 254 #define CMD_RING_ABORT          (1 << 2)
 255 /* true: command ring is running */
 256 #define CMD_RING_RUNNING        (1 << 3)
 257 /* bits 4:5 reserved and should be preserved */
 258 /* Command Ring pointer - bit mask for the lower 32 bits. */
 259 #define CMD_RING_RSVD_BITS      (0x3f)
 260
 261 /* CONFIG - Configure Register - config_reg bitmasks */
 262 /* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
 263 #define MAX_DEVS(p)     ((p) & 0xff)
 264 /* bits 8:31 - reserved and should be preserved */
 265
 266 /* PORTSC - Port Status and Control Register - port_status_base bitmasks */
 267 /* true: device connected */
 268 #define PORT_CONNECT    (1 << 0)
 269 /* true: port enabled */
 270 #define PORT_PE         (1 << 1)
 271 /* bit 2 reserved and zeroed */
 272 /* true: port has an over-current condition */
 273 #define PORT_OC         (1 << 3)
 274 /* true: port reset signaling asserted */
 275 #define PORT_RESET      (1 << 4)
 276 /* Port Link State - bits 5:8
 277  * A read gives the current link PM state of the port,
 278  * a write with Link State Write Strobe set sets the link state.
 279  */
 280 #define PORT_PLS_MASK   (0xf << 5)
 281 #define XDEV_U0         (0x0 << 5)
 282 #define XDEV_U2         (0x2 << 5)
 283 #define XDEV_U3         (0x3 << 5)
 284 #define XDEV_RESUME     (0xf << 5)
 285 /* true: port has power (see HCC_PPC) */
 286 #define PORT_POWER      (1 << 9)
 287 /* bits 10:13 indicate device speed:
 288  * 0 - undefined speed - port hasn't be initialized by a reset yet
 289  * 1 - full speed
 290  * 2 - low speed
 291  * 3 - high speed
 292  * 4 - super speed
 293  * 5-15 reserved
 294  */
 295 #define DEV_SPEED_MASK          (0xf << 10)
 296 #define XDEV_FS                 (0x1 << 10)
 297 #define XDEV_LS                 (0x2 << 10)
 298 #define XDEV_HS                 (0x3 << 10)
 299 #define XDEV_SS                 (0x4 << 10)
 300 #define DEV_UNDEFSPEED(p)       (((p) & DEV_SPEED_MASK) == (0x0<<10))
 301 #define DEV_FULLSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_FS)
 302 #define DEV_LOWSPEED(p)         (((p) & DEV_SPEED_MASK) == XDEV_LS)
 303 #define DEV_HIGHSPEED(p)        (((p) & DEV_SPEED_MASK) == XDEV_HS)
 304 #define DEV_SUPERSPEED(p)       (((p) & DEV_SPEED_MASK) == XDEV_SS)
 305 /* Bits 20:23 in the Slot Context are the speed for the device */
 306 #define SLOT_SPEED_FS           (XDEV_FS << 10)
 307 #define SLOT_SPEED_LS           (XDEV_LS << 10)
 308 #define SLOT_SPEED_HS           (XDEV_HS << 10)
 309 #define SLOT_SPEED_SS           (XDEV_SS << 10)
 310 /* Port Indicator Control */
 311 #define PORT_LED_OFF    (0 << 14)
 312 #define PORT_LED_AMBER  (1 << 14)
 313 #define PORT_LED_GREEN  (2 << 14)
 314 #define PORT_LED_MASK   (3 << 14)
 315 /* Port Link State Write Strobe - set this when changing link state */
 316 #define PORT_LINK_STROBE        (1 << 16)
 317 /* true: connect status change */
 318 #define PORT_CSC        (1 << 17)
 319 /* true: port enable change */
 320 #define PORT_PEC        (1 << 18)
 321 /* true: warm reset for a USB 3.0 device is done.  A "hot" reset puts the port
 322  * into an enabled state, and the device into the default state.  A "warm" reset
 323  * also resets the link, forcing the device through the link training sequence.
 324  * SW can also look at the Port Reset register to see when warm reset is done.
 325  */
 326 #define PORT_WRC        (1 << 19)
 327 /* true: over-current change */
 328 #define PORT_OCC        (1 << 20)
 329 /* true: reset change - 1 to 0 transition of PORT_RESET */
 330 #define PORT_RC         (1 << 21)
 331 /* port link status change - set on some port link state transitions:
 332  *  Transition                          Reason
 333  *  ------------------------------------------------------------------------------
 334  *  - U3 to Resume                      Wakeup signaling from a device
 335  *  - Resume to Recovery to U0          USB 3.0 device resume
 336  *  - Resume to U0                      USB 2.0 device resume
 337  *  - U3 to Recovery to U0              Software resume of USB 3.0 device complete
 338  *  - U3 to U0                          Software resume of USB 2.0 device complete
 339  *  - U2 to U0                          L1 resume of USB 2.1 device complete
 340  *  - U0 to U0 (???)                    L1 entry rejection by USB 2.1 device
 341  *  - U0 to disabled                    L1 entry error with USB 2.1 device
 342  *  - Any state to inactive             Error on USB 3.0 port
 343  */
 344 #define PORT_PLC        (1 << 22)
 345 /* port configure error change - port failed to configure its link partner */
 346 #define PORT_CEC        (1 << 23)
 347 /* Cold Attach Status - xHC can set this bit to report device attached during
 348  * Sx state. Warm port reset should be perfomed to clear this bit and move port
 349  * to connected state.
 350  */
 351 #define PORT_CAS        (1 << 24)
 352 /* wake on connect (enable) */
 353 #define PORT_WKCONN_E   (1 << 25)
 354 /* wake on disconnect (enable) */
 355 #define PORT_WKDISC_E   (1 << 26)
 356 /* wake on over-current (enable) */
 357 #define PORT_WKOC_E     (1 << 27)
 358 /* bits 28:29 reserved */
 359 /* true: device is removable - for USB 3.0 roothub emulation */
 360 #define PORT_DEV_REMOVE (1 << 30)
 361 /* Initiate a warm port reset - complete when PORT_WRC is '1' */
 362 #define PORT_WR         (1 << 31)
 363
 364 /* We mark duplicate entries with -1 */
 365 #define DUPLICATE_ENTRY ((u8)(-1))
 366
 367 /* Port Power Management Status and Control - port_power_base bitmasks */
 368 /* Inactivity timer value for transitions into U1, in microseconds.
 369  * Timeout can be up to 127us.  0xFF means an infinite timeout.
 370  */
 371 #define PORT_U1_TIMEOUT(p)      ((p) & 0xff)
 372 #define PORT_U1_TIMEOUT_MASK    0xff
 373 /* Inactivity timer value for transitions into U2 */
 374 #define PORT_U2_TIMEOUT(p)      (((p) & 0xff) << 8)
 375 #define PORT_U2_TIMEOUT_MASK    (0xff << 8)
 376 /* Bits 24:31 for port testing */
 377
 378 /* USB2 Protocol PORTSPMSC */
 379 #define PORT_L1S_MASK           7
 380 #define PORT_L1S_SUCCESS        1
 381 #define PORT_RWE                (1 << 3)
 382 #define PORT_HIRD(p)            (((p) & 0xf) << 4)
 383 #define PORT_HIRD_MASK          (0xf << 4)
 384 #define PORT_L1DS(p)            (((p) & 0xff) << 8)
 385 #define PORT_HLE                (1 << 16)
 386
 387 /**
 388  * struct xhci_intr_reg - Interrupt Register Set
 389  * @irq_pending:        IMAN - Interrupt Management Register.  Used to enable
 390  *                      interrupts and check for pending interrupts.
 391  * @irq_control:        IMOD - Interrupt Moderation Register.
 392  *                      Used to throttle interrupts.
 393  * @erst_size:          Number of segments in the Event Ring Segment Table (ERST).
 394  * @erst_base:          ERST base address.
 395  * @erst_dequeue:       Event ring dequeue pointer.
 396  *
 397  * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
 398  * Ring Segment Table (ERST) associated with it.  The event ring is comprised of
 399  * multiple segments of the same size.  The HC places events on the ring and
 400  * "updates the Cycle bit in the TRBs to indicate to software the current
 401  * position of the Enqueue Pointer." The HCD (Linux) processes those events and
 402  * updates the dequeue pointer.
 403  */
 404 struct xhci_intr_reg {
 405         __le32  irq_pending;
 406         __le32  irq_control;
 407         __le32  erst_size;
 408         __le32  rsvd;
 409         __le64  erst_base;
 410         __le64  erst_dequeue;
 411 };
 412
 413 /* irq_pending bitmasks */
 414 #define ER_IRQ_PENDING(p)       ((p) & 0x1)
 415 /* bits 2:31 need to be preserved */
 416 /* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
 417 #define ER_IRQ_CLEAR(p)         ((p) & 0xfffffffe)
 418 #define ER_IRQ_ENABLE(p)        ((ER_IRQ_CLEAR(p)) | 0x2)
 419 #define ER_IRQ_DISABLE(p)       ((ER_IRQ_CLEAR(p)) & ~(0x2))
 420
 421 /* irq_control bitmasks */
 422 /* Minimum interval between interrupts (in 250ns intervals).  The interval
 423  * between interrupts will be longer if there are no events on the event ring.
 424  * Default is 4000 (1 ms).
 425  */
 426 #define ER_IRQ_INTERVAL_MASK    (0xffff)
 427 /* Counter used to count down the time to the next interrupt - HW use only */
 428 #define ER_IRQ_COUNTER_MASK     (0xffff << 16)
 429
 430 /* erst_size bitmasks */
 431 /* Preserve bits 16:31 of erst_size */
 432 #define ERST_SIZE_MASK          (0xffff << 16)
 433
 434 /* erst_dequeue bitmasks */
 435 /* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
 436  * where the current dequeue pointer lies.  This is an optional HW hint.
 437  */
 438 #define ERST_DESI_MASK          (0x7)
 439 /* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
 440  * a work queue (or delayed service routine)?
 441  */
 442 #define ERST_EHB                (1 << 3)
 443 #define ERST_PTR_MASK           (0xf)
 444
 445 /**
 446  * struct xhci_run_regs
 447  * @microframe_index:
 448  *              MFINDEX - current microframe number
 449  *
 450  * Section 5.5 Host Controller Runtime Registers:
 451  * "Software should read and write these registers using only Dword (32 bit)
 452  * or larger accesses"
 453  */
 454 struct xhci_run_regs {
 455         __le32                  microframe_index;
 456         __le32                  rsvd[7];
 457         struct xhci_intr_reg    ir_set[128];
 458 };
 459
 460 /**
 461  * struct doorbell_array
 462  *
 463  * Bits  0 -  7: Endpoint target
 464  * Bits  8 - 15: RsvdZ
 465  * Bits 16 - 31: Stream ID
 466  *
 467  * Section 5.6
 468  */
 469 struct xhci_doorbell_array {
 470         __le32  doorbell[256];
 471 };
 472
 473 #define DB_VALUE(ep, stream)    ((((ep) + 1) & 0xff) | ((stream) << 16))
 474 #define DB_VALUE_HOST           0x00000000
 475
 476 /**
 477  * struct xhci_protocol_caps
 478  * @revision:           major revision, minor revision, capability ID,
 479  *                      and next capability pointer.
 480  * @name_string:        Four ASCII characters to say which spec this xHC
 481  *                      follows, typically "USB ".
 482  * @port_info:          Port offset, count, and protocol-defined information.
 483  */
 484 struct xhci_protocol_caps {
 485         u32     revision;
 486         u32     name_string;
 487         u32     port_info;
 488 };
 489
 490 #define XHCI_EXT_PORT_MAJOR(x)  (((x) >> 24) & 0xff)
 491 #define XHCI_EXT_PORT_OFF(x)    ((x) & 0xff)
 492 #define XHCI_EXT_PORT_COUNT(x)  (((x) >> 8) & 0xff)
 493
 494 /**
 495  * struct xhci_container_ctx
 496  * @type: Type of context.  Used to calculated offsets to contained contexts.
 497  * @size: Size of the context data
 498  * @bytes: The raw context data given to HW
 499  * @dma: dma address of the bytes
 500  *
 501  * Represents either a Device or Input context.  Holds a pointer to the raw
 502  * memory used for the context (bytes) and dma address of it (dma).
 503  */
 504 struct xhci_container_ctx {
 505         unsigned type;
 506 #define XHCI_CTX_TYPE_DEVICE  0x1
 507 #define XHCI_CTX_TYPE_INPUT   0x2
 508
 509         int size;
 510
 511         u8 *bytes;
 512         dma_addr_t dma;
 513 };
 514
 515 /**
 516  * struct xhci_slot_ctx
 517  * @dev_info:   Route string, device speed, hub info, and last valid endpoint
 518  * @dev_info2:  Max exit latency for device number, root hub port number
 519  * @tt_info:    tt_info is used to construct split transaction tokens
 520  * @dev_state:  slot state and device address
 521  *
 522  * Slot Context - section 6.2.1.1.  This assumes the HC uses 32-byte context
 523  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 524  * reserved at the end of the slot context for HC internal use.
 525  */
 526 struct xhci_slot_ctx {
 527         __le32  dev_info;
 528         __le32  dev_info2;
 529         __le32  tt_info;
 530         __le32  dev_state;
 531         /* offset 0x10 to 0x1f reserved for HC internal use */
 532         __le32  reserved[4];
 533 };
 534
 535 /* dev_info bitmasks */
 536 /* Route String - 0:19 */
 537 #define ROUTE_STRING_MASK       (0xfffff)
 538 /* Device speed - values defined by PORTSC Device Speed field - 20:23 */
 539 #define DEV_SPEED       (0xf << 20)
 540 /* bit 24 reserved */
 541 /* Is this LS/FS device connected through a HS hub? - bit 25 */
 542 #define DEV_MTT         (0x1 << 25)
 543 /* Set if the device is a hub - bit 26 */
 544 #define DEV_HUB         (0x1 << 26)
 545 /* Index of the last valid endpoint context in this device context - 27:31 */
 546 #define LAST_CTX_MASK   (0x1f << 27)
 547 #define LAST_CTX(p)     ((p) << 27)
 548 #define LAST_CTX_TO_EP_NUM(p)   (((p) >> 27) - 1)
 549 #define SLOT_FLAG       (1 << 0)
 550 #define EP0_FLAG        (1 << 1)
 551
 552 /* dev_info2 bitmasks */
 553 /* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
 554 #define MAX_EXIT        (0xffff)
 555 /* Root hub port number that is needed to access the USB device */
 556 #define ROOT_HUB_PORT(p)        (((p) & 0xff) << 16)
 557 #define DEVINFO_TO_ROOT_HUB_PORT(p)     (((p) >> 16) & 0xff)
 558 /* Maximum number of ports under a hub device */
 559 #define XHCI_MAX_PORTS(p)       (((p) & 0xff) << 24)
 560
 561 /* tt_info bitmasks */
 562 /*
 563  * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
 564  * The Slot ID of the hub that isolates the high speed signaling from
 565  * this low or full-speed device.  '0' if attached to root hub port.
 566  */
 567 #define TT_SLOT         (0xff)
 568 /*
 569  * The number of the downstream facing port of the high-speed hub
 570  * '0' if the device is not low or full speed.
 571  */
 572 #define TT_PORT         (0xff << 8)
 573 #define TT_THINK_TIME(p)        (((p) & 0x3) << 16)
 574
 575 /* dev_state bitmasks */
 576 /* USB device address - assigned by the HC */
 577 #define DEV_ADDR_MASK   (0xff)
 578 /* bits 8:26 reserved */
 579 /* Slot state */
 580 #define SLOT_STATE      (0x1f << 27)
 581 #define GET_SLOT_STATE(p)       (((p) & (0x1f << 27)) >> 27)
 582
 583 #define SLOT_STATE_DISABLED     0
 584 #define SLOT_STATE_ENABLED      SLOT_STATE_DISABLED
 585 #define SLOT_STATE_DEFAULT      1
 586 #define SLOT_STATE_ADDRESSED    2
 587 #define SLOT_STATE_CONFIGURED   3
 588
 589 /**
 590  * struct xhci_ep_ctx
 591  * @ep_info:    endpoint state, streams, mult, and interval information.
 592  * @ep_info2:   information on endpoint type, max packet size, max burst size,
 593  *              error count, and whether the HC will force an event for all
 594  *              transactions.
 595  * @deq:        64-bit ring dequeue pointer address.  If the endpoint only
 596  *              defines one stream, this points to the endpoint transfer ring.
 597  *              Otherwise, it points to a stream context array, which has a
 598  *              ring pointer for each flow.
 599  * @tx_info:
 600  *              Average TRB lengths for the endpoint ring and
 601  *              max payload within an Endpoint Service Interval Time (ESIT).
 602  *
 603  * Endpoint Context - section 6.2.1.2.  This assumes the HC uses 32-byte context
 604  * structures.  If the HC uses 64-byte contexts, there is an additional 32 bytes
 605  * reserved at the end of the endpoint context for HC internal use.
 606  */
 607 struct xhci_ep_ctx {
 608         __le32  ep_info;
 609         __le32  ep_info2;
 610         __le64  deq;
 611         __le32  tx_info;
 612         /* offset 0x14 - 0x1f reserved for HC internal use */
 613         __le32  reserved[3];
 614 };
 615
 616 /* ep_info bitmasks */
 617 /*
 618  * Endpoint State - bits 0:2
 619  * 0 - disabled
 620  * 1 - running
 621  * 2 - halted due to halt condition - ok to manipulate endpoint ring
 622  * 3 - stopped
 623  * 4 - TRB error
 624  * 5-7 - reserved
 625  */
 626 #define EP_STATE_MASK           (0xf)
 627 #define EP_STATE_DISABLED       0
 628 #define EP_STATE_RUNNING        1
 629 #define EP_STATE_HALTED         2
 630 #define EP_STATE_STOPPED        3
 631 #define EP_STATE_ERROR          4
 632 /* Mult - Max number of burtst within an interval, in EP companion desc. */
 633 #define EP_MULT(p)              (((p) & 0x3) << 8)
 634 #define CTX_TO_EP_MULT(p)       (((p) >> 8) & 0x3)
 635 /* bits 10:14 are Max Primary Streams */
 636 /* bit 15 is Linear Stream Array */
 637 /* Interval - period between requests to an endpoint - 125u increments. */
 638 #define EP_INTERVAL(p)          (((p) & 0xff) << 16)
 639 #define EP_INTERVAL_TO_UFRAMES(p)               (1 << (((p) >> 16) & 0xff))
 640 #define CTX_TO_EP_INTERVAL(p)   (((p) >> 16) & 0xff)
 641 #define EP_MAXPSTREAMS_MASK     (0x1f << 10)
 642 #define EP_MAXPSTREAMS(p)       (((p) << 10) & EP_MAXPSTREAMS_MASK)
 643 /* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
 644 #define EP_HAS_LSA              (1 << 15)
 645
 646 /* ep_info2 bitmasks */
 647 /*
 648  * Force Event - generate transfer events for all TRBs for this endpoint
 649  * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
 650  */
 651 #define FORCE_EVENT     (0x1)
 652 #define ERROR_COUNT(p)  (((p) & 0x3) << 1)
 653 #define CTX_TO_EP_TYPE(p)       (((p) >> 3) & 0x7)
 654 #define EP_TYPE(p)      ((p) << 3)
 655 #define ISOC_OUT_EP     1
 656 #define BULK_OUT_EP     2
 657 #define INT_OUT_EP      3
 658 #define CTRL_EP         4
 659 #define ISOC_IN_EP      5
 660 #define BULK_IN_EP      6
 661 #define INT_IN_EP       7
 662 /* bit 6 reserved */
 663 /* bit 7 is Host Initiate Disable - for disabling stream selection */
 664 #define MAX_BURST(p)    (((p)&0xff) << 8)
 665 #define CTX_TO_MAX_BURST(p)     (((p) >> 8) & 0xff)
 666 #define MAX_PACKET(p)   (((p)&0xffff) << 16)
 667 #define MAX_PACKET_MASK         (0xffff << 16)
 668 #define MAX_PACKET_DECODED(p)   (((p) >> 16) & 0xffff)
 669
 670 /* Get max packet size from ep desc. Bit 10..0 specify the max packet size.
 671  * USB2.0 spec 9.6.6.
 672  */
 673 #define GET_MAX_PACKET(p)       ((p) & 0x7ff)
 674
 675 /* tx_info bitmasks */
 676 #define AVG_TRB_LENGTH_FOR_EP(p)        ((p) & 0xffff)
 677 #define MAX_ESIT_PAYLOAD_FOR_EP(p)      (((p) & 0xffff) << 16)
 678 #define CTX_TO_MAX_ESIT_PAYLOAD(p)      (((p) >> 16) & 0xffff)
 679
 680 /* deq bitmasks */
 681 #define EP_CTX_CYCLE_MASK               (1 << 0)
 682
 683 #ifdef CONFIG_MTK_XHCI
 684 /* mtk scheduler bitmasks */
 685 #define BPKTS(p)        ((p) & 0x3f)
 686 #define BCSCOUNT(p)     (((p) & 0x7) << 8)
 687 #define BBM(p)          ((p) << 11)
 688 #define BOFFSET(p)      ((p) & 0x3fff)
 689 #define BREPEAT(p)      (((p) & 0x7fff) << 16)
 690 #endif
 691
 692 /**
 693  * struct xhci_input_control_context
 694  * Input control context; see section 6.2.5.
 695  *
 696  * @drop_context:       set the bit of the endpoint context you want to disable
 697  * @add_context:        set the bit of the endpoint context you want to enable
 698  */
 699 struct xhci_input_control_ctx {
 700         __le32  drop_flags;
 701         __le32  add_flags;
 702         __le32  rsvd2[6];
 703 };
 704
 705 #define EP_IS_ADDED(ctrl_ctx, i) \
 706         (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
 707 #define EP_IS_DROPPED(ctrl_ctx, i)       \
 708         (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
 709
 710 /* Represents everything that is needed to issue a command on the command ring.
 711  * It's useful to pre-allocate these for commands that cannot fail due to
 712  * out-of-memory errors, like freeing streams.
 713  */
 714 struct xhci_command {
 715         /* Input context for changing device state */
 716         struct xhci_container_ctx       *in_ctx;
 717         u32                             status;
 718         /* If completion is null, no one is waiting on this command
 719          * and the structure can be freed after the command completes.
 720          */
 721         struct completion               *completion;
 722         union xhci_trb                  *command_trb;
 723         struct list_head                cmd_list;
 724 };
 725
 726 /* drop context bitmasks */
 727 #define DROP_EP(x)      (0x1 << x)
 728 /* add context bitmasks */
 729 #define ADD_EP(x)       (0x1 << x)
 730
 731 struct xhci_stream_ctx {
 732         /* 64-bit stream ring address, cycle state, and stream type */
 733         __le64  stream_ring;
 734         /* offset 0x14 - 0x1f reserved for HC internal use */
 735         __le32  reserved[2];
 736 };
 737
 738 /* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
 739 #define SCT_FOR_CTX(p)          (((p) << 1) & 0x7)
 740 /* Secondary stream array type, dequeue pointer is to a transfer ring */
 741 #define SCT_SEC_TR              0
 742 /* Primary stream array type, dequeue pointer is to a transfer ring */
 743 #define SCT_PRI_TR              1
 744 /* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
 745 #define SCT_SSA_8               2
 746 #define SCT_SSA_16              3
 747 #define SCT_SSA_32              4
 748 #define SCT_SSA_64              5
 749 #define SCT_SSA_128             6
 750 #define SCT_SSA_256             7
 751
 752 /* Assume no secondary streams for now */
 753 struct xhci_stream_info {
 754         struct xhci_ring                **stream_rings;
 755         /* Number of streams, including stream 0 (which drivers can't use) */
 756         unsigned int                    num_streams;
 757         /* The stream context array may be bigger than
 758          * the number of streams the driver asked for
 759          */
 760         struct xhci_stream_ctx          *stream_ctx_array;
 761         unsigned int                    num_stream_ctxs;
 762         dma_addr_t                      ctx_array_dma;
 763         /* For mapping physical TRB addresses to segments in stream rings */
 764         struct radix_tree_root          trb_address_map;
 765         struct xhci_command             *free_streams_command;
 766 };
 767
 768 #define SMALL_STREAM_ARRAY_SIZE         256
 769 #define MEDIUM_STREAM_ARRAY_SIZE        1024
 770
 771 /* Some Intel xHCI host controllers need software to keep track of the bus
 772  * bandwidth.  Keep track of endpoint info here.  Each root port is allocated
 773  * the full bus bandwidth.  We must also treat TTs (including each port under a
 774  * multi-TT hub) as a separate bandwidth domain.  The direct memory interface
 775  * (DMI) also limits the total bandwidth (across all domains) that can be used.
 776  */
 777 struct xhci_bw_info {
 778         /* ep_interval is zero-based */
 779         unsigned int            ep_interval;
 780         /* mult and num_packets are one-based */
 781         unsigned int            mult;
 782         unsigned int            num_packets;
 783         unsigned int            max_packet_size;
 784         unsigned int            max_esit_payload;
 785         unsigned int            type;
 786 };
 787
 788 /* "Block" sizes in bytes the hardware uses for different device speeds.
 789  * The logic in this part of the hardware limits the number of bits the hardware
 790  * can use, so must represent bandwidth in a less precise manner to mimic what
 791  * the scheduler hardware computes.
 792  */
 793 #define FS_BLOCK        1
 794 #define HS_BLOCK        4
 795 #define SS_BLOCK        16
 796 #define DMI_BLOCK       32
 797
 798 /* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
 799  * with each byte transferred.  SuperSpeed devices have an initial overhead to
 800  * set up bursts.  These are in blocks, see above.  LS overhead has already been
 801  * translated into FS blocks.
 802  */
 803 #define DMI_OVERHEAD 8
 804 #define DMI_OVERHEAD_BURST 4
 805 #define SS_OVERHEAD 8
 806 #define SS_OVERHEAD_BURST 32
 807 #define HS_OVERHEAD 26
 808 #define FS_OVERHEAD 20
 809 #define LS_OVERHEAD 128
 810 /* The TTs need to claim roughly twice as much bandwidth (94 bytes per
 811  * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
 812  * of overhead associated with split transfers crossing microframe boundaries.
 813  * 31 blocks is pure protocol overhead.
 814  */
 815 #define TT_HS_OVERHEAD (31 + 94)
 816 #define TT_DMI_OVERHEAD (25 + 12)
 817
 818 /* Bandwidth limits in blocks */
 819 #define FS_BW_LIMIT             1285
 820 #define TT_BW_LIMIT             1320
 821 #define HS_BW_LIMIT             1607
 822 #define SS_BW_LIMIT_IN          3906
 823 #define DMI_BW_LIMIT_IN         3906
 824 #define SS_BW_LIMIT_OUT         3906
 825 #define DMI_BW_LIMIT_OUT        3906
 826
 827 /* Percentage of bus bandwidth reserved for non-periodic transfers */
 828 #define FS_BW_RESERVED          10
 829 #define HS_BW_RESERVED          20
 830 #define SS_BW_RESERVED          10
 831
 832 struct xhci_virt_ep {
 833         struct xhci_ring                *ring;
 834         /* Related to endpoints that are configured to use stream IDs only */
 835         struct xhci_stream_info         *stream_info;
 836         /* Temporary storage in case the configure endpoint command fails and we
 837          * have to restore the device state to the previous state
 838          */
 839         struct xhci_ring                *new_ring;
 840         unsigned int                    ep_state;
 841 #define SET_DEQ_PENDING         (1 << 0)
 842 #define EP_HALTED               (1 << 1)        /* For stall handling */
 843 #define EP_HALT_PENDING         (1 << 2)        /* For URB cancellation */
 844 /* Transitioning the endpoint to using streams, don't enqueue URBs */
 845 #define EP_GETTING_STREAMS      (1 << 3)
 846 #define EP_HAS_STREAMS          (1 << 4)
 847 /* Transitioning the endpoint to not using streams, don't enqueue URBs */
 848 #define EP_GETTING_NO_STREAMS   (1 << 5)
 849         /* ----  Related to URB cancellation ---- */
 850         struct list_head        cancelled_td_list;
 851         /* The TRB that was last reported in a stopped endpoint ring */
 852         union xhci_trb          *stopped_trb;
 853         struct xhci_td          *stopped_td;
 854         unsigned int            stopped_stream;
 855         /* Watchdog timer for stop endpoint command to cancel URBs */
 856         struct timer_list       stop_cmd_timer;
 857         int                     stop_cmds_pending;
 858         struct xhci_hcd         *xhci;
 859         /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
 860          * command.  We'll need to update the ring's dequeue segment and dequeue
 861          * pointer after the command completes.
 862          */
 863         struct xhci_segment     *queued_deq_seg;
 864         union xhci_trb          *queued_deq_ptr;
 865         /*
 866          * Sometimes the xHC can not process isochronous endpoint ring quickly
 867          * enough, and it will miss some isoc tds on the ring and generate
 868          * a Missed Service Error Event.
 869          * Set skip flag when receive a Missed Service Error Event and
 870          * process the missed tds on the endpoint ring.
 871          */
 872         bool                    skip;
 873         /* Bandwidth checking storage */
 874         struct xhci_bw_info     bw_info;
 875         struct list_head        bw_endpoint_list;
 876 };
 877
 878 enum xhci_overhead_type {
 879         LS_OVERHEAD_TYPE = 0,
 880         FS_OVERHEAD_TYPE,
 881         HS_OVERHEAD_TYPE,
 882 };
 883
 884 struct xhci_interval_bw {
 885         unsigned int            num_packets;
 886         /* Sorted by max packet size.
 887          * Head of the list is the greatest max packet size.
 888          */
 889         struct list_head        endpoints;
 890         /* How many endpoints of each speed are present. */
 891         unsigned int            overhead[3];
 892 };
 893
 894 #define XHCI_MAX_INTERVAL       16
 895
 896 struct xhci_interval_bw_table {
 897         unsigned int            interval0_esit_payload;
 898         struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
 899         /* Includes reserved bandwidth for async endpoints */
 900         unsigned int            bw_used;
 901         unsigned int            ss_bw_in;
 902         unsigned int            ss_bw_out;
 903 };
 904
 905
 906 struct xhci_virt_device {
 907         struct usb_device               *udev;
 908         /*
 909          * Commands to the hardware are passed an "input context" that
 910          * tells the hardware what to change in its data structures.
 911          * The hardware will return changes in an "output context" that
 912          * software must allocate for the hardware.  We need to keep
 913          * track of input and output contexts separately because
 914          * these commands might fail and we don't trust the hardware.
 915          */
 916         struct xhci_container_ctx       *out_ctx;
 917         /* Used for addressing devices and configuration changes */
 918         struct xhci_container_ctx       *in_ctx;
 919         /* Rings saved to ensure old alt settings can be re-instated */
 920         struct xhci_ring                **ring_cache;
 921         int                             num_rings_cached;
 922         /* Store xHC assigned device address */
 923         int                             address;
 924 #define XHCI_MAX_RINGS_CACHED   31
 925         struct xhci_virt_ep             eps[31];
 926         struct completion               cmd_completion;
 927         /* Status of the last command issued for this device */
 928         u32                             cmd_status;
 929         struct list_head                cmd_list;
 930         u8                              fake_port;
 931         u8                              real_port;
 932         struct xhci_interval_bw_table   *bw_table;
 933         struct xhci_tt_bw_info          *tt_info;
 934         /* The current max exit latency for the enabled USB3 link states. */
 935         u16                             current_mel;
 936 };
 937
 938 /*
 939  * For each roothub, keep track of the bandwidth information for each periodic
 940  * interval.
 941  *
 942  * If a high speed hub is attached to the roothub, each TT associated with that
 943  * hub is a separate bandwidth domain.  The interval information for the
 944  * endpoints on the devices under that TT will appear in the TT structure.
 945  */
 946 struct xhci_root_port_bw_info {
 947         struct list_head                tts;
 948         unsigned int                    num_active_tts;
 949         struct xhci_interval_bw_table   bw_table;
 950 };
 951
 952 struct xhci_tt_bw_info {
 953         struct list_head                tt_list;
 954         int                             slot_id;
 955         int                             ttport;
 956         struct xhci_interval_bw_table   bw_table;
 957         int                             active_eps;
 958 };
 959
 960
 961 /**
 962  * struct xhci_device_context_array
 963  * @dev_context_ptr     array of 64-bit DMA addresses for device contexts
 964  */
 965 struct xhci_device_context_array {
 966         /* 64-bit device addresses; we only write 32-bit addresses */
 967         __le64                  dev_context_ptrs[MAX_HC_SLOTS];
 968         /* private xHCD pointers */
 969         dma_addr_t      dma;
 970 };
 971 /* TODO: write function to set the 64-bit device DMA address */
 972 /*
 973  * TODO: change this to be dynamically sized at HC mem init time since the HC
 974  * might not be able to handle the maximum number of devices possible.
 975  */
 976
 977
 978 struct xhci_transfer_event {
 979         /* 64-bit buffer address, or immediate data */
 980         __le64  buffer;
 981         __le32  transfer_len;
 982         /* This field is interpreted differently based on the type of TRB */
 983         __le32  flags;
 984 };
 985
 986 /* Transfer event TRB length bit mask */
 987 /* bits 0:23 */
 988 #define EVENT_TRB_LEN(p)                ((p) & 0xffffff)
 989
 990 /** Transfer Event bit fields **/
 991 #define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
 992
 993 /* Completion Code - only applicable for some types of TRBs */
 994 #define COMP_CODE_MASK          (0xff << 24)
 995 #define GET_COMP_CODE(p)        (((p) & COMP_CODE_MASK) >> 24)
 996 #define COMP_SUCCESS    1
 997 /* Data Buffer Error */
 998 #define COMP_DB_ERR     2
 999 /* Babble Detected Error */
1000 #define COMP_BABBLE     3
1001 /* USB Transaction Error */
1002 #define COMP_TX_ERR     4
1003 /* TRB Error - some TRB field is invalid */
1004 #define COMP_TRB_ERR    5
1005 /* Stall Error - USB device is stalled */
1006 #define COMP_STALL      6
1007 /* Resource Error - HC doesn't have memory for that device configuration */
1008 #define COMP_ENOMEM     7
1009 /* Bandwidth Error - not enough room in schedule for this dev config */
1010 #define COMP_BW_ERR     8
1011 /* No Slots Available Error - HC ran out of device slots */
1012 #define COMP_ENOSLOTS   9
1013 /* Invalid Stream Type Error */
1014 #define COMP_STREAM_ERR 10
1015 /* Slot Not Enabled Error - doorbell rung for disabled device slot */
1016 #define COMP_EBADSLT    11
1017 /* Endpoint Not Enabled Error */
1018 #define COMP_EBADEP     12
1019 /* Short Packet */
1020 #define COMP_SHORT_TX   13
1021 /* Ring Underrun - doorbell rung for an empty isoc OUT ep ring */
1022 #define COMP_UNDERRUN   14
1023 /* Ring Overrun - isoc IN ep ring is empty when ep is scheduled to RX */
1024 #define COMP_OVERRUN    15
1025 /* Virtual Function Event Ring Full Error */
1026 #define COMP_VF_FULL    16
1027 /* Parameter Error - Context parameter is invalid */
1028 #define COMP_EINVAL     17
1029 /* Bandwidth Overrun Error - isoc ep exceeded its allocated bandwidth */
1030 #define COMP_BW_OVER    18
1031 /* Context State Error - illegal context state transition requested */
1032 #define COMP_CTX_STATE  19
1033 /* No Ping Response Error - HC didn't get PING_RESPONSE in time to TX */
1034 #define COMP_PING_ERR   20
1035 /* Event Ring is full */
1036 #define COMP_ER_FULL    21
1037 /* Incompatible Device Error */
1038 #define COMP_DEV_ERR    22
1039 /* Missed Service Error - HC couldn't service an isoc ep within interval */
1040 #define COMP_MISSED_INT 23
1041 /* Successfully stopped command ring */
1042 #define COMP_CMD_STOP   24
1043 /* Successfully aborted current command and stopped command ring */
1044 #define COMP_CMD_ABORT  25
1045 /* Stopped - transfer was terminated by a stop endpoint command */
1046 #define COMP_STOP       26
1047 /* Same as COMP_EP_STOPPED, but the transferred length in the event is invalid */
1048 #define COMP_STOP_INVAL 27
1049 /* Control Abort Error - Debug Capability - control pipe aborted */
1050 #define COMP_DBG_ABORT  28
1051 /* Max Exit Latency Too Large Error */
1052 #define COMP_MEL_ERR    29
1053 /* TRB type 30 reserved */
1054 /* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
1055 #define COMP_BUFF_OVER  31
1056 /* Event Lost Error - xHC has an "internal event overrun condition" */
1057 #define COMP_ISSUES     32
1058 /* Undefined Error - reported when other error codes don't apply */
1059 #define COMP_UNKNOWN    33
1060 /* Invalid Stream ID Error */
1061 #define COMP_STRID_ERR  34
1062 /* Secondary Bandwidth Error - may be returned by a Configure Endpoint cmd */
1063 #define COMP_2ND_BW_ERR 35
1064 /* Split Transaction Error */
1065 #define COMP_SPLIT_ERR  36
1066
1067 struct xhci_link_trb {
1068         /* 64-bit segment pointer*/
1069         __le64 segment_ptr;
1070         __le32 intr_target;
1071         __le32 control;
1072 };
1073
1074 /* control bitfields */
1075 #define LINK_TOGGLE     (0x1<<1)
1076
1077 /* Command completion event TRB */
1078 struct xhci_event_cmd {
1079         /* Pointer to command TRB, or the value passed by the event data trb */
1080         __le64 cmd_trb;
1081         __le32 status;
1082         __le32 flags;
1083 };
1084
1085 /* flags bitmasks */
1086 /* bits 16:23 are the virtual function ID */
1087 /* bits 24:31 are the slot ID */
1088 #define TRB_TO_SLOT_ID(p)       (((p) & (0xff<<24)) >> 24)
1089 #define SLOT_ID_FOR_TRB(p)      (((p) & 0xff) << 24)
1090
1091 /* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1092 #define TRB_TO_EP_INDEX(p)              ((((p) & (0x1f << 16)) >> 16) - 1)
1093 #define EP_ID_FOR_TRB(p)                ((((p) + 1) & 0x1f) << 16)
1094
1095 #define SUSPEND_PORT_FOR_TRB(p)         (((p) & 1) << 23)
1096 #define TRB_TO_SUSPEND_PORT(p)          (((p) & (1 << 23)) >> 23)
1097 #define LAST_EP_INDEX                   30
1098
1099 /* Set TR Dequeue Pointer command TRB fields */
1100 #define TRB_TO_STREAM_ID(p)             ((((p) & (0xffff << 16)) >> 16))
1101 #define STREAM_ID_FOR_TRB(p)            ((((p)) & 0xffff) << 16)
1102
1103
1104 /* Port Status Change Event TRB fields */
1105 /* Port ID - bits 31:24 */
1106 #define GET_PORT_ID(p)          (((p) & (0xff << 24)) >> 24)
1107
1108 /* Normal TRB fields */
1109 /* transfer_len bitmasks - bits 0:16 */
1110 #define TRB_LEN(p)              ((p) & 0x1ffff)
1111 /* Interrupter Target - which MSI-X vector to target the completion event at */
1112 #define TRB_INTR_TARGET(p)      (((p) & 0x3ff) << 22)
1113 #define GET_INTR_TARGET(p)      (((p) >> 22) & 0x3ff)
1114 #define TRB_TBC(p)              (((p) & 0x3) << 7)
1115 #define TRB_TLBPC(p)            (((p) & 0xf) << 16)
1116
1117 /* Cycle bit - indicates TRB ownership by HC or HCD */
1118 #define TRB_CYCLE               (1<<0)
1119 /*
1120  * Force next event data TRB to be evaluated before task switch.
1121  * Used to pass OS data back after a TD completes.
1122  */
1123 #define TRB_ENT                 (1<<1)
1124 /* Interrupt on short packet */
1125 #define TRB_ISP                 (1<<2)
1126 /* Set PCIe no snoop attribute */
1127 #define TRB_NO_SNOOP            (1<<3)
1128 /* Chain multiple TRBs into a TD */
1129 #define TRB_CHAIN               (1<<4)
1130 /* Interrupt on completion */
1131 #define TRB_IOC                 (1<<5)
1132 /* The buffer pointer contains immediate data */
1133 #define TRB_IDT                 (1<<6)
1134
1135 /* Block Event Interrupt */
1136 #define TRB_BEI                 (1<<9)
1137
1138 /* Control transfer TRB specific fields */
1139 #define TRB_DIR_IN              (1<<16)
1140 #define TRB_TX_TYPE(p)          ((p) << 16)
1141 #define TRB_DATA_OUT            2
1142 #define TRB_DATA_IN             3
1143
1144 /* Isochronous TRB specific fields */
1145 #define TRB_SIA                 (1<<31)
1146
1147 struct xhci_generic_trb {
1148         __le32 field[4];
1149 };
1150
1151 union xhci_trb {
1152         struct xhci_link_trb            link;
1153         struct xhci_transfer_event      trans_event;
1154         struct xhci_event_cmd           event_cmd;
1155         struct xhci_generic_trb         generic;
1156 };
1157
1158 /* TRB bit mask */
1159 #define TRB_TYPE_BITMASK        (0xfc00)
1160 #define TRB_TYPE(p)             ((p) << 10)
1161 #define TRB_FIELD_TO_TYPE(p)    (((p) & TRB_TYPE_BITMASK) >> 10)
1162 /* TRB type IDs */
1163 /* bulk, interrupt, isoc scatter/gather, and control data stage */
1164 #define TRB_NORMAL              1
1165 /* setup stage for control transfers */
1166 #define TRB_SETUP               2
1167 /* data stage for control transfers */
1168 #define TRB_DATA                3
1169 /* status stage for control transfers */
1170 #define TRB_STATUS              4
1171 /* isoc transfers */
1172 #define TRB_ISOC                5
1173 /* TRB for linking ring segments */
1174 #define TRB_LINK                6
1175 #define TRB_EVENT_DATA          7
1176 /* Transfer Ring No-op (not for the command ring) */
1177 #define TRB_TR_NOOP             8
1178 /* Command TRBs */
1179 /* Enable Slot Command */
1180 #define TRB_ENABLE_SLOT         9
1181 /* Disable Slot Command */
1182 #define TRB_DISABLE_SLOT        10
1183 /* Address Device Command */
1184 #define TRB_ADDR_DEV            11
1185 /* Configure Endpoint Command */
1186 #define TRB_CONFIG_EP           12
1187 /* Evaluate Context Command */
1188 #define TRB_EVAL_CONTEXT        13
1189 /* Reset Endpoint Command */
1190 #define TRB_RESET_EP            14
1191 /* Stop Transfer Ring Command */
1192 #define TRB_STOP_RING           15
1193 /* Set Transfer Ring Dequeue Pointer Command */
1194 #define TRB_SET_DEQ             16
1195 /* Reset Device Command */
1196 #define TRB_RESET_DEV           17
1197 /* Force Event Command (opt) */
1198 #define TRB_FORCE_EVENT         18
1199 /* Negotiate Bandwidth Command (opt) */
1200 #define TRB_NEG_BANDWIDTH       19
1201 /* Set Latency Tolerance Value Command (opt) */
1202 #define TRB_SET_LT              20
1203 /* Get port bandwidth Command */
1204 #define TRB_GET_BW              21
1205 /* Force Header Command - generate a transaction or link management packet */
1206 #define TRB_FORCE_HEADER        22
1207 /* No-op Command - not for transfer rings */
1208 #define TRB_CMD_NOOP            23
1209 /* TRB IDs 24-31 reserved */
1210 /* Event TRBS */
1211 /* Transfer Event */
1212 #define TRB_TRANSFER            32
1213 /* Command Completion Event */
1214 #define TRB_COMPLETION          33
1215 /* Port Status Change Event */
1216 #define TRB_PORT_STATUS         34
1217 /* Bandwidth Request Event (opt) */
1218 #define TRB_BANDWIDTH_EVENT     35
1219 /* Doorbell Event (opt) */
1220 #define TRB_DOORBELL            36
1221 /* Host Controller Event */
1222 #define TRB_HC_EVENT            37
1223 /* Device Notification Event - device sent function wake notification */
1224 #define TRB_DEV_NOTE            38
1225 /* MFINDEX Wrap Event - microframe counter wrapped */
1226 #define TRB_MFINDEX_WRAP        39
1227 /* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1228
1229 /* Nec vendor-specific command completion event. */
1230 #define TRB_NEC_CMD_COMP        48
1231 /* Get NEC firmware revision. */
1232 #define TRB_NEC_GET_FW          49
1233
1234 #define TRB_TYPE_LINK(x)        (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1235 /* Above, but for __le32 types -- can avoid work by swapping constants: */
1236 #define TRB_TYPE_LINK_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1237                                  cpu_to_le32(TRB_TYPE(TRB_LINK)))
1238 #define TRB_TYPE_NOOP_LE32(x)   (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1239                                  cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1240
1241 #define NEC_FW_MINOR(p)         (((p) >> 0) & 0xff)
1242 #define NEC_FW_MAJOR(p)         (((p) >> 8) & 0xff)
1243
1244 /*
1245  * TRBS_PER_SEGMENT must be a multiple of 4,
1246  * since the command ring is 64-byte aligned.
1247  * It must also be greater than 16.
1248  */
1249 #define TRBS_PER_SEGMENT        256
1250 /* Allow two commands + a link TRB, along with any reserved command TRBs */
1251 #define MAX_RSVD_CMD_TRBS       (TRBS_PER_SEGMENT - 3)
1252 #define TRB_SEGMENT_SIZE        (TRBS_PER_SEGMENT*16)
1253 #define TRB_SEGMENT_SHIFT       (ilog2(TRB_SEGMENT_SIZE))
1254 /* TRB buffer pointers can't cross 64KB boundaries */
1255 #define TRB_MAX_BUFF_SHIFT              16
1256 #define TRB_MAX_BUFF_SIZE       (1 << TRB_MAX_BUFF_SHIFT)
1257
1258 struct xhci_segment {
1259         union xhci_trb          *trbs;
1260         /* private to HCD */
1261         struct xhci_segment     *next;
1262         dma_addr_t              dma;
1263 };
1264
1265 struct xhci_td {
1266         struct list_head        td_list;
1267         struct list_head        cancelled_td_list;
1268         struct urb              *urb;
1269         struct xhci_segment     *start_seg;
1270         union xhci_trb          *first_trb;
1271         union xhci_trb          *last_trb;
1272         /* actual_length of the URB has already been set */
1273         bool                    urb_length_set;
1274 };
1275
1276 /* xHCI command default timeout value */
1277 #define XHCI_CMD_DEFAULT_TIMEOUT        (5 * HZ)
1278
1279 /* command descriptor */
1280 struct xhci_cd {
1281         struct list_head        cancel_cmd_list;
1282         struct xhci_command     *command;
1283         union xhci_trb          *cmd_trb;
1284 };
1285
1286 struct xhci_dequeue_state {
1287         struct xhci_segment *new_deq_seg;
1288         union xhci_trb *new_deq_ptr;
1289         int new_cycle_state;
1290 };
1291
1292 enum xhci_ring_type {
1293         TYPE_CTRL = 0,
1294         TYPE_ISOC,
1295         TYPE_BULK,
1296         TYPE_INTR,
1297         TYPE_STREAM,
1298         TYPE_COMMAND,
1299         TYPE_EVENT,
1300 };
1301
1302 struct xhci_ring {
1303         struct xhci_segment     *first_seg;
1304         struct xhci_segment     *last_seg;
1305         union  xhci_trb         *enqueue;
1306         struct xhci_segment     *enq_seg;
1307         unsigned int            enq_updates;
1308         union  xhci_trb         *dequeue;
1309         struct xhci_segment     *deq_seg;
1310         unsigned int            deq_updates;
1311         struct list_head        td_list;
1312         /*
1313          * Write the cycle state into the TRB cycle field to give ownership of
1314          * the TRB to the host controller (if we are the producer), or to check
1315          * if we own the TRB (if we are the consumer).  See section 4.9.1.
1316          */
1317         u32                     cycle_state;
1318         unsigned int            stream_id;
1319         unsigned int            num_segs;
1320         unsigned int            num_trbs_free;
1321         unsigned int            num_trbs_free_temp;
1322         enum xhci_ring_type     type;
1323         bool                    last_td_was_short;
1324 };
1325
1326 struct xhci_erst_entry {
1327         /* 64-bit event ring segment address */
1328         __le64  seg_addr;
1329         __le32  seg_size;
1330         /* Set to zero */
1331         __le32  rsvd;
1332 };
1333
1334 struct xhci_erst {
1335         struct xhci_erst_entry  *entries;
1336         unsigned int            num_entries;
1337         /* xhci->event_ring keeps track of segment dma addresses */
1338         dma_addr_t              erst_dma_addr;
1339         /* Num entries the ERST can contain */
1340         unsigned int            erst_size;
1341 };
1342
1343 struct xhci_scratchpad {
1344         u64 *sp_array;
1345         dma_addr_t sp_dma;
1346         void **sp_buffers;
1347         dma_addr_t *sp_dma_buffers;
1348 };
1349
1350 struct urb_priv {
1351         int     length;
1352         int     td_cnt;
1353         struct  xhci_td *td[0];
1354 };
1355
1356 /*
1357  * Each segment table entry is 4*32bits long.  1K seems like an ok size:
1358  * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1359  * meaning 64 ring segments.
1360  * Initial allocated size of the ERST, in number of entries */
1361 #define ERST_NUM_SEGS   1
1362 /* Initial allocated size of the ERST, in number of entries */
1363 #define ERST_SIZE       64
1364 /* Initial number of event segment rings allocated */
1365 #define ERST_ENTRIES    1
1366 /* Poll every 60 seconds */
1367 #define POLL_TIMEOUT    60
1368 /* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1369 #define XHCI_STOP_EP_CMD_TIMEOUT        5
1370 /* XXX: Make these module parameters */
1371
1372 struct s3_save {
1373         u32     command;
1374         u32     dev_nt;
1375         u64     dcbaa_ptr;
1376         u32     config_reg;
1377         u32     irq_pending;
1378         u32     irq_control;
1379         u32     erst_size;
1380         u64     erst_base;
1381         u64     erst_dequeue;
1382 };
1383
1384 /* Use for lpm */
1385 struct dev_info {
1386         u32                     dev_id;
1387         struct  list_head       list;
1388 };
1389
1390 struct xhci_bus_state {
1391         unsigned long           bus_suspended;
1392         unsigned long           next_statechange;
1393
1394         /* Port suspend arrays are indexed by the portnum of the fake roothub */
1395         /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1396         u32                     port_c_suspend;
1397         u32                     suspended_ports;
1398         u32                     port_remote_wakeup;
1399         unsigned long           resume_done[USB_MAXCHILDREN];
1400         /* which ports have started to resume */
1401         unsigned long           resuming_ports;
1402 };
1403
1404 static inline unsigned int hcd_index(struct usb_hcd *hcd)
1405 {
1406         if (hcd->speed == HCD_USB3)
1407                 return 0;
1408         else
1409                 return 1;
1410 }
1411
1412 /* There is one xhci_hcd structure per controller */
1413 struct xhci_hcd {
1414         struct usb_hcd *main_hcd;
1415         struct usb_hcd *shared_hcd;
1416         /* glue to PCI and HCD framework */
1417         struct xhci_cap_regs __iomem *cap_regs;
1418         struct xhci_op_regs __iomem *op_regs;
1419         struct xhci_run_regs __iomem *run_regs;
1420         struct xhci_doorbell_array __iomem *dba;
1421         /* Our HCD's current interrupter register set */
1422         struct  xhci_intr_reg __iomem *ir_set;
1423
1424         #ifdef CONFIG_MTK_XHCI
1425         unsigned long base_regs;
1426         unsigned long sif_regs;
1427         unsigned long sif2_regs;
1428         #endif
1429
1430         /* Cached register copies of read-only HC data */
1431         __u32           hcs_params1;
1432         __u32           hcs_params2;
1433         __u32           hcs_params3;
1434         __u32           hcc_params;
1435
1436         spinlock_t      lock;
1437
1438         /* packed release number */
1439         u8              sbrn;
1440         u16             hci_version;
1441         u8              max_slots;
1442         u8              max_interrupters;
1443         u8              max_ports;
1444         u8              isoc_threshold;
1445         int             event_ring_max;
1446         int             addr_64;
1447         /* 4KB min, 128MB max */
1448         int             page_size;
1449         /* Valid values are 12 to 20, inclusive */
1450         int             page_shift;
1451         /* msi-x vectors */
1452         int             msix_count;
1453         struct msix_entry       *msix_entries;
1454         /* data structures */
1455         struct xhci_device_context_array *dcbaa;
1456         struct xhci_ring        *cmd_ring;
1457         unsigned int            cmd_ring_state;
1458 #define CMD_RING_STATE_RUNNING         (1 << 0)
1459 #define CMD_RING_STATE_ABORTED         (1 << 1)
1460 #define CMD_RING_STATE_STOPPED         (1 << 2)
1461         struct list_head        cancel_cmd_list;
1462         unsigned int            cmd_ring_reserved_trbs;
1463         struct xhci_ring        *event_ring;
1464         struct xhci_erst        erst;
1465         /* Scratchpad */
1466         struct xhci_scratchpad  *scratchpad;
1467         /* Store LPM test failed devices' information */
1468         struct list_head        lpm_failed_devs;
1469
1470         /* slot enabling and address device helpers */
1471         struct completion       addr_dev;
1472         int slot_id;
1473         /* For USB 3.0 LPM enable/disable. */
1474         struct xhci_command             *lpm_command;
1475         /* Internal mirror of the HW's dcbaa */
1476         struct xhci_virt_device *devs[MAX_HC_SLOTS];
1477         /* For keeping track of bandwidth domains per roothub. */
1478         struct xhci_root_port_bw_info   *rh_bw;
1479
1480         /* DMA pools */
1481         struct dma_pool *device_pool;
1482         struct dma_pool *segment_pool;
1483         struct dma_pool *small_streams_pool;
1484         struct dma_pool *medium_streams_pool;
1485
1486 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1487         /* Poll the rings - for debugging */
1488         struct timer_list       event_ring_timer;
1489         int                     zombie;
1490 #endif
1491         /* Host controller watchdog timer structures */
1492         unsigned int            xhc_state;
1493
1494         u32                     command;
1495         struct s3_save          s3;
1496 /* Host controller is dying - not responding to commands. "I'm not dead yet!"
1497  *
1498  * xHC interrupts have been disabled and a watchdog timer will (or has already)
1499  * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code.  Any code
1500  * that sees this status (other than the timer that set it) should stop touching
1501  * hardware immediately.  Interrupt handlers should return immediately when
1502  * they see this status (any time they drop and re-acquire xhci->lock).
1503  * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1504  * putting the TD on the canceled list, etc.
1505  *
1506  * There are no reports of xHCI host controllers that display this issue.
1507  */
1508 #define XHCI_STATE_DYING        (1 << 0)
1509 #define XHCI_STATE_HALTED       (1 << 1)
1510         /* Statistics */
1511         int                     error_bitmask;
1512         unsigned int            quirks;
1513 #define XHCI_LINK_TRB_QUIRK     (1 << 0)
1514 #define XHCI_RESET_EP_QUIRK     (1 << 1)
1515 #define XHCI_NEC_HOST           (1 << 2)
1516 #ifndef CONFIG_MTK_XHCI
1517 #define XHCI_AMD_PLL_FIX        (1 << 3)
1518 #endif
1519 #define XHCI_SPURIOUS_SUCCESS   (1 << 4)
1520 /*
1521  * Certain Intel host controllers have a limit to the number of endpoint
1522  * contexts they can handle.  Ideally, they would signal that they can't handle
1523  * anymore endpoint contexts by returning a Resource Error for the Configure
1524  * Endpoint command, but they don't.  Instead they expect software to keep track
1525  * of the number of active endpoints for them, across configure endpoint
1526  * commands, reset device commands, disable slot commands, and address device
1527  * commands.
1528  */
1529 #define XHCI_EP_LIMIT_QUIRK     (1 << 5)
1530 #define XHCI_BROKEN_MSI         (1 << 6)
1531 #define XHCI_RESET_ON_RESUME    (1 << 7)
1532 #define XHCI_SW_BW_CHECKING     (1 << 8)
1533 #ifndef CONFIG_MTK_XHCI
1534 #define XHCI_AMD_0x96_HOST      (1 << 9)
1535 #endif
1536 #define XHCI_TRUST_TX_LENGTH    (1 << 10)
1537 #define XHCI_LPM_SUPPORT        (1 << 11)
1538 #define XHCI_INTEL_HOST         (1 << 12)
1539 #define XHCI_SPURIOUS_REBOOT    (1 << 13)
1540 #define XHCI_COMP_MODE_QUIRK    (1 << 14)
1541 #define XHCI_AVOID_BEI          (1 << 15)
1542 #define XHCI_PLAT               (1 << 16)
1543         unsigned int            num_active_eps;
1544         unsigned int            limit_active_eps;
1545         /* There are two roothubs to keep track of bus suspend info for */
1546         struct xhci_bus_state   bus_state[2];
1547         /* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
1548         u8                      *port_array;
1549         /* Array of pointers to USB 3.0 PORTSC registers */
1550         __le32 __iomem          **usb3_ports;
1551         unsigned int            num_usb3_ports;
1552         /* Array of pointers to USB 2.0 PORTSC registers */
1553         __le32 __iomem          **usb2_ports;
1554         unsigned int            num_usb2_ports;
1555         /* support xHCI 0.96 spec USB2 software LPM */
1556         unsigned                sw_lpm_support:1;
1557         /* support xHCI 1.0 spec USB2 hardware LPM */
1558         unsigned                hw_lpm_support:1;
1559         /* Compliance Mode Recovery Data */
1560         struct timer_list       comp_mode_recovery_timer;
1561         u32                     port_status_u0;
1562 /* Compliance Mode Timer Triggered every 2 seconds */
1563 #define COMP_MODE_RCVRY_MSECS 2000
1564 };
1565
1566 /* convert between an HCD pointer and the corresponding EHCI_HCD */
1567 static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1568 {
1569         return *((struct xhci_hcd **) (hcd->hcd_priv));
1570 }
1571
1572 static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1573 {
1574         return xhci->main_hcd;
1575 }
1576
1577 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1578 #define XHCI_DEBUG      1
1579 #else
1580 #define XHCI_DEBUG      0
1581 #endif
1582
1583 #define xhci_dbg(xhci, fmt, args...) \
1584         do { if (XHCI_DEBUG) dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1585 #define xhci_info(xhci, fmt, args...) \
1586         do { if (XHCI_DEBUG) dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args); } while (0)
1587 #define xhci_err(xhci, fmt, args...) \
1588         dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1589 #define xhci_warn(xhci, fmt, args...) \
1590         dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1591 #define xhci_warn_ratelimited(xhci, fmt, args...) \
1592         dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1593
1594 /* TODO: copied from ehci.h - can be refactored? */
1595 /* xHCI spec says all registers are little endian */
1596 static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
1597                 void __iomem *regs)
1598 {
1599         return readl(regs);
1600 }
1601 static inline void xhci_writel(struct xhci_hcd *xhci,
1602                 const unsigned int val, void __iomem *regs)
1603 {
1604         writel(val, regs);
1605 }
1606
1607 /*
1608  * Registers should always be accessed with double word or quad word accesses.
1609  *
1610  * Some xHCI implementations may support 64-bit address pointers.  Registers
1611  * with 64-bit address pointers should be written to with dword accesses by
1612  * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1613  * xHCI implementations that do not support 64-bit address pointers will ignore
1614  * the high dword, and write order is irrelevant.
1615  */
1616 static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1617                 __le64 __iomem *regs)
1618 {
1619         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1620         u64 val_lo = readl(ptr);
1621         u64 val_hi = readl(ptr + 1);
1622         return val_lo + (val_hi << 32);
1623 }
1624 static inline void xhci_write_64(struct xhci_hcd *xhci,
1625                                  const u64 val, __le64 __iomem *regs)
1626 {
1627         __u32 __iomem *ptr = (__u32 __iomem *) regs;
1628         u32 val_lo = lower_32_bits(val);
1629         u32 val_hi = upper_32_bits(val);
1630
1631         writel(val_lo, ptr);
1632         writel(val_hi, ptr + 1);
1633 }
1634
1635 static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1636 {
1637         return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1638 }
1639
1640 /* xHCI debugging */
1641 void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num);
1642 void xhci_print_registers(struct xhci_hcd *xhci);
1643 void xhci_dbg_regs(struct xhci_hcd *xhci);
1644 void xhci_print_run_regs(struct xhci_hcd *xhci);
1645 void xhci_print_trb_offsets(struct xhci_hcd *xhci, union xhci_trb *trb);
1646 void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb);
1647 void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg);
1648 void xhci_debug_ring(struct xhci_hcd *xhci, struct xhci_ring *ring);
1649 void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
1650 void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci);
1651 void xhci_dbg_ring_ptrs(struct xhci_hcd *xhci, struct xhci_ring *ring);
1652 void xhci_dbg_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int last_ep);
1653 char *xhci_get_slot_state(struct xhci_hcd *xhci,
1654                 struct xhci_container_ctx *ctx);
1655 void xhci_dbg_ep_rings(struct xhci_hcd *xhci,
1656                 unsigned int slot_id, unsigned int ep_index,
1657                 struct xhci_virt_ep *ep);
1658
1659 /* xHCI memory management */
1660 void xhci_mem_cleanup(struct xhci_hcd *xhci);
1661 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1662 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1663 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1664 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1665 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1666                 struct usb_device *udev);
1667 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1668 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc);
1669 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index);
1670 unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1671 void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1672 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
1673                 struct xhci_bw_info *ep_bw,
1674                 struct xhci_interval_bw_table *bw_table,
1675                 struct usb_device *udev,
1676                 struct xhci_virt_ep *virt_ep,
1677                 struct xhci_tt_bw_info *tt_info);
1678 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1679                 struct xhci_virt_device *virt_dev,
1680                 int old_active_eps);
1681 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1682 void xhci_update_bw_info(struct xhci_hcd *xhci,
1683                 struct xhci_container_ctx *in_ctx,
1684                 struct xhci_input_control_ctx *ctrl_ctx,
1685                 struct xhci_virt_device *virt_dev);
1686 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1687                 struct xhci_container_ctx *in_ctx,
1688                 struct xhci_container_ctx *out_ctx,
1689                 unsigned int ep_index);
1690 void xhci_slot_copy(struct xhci_hcd *xhci,
1691                 struct xhci_container_ctx *in_ctx,
1692                 struct xhci_container_ctx *out_ctx);
1693 int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1694                 struct usb_device *udev, struct usb_host_endpoint *ep,
1695                 gfp_t mem_flags);
1696 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1697 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1698                                 unsigned int num_trbs, gfp_t flags);
1699 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
1700                 struct xhci_virt_device *virt_dev,
1701                 unsigned int ep_index);
1702 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1703                 unsigned int num_stream_ctxs,
1704                 unsigned int num_streams, gfp_t flags);
1705 void xhci_free_stream_info(struct xhci_hcd *xhci,
1706                 struct xhci_stream_info *stream_info);
1707 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1708                 struct xhci_ep_ctx *ep_ctx,
1709                 struct xhci_stream_info *stream_info);
1710 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
1711                 struct xhci_ep_ctx *ep_ctx,
1712                 struct xhci_virt_ep *ep);
1713 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1714         struct xhci_virt_device *virt_dev, bool drop_control_ep);
1715 struct xhci_ring *xhci_dma_to_transfer_ring(
1716                 struct xhci_virt_ep *ep,
1717                 u64 address);
1718 struct xhci_ring *xhci_stream_id_to_ring(
1719                 struct xhci_virt_device *dev,
1720                 unsigned int ep_index,
1721                 unsigned int stream_id);
1722 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1723                 bool allocate_in_ctx, bool allocate_completion,
1724                 gfp_t mem_flags);
1725 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv);
1726 void xhci_free_command(struct xhci_hcd *xhci,
1727                 struct xhci_command *command);
1728
1729 #ifdef CONFIG_PCI
1730 /* xHCI PCI glue */
1731 int xhci_register_pci(void);
1732 void xhci_unregister_pci(void);
1733 #else
1734 static inline int xhci_register_pci(void) { return 0; }
1735 static inline void xhci_unregister_pci(void) {}
1736 #endif
1737
1738 #if defined(CONFIG_USB_XHCI_PLATFORM) \
1739         || defined(CONFIG_USB_XHCI_PLATFORM_MODULE)
1740 int xhci_register_plat(void);
1741 void xhci_unregister_plat(void);
1742 #else
1743 static inline int xhci_register_plat(void)
1744 { return 0; }
1745 static inline void xhci_unregister_plat(void)
1746 {  }
1747 #endif
1748
1749 /* xHCI host controller glue */
1750 typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1751 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
1752                 u32 mask, u32 done, int usec);
1753 void xhci_quiesce(struct xhci_hcd *xhci);
1754 int xhci_halt(struct xhci_hcd *xhci);
1755 int xhci_reset(struct xhci_hcd *xhci);
1756 int xhci_init(struct usb_hcd *hcd);
1757 int xhci_run(struct usb_hcd *hcd);
1758 void xhci_stop(struct usb_hcd *hcd);
1759 void xhci_shutdown(struct usb_hcd *hcd);
1760 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1761
1762 #ifdef  CONFIG_PM
1763 int xhci_suspend(struct xhci_hcd *xhci);
1764 int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
1765 #else
1766 #define xhci_suspend    NULL
1767 #define xhci_resume     NULL
1768 #endif
1769
1770 int xhci_get_frame(struct usb_hcd *hcd);
1771 irqreturn_t xhci_irq(struct usb_hcd *hcd);
1772 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd);
1773 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1774 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev);
1775 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1776                 struct xhci_virt_device *virt_dev,
1777                 struct usb_device *hdev,
1778                 struct usb_tt *tt, gfp_t mem_flags);
1779 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
1780                 struct usb_host_endpoint **eps, unsigned int num_eps,
1781                 unsigned int num_streams, gfp_t mem_flags);
1782 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
1783                 struct usb_host_endpoint **eps, unsigned int num_eps,
1784                 gfp_t mem_flags);
1785 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev);
1786 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev);
1787 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
1788                                 struct usb_device *udev, int enable);
1789 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1790                         struct usb_tt *tt, gfp_t mem_flags);
1791 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags);
1792 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
1793 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1794 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev, struct usb_host_endpoint *ep);
1795 void xhci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
1796 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev);
1797 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1798 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1799
1800 /* xHCI ring, segment, TRB, and TD functions */
1801 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1802 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1803                 union xhci_trb *start_trb, union xhci_trb *end_trb,
1804                 dma_addr_t suspect_dma);
1805 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1806 void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1807 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id);
1808 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1809                 u32 slot_id);
1810 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
1811                 u32 field1, u32 field2, u32 field3, u32 field4);
1812 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
1813                 unsigned int ep_index, int suspend);
1814 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1815                 int slot_id, unsigned int ep_index);
1816 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1817                 int slot_id, unsigned int ep_index);
1818 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1819                 int slot_id, unsigned int ep_index);
1820 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1821                 struct urb *urb, int slot_id, unsigned int ep_index);
1822 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1823                 u32 slot_id, bool command_must_succeed);
1824 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
1825                 u32 slot_id, bool command_must_succeed);
1826 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
1827                 unsigned int ep_index);
1828 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id);
1829 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
1830                 unsigned int slot_id, unsigned int ep_index,
1831                 unsigned int stream_id, struct xhci_td *cur_td,
1832                 struct xhci_dequeue_state *state);
1833 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
1834                 unsigned int slot_id, unsigned int ep_index,
1835                 unsigned int stream_id,
1836                 struct xhci_dequeue_state *deq_state);
1837 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
1838                 struct usb_device *udev, unsigned int ep_index);
1839 void xhci_queue_config_ep_quirk(struct xhci_hcd *xhci,
1840                 unsigned int slot_id, unsigned int ep_index,
1841                 struct xhci_dequeue_state *deq_state);
1842 void xhci_stop_endpoint_command_watchdog(unsigned long arg);
1843 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
1844                 union xhci_trb *cmd_trb);
1845 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1846                 unsigned int ep_index, unsigned int stream_id);
1847 union xhci_trb *xhci_find_next_enqueue(struct xhci_ring *ring);
1848
1849 /* xHCI roothub code */
1850 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1851                                 int port_id, u32 link_state);
1852 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
1853                         struct usb_device *udev, enum usb3_link_state state);
1854 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
1855                         struct usb_device *udev, enum usb3_link_state state);
1856 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
1857                                 int port_id, u32 port_bit);
1858 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1859                 char *buf, u16 wLength);
1860 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1861 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1862
1863 #ifdef CONFIG_PM
1864 int xhci_bus_suspend(struct usb_hcd *hcd);
1865 int xhci_bus_resume(struct usb_hcd *hcd);
1866 #else
1867 #define xhci_bus_suspend        NULL
1868 #define xhci_bus_resume         NULL
1869 #endif  /* CONFIG_PM */
1870
1871 u32 xhci_port_state_to_neutral(u32 state);
1872 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
1873                 u16 port);
1874 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1875
1876 /* xHCI contexts */
1877 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1878 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1879 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1880
1881 /* xHCI quirks */
1882 bool xhci_compliance_mode_recovery_timer_quirk_check(void);
1883
1884 #endif /* __LINUX_XHCI_HCD_H */