usb/xhci: fix compilation warning when !CONFIG_PCI && !CONFIG_PM
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / host / xhci.c
1 /*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/pci.h>
24 #include <linux/irq.h>
25 #include <linux/log2.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/slab.h>
29 #include <linux/dmi.h>
30
31 #include "xhci.h"
32
33 #define DRIVER_AUTHOR "Sarah Sharp"
34 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
35
36 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
37 static int link_quirk;
38 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
39 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
40
41 /* TODO: copied from ehci-hcd.c - can this be refactored? */
42 /*
43 * xhci_handshake - spin reading hc until handshake completes or fails
44 * @ptr: address of hc register to be read
45 * @mask: bits to look at in result of read
46 * @done: value of those bits when handshake succeeds
47 * @usec: timeout in microseconds
48 *
49 * Returns negative errno, or zero on success
50 *
51 * Success happens when the "mask" bits have the specified value (hardware
52 * handshake done). There are two failure modes: "usec" have passed (major
53 * hardware flakeout), or the register reads as all-ones (hardware removed).
54 */
55 int xhci_handshake(struct xhci_hcd *xhci, void __iomem *ptr,
56 u32 mask, u32 done, int usec)
57 {
58 u32 result;
59
60 do {
61 result = xhci_readl(xhci, ptr);
62 if (result == ~(u32)0) /* card removed */
63 return -ENODEV;
64 result &= mask;
65 if (result == done)
66 return 0;
67 udelay(1);
68 usec--;
69 } while (usec > 0);
70 return -ETIMEDOUT;
71 }
72
73 /*
74 * Disable interrupts and begin the xHCI halting process.
75 */
76 void xhci_quiesce(struct xhci_hcd *xhci)
77 {
78 u32 halted;
79 u32 cmd;
80 u32 mask;
81
82 mask = ~(XHCI_IRQS);
83 halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
84 if (!halted)
85 mask &= ~CMD_RUN;
86
87 cmd = xhci_readl(xhci, &xhci->op_regs->command);
88 cmd &= mask;
89 xhci_writel(xhci, cmd, &xhci->op_regs->command);
90 }
91
92 /*
93 * Force HC into halt state.
94 *
95 * Disable any IRQs and clear the run/stop bit.
96 * HC will complete any current and actively pipelined transactions, and
97 * should halt within 16 ms of the run/stop bit being cleared.
98 * Read HC Halted bit in the status register to see when the HC is finished.
99 */
100 int xhci_halt(struct xhci_hcd *xhci)
101 {
102 int ret;
103 xhci_dbg(xhci, "// Halt the HC\n");
104 xhci_quiesce(xhci);
105
106 ret = xhci_handshake(xhci, &xhci->op_regs->status,
107 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
108 if (!ret) {
109 xhci->xhc_state |= XHCI_STATE_HALTED;
110 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
111 } else
112 xhci_warn(xhci, "Host not halted after %u microseconds.\n",
113 XHCI_MAX_HALT_USEC);
114 return ret;
115 }
116
117 /*
118 * Set the run bit and wait for the host to be running.
119 */
120 static int xhci_start(struct xhci_hcd *xhci)
121 {
122 u32 temp;
123 int ret;
124
125 temp = xhci_readl(xhci, &xhci->op_regs->command);
126 temp |= (CMD_RUN);
127 xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
128 temp);
129 xhci_writel(xhci, temp, &xhci->op_regs->command);
130
131 /*
132 * Wait for the HCHalted Status bit to be 0 to indicate the host is
133 * running.
134 */
135 ret = xhci_handshake(xhci, &xhci->op_regs->status,
136 STS_HALT, 0, XHCI_MAX_HALT_USEC);
137 if (ret == -ETIMEDOUT)
138 xhci_err(xhci, "Host took too long to start, "
139 "waited %u microseconds.\n",
140 XHCI_MAX_HALT_USEC);
141 if (!ret)
142 xhci->xhc_state &= ~XHCI_STATE_HALTED;
143 return ret;
144 }
145
146 /*
147 * Reset a halted HC.
148 *
149 * This resets pipelines, timers, counters, state machines, etc.
150 * Transactions will be terminated immediately, and operational registers
151 * will be set to their defaults.
152 */
153 int xhci_reset(struct xhci_hcd *xhci)
154 {
155 u32 command;
156 u32 state;
157 int ret, i;
158
159 state = xhci_readl(xhci, &xhci->op_regs->status);
160 if ((state & STS_HALT) == 0) {
161 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
162 return 0;
163 }
164
165 xhci_dbg(xhci, "// Reset the HC\n");
166 command = xhci_readl(xhci, &xhci->op_regs->command);
167 command |= CMD_RESET;
168 xhci_writel(xhci, command, &xhci->op_regs->command);
169
170 ret = xhci_handshake(xhci, &xhci->op_regs->command,
171 CMD_RESET, 0, 10 * 1000 * 1000);
172 if (ret)
173 return ret;
174
175 xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
176 /*
177 * xHCI cannot write to any doorbells or operational registers other
178 * than status until the "Controller Not Ready" flag is cleared.
179 */
180 ret = xhci_handshake(xhci, &xhci->op_regs->status,
181 STS_CNR, 0, 10 * 1000 * 1000);
182
183 for (i = 0; i < 2; ++i) {
184 xhci->bus_state[i].port_c_suspend = 0;
185 xhci->bus_state[i].suspended_ports = 0;
186 xhci->bus_state[i].resuming_ports = 0;
187 }
188
189 return ret;
190 }
191
192 #ifdef CONFIG_PCI
193 static int xhci_free_msi(struct xhci_hcd *xhci)
194 {
195 int i;
196
197 if (!xhci->msix_entries)
198 return -EINVAL;
199
200 for (i = 0; i < xhci->msix_count; i++)
201 if (xhci->msix_entries[i].vector)
202 free_irq(xhci->msix_entries[i].vector,
203 xhci_to_hcd(xhci));
204 return 0;
205 }
206
207 /*
208 * Set up MSI
209 */
210 static int xhci_setup_msi(struct xhci_hcd *xhci)
211 {
212 int ret;
213 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
214
215 ret = pci_enable_msi(pdev);
216 if (ret) {
217 xhci_dbg(xhci, "failed to allocate MSI entry\n");
218 return ret;
219 }
220
221 ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
222 0, "xhci_hcd", xhci_to_hcd(xhci));
223 if (ret) {
224 xhci_dbg(xhci, "disable MSI interrupt\n");
225 pci_disable_msi(pdev);
226 }
227
228 return ret;
229 }
230
231 /*
232 * Free IRQs
233 * free all IRQs request
234 */
235 static void xhci_free_irq(struct xhci_hcd *xhci)
236 {
237 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
238 int ret;
239
240 /* return if using legacy interrupt */
241 if (xhci_to_hcd(xhci)->irq > 0)
242 return;
243
244 ret = xhci_free_msi(xhci);
245 if (!ret)
246 return;
247 if (pdev->irq > 0)
248 free_irq(pdev->irq, xhci_to_hcd(xhci));
249
250 return;
251 }
252
253 /*
254 * Set up MSI-X
255 */
256 static int xhci_setup_msix(struct xhci_hcd *xhci)
257 {
258 int i, ret = 0;
259 struct usb_hcd *hcd = xhci_to_hcd(xhci);
260 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
261
262 /*
263 * calculate number of msi-x vectors supported.
264 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
265 * with max number of interrupters based on the xhci HCSPARAMS1.
266 * - num_online_cpus: maximum msi-x vectors per CPUs core.
267 * Add additional 1 vector to ensure always available interrupt.
268 */
269 xhci->msix_count = min(num_online_cpus() + 1,
270 HCS_MAX_INTRS(xhci->hcs_params1));
271
272 xhci->msix_entries =
273 kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
274 GFP_KERNEL);
275 if (!xhci->msix_entries) {
276 xhci_err(xhci, "Failed to allocate MSI-X entries\n");
277 return -ENOMEM;
278 }
279
280 for (i = 0; i < xhci->msix_count; i++) {
281 xhci->msix_entries[i].entry = i;
282 xhci->msix_entries[i].vector = 0;
283 }
284
285 ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
286 if (ret) {
287 xhci_dbg(xhci, "Failed to enable MSI-X\n");
288 goto free_entries;
289 }
290
291 for (i = 0; i < xhci->msix_count; i++) {
292 ret = request_irq(xhci->msix_entries[i].vector,
293 (irq_handler_t)xhci_msi_irq,
294 0, "xhci_hcd", xhci_to_hcd(xhci));
295 if (ret)
296 goto disable_msix;
297 }
298
299 hcd->msix_enabled = 1;
300 return ret;
301
302 disable_msix:
303 xhci_dbg(xhci, "disable MSI-X interrupt\n");
304 xhci_free_irq(xhci);
305 pci_disable_msix(pdev);
306 free_entries:
307 kfree(xhci->msix_entries);
308 xhci->msix_entries = NULL;
309 return ret;
310 }
311
312 /* Free any IRQs and disable MSI-X */
313 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
314 {
315 struct usb_hcd *hcd = xhci_to_hcd(xhci);
316 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
317
318 if (xhci->quirks & XHCI_PLAT)
319 return;
320
321 xhci_free_irq(xhci);
322
323 if (xhci->msix_entries) {
324 pci_disable_msix(pdev);
325 kfree(xhci->msix_entries);
326 xhci->msix_entries = NULL;
327 } else {
328 pci_disable_msi(pdev);
329 }
330
331 hcd->msix_enabled = 0;
332 return;
333 }
334
335 static void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
336 {
337 int i;
338
339 if (xhci->msix_entries) {
340 for (i = 0; i < xhci->msix_count; i++)
341 synchronize_irq(xhci->msix_entries[i].vector);
342 }
343 }
344
345 static int xhci_try_enable_msi(struct usb_hcd *hcd)
346 {
347 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
348 struct pci_dev *pdev;
349 int ret;
350
351 /* The xhci platform device has set up IRQs through usb_add_hcd. */
352 if (xhci->quirks & XHCI_PLAT)
353 return 0;
354
355 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
356 /*
357 * Some Fresco Logic host controllers advertise MSI, but fail to
358 * generate interrupts. Don't even try to enable MSI.
359 */
360 if (xhci->quirks & XHCI_BROKEN_MSI)
361 goto legacy_irq;
362
363 /* unregister the legacy interrupt */
364 if (hcd->irq)
365 free_irq(hcd->irq, hcd);
366 hcd->irq = 0;
367
368 ret = xhci_setup_msix(xhci);
369 if (ret)
370 /* fall back to msi*/
371 ret = xhci_setup_msi(xhci);
372
373 if (!ret)
374 /* hcd->irq is 0, we have MSI */
375 return 0;
376
377 if (!pdev->irq) {
378 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
379 return -EINVAL;
380 }
381
382 legacy_irq:
383 /* fall back to legacy interrupt*/
384 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
385 hcd->irq_descr, hcd);
386 if (ret) {
387 xhci_err(xhci, "request interrupt %d failed\n",
388 pdev->irq);
389 return ret;
390 }
391 hcd->irq = pdev->irq;
392 return 0;
393 }
394
395 #else
396
397 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
398 {
399 return 0;
400 }
401
402 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
403 {
404 }
405
406 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
407 {
408 }
409
410 #endif
411
412 static void compliance_mode_recovery(unsigned long arg)
413 {
414 struct xhci_hcd *xhci;
415 struct usb_hcd *hcd;
416 u32 temp;
417 int i;
418
419 xhci = (struct xhci_hcd *)arg;
420
421 for (i = 0; i < xhci->num_usb3_ports; i++) {
422 temp = xhci_readl(xhci, xhci->usb3_ports[i]);
423 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
424 /*
425 * Compliance Mode Detected. Letting USB Core
426 * handle the Warm Reset
427 */
428 xhci_dbg(xhci, "Compliance mode detected->port %d\n",
429 i + 1);
430 xhci_dbg(xhci, "Attempting compliance mode recovery\n");
431 hcd = xhci->shared_hcd;
432
433 if (hcd->state == HC_STATE_SUSPENDED)
434 usb_hcd_resume_root_hub(hcd);
435
436 usb_hcd_poll_rh_status(hcd);
437 }
438 }
439
440 if (xhci->port_status_u0 != ((1 << xhci->num_usb3_ports)-1))
441 mod_timer(&xhci->comp_mode_recovery_timer,
442 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
443 }
444
445 /*
446 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
447 * that causes ports behind that hardware to enter compliance mode sometimes.
448 * The quirk creates a timer that polls every 2 seconds the link state of
449 * each host controller's port and recovers it by issuing a Warm reset
450 * if Compliance mode is detected, otherwise the port will become "dead" (no
451 * device connections or disconnections will be detected anymore). Becasue no
452 * status event is generated when entering compliance mode (per xhci spec),
453 * this quirk is needed on systems that have the failing hardware installed.
454 */
455 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
456 {
457 xhci->port_status_u0 = 0;
458 init_timer(&xhci->comp_mode_recovery_timer);
459
460 xhci->comp_mode_recovery_timer.data = (unsigned long) xhci;
461 xhci->comp_mode_recovery_timer.function = compliance_mode_recovery;
462 xhci->comp_mode_recovery_timer.expires = jiffies +
463 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
464
465 set_timer_slack(&xhci->comp_mode_recovery_timer,
466 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
467 add_timer(&xhci->comp_mode_recovery_timer);
468 xhci_dbg(xhci, "Compliance mode recovery timer initialized\n");
469 }
470
471 /*
472 * This function identifies the systems that have installed the SN65LVPE502CP
473 * USB3.0 re-driver and that need the Compliance Mode Quirk.
474 * Systems:
475 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
476 */
477 bool xhci_compliance_mode_recovery_timer_quirk_check(void)
478 {
479 const char *dmi_product_name, *dmi_sys_vendor;
480
481 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
482 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
483 if (!dmi_product_name || !dmi_sys_vendor)
484 return false;
485
486 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
487 return false;
488
489 if (strstr(dmi_product_name, "Z420") ||
490 strstr(dmi_product_name, "Z620") ||
491 strstr(dmi_product_name, "Z820") ||
492 strstr(dmi_product_name, "Z1 Workstation"))
493 return true;
494
495 return false;
496 }
497
498 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
499 {
500 return (xhci->port_status_u0 == ((1 << xhci->num_usb3_ports)-1));
501 }
502
503
504 /*
505 * Initialize memory for HCD and xHC (one-time init).
506 *
507 * Program the PAGESIZE register, initialize the device context array, create
508 * device contexts (?), set up a command ring segment (or two?), create event
509 * ring (one for now).
510 */
511 int xhci_init(struct usb_hcd *hcd)
512 {
513 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
514 int retval = 0;
515
516 xhci_dbg(xhci, "xhci_init\n");
517 spin_lock_init(&xhci->lock);
518 if (xhci->hci_version == 0x95 && link_quirk) {
519 xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
520 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
521 } else {
522 xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
523 }
524 retval = xhci_mem_init(xhci, GFP_KERNEL);
525 xhci_dbg(xhci, "Finished xhci_init\n");
526
527 /* Initializing Compliance Mode Recovery Data If Needed */
528 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
529 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
530 compliance_mode_recovery_timer_init(xhci);
531 }
532
533 return retval;
534 }
535
536 /*-------------------------------------------------------------------------*/
537
538
539 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
540 static void xhci_event_ring_work(unsigned long arg)
541 {
542 unsigned long flags;
543 int temp;
544 u64 temp_64;
545 struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
546 int i, j;
547
548 xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
549
550 spin_lock_irqsave(&xhci->lock, flags);
551 temp = xhci_readl(xhci, &xhci->op_regs->status);
552 xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
553 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
554 (xhci->xhc_state & XHCI_STATE_HALTED)) {
555 xhci_dbg(xhci, "HW died, polling stopped.\n");
556 spin_unlock_irqrestore(&xhci->lock, flags);
557 return;
558 }
559
560 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
561 xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
562 xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
563 xhci->error_bitmask = 0;
564 xhci_dbg(xhci, "Event ring:\n");
565 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
566 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
567 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
568 temp_64 &= ~ERST_PTR_MASK;
569 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
570 xhci_dbg(xhci, "Command ring:\n");
571 xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
572 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
573 xhci_dbg_cmd_ptrs(xhci);
574 for (i = 0; i < MAX_HC_SLOTS; ++i) {
575 if (!xhci->devs[i])
576 continue;
577 for (j = 0; j < 31; ++j) {
578 xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
579 }
580 }
581 spin_unlock_irqrestore(&xhci->lock, flags);
582
583 if (!xhci->zombie)
584 mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
585 else
586 xhci_dbg(xhci, "Quit polling the event ring.\n");
587 }
588 #endif
589
590 static int xhci_run_finished(struct xhci_hcd *xhci)
591 {
592 if (xhci_start(xhci)) {
593 xhci_halt(xhci);
594 return -ENODEV;
595 }
596 xhci->shared_hcd->state = HC_STATE_RUNNING;
597 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
598
599 if (xhci->quirks & XHCI_NEC_HOST)
600 xhci_ring_cmd_db(xhci);
601
602 xhci_dbg(xhci, "Finished xhci_run for USB3 roothub\n");
603 return 0;
604 }
605
606 /*
607 * Start the HC after it was halted.
608 *
609 * This function is called by the USB core when the HC driver is added.
610 * Its opposite is xhci_stop().
611 *
612 * xhci_init() must be called once before this function can be called.
613 * Reset the HC, enable device slot contexts, program DCBAAP, and
614 * set command ring pointer and event ring pointer.
615 *
616 * Setup MSI-X vectors and enable interrupts.
617 */
618 int xhci_run(struct usb_hcd *hcd)
619 {
620 u32 temp;
621 u64 temp_64;
622 int ret;
623 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
624
625 /* Start the xHCI host controller running only after the USB 2.0 roothub
626 * is setup.
627 */
628
629 hcd->uses_new_polling = 1;
630 if (!usb_hcd_is_primary_hcd(hcd))
631 return xhci_run_finished(xhci);
632
633 xhci_dbg(xhci, "xhci_run\n");
634
635 ret = xhci_try_enable_msi(hcd);
636 if (ret)
637 return ret;
638
639 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
640 init_timer(&xhci->event_ring_timer);
641 xhci->event_ring_timer.data = (unsigned long) xhci;
642 xhci->event_ring_timer.function = xhci_event_ring_work;
643 /* Poll the event ring */
644 xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
645 xhci->zombie = 0;
646 xhci_dbg(xhci, "Setting event ring polling timer\n");
647 add_timer(&xhci->event_ring_timer);
648 #endif
649
650 xhci_dbg(xhci, "Command ring memory map follows:\n");
651 xhci_debug_ring(xhci, xhci->cmd_ring);
652 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
653 xhci_dbg_cmd_ptrs(xhci);
654
655 xhci_dbg(xhci, "ERST memory map follows:\n");
656 xhci_dbg_erst(xhci, &xhci->erst);
657 xhci_dbg(xhci, "Event ring:\n");
658 xhci_debug_ring(xhci, xhci->event_ring);
659 xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
660 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
661 temp_64 &= ~ERST_PTR_MASK;
662 xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
663
664 xhci_dbg(xhci, "// Set the interrupt modulation register\n");
665 temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
666 temp &= ~ER_IRQ_INTERVAL_MASK;
667 temp |= (u32) 160;
668 xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
669
670 /* Set the HCD state before we enable the irqs */
671 temp = xhci_readl(xhci, &xhci->op_regs->command);
672 temp |= (CMD_EIE);
673 xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
674 temp);
675 xhci_writel(xhci, temp, &xhci->op_regs->command);
676
677 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
678 xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
679 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
680 xhci_writel(xhci, ER_IRQ_ENABLE(temp),
681 &xhci->ir_set->irq_pending);
682 xhci_print_ir_set(xhci, 0);
683
684 if (xhci->quirks & XHCI_NEC_HOST)
685 xhci_queue_vendor_command(xhci, 0, 0, 0,
686 TRB_TYPE(TRB_NEC_GET_FW));
687
688 xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
689 return 0;
690 }
691
692 static void xhci_only_stop_hcd(struct usb_hcd *hcd)
693 {
694 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
695
696 spin_lock_irq(&xhci->lock);
697 xhci_halt(xhci);
698
699 /* The shared_hcd is going to be deallocated shortly (the USB core only
700 * calls this function when allocation fails in usb_add_hcd(), or
701 * usb_remove_hcd() is called). So we need to unset xHCI's pointer.
702 */
703 xhci->shared_hcd = NULL;
704 spin_unlock_irq(&xhci->lock);
705 }
706
707 /*
708 * Stop xHCI driver.
709 *
710 * This function is called by the USB core when the HC driver is removed.
711 * Its opposite is xhci_run().
712 *
713 * Disable device contexts, disable IRQs, and quiesce the HC.
714 * Reset the HC, finish any completed transactions, and cleanup memory.
715 */
716 void xhci_stop(struct usb_hcd *hcd)
717 {
718 u32 temp;
719 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
720
721 if (!usb_hcd_is_primary_hcd(hcd)) {
722 xhci_only_stop_hcd(xhci->shared_hcd);
723 return;
724 }
725
726 spin_lock_irq(&xhci->lock);
727 /* Make sure the xHC is halted for a USB3 roothub
728 * (xhci_stop() could be called as part of failed init).
729 */
730 xhci_halt(xhci);
731 xhci_reset(xhci);
732 spin_unlock_irq(&xhci->lock);
733
734 xhci_cleanup_msix(xhci);
735
736 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
737 /* Tell the event ring poll function not to reschedule */
738 xhci->zombie = 1;
739 del_timer_sync(&xhci->event_ring_timer);
740 #endif
741
742 /* Deleting Compliance Mode Recovery Timer */
743 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
744 (!(xhci_all_ports_seen_u0(xhci)))) {
745 del_timer_sync(&xhci->comp_mode_recovery_timer);
746 xhci_dbg(xhci, "%s: compliance mode recovery timer deleted\n",
747 __func__);
748 }
749
750 if (xhci->quirks & XHCI_AMD_PLL_FIX)
751 usb_amd_dev_put();
752
753 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
754 temp = xhci_readl(xhci, &xhci->op_regs->status);
755 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
756 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
757 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
758 &xhci->ir_set->irq_pending);
759 xhci_print_ir_set(xhci, 0);
760
761 xhci_dbg(xhci, "cleaning up memory\n");
762 xhci_mem_cleanup(xhci);
763 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
764 xhci_readl(xhci, &xhci->op_regs->status));
765 }
766
767 /*
768 * Shutdown HC (not bus-specific)
769 *
770 * This is called when the machine is rebooting or halting. We assume that the
771 * machine will be powered off, and the HC's internal state will be reset.
772 * Don't bother to free memory.
773 *
774 * This will only ever be called with the main usb_hcd (the USB3 roothub).
775 */
776 void xhci_shutdown(struct usb_hcd *hcd)
777 {
778 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
779
780 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
781 usb_disable_xhci_ports(to_pci_dev(hcd->self.controller));
782
783 spin_lock_irq(&xhci->lock);
784 xhci_halt(xhci);
785 spin_unlock_irq(&xhci->lock);
786
787 xhci_cleanup_msix(xhci);
788
789 xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
790 xhci_readl(xhci, &xhci->op_regs->status));
791 }
792
793 #ifdef CONFIG_PM
794 static void xhci_save_registers(struct xhci_hcd *xhci)
795 {
796 xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
797 xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
798 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
799 xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
800 xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
801 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
802 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
803 xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
804 xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
805 }
806
807 static void xhci_restore_registers(struct xhci_hcd *xhci)
808 {
809 xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
810 xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
811 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
812 xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
813 xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
814 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
815 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
816 xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
817 xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
818 }
819
820 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
821 {
822 u64 val_64;
823
824 /* step 2: initialize command ring buffer */
825 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
826 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
827 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
828 xhci->cmd_ring->dequeue) &
829 (u64) ~CMD_RING_RSVD_BITS) |
830 xhci->cmd_ring->cycle_state;
831 xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
832 (long unsigned long) val_64);
833 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
834 }
835
836 /*
837 * The whole command ring must be cleared to zero when we suspend the host.
838 *
839 * The host doesn't save the command ring pointer in the suspend well, so we
840 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
841 * aligned, because of the reserved bits in the command ring dequeue pointer
842 * register. Therefore, we can't just set the dequeue pointer back in the
843 * middle of the ring (TRBs are 16-byte aligned).
844 */
845 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
846 {
847 struct xhci_ring *ring;
848 struct xhci_segment *seg;
849
850 ring = xhci->cmd_ring;
851 seg = ring->deq_seg;
852 do {
853 memset(seg->trbs, 0,
854 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
855 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
856 cpu_to_le32(~TRB_CYCLE);
857 seg = seg->next;
858 } while (seg != ring->deq_seg);
859
860 /* Reset the software enqueue and dequeue pointers */
861 ring->deq_seg = ring->first_seg;
862 ring->dequeue = ring->first_seg->trbs;
863 ring->enq_seg = ring->deq_seg;
864 ring->enqueue = ring->dequeue;
865
866 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
867 /*
868 * Ring is now zeroed, so the HW should look for change of ownership
869 * when the cycle bit is set to 1.
870 */
871 ring->cycle_state = 1;
872
873 /*
874 * Reset the hardware dequeue pointer.
875 * Yes, this will need to be re-written after resume, but we're paranoid
876 * and want to make sure the hardware doesn't access bogus memory
877 * because, say, the BIOS or an SMI started the host without changing
878 * the command ring pointers.
879 */
880 xhci_set_cmd_ring_deq(xhci);
881 }
882
883 /*
884 * Stop HC (not bus-specific)
885 *
886 * This is called when the machine transition into S3/S4 mode.
887 *
888 */
889 int xhci_suspend(struct xhci_hcd *xhci)
890 {
891 int rc = 0;
892 struct usb_hcd *hcd = xhci_to_hcd(xhci);
893 u32 command;
894
895 if (hcd->state != HC_STATE_SUSPENDED ||
896 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
897 return -EINVAL;
898
899 /* Don't poll the roothubs on bus suspend. */
900 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
901 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
902 del_timer_sync(&hcd->rh_timer);
903
904 spin_lock_irq(&xhci->lock);
905 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
906 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
907 /* step 1: stop endpoint */
908 /* skipped assuming that port suspend has done */
909
910 /* step 2: clear Run/Stop bit */
911 command = xhci_readl(xhci, &xhci->op_regs->command);
912 command &= ~CMD_RUN;
913 xhci_writel(xhci, command, &xhci->op_regs->command);
914 if (xhci_handshake(xhci, &xhci->op_regs->status,
915 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC)) {
916 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
917 spin_unlock_irq(&xhci->lock);
918 return -ETIMEDOUT;
919 }
920 xhci_clear_command_ring(xhci);
921
922 /* step 3: save registers */
923 xhci_save_registers(xhci);
924
925 /* step 4: set CSS flag */
926 command = xhci_readl(xhci, &xhci->op_regs->command);
927 command |= CMD_CSS;
928 xhci_writel(xhci, command, &xhci->op_regs->command);
929 if (xhci_handshake(xhci, &xhci->op_regs->status,
930 STS_SAVE, 0, 10 * 1000)) {
931 xhci_warn(xhci, "WARN: xHC save state timeout\n");
932 spin_unlock_irq(&xhci->lock);
933 return -ETIMEDOUT;
934 }
935 spin_unlock_irq(&xhci->lock);
936
937 /*
938 * Deleting Compliance Mode Recovery Timer because the xHCI Host
939 * is about to be suspended.
940 */
941 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
942 (!(xhci_all_ports_seen_u0(xhci)))) {
943 del_timer_sync(&xhci->comp_mode_recovery_timer);
944 xhci_dbg(xhci, "%s: compliance mode recovery timer deleted\n",
945 __func__);
946 }
947
948 /* step 5: remove core well power */
949 /* synchronize irq when using MSI-X */
950 xhci_msix_sync_irqs(xhci);
951
952 return rc;
953 }
954
955 /*
956 * start xHC (not bus-specific)
957 *
958 * This is called when the machine transition from S3/S4 mode.
959 *
960 */
961 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
962 {
963 u32 command, temp = 0;
964 struct usb_hcd *hcd = xhci_to_hcd(xhci);
965 struct usb_hcd *secondary_hcd;
966 int retval = 0;
967 bool comp_timer_running = false;
968
969 /* Wait a bit if either of the roothubs need to settle from the
970 * transition into bus suspend.
971 */
972 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
973 time_before(jiffies,
974 xhci->bus_state[1].next_statechange))
975 msleep(100);
976
977 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
978 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
979
980 spin_lock_irq(&xhci->lock);
981 if (xhci->quirks & XHCI_RESET_ON_RESUME)
982 hibernated = true;
983
984 if (!hibernated) {
985 /* step 1: restore register */
986 xhci_restore_registers(xhci);
987 /* step 2: initialize command ring buffer */
988 xhci_set_cmd_ring_deq(xhci);
989 /* step 3: restore state and start state*/
990 /* step 3: set CRS flag */
991 command = xhci_readl(xhci, &xhci->op_regs->command);
992 command |= CMD_CRS;
993 xhci_writel(xhci, command, &xhci->op_regs->command);
994 if (xhci_handshake(xhci, &xhci->op_regs->status,
995 STS_RESTORE, 0, 10 * 1000)) {
996 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
997 spin_unlock_irq(&xhci->lock);
998 return -ETIMEDOUT;
999 }
1000 temp = xhci_readl(xhci, &xhci->op_regs->status);
1001 }
1002
1003 /* If restore operation fails, re-initialize the HC during resume */
1004 if ((temp & STS_SRE) || hibernated) {
1005
1006 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1007 !(xhci_all_ports_seen_u0(xhci))) {
1008 del_timer_sync(&xhci->comp_mode_recovery_timer);
1009 xhci_dbg(xhci, "Compliance Mode Recovery Timer deleted!\n");
1010 }
1011
1012 /* Let the USB core know _both_ roothubs lost power. */
1013 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1014 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1015
1016 xhci_dbg(xhci, "Stop HCD\n");
1017 xhci_halt(xhci);
1018 xhci_reset(xhci);
1019 spin_unlock_irq(&xhci->lock);
1020 xhci_cleanup_msix(xhci);
1021
1022 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
1023 /* Tell the event ring poll function not to reschedule */
1024 xhci->zombie = 1;
1025 del_timer_sync(&xhci->event_ring_timer);
1026 #endif
1027
1028 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1029 temp = xhci_readl(xhci, &xhci->op_regs->status);
1030 xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
1031 temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
1032 xhci_writel(xhci, ER_IRQ_DISABLE(temp),
1033 &xhci->ir_set->irq_pending);
1034 xhci_print_ir_set(xhci, 0);
1035
1036 xhci_dbg(xhci, "cleaning up memory\n");
1037 xhci_mem_cleanup(xhci);
1038 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1039 xhci_readl(xhci, &xhci->op_regs->status));
1040
1041 /* USB core calls the PCI reinit and start functions twice:
1042 * first with the primary HCD, and then with the secondary HCD.
1043 * If we don't do the same, the host will never be started.
1044 */
1045 if (!usb_hcd_is_primary_hcd(hcd))
1046 secondary_hcd = hcd;
1047 else
1048 secondary_hcd = xhci->shared_hcd;
1049
1050 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1051 retval = xhci_init(hcd->primary_hcd);
1052 if (retval)
1053 return retval;
1054 comp_timer_running = true;
1055
1056 xhci_dbg(xhci, "Start the primary HCD\n");
1057 retval = xhci_run(hcd->primary_hcd);
1058 if (!retval) {
1059 xhci_dbg(xhci, "Start the secondary HCD\n");
1060 retval = xhci_run(secondary_hcd);
1061 }
1062 hcd->state = HC_STATE_SUSPENDED;
1063 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1064 goto done;
1065 }
1066
1067 /* step 4: set Run/Stop bit */
1068 command = xhci_readl(xhci, &xhci->op_regs->command);
1069 command |= CMD_RUN;
1070 xhci_writel(xhci, command, &xhci->op_regs->command);
1071 xhci_handshake(xhci, &xhci->op_regs->status, STS_HALT,
1072 0, 250 * 1000);
1073
1074 /* step 5: walk topology and initialize portsc,
1075 * portpmsc and portli
1076 */
1077 /* this is done in bus_resume */
1078
1079 /* step 6: restart each of the previously
1080 * Running endpoints by ringing their doorbells
1081 */
1082
1083 spin_unlock_irq(&xhci->lock);
1084
1085 done:
1086 if (retval == 0) {
1087 usb_hcd_resume_root_hub(hcd);
1088 usb_hcd_resume_root_hub(xhci->shared_hcd);
1089 }
1090
1091 /*
1092 * If system is subject to the Quirk, Compliance Mode Timer needs to
1093 * be re-initialized Always after a system resume. Ports are subject
1094 * to suffer the Compliance Mode issue again. It doesn't matter if
1095 * ports have entered previously to U0 before system's suspension.
1096 */
1097 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1098 compliance_mode_recovery_timer_init(xhci);
1099
1100 /* Re-enable port polling. */
1101 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1102 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1103 usb_hcd_poll_rh_status(hcd);
1104
1105 return retval;
1106 }
1107 #endif /* CONFIG_PM */
1108
1109 /*-------------------------------------------------------------------------*/
1110
1111 /**
1112 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1113 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1114 * value to right shift 1 for the bitmask.
1115 *
1116 * Index = (epnum * 2) + direction - 1,
1117 * where direction = 0 for OUT, 1 for IN.
1118 * For control endpoints, the IN index is used (OUT index is unused), so
1119 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1120 */
1121 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1122 {
1123 unsigned int index;
1124 if (usb_endpoint_xfer_control(desc))
1125 index = (unsigned int) (usb_endpoint_num(desc)*2);
1126 else
1127 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1128 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1129 return index;
1130 }
1131
1132 /* Find the flag for this endpoint (for use in the control context). Use the
1133 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1134 * bit 1, etc.
1135 */
1136 unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1137 {
1138 return 1 << (xhci_get_endpoint_index(desc) + 1);
1139 }
1140
1141 /* Find the flag for this endpoint (for use in the control context). Use the
1142 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1143 * bit 1, etc.
1144 */
1145 unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1146 {
1147 return 1 << (ep_index + 1);
1148 }
1149
1150 /* Compute the last valid endpoint context index. Basically, this is the
1151 * endpoint index plus one. For slot contexts with more than valid endpoint,
1152 * we find the most significant bit set in the added contexts flags.
1153 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1154 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1155 */
1156 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1157 {
1158 return fls(added_ctxs) - 1;
1159 }
1160
1161 /* Returns 1 if the arguments are OK;
1162 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1163 */
1164 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1165 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1166 const char *func) {
1167 struct xhci_hcd *xhci;
1168 struct xhci_virt_device *virt_dev;
1169
1170 if (!hcd || (check_ep && !ep) || !udev) {
1171 printk(KERN_DEBUG "xHCI %s called with invalid args\n",
1172 func);
1173 return -EINVAL;
1174 }
1175 if (!udev->parent) {
1176 printk(KERN_DEBUG "xHCI %s called for root hub\n",
1177 func);
1178 return 0;
1179 }
1180
1181 xhci = hcd_to_xhci(hcd);
1182 if (check_virt_dev) {
1183 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1184 printk(KERN_DEBUG "xHCI %s called with unaddressed "
1185 "device\n", func);
1186 return -EINVAL;
1187 }
1188
1189 virt_dev = xhci->devs[udev->slot_id];
1190 if (virt_dev->udev != udev) {
1191 printk(KERN_DEBUG "xHCI %s called with udev and "
1192 "virt_dev does not match\n", func);
1193 return -EINVAL;
1194 }
1195 }
1196
1197 if (xhci->xhc_state & XHCI_STATE_HALTED)
1198 return -ENODEV;
1199
1200 return 1;
1201 }
1202
1203 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1204 struct usb_device *udev, struct xhci_command *command,
1205 bool ctx_change, bool must_succeed);
1206
1207 /*
1208 * Full speed devices may have a max packet size greater than 8 bytes, but the
1209 * USB core doesn't know that until it reads the first 8 bytes of the
1210 * descriptor. If the usb_device's max packet size changes after that point,
1211 * we need to issue an evaluate context command and wait on it.
1212 */
1213 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1214 unsigned int ep_index, struct urb *urb)
1215 {
1216 struct xhci_container_ctx *in_ctx;
1217 struct xhci_container_ctx *out_ctx;
1218 struct xhci_input_control_ctx *ctrl_ctx;
1219 struct xhci_ep_ctx *ep_ctx;
1220 int max_packet_size;
1221 int hw_max_packet_size;
1222 int ret = 0;
1223
1224 out_ctx = xhci->devs[slot_id]->out_ctx;
1225 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1226 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1227 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1228 if (hw_max_packet_size != max_packet_size) {
1229 xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
1230 xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
1231 max_packet_size);
1232 xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
1233 hw_max_packet_size);
1234 xhci_dbg(xhci, "Issuing evaluate context command.\n");
1235
1236 /* Set up the modified control endpoint 0 */
1237 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1238 xhci->devs[slot_id]->out_ctx, ep_index);
1239 in_ctx = xhci->devs[slot_id]->in_ctx;
1240 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1241 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1242 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1243
1244 /* Set up the input context flags for the command */
1245 /* FIXME: This won't work if a non-default control endpoint
1246 * changes max packet sizes.
1247 */
1248 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1249 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1250 ctrl_ctx->drop_flags = 0;
1251
1252 xhci_dbg(xhci, "Slot %d input context\n", slot_id);
1253 xhci_dbg_ctx(xhci, in_ctx, ep_index);
1254 xhci_dbg(xhci, "Slot %d output context\n", slot_id);
1255 xhci_dbg_ctx(xhci, out_ctx, ep_index);
1256
1257 ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
1258 true, false);
1259
1260 /* Clean up the input context for later use by bandwidth
1261 * functions.
1262 */
1263 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1264 }
1265 return ret;
1266 }
1267
1268 /*
1269 * non-error returns are a promise to giveback() the urb later
1270 * we drop ownership so next owner (or urb unlink) can get it
1271 */
1272 int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1273 {
1274 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1275 struct xhci_td *buffer;
1276 unsigned long flags;
1277 int ret = 0;
1278 unsigned int slot_id, ep_index;
1279 struct urb_priv *urb_priv;
1280 int size, i;
1281
1282 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1283 true, true, __func__) <= 0)
1284 return -EINVAL;
1285
1286 slot_id = urb->dev->slot_id;
1287 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1288
1289 if (!HCD_HW_ACCESSIBLE(hcd)) {
1290 if (!in_interrupt())
1291 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1292 ret = -ESHUTDOWN;
1293 goto exit;
1294 }
1295
1296 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1297 size = urb->number_of_packets;
1298 else
1299 size = 1;
1300
1301 urb_priv = kzalloc(sizeof(struct urb_priv) +
1302 size * sizeof(struct xhci_td *), mem_flags);
1303 if (!urb_priv)
1304 return -ENOMEM;
1305
1306 buffer = kzalloc(size * sizeof(struct xhci_td), mem_flags);
1307 if (!buffer) {
1308 kfree(urb_priv);
1309 return -ENOMEM;
1310 }
1311
1312 for (i = 0; i < size; i++) {
1313 urb_priv->td[i] = buffer;
1314 buffer++;
1315 }
1316
1317 urb_priv->length = size;
1318 urb_priv->td_cnt = 0;
1319 urb->hcpriv = urb_priv;
1320
1321 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1322 /* Check to see if the max packet size for the default control
1323 * endpoint changed during FS device enumeration
1324 */
1325 if (urb->dev->speed == USB_SPEED_FULL) {
1326 ret = xhci_check_maxpacket(xhci, slot_id,
1327 ep_index, urb);
1328 if (ret < 0) {
1329 xhci_urb_free_priv(xhci, urb_priv);
1330 urb->hcpriv = NULL;
1331 return ret;
1332 }
1333 }
1334
1335 /* We have a spinlock and interrupts disabled, so we must pass
1336 * atomic context to this function, which may allocate memory.
1337 */
1338 spin_lock_irqsave(&xhci->lock, flags);
1339 if (xhci->xhc_state & XHCI_STATE_DYING)
1340 goto dying;
1341 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1342 slot_id, ep_index);
1343 if (ret)
1344 goto free_priv;
1345 spin_unlock_irqrestore(&xhci->lock, flags);
1346 } else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
1347 spin_lock_irqsave(&xhci->lock, flags);
1348 if (xhci->xhc_state & XHCI_STATE_DYING)
1349 goto dying;
1350 if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1351 EP_GETTING_STREAMS) {
1352 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1353 "is transitioning to using streams.\n");
1354 ret = -EINVAL;
1355 } else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
1356 EP_GETTING_NO_STREAMS) {
1357 xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
1358 "is transitioning to "
1359 "not having streams.\n");
1360 ret = -EINVAL;
1361 } else {
1362 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1363 slot_id, ep_index);
1364 }
1365 if (ret)
1366 goto free_priv;
1367 spin_unlock_irqrestore(&xhci->lock, flags);
1368 } else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
1369 spin_lock_irqsave(&xhci->lock, flags);
1370 if (xhci->xhc_state & XHCI_STATE_DYING)
1371 goto dying;
1372 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1373 slot_id, ep_index);
1374 if (ret)
1375 goto free_priv;
1376 spin_unlock_irqrestore(&xhci->lock, flags);
1377 } else {
1378 spin_lock_irqsave(&xhci->lock, flags);
1379 if (xhci->xhc_state & XHCI_STATE_DYING)
1380 goto dying;
1381 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1382 slot_id, ep_index);
1383 if (ret)
1384 goto free_priv;
1385 spin_unlock_irqrestore(&xhci->lock, flags);
1386 }
1387 exit:
1388 return ret;
1389 dying:
1390 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
1391 "non-responsive xHCI host.\n",
1392 urb->ep->desc.bEndpointAddress, urb);
1393 ret = -ESHUTDOWN;
1394 free_priv:
1395 xhci_urb_free_priv(xhci, urb_priv);
1396 urb->hcpriv = NULL;
1397 spin_unlock_irqrestore(&xhci->lock, flags);
1398 return ret;
1399 }
1400
1401 /* Get the right ring for the given URB.
1402 * If the endpoint supports streams, boundary check the URB's stream ID.
1403 * If the endpoint doesn't support streams, return the singular endpoint ring.
1404 */
1405 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1406 struct urb *urb)
1407 {
1408 unsigned int slot_id;
1409 unsigned int ep_index;
1410 unsigned int stream_id;
1411 struct xhci_virt_ep *ep;
1412
1413 slot_id = urb->dev->slot_id;
1414 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1415 stream_id = urb->stream_id;
1416 ep = &xhci->devs[slot_id]->eps[ep_index];
1417 /* Common case: no streams */
1418 if (!(ep->ep_state & EP_HAS_STREAMS))
1419 return ep->ring;
1420
1421 if (stream_id == 0) {
1422 xhci_warn(xhci,
1423 "WARN: Slot ID %u, ep index %u has streams, "
1424 "but URB has no stream ID.\n",
1425 slot_id, ep_index);
1426 return NULL;
1427 }
1428
1429 if (stream_id < ep->stream_info->num_streams)
1430 return ep->stream_info->stream_rings[stream_id];
1431
1432 xhci_warn(xhci,
1433 "WARN: Slot ID %u, ep index %u has "
1434 "stream IDs 1 to %u allocated, "
1435 "but stream ID %u is requested.\n",
1436 slot_id, ep_index,
1437 ep->stream_info->num_streams - 1,
1438 stream_id);
1439 return NULL;
1440 }
1441
1442 /*
1443 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1444 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1445 * should pick up where it left off in the TD, unless a Set Transfer Ring
1446 * Dequeue Pointer is issued.
1447 *
1448 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1449 * the ring. Since the ring is a contiguous structure, they can't be physically
1450 * removed. Instead, there are two options:
1451 *
1452 * 1) If the HC is in the middle of processing the URB to be canceled, we
1453 * simply move the ring's dequeue pointer past those TRBs using the Set
1454 * Transfer Ring Dequeue Pointer command. This will be the common case,
1455 * when drivers timeout on the last submitted URB and attempt to cancel.
1456 *
1457 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1458 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1459 * HC will need to invalidate the any TRBs it has cached after the stop
1460 * endpoint command, as noted in the xHCI 0.95 errata.
1461 *
1462 * 3) The TD may have completed by the time the Stop Endpoint Command
1463 * completes, so software needs to handle that case too.
1464 *
1465 * This function should protect against the TD enqueueing code ringing the
1466 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1467 * It also needs to account for multiple cancellations on happening at the same
1468 * time for the same endpoint.
1469 *
1470 * Note that this function can be called in any context, or so says
1471 * usb_hcd_unlink_urb()
1472 */
1473 int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1474 {
1475 unsigned long flags;
1476 int ret, i;
1477 u32 temp;
1478 struct xhci_hcd *xhci;
1479 struct urb_priv *urb_priv;
1480 struct xhci_td *td;
1481 unsigned int ep_index;
1482 struct xhci_ring *ep_ring;
1483 struct xhci_virt_ep *ep;
1484
1485 xhci = hcd_to_xhci(hcd);
1486 spin_lock_irqsave(&xhci->lock, flags);
1487 /* Make sure the URB hasn't completed or been unlinked already */
1488 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1489 if (ret || !urb->hcpriv)
1490 goto done;
1491 temp = xhci_readl(xhci, &xhci->op_regs->status);
1492 if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_HALTED)) {
1493 xhci_dbg(xhci, "HW died, freeing TD.\n");
1494 urb_priv = urb->hcpriv;
1495 for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
1496 td = urb_priv->td[i];
1497 if (!list_empty(&td->td_list))
1498 list_del_init(&td->td_list);
1499 if (!list_empty(&td->cancelled_td_list))
1500 list_del_init(&td->cancelled_td_list);
1501 }
1502
1503 usb_hcd_unlink_urb_from_ep(hcd, urb);
1504 spin_unlock_irqrestore(&xhci->lock, flags);
1505 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1506 xhci_urb_free_priv(xhci, urb_priv);
1507 return ret;
1508 }
1509 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
1510 (xhci->xhc_state & XHCI_STATE_HALTED)) {
1511 xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
1512 "non-responsive xHCI host.\n",
1513 urb->ep->desc.bEndpointAddress, urb);
1514 /* Let the stop endpoint command watchdog timer (which set this
1515 * state) finish cleaning up the endpoint TD lists. We must
1516 * have caught it in the middle of dropping a lock and giving
1517 * back an URB.
1518 */
1519 goto done;
1520 }
1521
1522 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1523 ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
1524 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1525 if (!ep_ring) {
1526 ret = -EINVAL;
1527 goto done;
1528 }
1529
1530 urb_priv = urb->hcpriv;
1531 i = urb_priv->td_cnt;
1532 if (i < urb_priv->length)
1533 xhci_dbg(xhci, "Cancel URB %p, dev %s, ep 0x%x, "
1534 "starting at offset 0x%llx\n",
1535 urb, urb->dev->devpath,
1536 urb->ep->desc.bEndpointAddress,
1537 (unsigned long long) xhci_trb_virt_to_dma(
1538 urb_priv->td[i]->start_seg,
1539 urb_priv->td[i]->first_trb));
1540
1541 for (; i < urb_priv->length; i++) {
1542 td = urb_priv->td[i];
1543 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1544 }
1545
1546 /* Queue a stop endpoint command, but only if this is
1547 * the first cancellation to be handled.
1548 */
1549 if (!(ep->ep_state & EP_HALT_PENDING)) {
1550 ep->ep_state |= EP_HALT_PENDING;
1551 ep->stop_cmds_pending++;
1552 ep->stop_cmd_timer.expires = jiffies +
1553 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1554 add_timer(&ep->stop_cmd_timer);
1555 xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
1556 xhci_ring_cmd_db(xhci);
1557 }
1558 done:
1559 spin_unlock_irqrestore(&xhci->lock, flags);
1560 return ret;
1561 }
1562
1563 /* Drop an endpoint from a new bandwidth configuration for this device.
1564 * Only one call to this function is allowed per endpoint before
1565 * check_bandwidth() or reset_bandwidth() must be called.
1566 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1567 * add the endpoint to the schedule with possibly new parameters denoted by a
1568 * different endpoint descriptor in usb_host_endpoint.
1569 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1570 * not allowed.
1571 *
1572 * The USB core will not allow URBs to be queued to an endpoint that is being
1573 * disabled, so there's no need for mutual exclusion to protect
1574 * the xhci->devs[slot_id] structure.
1575 */
1576 int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1577 struct usb_host_endpoint *ep)
1578 {
1579 struct xhci_hcd *xhci;
1580 struct xhci_container_ctx *in_ctx, *out_ctx;
1581 struct xhci_input_control_ctx *ctrl_ctx;
1582 struct xhci_slot_ctx *slot_ctx;
1583 unsigned int last_ctx;
1584 unsigned int ep_index;
1585 struct xhci_ep_ctx *ep_ctx;
1586 u32 drop_flag;
1587 u32 new_add_flags, new_drop_flags, new_slot_info;
1588 int ret;
1589
1590 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1591 if (ret <= 0)
1592 return ret;
1593 xhci = hcd_to_xhci(hcd);
1594 if (xhci->xhc_state & XHCI_STATE_DYING)
1595 return -ENODEV;
1596
1597 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1598 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1599 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1600 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1601 __func__, drop_flag);
1602 return 0;
1603 }
1604
1605 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1606 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1607 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1608 ep_index = xhci_get_endpoint_index(&ep->desc);
1609 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1610 /* If the HC already knows the endpoint is disabled,
1611 * or the HCD has noted it is disabled, ignore this request
1612 */
1613 if (((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1614 cpu_to_le32(EP_STATE_DISABLED)) ||
1615 le32_to_cpu(ctrl_ctx->drop_flags) &
1616 xhci_get_endpoint_flag(&ep->desc)) {
1617 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1618 __func__, ep);
1619 return 0;
1620 }
1621
1622 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1623 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1624
1625 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1626 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1627
1628 last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
1629 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1630 /* Update the last valid endpoint context, if we deleted the last one */
1631 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
1632 LAST_CTX(last_ctx)) {
1633 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1634 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1635 }
1636 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1637
1638 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1639
1640 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1641 (unsigned int) ep->desc.bEndpointAddress,
1642 udev->slot_id,
1643 (unsigned int) new_drop_flags,
1644 (unsigned int) new_add_flags,
1645 (unsigned int) new_slot_info);
1646 return 0;
1647 }
1648
1649 /* Add an endpoint to a new possible bandwidth configuration for this device.
1650 * Only one call to this function is allowed per endpoint before
1651 * check_bandwidth() or reset_bandwidth() must be called.
1652 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1653 * add the endpoint to the schedule with possibly new parameters denoted by a
1654 * different endpoint descriptor in usb_host_endpoint.
1655 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1656 * not allowed.
1657 *
1658 * The USB core will not allow URBs to be queued to an endpoint until the
1659 * configuration or alt setting is installed in the device, so there's no need
1660 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1661 */
1662 int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1663 struct usb_host_endpoint *ep)
1664 {
1665 struct xhci_hcd *xhci;
1666 struct xhci_container_ctx *in_ctx, *out_ctx;
1667 unsigned int ep_index;
1668 struct xhci_slot_ctx *slot_ctx;
1669 struct xhci_input_control_ctx *ctrl_ctx;
1670 u32 added_ctxs;
1671 unsigned int last_ctx;
1672 u32 new_add_flags, new_drop_flags, new_slot_info;
1673 struct xhci_virt_device *virt_dev;
1674 int ret = 0;
1675
1676 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1677 if (ret <= 0) {
1678 /* So we won't queue a reset ep command for a root hub */
1679 ep->hcpriv = NULL;
1680 return ret;
1681 }
1682 xhci = hcd_to_xhci(hcd);
1683 if (xhci->xhc_state & XHCI_STATE_DYING)
1684 return -ENODEV;
1685
1686 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1687 last_ctx = xhci_last_valid_endpoint(added_ctxs);
1688 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1689 /* FIXME when we have to issue an evaluate endpoint command to
1690 * deal with ep0 max packet size changing once we get the
1691 * descriptors
1692 */
1693 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1694 __func__, added_ctxs);
1695 return 0;
1696 }
1697
1698 virt_dev = xhci->devs[udev->slot_id];
1699 in_ctx = virt_dev->in_ctx;
1700 out_ctx = virt_dev->out_ctx;
1701 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1702 ep_index = xhci_get_endpoint_index(&ep->desc);
1703
1704 /* If this endpoint is already in use, and the upper layers are trying
1705 * to add it again without dropping it, reject the addition.
1706 */
1707 if (virt_dev->eps[ep_index].ring &&
1708 !(le32_to_cpu(ctrl_ctx->drop_flags) &
1709 xhci_get_endpoint_flag(&ep->desc))) {
1710 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1711 "without dropping it.\n",
1712 (unsigned int) ep->desc.bEndpointAddress);
1713 return -EINVAL;
1714 }
1715
1716 /* If the HCD has already noted the endpoint is enabled,
1717 * ignore this request.
1718 */
1719 if (le32_to_cpu(ctrl_ctx->add_flags) &
1720 xhci_get_endpoint_flag(&ep->desc)) {
1721 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1722 __func__, ep);
1723 return 0;
1724 }
1725
1726 /*
1727 * Configuration and alternate setting changes must be done in
1728 * process context, not interrupt context (or so documenation
1729 * for usb_set_interface() and usb_set_configuration() claim).
1730 */
1731 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1732 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1733 __func__, ep->desc.bEndpointAddress);
1734 return -ENOMEM;
1735 }
1736
1737 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1738 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1739
1740 /* If xhci_endpoint_disable() was called for this endpoint, but the
1741 * xHC hasn't been notified yet through the check_bandwidth() call,
1742 * this re-adds a new state for the endpoint from the new endpoint
1743 * descriptors. We must drop and re-add this endpoint, so we leave the
1744 * drop flags alone.
1745 */
1746 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1747
1748 slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1749 /* Update the last valid endpoint context, if we just added one past */
1750 if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
1751 LAST_CTX(last_ctx)) {
1752 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1753 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
1754 }
1755 new_slot_info = le32_to_cpu(slot_ctx->dev_info);
1756
1757 /* Store the usb_device pointer for later use */
1758 ep->hcpriv = udev;
1759
1760 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
1761 (unsigned int) ep->desc.bEndpointAddress,
1762 udev->slot_id,
1763 (unsigned int) new_drop_flags,
1764 (unsigned int) new_add_flags,
1765 (unsigned int) new_slot_info);
1766 return 0;
1767 }
1768
1769 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1770 {
1771 struct xhci_input_control_ctx *ctrl_ctx;
1772 struct xhci_ep_ctx *ep_ctx;
1773 struct xhci_slot_ctx *slot_ctx;
1774 int i;
1775
1776 /* When a device's add flag and drop flag are zero, any subsequent
1777 * configure endpoint command will leave that endpoint's state
1778 * untouched. Make sure we don't leave any old state in the input
1779 * endpoint contexts.
1780 */
1781 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
1782 ctrl_ctx->drop_flags = 0;
1783 ctrl_ctx->add_flags = 0;
1784 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1785 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1786 /* Endpoint 0 is always valid */
1787 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1788 for (i = 1; i < 31; ++i) {
1789 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1790 ep_ctx->ep_info = 0;
1791 ep_ctx->ep_info2 = 0;
1792 ep_ctx->deq = 0;
1793 ep_ctx->tx_info = 0;
1794 }
1795 }
1796
1797 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1798 struct usb_device *udev, u32 *cmd_status)
1799 {
1800 int ret;
1801
1802 switch (*cmd_status) {
1803 case COMP_ENOMEM:
1804 dev_warn(&udev->dev, "Not enough host controller resources "
1805 "for new device state.\n");
1806 ret = -ENOMEM;
1807 /* FIXME: can we allocate more resources for the HC? */
1808 break;
1809 case COMP_BW_ERR:
1810 case COMP_2ND_BW_ERR:
1811 dev_warn(&udev->dev, "Not enough bandwidth "
1812 "for new device state.\n");
1813 ret = -ENOSPC;
1814 /* FIXME: can we go back to the old state? */
1815 break;
1816 case COMP_TRB_ERR:
1817 /* the HCD set up something wrong */
1818 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1819 "add flag = 1, "
1820 "and endpoint is not disabled.\n");
1821 ret = -EINVAL;
1822 break;
1823 case COMP_DEV_ERR:
1824 dev_warn(&udev->dev, "ERROR: Incompatible device for endpoint "
1825 "configure command.\n");
1826 ret = -ENODEV;
1827 break;
1828 case COMP_SUCCESS:
1829 dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
1830 ret = 0;
1831 break;
1832 default:
1833 xhci_err(xhci, "ERROR: unexpected command completion "
1834 "code 0x%x.\n", *cmd_status);
1835 ret = -EINVAL;
1836 break;
1837 }
1838 return ret;
1839 }
1840
1841 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1842 struct usb_device *udev, u32 *cmd_status)
1843 {
1844 int ret;
1845 struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
1846
1847 switch (*cmd_status) {
1848 case COMP_EINVAL:
1849 dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
1850 "context command.\n");
1851 ret = -EINVAL;
1852 break;
1853 case COMP_EBADSLT:
1854 dev_warn(&udev->dev, "WARN: slot not enabled for"
1855 "evaluate context command.\n");
1856 ret = -EINVAL;
1857 break;
1858 case COMP_CTX_STATE:
1859 dev_warn(&udev->dev, "WARN: invalid context state for "
1860 "evaluate context command.\n");
1861 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
1862 ret = -EINVAL;
1863 break;
1864 case COMP_DEV_ERR:
1865 dev_warn(&udev->dev, "ERROR: Incompatible device for evaluate "
1866 "context command.\n");
1867 ret = -ENODEV;
1868 break;
1869 case COMP_MEL_ERR:
1870 /* Max Exit Latency too large error */
1871 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1872 ret = -EINVAL;
1873 break;
1874 case COMP_SUCCESS:
1875 dev_dbg(&udev->dev, "Successful evaluate context command\n");
1876 ret = 0;
1877 break;
1878 default:
1879 xhci_err(xhci, "ERROR: unexpected command completion "
1880 "code 0x%x.\n", *cmd_status);
1881 ret = -EINVAL;
1882 break;
1883 }
1884 return ret;
1885 }
1886
1887 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
1888 struct xhci_container_ctx *in_ctx)
1889 {
1890 struct xhci_input_control_ctx *ctrl_ctx;
1891 u32 valid_add_flags;
1892 u32 valid_drop_flags;
1893
1894 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1895 /* Ignore the slot flag (bit 0), and the default control endpoint flag
1896 * (bit 1). The default control endpoint is added during the Address
1897 * Device command and is never removed until the slot is disabled.
1898 */
1899 valid_add_flags = ctrl_ctx->add_flags >> 2;
1900 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1901
1902 /* Use hweight32 to count the number of ones in the add flags, or
1903 * number of endpoints added. Don't count endpoints that are changed
1904 * (both added and dropped).
1905 */
1906 return hweight32(valid_add_flags) -
1907 hweight32(valid_add_flags & valid_drop_flags);
1908 }
1909
1910 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
1911 struct xhci_container_ctx *in_ctx)
1912 {
1913 struct xhci_input_control_ctx *ctrl_ctx;
1914 u32 valid_add_flags;
1915 u32 valid_drop_flags;
1916
1917 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
1918 valid_add_flags = ctrl_ctx->add_flags >> 2;
1919 valid_drop_flags = ctrl_ctx->drop_flags >> 2;
1920
1921 return hweight32(valid_drop_flags) -
1922 hweight32(valid_add_flags & valid_drop_flags);
1923 }
1924
1925 /*
1926 * We need to reserve the new number of endpoints before the configure endpoint
1927 * command completes. We can't subtract the dropped endpoints from the number
1928 * of active endpoints until the command completes because we can oversubscribe
1929 * the host in this case:
1930 *
1931 * - the first configure endpoint command drops more endpoints than it adds
1932 * - a second configure endpoint command that adds more endpoints is queued
1933 * - the first configure endpoint command fails, so the config is unchanged
1934 * - the second command may succeed, even though there isn't enough resources
1935 *
1936 * Must be called with xhci->lock held.
1937 */
1938 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
1939 struct xhci_container_ctx *in_ctx)
1940 {
1941 u32 added_eps;
1942
1943 added_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1944 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
1945 xhci_dbg(xhci, "Not enough ep ctxs: "
1946 "%u active, need to add %u, limit is %u.\n",
1947 xhci->num_active_eps, added_eps,
1948 xhci->limit_active_eps);
1949 return -ENOMEM;
1950 }
1951 xhci->num_active_eps += added_eps;
1952 xhci_dbg(xhci, "Adding %u ep ctxs, %u now active.\n", added_eps,
1953 xhci->num_active_eps);
1954 return 0;
1955 }
1956
1957 /*
1958 * The configure endpoint was failed by the xHC for some other reason, so we
1959 * need to revert the resources that failed configuration would have used.
1960 *
1961 * Must be called with xhci->lock held.
1962 */
1963 static void xhci_free_host_resources(struct xhci_hcd *xhci,
1964 struct xhci_container_ctx *in_ctx)
1965 {
1966 u32 num_failed_eps;
1967
1968 num_failed_eps = xhci_count_num_new_endpoints(xhci, in_ctx);
1969 xhci->num_active_eps -= num_failed_eps;
1970 xhci_dbg(xhci, "Removing %u failed ep ctxs, %u now active.\n",
1971 num_failed_eps,
1972 xhci->num_active_eps);
1973 }
1974
1975 /*
1976 * Now that the command has completed, clean up the active endpoint count by
1977 * subtracting out the endpoints that were dropped (but not changed).
1978 *
1979 * Must be called with xhci->lock held.
1980 */
1981 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
1982 struct xhci_container_ctx *in_ctx)
1983 {
1984 u32 num_dropped_eps;
1985
1986 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, in_ctx);
1987 xhci->num_active_eps -= num_dropped_eps;
1988 if (num_dropped_eps)
1989 xhci_dbg(xhci, "Removing %u dropped ep ctxs, %u now active.\n",
1990 num_dropped_eps,
1991 xhci->num_active_eps);
1992 }
1993
1994 static unsigned int xhci_get_block_size(struct usb_device *udev)
1995 {
1996 switch (udev->speed) {
1997 case USB_SPEED_LOW:
1998 case USB_SPEED_FULL:
1999 return FS_BLOCK;
2000 case USB_SPEED_HIGH:
2001 return HS_BLOCK;
2002 case USB_SPEED_SUPER:
2003 return SS_BLOCK;
2004 case USB_SPEED_UNKNOWN:
2005 case USB_SPEED_WIRELESS:
2006 default:
2007 /* Should never happen */
2008 return 1;
2009 }
2010 }
2011
2012 static unsigned int
2013 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2014 {
2015 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2016 return LS_OVERHEAD;
2017 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2018 return FS_OVERHEAD;
2019 return HS_OVERHEAD;
2020 }
2021
2022 /* If we are changing a LS/FS device under a HS hub,
2023 * make sure (if we are activating a new TT) that the HS bus has enough
2024 * bandwidth for this new TT.
2025 */
2026 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2027 struct xhci_virt_device *virt_dev,
2028 int old_active_eps)
2029 {
2030 struct xhci_interval_bw_table *bw_table;
2031 struct xhci_tt_bw_info *tt_info;
2032
2033 /* Find the bandwidth table for the root port this TT is attached to. */
2034 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2035 tt_info = virt_dev->tt_info;
2036 /* If this TT already had active endpoints, the bandwidth for this TT
2037 * has already been added. Removing all periodic endpoints (and thus
2038 * making the TT enactive) will only decrease the bandwidth used.
2039 */
2040 if (old_active_eps)
2041 return 0;
2042 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2043 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2044 return -ENOMEM;
2045 return 0;
2046 }
2047 /* Not sure why we would have no new active endpoints...
2048 *
2049 * Maybe because of an Evaluate Context change for a hub update or a
2050 * control endpoint 0 max packet size change?
2051 * FIXME: skip the bandwidth calculation in that case.
2052 */
2053 return 0;
2054 }
2055
2056 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2057 struct xhci_virt_device *virt_dev)
2058 {
2059 unsigned int bw_reserved;
2060
2061 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2062 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2063 return -ENOMEM;
2064
2065 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2066 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2067 return -ENOMEM;
2068
2069 return 0;
2070 }
2071
2072 /*
2073 * This algorithm is a very conservative estimate of the worst-case scheduling
2074 * scenario for any one interval. The hardware dynamically schedules the
2075 * packets, so we can't tell which microframe could be the limiting factor in
2076 * the bandwidth scheduling. This only takes into account periodic endpoints.
2077 *
2078 * Obviously, we can't solve an NP complete problem to find the minimum worst
2079 * case scenario. Instead, we come up with an estimate that is no less than
2080 * the worst case bandwidth used for any one microframe, but may be an
2081 * over-estimate.
2082 *
2083 * We walk the requirements for each endpoint by interval, starting with the
2084 * smallest interval, and place packets in the schedule where there is only one
2085 * possible way to schedule packets for that interval. In order to simplify
2086 * this algorithm, we record the largest max packet size for each interval, and
2087 * assume all packets will be that size.
2088 *
2089 * For interval 0, we obviously must schedule all packets for each interval.
2090 * The bandwidth for interval 0 is just the amount of data to be transmitted
2091 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2092 * the number of packets).
2093 *
2094 * For interval 1, we have two possible microframes to schedule those packets
2095 * in. For this algorithm, if we can schedule the same number of packets for
2096 * each possible scheduling opportunity (each microframe), we will do so. The
2097 * remaining number of packets will be saved to be transmitted in the gaps in
2098 * the next interval's scheduling sequence.
2099 *
2100 * As we move those remaining packets to be scheduled with interval 2 packets,
2101 * we have to double the number of remaining packets to transmit. This is
2102 * because the intervals are actually powers of 2, and we would be transmitting
2103 * the previous interval's packets twice in this interval. We also have to be
2104 * sure that when we look at the largest max packet size for this interval, we
2105 * also look at the largest max packet size for the remaining packets and take
2106 * the greater of the two.
2107 *
2108 * The algorithm continues to evenly distribute packets in each scheduling
2109 * opportunity, and push the remaining packets out, until we get to the last
2110 * interval. Then those packets and their associated overhead are just added
2111 * to the bandwidth used.
2112 */
2113 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2114 struct xhci_virt_device *virt_dev,
2115 int old_active_eps)
2116 {
2117 unsigned int bw_reserved;
2118 unsigned int max_bandwidth;
2119 unsigned int bw_used;
2120 unsigned int block_size;
2121 struct xhci_interval_bw_table *bw_table;
2122 unsigned int packet_size = 0;
2123 unsigned int overhead = 0;
2124 unsigned int packets_transmitted = 0;
2125 unsigned int packets_remaining = 0;
2126 unsigned int i;
2127
2128 if (virt_dev->udev->speed == USB_SPEED_SUPER)
2129 return xhci_check_ss_bw(xhci, virt_dev);
2130
2131 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2132 max_bandwidth = HS_BW_LIMIT;
2133 /* Convert percent of bus BW reserved to blocks reserved */
2134 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2135 } else {
2136 max_bandwidth = FS_BW_LIMIT;
2137 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2138 }
2139
2140 bw_table = virt_dev->bw_table;
2141 /* We need to translate the max packet size and max ESIT payloads into
2142 * the units the hardware uses.
2143 */
2144 block_size = xhci_get_block_size(virt_dev->udev);
2145
2146 /* If we are manipulating a LS/FS device under a HS hub, double check
2147 * that the HS bus has enough bandwidth if we are activing a new TT.
2148 */
2149 if (virt_dev->tt_info) {
2150 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2151 virt_dev->real_port);
2152 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2153 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2154 "newly activated TT.\n");
2155 return -ENOMEM;
2156 }
2157 xhci_dbg(xhci, "Recalculating BW for TT slot %u port %u\n",
2158 virt_dev->tt_info->slot_id,
2159 virt_dev->tt_info->ttport);
2160 } else {
2161 xhci_dbg(xhci, "Recalculating BW for rootport %u\n",
2162 virt_dev->real_port);
2163 }
2164
2165 /* Add in how much bandwidth will be used for interval zero, or the
2166 * rounded max ESIT payload + number of packets * largest overhead.
2167 */
2168 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2169 bw_table->interval_bw[0].num_packets *
2170 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2171
2172 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2173 unsigned int bw_added;
2174 unsigned int largest_mps;
2175 unsigned int interval_overhead;
2176
2177 /*
2178 * How many packets could we transmit in this interval?
2179 * If packets didn't fit in the previous interval, we will need
2180 * to transmit that many packets twice within this interval.
2181 */
2182 packets_remaining = 2 * packets_remaining +
2183 bw_table->interval_bw[i].num_packets;
2184
2185 /* Find the largest max packet size of this or the previous
2186 * interval.
2187 */
2188 if (list_empty(&bw_table->interval_bw[i].endpoints))
2189 largest_mps = 0;
2190 else {
2191 struct xhci_virt_ep *virt_ep;
2192 struct list_head *ep_entry;
2193
2194 ep_entry = bw_table->interval_bw[i].endpoints.next;
2195 virt_ep = list_entry(ep_entry,
2196 struct xhci_virt_ep, bw_endpoint_list);
2197 /* Convert to blocks, rounding up */
2198 largest_mps = DIV_ROUND_UP(
2199 virt_ep->bw_info.max_packet_size,
2200 block_size);
2201 }
2202 if (largest_mps > packet_size)
2203 packet_size = largest_mps;
2204
2205 /* Use the larger overhead of this or the previous interval. */
2206 interval_overhead = xhci_get_largest_overhead(
2207 &bw_table->interval_bw[i]);
2208 if (interval_overhead > overhead)
2209 overhead = interval_overhead;
2210
2211 /* How many packets can we evenly distribute across
2212 * (1 << (i + 1)) possible scheduling opportunities?
2213 */
2214 packets_transmitted = packets_remaining >> (i + 1);
2215
2216 /* Add in the bandwidth used for those scheduled packets */
2217 bw_added = packets_transmitted * (overhead + packet_size);
2218
2219 /* How many packets do we have remaining to transmit? */
2220 packets_remaining = packets_remaining % (1 << (i + 1));
2221
2222 /* What largest max packet size should those packets have? */
2223 /* If we've transmitted all packets, don't carry over the
2224 * largest packet size.
2225 */
2226 if (packets_remaining == 0) {
2227 packet_size = 0;
2228 overhead = 0;
2229 } else if (packets_transmitted > 0) {
2230 /* Otherwise if we do have remaining packets, and we've
2231 * scheduled some packets in this interval, take the
2232 * largest max packet size from endpoints with this
2233 * interval.
2234 */
2235 packet_size = largest_mps;
2236 overhead = interval_overhead;
2237 }
2238 /* Otherwise carry over packet_size and overhead from the last
2239 * time we had a remainder.
2240 */
2241 bw_used += bw_added;
2242 if (bw_used > max_bandwidth) {
2243 xhci_warn(xhci, "Not enough bandwidth. "
2244 "Proposed: %u, Max: %u\n",
2245 bw_used, max_bandwidth);
2246 return -ENOMEM;
2247 }
2248 }
2249 /*
2250 * Ok, we know we have some packets left over after even-handedly
2251 * scheduling interval 15. We don't know which microframes they will
2252 * fit into, so we over-schedule and say they will be scheduled every
2253 * microframe.
2254 */
2255 if (packets_remaining > 0)
2256 bw_used += overhead + packet_size;
2257
2258 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2259 unsigned int port_index = virt_dev->real_port - 1;
2260
2261 /* OK, we're manipulating a HS device attached to a
2262 * root port bandwidth domain. Include the number of active TTs
2263 * in the bandwidth used.
2264 */
2265 bw_used += TT_HS_OVERHEAD *
2266 xhci->rh_bw[port_index].num_active_tts;
2267 }
2268
2269 xhci_dbg(xhci, "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2270 "Available: %u " "percent\n",
2271 bw_used, max_bandwidth, bw_reserved,
2272 (max_bandwidth - bw_used - bw_reserved) * 100 /
2273 max_bandwidth);
2274
2275 bw_used += bw_reserved;
2276 if (bw_used > max_bandwidth) {
2277 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2278 bw_used, max_bandwidth);
2279 return -ENOMEM;
2280 }
2281
2282 bw_table->bw_used = bw_used;
2283 return 0;
2284 }
2285
2286 static bool xhci_is_async_ep(unsigned int ep_type)
2287 {
2288 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2289 ep_type != ISOC_IN_EP &&
2290 ep_type != INT_IN_EP);
2291 }
2292
2293 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2294 {
2295 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2296 }
2297
2298 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2299 {
2300 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2301
2302 if (ep_bw->ep_interval == 0)
2303 return SS_OVERHEAD_BURST +
2304 (ep_bw->mult * ep_bw->num_packets *
2305 (SS_OVERHEAD + mps));
2306 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2307 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2308 1 << ep_bw->ep_interval);
2309
2310 }
2311
2312 void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2313 struct xhci_bw_info *ep_bw,
2314 struct xhci_interval_bw_table *bw_table,
2315 struct usb_device *udev,
2316 struct xhci_virt_ep *virt_ep,
2317 struct xhci_tt_bw_info *tt_info)
2318 {
2319 struct xhci_interval_bw *interval_bw;
2320 int normalized_interval;
2321
2322 if (xhci_is_async_ep(ep_bw->type))
2323 return;
2324
2325 if (udev->speed == USB_SPEED_SUPER) {
2326 if (xhci_is_sync_in_ep(ep_bw->type))
2327 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2328 xhci_get_ss_bw_consumed(ep_bw);
2329 else
2330 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2331 xhci_get_ss_bw_consumed(ep_bw);
2332 return;
2333 }
2334
2335 /* SuperSpeed endpoints never get added to intervals in the table, so
2336 * this check is only valid for HS/FS/LS devices.
2337 */
2338 if (list_empty(&virt_ep->bw_endpoint_list))
2339 return;
2340 /* For LS/FS devices, we need to translate the interval expressed in
2341 * microframes to frames.
2342 */
2343 if (udev->speed == USB_SPEED_HIGH)
2344 normalized_interval = ep_bw->ep_interval;
2345 else
2346 normalized_interval = ep_bw->ep_interval - 3;
2347
2348 if (normalized_interval == 0)
2349 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2350 interval_bw = &bw_table->interval_bw[normalized_interval];
2351 interval_bw->num_packets -= ep_bw->num_packets;
2352 switch (udev->speed) {
2353 case USB_SPEED_LOW:
2354 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2355 break;
2356 case USB_SPEED_FULL:
2357 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2358 break;
2359 case USB_SPEED_HIGH:
2360 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2361 break;
2362 case USB_SPEED_SUPER:
2363 case USB_SPEED_UNKNOWN:
2364 case USB_SPEED_WIRELESS:
2365 /* Should never happen because only LS/FS/HS endpoints will get
2366 * added to the endpoint list.
2367 */
2368 return;
2369 }
2370 if (tt_info)
2371 tt_info->active_eps -= 1;
2372 list_del_init(&virt_ep->bw_endpoint_list);
2373 }
2374
2375 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2376 struct xhci_bw_info *ep_bw,
2377 struct xhci_interval_bw_table *bw_table,
2378 struct usb_device *udev,
2379 struct xhci_virt_ep *virt_ep,
2380 struct xhci_tt_bw_info *tt_info)
2381 {
2382 struct xhci_interval_bw *interval_bw;
2383 struct xhci_virt_ep *smaller_ep;
2384 int normalized_interval;
2385
2386 if (xhci_is_async_ep(ep_bw->type))
2387 return;
2388
2389 if (udev->speed == USB_SPEED_SUPER) {
2390 if (xhci_is_sync_in_ep(ep_bw->type))
2391 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2392 xhci_get_ss_bw_consumed(ep_bw);
2393 else
2394 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2395 xhci_get_ss_bw_consumed(ep_bw);
2396 return;
2397 }
2398
2399 /* For LS/FS devices, we need to translate the interval expressed in
2400 * microframes to frames.
2401 */
2402 if (udev->speed == USB_SPEED_HIGH)
2403 normalized_interval = ep_bw->ep_interval;
2404 else
2405 normalized_interval = ep_bw->ep_interval - 3;
2406
2407 if (normalized_interval == 0)
2408 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2409 interval_bw = &bw_table->interval_bw[normalized_interval];
2410 interval_bw->num_packets += ep_bw->num_packets;
2411 switch (udev->speed) {
2412 case USB_SPEED_LOW:
2413 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2414 break;
2415 case USB_SPEED_FULL:
2416 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2417 break;
2418 case USB_SPEED_HIGH:
2419 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2420 break;
2421 case USB_SPEED_SUPER:
2422 case USB_SPEED_UNKNOWN:
2423 case USB_SPEED_WIRELESS:
2424 /* Should never happen because only LS/FS/HS endpoints will get
2425 * added to the endpoint list.
2426 */
2427 return;
2428 }
2429
2430 if (tt_info)
2431 tt_info->active_eps += 1;
2432 /* Insert the endpoint into the list, largest max packet size first. */
2433 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2434 bw_endpoint_list) {
2435 if (ep_bw->max_packet_size >=
2436 smaller_ep->bw_info.max_packet_size) {
2437 /* Add the new ep before the smaller endpoint */
2438 list_add_tail(&virt_ep->bw_endpoint_list,
2439 &smaller_ep->bw_endpoint_list);
2440 return;
2441 }
2442 }
2443 /* Add the new endpoint at the end of the list. */
2444 list_add_tail(&virt_ep->bw_endpoint_list,
2445 &interval_bw->endpoints);
2446 }
2447
2448 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2449 struct xhci_virt_device *virt_dev,
2450 int old_active_eps)
2451 {
2452 struct xhci_root_port_bw_info *rh_bw_info;
2453 if (!virt_dev->tt_info)
2454 return;
2455
2456 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2457 if (old_active_eps == 0 &&
2458 virt_dev->tt_info->active_eps != 0) {
2459 rh_bw_info->num_active_tts += 1;
2460 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2461 } else if (old_active_eps != 0 &&
2462 virt_dev->tt_info->active_eps == 0) {
2463 rh_bw_info->num_active_tts -= 1;
2464 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2465 }
2466 }
2467
2468 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2469 struct xhci_virt_device *virt_dev,
2470 struct xhci_container_ctx *in_ctx)
2471 {
2472 struct xhci_bw_info ep_bw_info[31];
2473 int i;
2474 struct xhci_input_control_ctx *ctrl_ctx;
2475 int old_active_eps = 0;
2476
2477 if (virt_dev->tt_info)
2478 old_active_eps = virt_dev->tt_info->active_eps;
2479
2480 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2481
2482 for (i = 0; i < 31; i++) {
2483 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2484 continue;
2485
2486 /* Make a copy of the BW info in case we need to revert this */
2487 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2488 sizeof(ep_bw_info[i]));
2489 /* Drop the endpoint from the interval table if the endpoint is
2490 * being dropped or changed.
2491 */
2492 if (EP_IS_DROPPED(ctrl_ctx, i))
2493 xhci_drop_ep_from_interval_table(xhci,
2494 &virt_dev->eps[i].bw_info,
2495 virt_dev->bw_table,
2496 virt_dev->udev,
2497 &virt_dev->eps[i],
2498 virt_dev->tt_info);
2499 }
2500 /* Overwrite the information stored in the endpoints' bw_info */
2501 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2502 for (i = 0; i < 31; i++) {
2503 /* Add any changed or added endpoints to the interval table */
2504 if (EP_IS_ADDED(ctrl_ctx, i))
2505 xhci_add_ep_to_interval_table(xhci,
2506 &virt_dev->eps[i].bw_info,
2507 virt_dev->bw_table,
2508 virt_dev->udev,
2509 &virt_dev->eps[i],
2510 virt_dev->tt_info);
2511 }
2512
2513 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2514 /* Ok, this fits in the bandwidth we have.
2515 * Update the number of active TTs.
2516 */
2517 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2518 return 0;
2519 }
2520
2521 /* We don't have enough bandwidth for this, revert the stored info. */
2522 for (i = 0; i < 31; i++) {
2523 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2524 continue;
2525
2526 /* Drop the new copies of any added or changed endpoints from
2527 * the interval table.
2528 */
2529 if (EP_IS_ADDED(ctrl_ctx, i)) {
2530 xhci_drop_ep_from_interval_table(xhci,
2531 &virt_dev->eps[i].bw_info,
2532 virt_dev->bw_table,
2533 virt_dev->udev,
2534 &virt_dev->eps[i],
2535 virt_dev->tt_info);
2536 }
2537 /* Revert the endpoint back to its old information */
2538 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2539 sizeof(ep_bw_info[i]));
2540 /* Add any changed or dropped endpoints back into the table */
2541 if (EP_IS_DROPPED(ctrl_ctx, i))
2542 xhci_add_ep_to_interval_table(xhci,
2543 &virt_dev->eps[i].bw_info,
2544 virt_dev->bw_table,
2545 virt_dev->udev,
2546 &virt_dev->eps[i],
2547 virt_dev->tt_info);
2548 }
2549 return -ENOMEM;
2550 }
2551
2552
2553 /* Issue a configure endpoint command or evaluate context command
2554 * and wait for it to finish.
2555 */
2556 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2557 struct usb_device *udev,
2558 struct xhci_command *command,
2559 bool ctx_change, bool must_succeed)
2560 {
2561 int ret;
2562 int timeleft;
2563 unsigned long flags;
2564 struct xhci_container_ctx *in_ctx;
2565 struct completion *cmd_completion;
2566 u32 *cmd_status;
2567 struct xhci_virt_device *virt_dev;
2568 union xhci_trb *cmd_trb;
2569
2570 spin_lock_irqsave(&xhci->lock, flags);
2571 virt_dev = xhci->devs[udev->slot_id];
2572
2573 if (command)
2574 in_ctx = command->in_ctx;
2575 else
2576 in_ctx = virt_dev->in_ctx;
2577
2578 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2579 xhci_reserve_host_resources(xhci, in_ctx)) {
2580 spin_unlock_irqrestore(&xhci->lock, flags);
2581 xhci_warn(xhci, "Not enough host resources, "
2582 "active endpoint contexts = %u\n",
2583 xhci->num_active_eps);
2584 return -ENOMEM;
2585 }
2586 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2587 xhci_reserve_bandwidth(xhci, virt_dev, in_ctx)) {
2588 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2589 xhci_free_host_resources(xhci, in_ctx);
2590 spin_unlock_irqrestore(&xhci->lock, flags);
2591 xhci_warn(xhci, "Not enough bandwidth\n");
2592 return -ENOMEM;
2593 }
2594
2595 if (command) {
2596 cmd_completion = command->completion;
2597 cmd_status = &command->status;
2598 command->command_trb = xhci_find_next_enqueue(xhci->cmd_ring);
2599 list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
2600 } else {
2601 cmd_completion = &virt_dev->cmd_completion;
2602 cmd_status = &virt_dev->cmd_status;
2603 }
2604 init_completion(cmd_completion);
2605
2606 cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring);
2607 if (!ctx_change)
2608 ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
2609 udev->slot_id, must_succeed);
2610 else
2611 ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
2612 udev->slot_id, must_succeed);
2613 if (ret < 0) {
2614 if (command)
2615 list_del(&command->cmd_list);
2616 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2617 xhci_free_host_resources(xhci, in_ctx);
2618 spin_unlock_irqrestore(&xhci->lock, flags);
2619 xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
2620 return -ENOMEM;
2621 }
2622 xhci_ring_cmd_db(xhci);
2623 spin_unlock_irqrestore(&xhci->lock, flags);
2624
2625 /* Wait for the configure endpoint command to complete */
2626 timeleft = wait_for_completion_interruptible_timeout(
2627 cmd_completion,
2628 XHCI_CMD_DEFAULT_TIMEOUT);
2629 if (timeleft <= 0) {
2630 xhci_warn(xhci, "%s while waiting for %s command\n",
2631 timeleft == 0 ? "Timeout" : "Signal",
2632 ctx_change == 0 ?
2633 "configure endpoint" :
2634 "evaluate context");
2635 /* cancel the configure endpoint command */
2636 ret = xhci_cancel_cmd(xhci, command, cmd_trb);
2637 if (ret < 0)
2638 return ret;
2639 return -ETIME;
2640 }
2641
2642 if (!ctx_change)
2643 ret = xhci_configure_endpoint_result(xhci, udev, cmd_status);
2644 else
2645 ret = xhci_evaluate_context_result(xhci, udev, cmd_status);
2646
2647 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2648 spin_lock_irqsave(&xhci->lock, flags);
2649 /* If the command failed, remove the reserved resources.
2650 * Otherwise, clean up the estimate to include dropped eps.
2651 */
2652 if (ret)
2653 xhci_free_host_resources(xhci, in_ctx);
2654 else
2655 xhci_finish_resource_reservation(xhci, in_ctx);
2656 spin_unlock_irqrestore(&xhci->lock, flags);
2657 }
2658 return ret;
2659 }
2660
2661 /* Called after one or more calls to xhci_add_endpoint() or
2662 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2663 * to call xhci_reset_bandwidth().
2664 *
2665 * Since we are in the middle of changing either configuration or
2666 * installing a new alt setting, the USB core won't allow URBs to be
2667 * enqueued for any endpoint on the old config or interface. Nothing
2668 * else should be touching the xhci->devs[slot_id] structure, so we
2669 * don't need to take the xhci->lock for manipulating that.
2670 */
2671 int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2672 {
2673 int i;
2674 int ret = 0;
2675 struct xhci_hcd *xhci;
2676 struct xhci_virt_device *virt_dev;
2677 struct xhci_input_control_ctx *ctrl_ctx;
2678 struct xhci_slot_ctx *slot_ctx;
2679
2680 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2681 if (ret <= 0)
2682 return ret;
2683 xhci = hcd_to_xhci(hcd);
2684 if (xhci->xhc_state & XHCI_STATE_DYING)
2685 return -ENODEV;
2686
2687 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2688 virt_dev = xhci->devs[udev->slot_id];
2689
2690 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2691 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
2692 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2693 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2694 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2695
2696 /* Don't issue the command if there's no endpoints to update. */
2697 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2698 ctrl_ctx->drop_flags == 0)
2699 return 0;
2700
2701 xhci_dbg(xhci, "New Input Control Context:\n");
2702 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2703 xhci_dbg_ctx(xhci, virt_dev->in_ctx,
2704 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2705
2706 ret = xhci_configure_endpoint(xhci, udev, NULL,
2707 false, false);
2708 if (ret) {
2709 /* Callee should call reset_bandwidth() */
2710 return ret;
2711 }
2712
2713 xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
2714 xhci_dbg_ctx(xhci, virt_dev->out_ctx,
2715 LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
2716
2717 /* Free any rings that were dropped, but not changed. */
2718 for (i = 1; i < 31; ++i) {
2719 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2720 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1))))
2721 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2722 }
2723 xhci_zero_in_ctx(xhci, virt_dev);
2724 /*
2725 * Install any rings for completely new endpoints or changed endpoints,
2726 * and free or cache any old rings from changed endpoints.
2727 */
2728 for (i = 1; i < 31; ++i) {
2729 if (!virt_dev->eps[i].new_ring)
2730 continue;
2731 /* Only cache or free the old ring if it exists.
2732 * It may not if this is the first add of an endpoint.
2733 */
2734 if (virt_dev->eps[i].ring) {
2735 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
2736 }
2737 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2738 virt_dev->eps[i].new_ring = NULL;
2739 }
2740
2741 return ret;
2742 }
2743
2744 void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2745 {
2746 struct xhci_hcd *xhci;
2747 struct xhci_virt_device *virt_dev;
2748 int i, ret;
2749
2750 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2751 if (ret <= 0)
2752 return;
2753 xhci = hcd_to_xhci(hcd);
2754
2755 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2756 virt_dev = xhci->devs[udev->slot_id];
2757 /* Free any rings allocated for added endpoints */
2758 for (i = 0; i < 31; ++i) {
2759 if (virt_dev->eps[i].new_ring) {
2760 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2761 virt_dev->eps[i].new_ring = NULL;
2762 }
2763 }
2764 xhci_zero_in_ctx(xhci, virt_dev);
2765 }
2766
2767 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2768 struct xhci_container_ctx *in_ctx,
2769 struct xhci_container_ctx *out_ctx,
2770 u32 add_flags, u32 drop_flags)
2771 {
2772 struct xhci_input_control_ctx *ctrl_ctx;
2773 ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
2774 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2775 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2776 xhci_slot_copy(xhci, in_ctx, out_ctx);
2777 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2778
2779 xhci_dbg(xhci, "Input Context:\n");
2780 xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
2781 }
2782
2783 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2784 unsigned int slot_id, unsigned int ep_index,
2785 struct xhci_dequeue_state *deq_state)
2786 {
2787 struct xhci_container_ctx *in_ctx;
2788 struct xhci_ep_ctx *ep_ctx;
2789 u32 added_ctxs;
2790 dma_addr_t addr;
2791
2792 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2793 xhci->devs[slot_id]->out_ctx, ep_index);
2794 in_ctx = xhci->devs[slot_id]->in_ctx;
2795 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2796 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2797 deq_state->new_deq_ptr);
2798 if (addr == 0) {
2799 xhci_warn(xhci, "WARN Cannot submit config ep after "
2800 "reset ep command\n");
2801 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2802 deq_state->new_deq_seg,
2803 deq_state->new_deq_ptr);
2804 return;
2805 }
2806 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2807
2808 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2809 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2810 xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
2811 }
2812
2813 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
2814 struct usb_device *udev, unsigned int ep_index)
2815 {
2816 struct xhci_dequeue_state deq_state;
2817 struct xhci_virt_ep *ep;
2818
2819 xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
2820 ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2821 /* We need to move the HW's dequeue pointer past this TD,
2822 * or it will attempt to resend it on the next doorbell ring.
2823 */
2824 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2825 ep_index, ep->stopped_stream, ep->stopped_td,
2826 &deq_state);
2827
2828 /* HW with the reset endpoint quirk will use the saved dequeue state to
2829 * issue a configure endpoint command later.
2830 */
2831 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2832 xhci_dbg(xhci, "Queueing new dequeue state\n");
2833 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2834 ep_index, ep->stopped_stream, &deq_state);
2835 } else {
2836 /* Better hope no one uses the input context between now and the
2837 * reset endpoint completion!
2838 * XXX: No idea how this hardware will react when stream rings
2839 * are enabled.
2840 */
2841 xhci_dbg(xhci, "Setting up input context for "
2842 "configure endpoint command\n");
2843 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
2844 ep_index, &deq_state);
2845 }
2846 }
2847
2848 /* Deal with stalled endpoints. The core should have sent the control message
2849 * to clear the halt condition. However, we need to make the xHCI hardware
2850 * reset its sequence number, since a device will expect a sequence number of
2851 * zero after the halt condition is cleared.
2852 * Context: in_interrupt
2853 */
2854 void xhci_endpoint_reset(struct usb_hcd *hcd,
2855 struct usb_host_endpoint *ep)
2856 {
2857 struct xhci_hcd *xhci;
2858 struct usb_device *udev;
2859 unsigned int ep_index;
2860 unsigned long flags;
2861 int ret;
2862 struct xhci_virt_ep *virt_ep;
2863
2864 xhci = hcd_to_xhci(hcd);
2865 udev = (struct usb_device *) ep->hcpriv;
2866 /* Called with a root hub endpoint (or an endpoint that wasn't added
2867 * with xhci_add_endpoint()
2868 */
2869 if (!ep->hcpriv)
2870 return;
2871 ep_index = xhci_get_endpoint_index(&ep->desc);
2872 virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
2873 if (!virt_ep->stopped_td) {
2874 xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
2875 ep->desc.bEndpointAddress);
2876 return;
2877 }
2878 if (usb_endpoint_xfer_control(&ep->desc)) {
2879 xhci_dbg(xhci, "Control endpoint stall already handled.\n");
2880 return;
2881 }
2882
2883 xhci_dbg(xhci, "Queueing reset endpoint command\n");
2884 spin_lock_irqsave(&xhci->lock, flags);
2885 ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
2886 /*
2887 * Can't change the ring dequeue pointer until it's transitioned to the
2888 * stopped state, which is only upon a successful reset endpoint
2889 * command. Better hope that last command worked!
2890 */
2891 if (!ret) {
2892 xhci_cleanup_stalled_ring(xhci, udev, ep_index);
2893 kfree(virt_ep->stopped_td);
2894 xhci_ring_cmd_db(xhci);
2895 }
2896 virt_ep->stopped_td = NULL;
2897 virt_ep->stopped_trb = NULL;
2898 virt_ep->stopped_stream = 0;
2899 spin_unlock_irqrestore(&xhci->lock, flags);
2900
2901 if (ret)
2902 xhci_warn(xhci, "FIXME allocate a new ring segment\n");
2903 }
2904
2905 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
2906 struct usb_device *udev, struct usb_host_endpoint *ep,
2907 unsigned int slot_id)
2908 {
2909 int ret;
2910 unsigned int ep_index;
2911 unsigned int ep_state;
2912
2913 if (!ep)
2914 return -EINVAL;
2915 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
2916 if (ret <= 0)
2917 return -EINVAL;
2918 if (ep->ss_ep_comp.bmAttributes == 0) {
2919 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
2920 " descriptor for ep 0x%x does not support streams\n",
2921 ep->desc.bEndpointAddress);
2922 return -EINVAL;
2923 }
2924
2925 ep_index = xhci_get_endpoint_index(&ep->desc);
2926 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
2927 if (ep_state & EP_HAS_STREAMS ||
2928 ep_state & EP_GETTING_STREAMS) {
2929 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
2930 "already has streams set up.\n",
2931 ep->desc.bEndpointAddress);
2932 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
2933 "dynamic stream context array reallocation.\n");
2934 return -EINVAL;
2935 }
2936 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
2937 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
2938 "endpoint 0x%x; URBs are pending.\n",
2939 ep->desc.bEndpointAddress);
2940 return -EINVAL;
2941 }
2942 return 0;
2943 }
2944
2945 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
2946 unsigned int *num_streams, unsigned int *num_stream_ctxs)
2947 {
2948 unsigned int max_streams;
2949
2950 /* The stream context array size must be a power of two */
2951 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
2952 /*
2953 * Find out how many primary stream array entries the host controller
2954 * supports. Later we may use secondary stream arrays (similar to 2nd
2955 * level page entries), but that's an optional feature for xHCI host
2956 * controllers. xHCs must support at least 4 stream IDs.
2957 */
2958 max_streams = HCC_MAX_PSA(xhci->hcc_params);
2959 if (*num_stream_ctxs > max_streams) {
2960 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
2961 max_streams);
2962 *num_stream_ctxs = max_streams;
2963 *num_streams = max_streams;
2964 }
2965 }
2966
2967 /* Returns an error code if one of the endpoint already has streams.
2968 * This does not change any data structures, it only checks and gathers
2969 * information.
2970 */
2971 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
2972 struct usb_device *udev,
2973 struct usb_host_endpoint **eps, unsigned int num_eps,
2974 unsigned int *num_streams, u32 *changed_ep_bitmask)
2975 {
2976 unsigned int max_streams;
2977 unsigned int endpoint_flag;
2978 int i;
2979 int ret;
2980
2981 for (i = 0; i < num_eps; i++) {
2982 ret = xhci_check_streams_endpoint(xhci, udev,
2983 eps[i], udev->slot_id);
2984 if (ret < 0)
2985 return ret;
2986
2987 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
2988 if (max_streams < (*num_streams - 1)) {
2989 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
2990 eps[i]->desc.bEndpointAddress,
2991 max_streams);
2992 *num_streams = max_streams+1;
2993 }
2994
2995 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
2996 if (*changed_ep_bitmask & endpoint_flag)
2997 return -EINVAL;
2998 *changed_ep_bitmask |= endpoint_flag;
2999 }
3000 return 0;
3001 }
3002
3003 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3004 struct usb_device *udev,
3005 struct usb_host_endpoint **eps, unsigned int num_eps)
3006 {
3007 u32 changed_ep_bitmask = 0;
3008 unsigned int slot_id;
3009 unsigned int ep_index;
3010 unsigned int ep_state;
3011 int i;
3012
3013 slot_id = udev->slot_id;
3014 if (!xhci->devs[slot_id])
3015 return 0;
3016
3017 for (i = 0; i < num_eps; i++) {
3018 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3019 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3020 /* Are streams already being freed for the endpoint? */
3021 if (ep_state & EP_GETTING_NO_STREAMS) {
3022 xhci_warn(xhci, "WARN Can't disable streams for "
3023 "endpoint 0x%x\n, "
3024 "streams are being disabled already.",
3025 eps[i]->desc.bEndpointAddress);
3026 return 0;
3027 }
3028 /* Are there actually any streams to free? */
3029 if (!(ep_state & EP_HAS_STREAMS) &&
3030 !(ep_state & EP_GETTING_STREAMS)) {
3031 xhci_warn(xhci, "WARN Can't disable streams for "
3032 "endpoint 0x%x\n, "
3033 "streams are already disabled!",
3034 eps[i]->desc.bEndpointAddress);
3035 xhci_warn(xhci, "WARN xhci_free_streams() called "
3036 "with non-streams endpoint\n");
3037 return 0;
3038 }
3039 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3040 }
3041 return changed_ep_bitmask;
3042 }
3043
3044 /*
3045 * The USB device drivers use this function (though the HCD interface in USB
3046 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3047 * coordinate mass storage command queueing across multiple endpoints (basically
3048 * a stream ID == a task ID).
3049 *
3050 * Setting up streams involves allocating the same size stream context array
3051 * for each endpoint and issuing a configure endpoint command for all endpoints.
3052 *
3053 * Don't allow the call to succeed if one endpoint only supports one stream
3054 * (which means it doesn't support streams at all).
3055 *
3056 * Drivers may get less stream IDs than they asked for, if the host controller
3057 * hardware or endpoints claim they can't support the number of requested
3058 * stream IDs.
3059 */
3060 int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3061 struct usb_host_endpoint **eps, unsigned int num_eps,
3062 unsigned int num_streams, gfp_t mem_flags)
3063 {
3064 int i, ret;
3065 struct xhci_hcd *xhci;
3066 struct xhci_virt_device *vdev;
3067 struct xhci_command *config_cmd;
3068 unsigned int ep_index;
3069 unsigned int num_stream_ctxs;
3070 unsigned long flags;
3071 u32 changed_ep_bitmask = 0;
3072
3073 if (!eps)
3074 return -EINVAL;
3075
3076 /* Add one to the number of streams requested to account for
3077 * stream 0 that is reserved for xHCI usage.
3078 */
3079 num_streams += 1;
3080 xhci = hcd_to_xhci(hcd);
3081 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3082 num_streams);
3083
3084 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
3085 if (!config_cmd) {
3086 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
3087 return -ENOMEM;
3088 }
3089
3090 /* Check to make sure all endpoints are not already configured for
3091 * streams. While we're at it, find the maximum number of streams that
3092 * all the endpoints will support and check for duplicate endpoints.
3093 */
3094 spin_lock_irqsave(&xhci->lock, flags);
3095 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3096 num_eps, &num_streams, &changed_ep_bitmask);
3097 if (ret < 0) {
3098 xhci_free_command(xhci, config_cmd);
3099 spin_unlock_irqrestore(&xhci->lock, flags);
3100 return ret;
3101 }
3102 if (num_streams <= 1) {
3103 xhci_warn(xhci, "WARN: endpoints can't handle "
3104 "more than one stream.\n");
3105 xhci_free_command(xhci, config_cmd);
3106 spin_unlock_irqrestore(&xhci->lock, flags);
3107 return -EINVAL;
3108 }
3109 vdev = xhci->devs[udev->slot_id];
3110 /* Mark each endpoint as being in transition, so
3111 * xhci_urb_enqueue() will reject all URBs.
3112 */
3113 for (i = 0; i < num_eps; i++) {
3114 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3115 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3116 }
3117 spin_unlock_irqrestore(&xhci->lock, flags);
3118
3119 /* Setup internal data structures and allocate HW data structures for
3120 * streams (but don't install the HW structures in the input context
3121 * until we're sure all memory allocation succeeded).
3122 */
3123 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3124 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3125 num_stream_ctxs, num_streams);
3126
3127 for (i = 0; i < num_eps; i++) {
3128 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3129 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3130 num_stream_ctxs,
3131 num_streams, mem_flags);
3132 if (!vdev->eps[ep_index].stream_info)
3133 goto cleanup;
3134 /* Set maxPstreams in endpoint context and update deq ptr to
3135 * point to stream context array. FIXME
3136 */
3137 }
3138
3139 /* Set up the input context for a configure endpoint command. */
3140 for (i = 0; i < num_eps; i++) {
3141 struct xhci_ep_ctx *ep_ctx;
3142
3143 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3144 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3145
3146 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3147 vdev->out_ctx, ep_index);
3148 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3149 vdev->eps[ep_index].stream_info);
3150 }
3151 /* Tell the HW to drop its old copy of the endpoint context info
3152 * and add the updated copy from the input context.
3153 */
3154 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3155 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
3156
3157 /* Issue and wait for the configure endpoint command */
3158 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3159 false, false);
3160
3161 /* xHC rejected the configure endpoint command for some reason, so we
3162 * leave the old ring intact and free our internal streams data
3163 * structure.
3164 */
3165 if (ret < 0)
3166 goto cleanup;
3167
3168 spin_lock_irqsave(&xhci->lock, flags);
3169 for (i = 0; i < num_eps; i++) {
3170 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3171 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3172 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3173 udev->slot_id, ep_index);
3174 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3175 }
3176 xhci_free_command(xhci, config_cmd);
3177 spin_unlock_irqrestore(&xhci->lock, flags);
3178
3179 /* Subtract 1 for stream 0, which drivers can't use */
3180 return num_streams - 1;
3181
3182 cleanup:
3183 /* If it didn't work, free the streams! */
3184 for (i = 0; i < num_eps; i++) {
3185 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3186 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3187 vdev->eps[ep_index].stream_info = NULL;
3188 /* FIXME Unset maxPstreams in endpoint context and
3189 * update deq ptr to point to normal string ring.
3190 */
3191 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3192 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3193 xhci_endpoint_zero(xhci, vdev, eps[i]);
3194 }
3195 xhci_free_command(xhci, config_cmd);
3196 return -ENOMEM;
3197 }
3198
3199 /* Transition the endpoint from using streams to being a "normal" endpoint
3200 * without streams.
3201 *
3202 * Modify the endpoint context state, submit a configure endpoint command,
3203 * and free all endpoint rings for streams if that completes successfully.
3204 */
3205 int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3206 struct usb_host_endpoint **eps, unsigned int num_eps,
3207 gfp_t mem_flags)
3208 {
3209 int i, ret;
3210 struct xhci_hcd *xhci;
3211 struct xhci_virt_device *vdev;
3212 struct xhci_command *command;
3213 unsigned int ep_index;
3214 unsigned long flags;
3215 u32 changed_ep_bitmask;
3216
3217 xhci = hcd_to_xhci(hcd);
3218 vdev = xhci->devs[udev->slot_id];
3219
3220 /* Set up a configure endpoint command to remove the streams rings */
3221 spin_lock_irqsave(&xhci->lock, flags);
3222 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3223 udev, eps, num_eps);
3224 if (changed_ep_bitmask == 0) {
3225 spin_unlock_irqrestore(&xhci->lock, flags);
3226 return -EINVAL;
3227 }
3228
3229 /* Use the xhci_command structure from the first endpoint. We may have
3230 * allocated too many, but the driver may call xhci_free_streams() for
3231 * each endpoint it grouped into one call to xhci_alloc_streams().
3232 */
3233 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3234 command = vdev->eps[ep_index].stream_info->free_streams_command;
3235 for (i = 0; i < num_eps; i++) {
3236 struct xhci_ep_ctx *ep_ctx;
3237
3238 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3239 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3240 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3241 EP_GETTING_NO_STREAMS;
3242
3243 xhci_endpoint_copy(xhci, command->in_ctx,
3244 vdev->out_ctx, ep_index);
3245 xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
3246 &vdev->eps[ep_index]);
3247 }
3248 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3249 vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
3250 spin_unlock_irqrestore(&xhci->lock, flags);
3251
3252 /* Issue and wait for the configure endpoint command,
3253 * which must succeed.
3254 */
3255 ret = xhci_configure_endpoint(xhci, udev, command,
3256 false, true);
3257
3258 /* xHC rejected the configure endpoint command for some reason, so we
3259 * leave the streams rings intact.
3260 */
3261 if (ret < 0)
3262 return ret;
3263
3264 spin_lock_irqsave(&xhci->lock, flags);
3265 for (i = 0; i < num_eps; i++) {
3266 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3267 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3268 vdev->eps[ep_index].stream_info = NULL;
3269 /* FIXME Unset maxPstreams in endpoint context and
3270 * update deq ptr to point to normal string ring.
3271 */
3272 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3273 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3274 }
3275 spin_unlock_irqrestore(&xhci->lock, flags);
3276
3277 return 0;
3278 }
3279
3280 /*
3281 * Deletes endpoint resources for endpoints that were active before a Reset
3282 * Device command, or a Disable Slot command. The Reset Device command leaves
3283 * the control endpoint intact, whereas the Disable Slot command deletes it.
3284 *
3285 * Must be called with xhci->lock held.
3286 */
3287 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3288 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3289 {
3290 int i;
3291 unsigned int num_dropped_eps = 0;
3292 unsigned int drop_flags = 0;
3293
3294 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3295 if (virt_dev->eps[i].ring) {
3296 drop_flags |= 1 << i;
3297 num_dropped_eps++;
3298 }
3299 }
3300 xhci->num_active_eps -= num_dropped_eps;
3301 if (num_dropped_eps)
3302 xhci_dbg(xhci, "Dropped %u ep ctxs, flags = 0x%x, "
3303 "%u now active.\n",
3304 num_dropped_eps, drop_flags,
3305 xhci->num_active_eps);
3306 }
3307
3308 /*
3309 * This submits a Reset Device Command, which will set the device state to 0,
3310 * set the device address to 0, and disable all the endpoints except the default
3311 * control endpoint. The USB core should come back and call
3312 * xhci_address_device(), and then re-set up the configuration. If this is
3313 * called because of a usb_reset_and_verify_device(), then the old alternate
3314 * settings will be re-installed through the normal bandwidth allocation
3315 * functions.
3316 *
3317 * Wait for the Reset Device command to finish. Remove all structures
3318 * associated with the endpoints that were disabled. Clear the input device
3319 * structure? Cache the rings? Reset the control endpoint 0 max packet size?
3320 *
3321 * If the virt_dev to be reset does not exist or does not match the udev,
3322 * it means the device is lost, possibly due to the xHC restore error and
3323 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3324 * re-allocate the device.
3325 */
3326 int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
3327 {
3328 int ret, i;
3329 unsigned long flags;
3330 struct xhci_hcd *xhci;
3331 unsigned int slot_id;
3332 struct xhci_virt_device *virt_dev;
3333 struct xhci_command *reset_device_cmd;
3334 int timeleft;
3335 int last_freed_endpoint;
3336 struct xhci_slot_ctx *slot_ctx;
3337 int old_active_eps = 0;
3338
3339 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3340 if (ret <= 0)
3341 return ret;
3342 xhci = hcd_to_xhci(hcd);
3343 slot_id = udev->slot_id;
3344 virt_dev = xhci->devs[slot_id];
3345 if (!virt_dev) {
3346 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3347 "not exist. Re-allocate the device\n", slot_id);
3348 ret = xhci_alloc_dev(hcd, udev);
3349 if (ret == 1)
3350 return 0;
3351 else
3352 return -EINVAL;
3353 }
3354
3355 if (virt_dev->udev != udev) {
3356 /* If the virt_dev and the udev does not match, this virt_dev
3357 * may belong to another udev.
3358 * Re-allocate the device.
3359 */
3360 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3361 "not match the udev. Re-allocate the device\n",
3362 slot_id);
3363 ret = xhci_alloc_dev(hcd, udev);
3364 if (ret == 1)
3365 return 0;
3366 else
3367 return -EINVAL;
3368 }
3369
3370 /* If device is not setup, there is no point in resetting it */
3371 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3372 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3373 SLOT_STATE_DISABLED)
3374 return 0;
3375
3376 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3377 /* Allocate the command structure that holds the struct completion.
3378 * Assume we're in process context, since the normal device reset
3379 * process has to wait for the device anyway. Storage devices are
3380 * reset as part of error handling, so use GFP_NOIO instead of
3381 * GFP_KERNEL.
3382 */
3383 reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
3384 if (!reset_device_cmd) {
3385 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3386 return -ENOMEM;
3387 }
3388
3389 /* Attempt to submit the Reset Device command to the command ring */
3390 spin_lock_irqsave(&xhci->lock, flags);
3391 reset_device_cmd->command_trb = xhci_find_next_enqueue(xhci->cmd_ring);
3392
3393 list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
3394 ret = xhci_queue_reset_device(xhci, slot_id);
3395 if (ret) {
3396 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3397 list_del(&reset_device_cmd->cmd_list);
3398 spin_unlock_irqrestore(&xhci->lock, flags);
3399 goto command_cleanup;
3400 }
3401 xhci_ring_cmd_db(xhci);
3402 spin_unlock_irqrestore(&xhci->lock, flags);
3403
3404 /* Wait for the Reset Device command to finish */
3405 timeleft = wait_for_completion_interruptible_timeout(
3406 reset_device_cmd->completion,
3407 USB_CTRL_SET_TIMEOUT);
3408 if (timeleft <= 0) {
3409 xhci_warn(xhci, "%s while waiting for reset device command\n",
3410 timeleft == 0 ? "Timeout" : "Signal");
3411 spin_lock_irqsave(&xhci->lock, flags);
3412 /* The timeout might have raced with the event ring handler, so
3413 * only delete from the list if the item isn't poisoned.
3414 */
3415 if (reset_device_cmd->cmd_list.next != LIST_POISON1)
3416 list_del(&reset_device_cmd->cmd_list);
3417 spin_unlock_irqrestore(&xhci->lock, flags);
3418 ret = -ETIME;
3419 goto command_cleanup;
3420 }
3421
3422 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3423 * unless we tried to reset a slot ID that wasn't enabled,
3424 * or the device wasn't in the addressed or configured state.
3425 */
3426 ret = reset_device_cmd->status;
3427 switch (ret) {
3428 case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
3429 case COMP_CTX_STATE: /* 0.96 completion code for same thing */
3430 xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
3431 slot_id,
3432 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3433 xhci_info(xhci, "Not freeing device rings.\n");
3434 /* Don't treat this as an error. May change my mind later. */
3435 ret = 0;
3436 goto command_cleanup;
3437 case COMP_SUCCESS:
3438 xhci_dbg(xhci, "Successful reset device command.\n");
3439 break;
3440 default:
3441 if (xhci_is_vendor_info_code(xhci, ret))
3442 break;
3443 xhci_warn(xhci, "Unknown completion code %u for "
3444 "reset device command.\n", ret);
3445 ret = -EINVAL;
3446 goto command_cleanup;
3447 }
3448
3449 /* Free up host controller endpoint resources */
3450 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3451 spin_lock_irqsave(&xhci->lock, flags);
3452 /* Don't delete the default control endpoint resources */
3453 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3454 spin_unlock_irqrestore(&xhci->lock, flags);
3455 }
3456
3457 /* Everything but endpoint 0 is disabled, so free or cache the rings. */
3458 last_freed_endpoint = 1;
3459 for (i = 1; i < 31; ++i) {
3460 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3461
3462 if (ep->ep_state & EP_HAS_STREAMS) {
3463 xhci_free_stream_info(xhci, ep->stream_info);
3464 ep->stream_info = NULL;
3465 ep->ep_state &= ~EP_HAS_STREAMS;
3466 }
3467
3468 if (ep->ring) {
3469 xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
3470 last_freed_endpoint = i;
3471 }
3472 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3473 xhci_drop_ep_from_interval_table(xhci,
3474 &virt_dev->eps[i].bw_info,
3475 virt_dev->bw_table,
3476 udev,
3477 &virt_dev->eps[i],
3478 virt_dev->tt_info);
3479 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3480 }
3481 /* If necessary, update the number of active TTs on this root port */
3482 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3483
3484 xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
3485 xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
3486 ret = 0;
3487
3488 command_cleanup:
3489 xhci_free_command(xhci, reset_device_cmd);
3490 return ret;
3491 }
3492
3493 /*
3494 * At this point, the struct usb_device is about to go away, the device has
3495 * disconnected, and all traffic has been stopped and the endpoints have been
3496 * disabled. Free any HC data structures associated with that device.
3497 */
3498 void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3499 {
3500 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3501 struct xhci_virt_device *virt_dev;
3502 struct device *dev = hcd->self.controller;
3503 unsigned long flags;
3504 u32 state;
3505 int i, ret;
3506
3507 #ifndef CONFIG_USB_DEFAULT_PERSIST
3508 /*
3509 * We called pm_runtime_get_noresume when the device was attached.
3510 * Decrement the counter here to allow controller to runtime suspend
3511 * if no devices remain.
3512 */
3513 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3514 pm_runtime_put_noidle(dev);
3515 #endif
3516
3517 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3518 /* If the host is halted due to driver unload, we still need to free the
3519 * device.
3520 */
3521 if (ret <= 0 && ret != -ENODEV)
3522 return;
3523
3524 virt_dev = xhci->devs[udev->slot_id];
3525
3526 /* Stop any wayward timer functions (which may grab the lock) */
3527 for (i = 0; i < 31; ++i) {
3528 virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
3529 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3530 }
3531
3532 if (udev->usb2_hw_lpm_enabled) {
3533 xhci_set_usb2_hardware_lpm(hcd, udev, 0);
3534 udev->usb2_hw_lpm_enabled = 0;
3535 }
3536
3537 spin_lock_irqsave(&xhci->lock, flags);
3538 /* Don't disable the slot if the host controller is dead. */
3539 state = xhci_readl(xhci, &xhci->op_regs->status);
3540 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3541 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3542 xhci_free_virt_device(xhci, udev->slot_id);
3543 spin_unlock_irqrestore(&xhci->lock, flags);
3544 return;
3545 }
3546
3547 if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
3548 spin_unlock_irqrestore(&xhci->lock, flags);
3549 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3550 return;
3551 }
3552 xhci_ring_cmd_db(xhci);
3553 spin_unlock_irqrestore(&xhci->lock, flags);
3554 /*
3555 * Event command completion handler will free any data structures
3556 * associated with the slot. XXX Can free sleep?
3557 */
3558 }
3559
3560 /*
3561 * Checks if we have enough host controller resources for the default control
3562 * endpoint.
3563 *
3564 * Must be called with xhci->lock held.
3565 */
3566 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3567 {
3568 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3569 xhci_dbg(xhci, "Not enough ep ctxs: "
3570 "%u active, need to add 1, limit is %u.\n",
3571 xhci->num_active_eps, xhci->limit_active_eps);
3572 return -ENOMEM;
3573 }
3574 xhci->num_active_eps += 1;
3575 xhci_dbg(xhci, "Adding 1 ep ctx, %u now active.\n",
3576 xhci->num_active_eps);
3577 return 0;
3578 }
3579
3580
3581 /*
3582 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3583 * timed out, or allocating memory failed. Returns 1 on success.
3584 */
3585 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3586 {
3587 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3588 struct device *dev = hcd->self.controller;
3589 unsigned long flags;
3590 int timeleft;
3591 int ret;
3592 union xhci_trb *cmd_trb;
3593
3594 spin_lock_irqsave(&xhci->lock, flags);
3595 cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring);
3596 ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
3597 if (ret) {
3598 spin_unlock_irqrestore(&xhci->lock, flags);
3599 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3600 return 0;
3601 }
3602 xhci_ring_cmd_db(xhci);
3603 spin_unlock_irqrestore(&xhci->lock, flags);
3604
3605 /* XXX: how much time for xHC slot assignment? */
3606 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3607 XHCI_CMD_DEFAULT_TIMEOUT);
3608 if (timeleft <= 0) {
3609 xhci_warn(xhci, "%s while waiting for a slot\n",
3610 timeleft == 0 ? "Timeout" : "Signal");
3611 /* cancel the enable slot request */
3612 return xhci_cancel_cmd(xhci, NULL, cmd_trb);
3613 }
3614
3615 if (!xhci->slot_id) {
3616 xhci_err(xhci, "Error while assigning device slot ID\n");
3617 return 0;
3618 }
3619
3620 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3621 spin_lock_irqsave(&xhci->lock, flags);
3622 ret = xhci_reserve_host_control_ep_resources(xhci);
3623 if (ret) {
3624 spin_unlock_irqrestore(&xhci->lock, flags);
3625 xhci_warn(xhci, "Not enough host resources, "
3626 "active endpoint contexts = %u\n",
3627 xhci->num_active_eps);
3628 goto disable_slot;
3629 }
3630 spin_unlock_irqrestore(&xhci->lock, flags);
3631 }
3632 /* Use GFP_NOIO, since this function can be called from
3633 * xhci_discover_or_reset_device(), which may be called as part of
3634 * mass storage driver error handling.
3635 */
3636 if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
3637 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3638 goto disable_slot;
3639 }
3640 udev->slot_id = xhci->slot_id;
3641
3642 #ifndef CONFIG_USB_DEFAULT_PERSIST
3643 /*
3644 * If resetting upon resume, we can't put the controller into runtime
3645 * suspend if there is a device attached.
3646 */
3647 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3648 pm_runtime_get_noresume(dev);
3649 #endif
3650
3651 /* Is this a LS or FS device under a HS hub? */
3652 /* Hub or peripherial? */
3653 return 1;
3654
3655 disable_slot:
3656 /* Disable slot, if we can do it without mem alloc */
3657 spin_lock_irqsave(&xhci->lock, flags);
3658 if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
3659 xhci_ring_cmd_db(xhci);
3660 spin_unlock_irqrestore(&xhci->lock, flags);
3661 return 0;
3662 }
3663
3664 /*
3665 * Issue an Address Device command (which will issue a SetAddress request to
3666 * the device).
3667 * We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
3668 * we should only issue and wait on one address command at the same time.
3669 *
3670 * We add one to the device address issued by the hardware because the USB core
3671 * uses address 1 for the root hubs (even though they're not really devices).
3672 */
3673 int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
3674 {
3675 unsigned long flags;
3676 int timeleft;
3677 struct xhci_virt_device *virt_dev;
3678 int ret = 0;
3679 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3680 struct xhci_slot_ctx *slot_ctx;
3681 struct xhci_input_control_ctx *ctrl_ctx;
3682 u64 temp_64;
3683 union xhci_trb *cmd_trb;
3684
3685 if (!udev->slot_id) {
3686 xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
3687 return -EINVAL;
3688 }
3689
3690 virt_dev = xhci->devs[udev->slot_id];
3691
3692 if (WARN_ON(!virt_dev)) {
3693 /*
3694 * In plug/unplug torture test with an NEC controller,
3695 * a zero-dereference was observed once due to virt_dev = 0.
3696 * Print useful debug rather than crash if it is observed again!
3697 */
3698 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3699 udev->slot_id);
3700 return -EINVAL;
3701 }
3702
3703 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3704 /*
3705 * If this is the first Set Address since device plug-in or
3706 * virt_device realloaction after a resume with an xHCI power loss,
3707 * then set up the slot context.
3708 */
3709 if (!slot_ctx->dev_info)
3710 xhci_setup_addressable_virt_dev(xhci, udev);
3711 /* Otherwise, update the control endpoint ring enqueue pointer. */
3712 else
3713 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3714 ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
3715 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3716 ctrl_ctx->drop_flags = 0;
3717
3718 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3719 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3720
3721 spin_lock_irqsave(&xhci->lock, flags);
3722 cmd_trb = xhci_find_next_enqueue(xhci->cmd_ring);
3723 ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
3724 udev->slot_id);
3725 if (ret) {
3726 spin_unlock_irqrestore(&xhci->lock, flags);
3727 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3728 return ret;
3729 }
3730 xhci_ring_cmd_db(xhci);
3731 spin_unlock_irqrestore(&xhci->lock, flags);
3732
3733 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
3734 timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
3735 XHCI_CMD_DEFAULT_TIMEOUT);
3736 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
3737 * the SetAddress() "recovery interval" required by USB and aborting the
3738 * command on a timeout.
3739 */
3740 if (timeleft <= 0) {
3741 xhci_warn(xhci, "%s while waiting for address device command\n",
3742 timeleft == 0 ? "Timeout" : "Signal");
3743 /* cancel the address device command */
3744 ret = xhci_cancel_cmd(xhci, NULL, cmd_trb);
3745 if (ret < 0)
3746 return ret;
3747 return -ETIME;
3748 }
3749
3750 switch (virt_dev->cmd_status) {
3751 case COMP_CTX_STATE:
3752 case COMP_EBADSLT:
3753 xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
3754 udev->slot_id);
3755 ret = -EINVAL;
3756 break;
3757 case COMP_TX_ERR:
3758 dev_warn(&udev->dev, "Device not responding to set address.\n");
3759 ret = -EPROTO;
3760 break;
3761 case COMP_DEV_ERR:
3762 dev_warn(&udev->dev, "ERROR: Incompatible device for address "
3763 "device command.\n");
3764 ret = -ENODEV;
3765 break;
3766 case COMP_SUCCESS:
3767 xhci_dbg(xhci, "Successful Address Device command\n");
3768 break;
3769 default:
3770 xhci_err(xhci, "ERROR: unexpected command completion "
3771 "code 0x%x.\n", virt_dev->cmd_status);
3772 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3773 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3774 ret = -EINVAL;
3775 break;
3776 }
3777 if (ret) {
3778 return ret;
3779 }
3780 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
3781 xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
3782 xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
3783 udev->slot_id,
3784 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
3785 (unsigned long long)
3786 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
3787 xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
3788 (unsigned long long)virt_dev->out_ctx->dma);
3789 xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
3790 xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
3791 xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
3792 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
3793 /*
3794 * USB core uses address 1 for the roothubs, so we add one to the
3795 * address given back to us by the HC.
3796 */
3797 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3798 /* Use kernel assigned address for devices; store xHC assigned
3799 * address locally. */
3800 virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
3801 + 1;
3802 /* Zero the input context control for later use */
3803 ctrl_ctx->add_flags = 0;
3804 ctrl_ctx->drop_flags = 0;
3805
3806 xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
3807
3808 return 0;
3809 }
3810
3811 /*
3812 * Transfer the port index into real index in the HW port status
3813 * registers. Caculate offset between the port's PORTSC register
3814 * and port status base. Divide the number of per port register
3815 * to get the real index. The raw port number bases 1.
3816 */
3817 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
3818 {
3819 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3820 __le32 __iomem *base_addr = &xhci->op_regs->port_status_base;
3821 __le32 __iomem *addr;
3822 int raw_port;
3823
3824 if (hcd->speed != HCD_USB3)
3825 addr = xhci->usb2_ports[port1 - 1];
3826 else
3827 addr = xhci->usb3_ports[port1 - 1];
3828
3829 raw_port = (addr - base_addr)/NUM_PORT_REGS + 1;
3830 return raw_port;
3831 }
3832
3833 #ifdef CONFIG_PM_RUNTIME
3834
3835 /* BESL to HIRD Encoding array for USB2 LPM */
3836 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
3837 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
3838
3839 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
3840 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
3841 struct usb_device *udev)
3842 {
3843 int u2del, besl, besl_host;
3844 int besl_device = 0;
3845 u32 field;
3846
3847 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
3848 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
3849
3850 if (field & USB_BESL_SUPPORT) {
3851 for (besl_host = 0; besl_host < 16; besl_host++) {
3852 if (xhci_besl_encoding[besl_host] >= u2del)
3853 break;
3854 }
3855 /* Use baseline BESL value as default */
3856 if (field & USB_BESL_BASELINE_VALID)
3857 besl_device = USB_GET_BESL_BASELINE(field);
3858 else if (field & USB_BESL_DEEP_VALID)
3859 besl_device = USB_GET_BESL_DEEP(field);
3860 } else {
3861 if (u2del <= 50)
3862 besl_host = 0;
3863 else
3864 besl_host = (u2del - 51) / 75 + 1;
3865 }
3866
3867 besl = besl_host + besl_device;
3868 if (besl > 15)
3869 besl = 15;
3870
3871 return besl;
3872 }
3873
3874 static int xhci_usb2_software_lpm_test(struct usb_hcd *hcd,
3875 struct usb_device *udev)
3876 {
3877 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3878 struct dev_info *dev_info;
3879 __le32 __iomem **port_array;
3880 __le32 __iomem *addr, *pm_addr;
3881 u32 temp, dev_id;
3882 unsigned int port_num;
3883 unsigned long flags;
3884 int hird;
3885 int ret;
3886
3887 if (hcd->speed == HCD_USB3 || !xhci->sw_lpm_support ||
3888 !udev->lpm_capable)
3889 return -EINVAL;
3890
3891 /* we only support lpm for non-hub device connected to root hub yet */
3892 if (!udev->parent || udev->parent->parent ||
3893 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
3894 return -EINVAL;
3895
3896 spin_lock_irqsave(&xhci->lock, flags);
3897
3898 /* Look for devices in lpm_failed_devs list */
3899 dev_id = le16_to_cpu(udev->descriptor.idVendor) << 16 |
3900 le16_to_cpu(udev->descriptor.idProduct);
3901 list_for_each_entry(dev_info, &xhci->lpm_failed_devs, list) {
3902 if (dev_info->dev_id == dev_id) {
3903 ret = -EINVAL;
3904 goto finish;
3905 }
3906 }
3907
3908 port_array = xhci->usb2_ports;
3909 port_num = udev->portnum - 1;
3910
3911 if (port_num > HCS_MAX_PORTS(xhci->hcs_params1)) {
3912 xhci_dbg(xhci, "invalid port number %d\n", udev->portnum);
3913 ret = -EINVAL;
3914 goto finish;
3915 }
3916
3917 /*
3918 * Test USB 2.0 software LPM.
3919 * FIXME: some xHCI 1.0 hosts may implement a new register to set up
3920 * hardware-controlled USB 2.0 LPM. See section 5.4.11 and 4.23.5.1.1.1
3921 * in the June 2011 errata release.
3922 */
3923 xhci_dbg(xhci, "test port %d software LPM\n", port_num);
3924 /*
3925 * Set L1 Device Slot and HIRD/BESL.
3926 * Check device's USB 2.0 extension descriptor to determine whether
3927 * HIRD or BESL shoule be used. See USB2.0 LPM errata.
3928 */
3929 pm_addr = port_array[port_num] + 1;
3930 hird = xhci_calculate_hird_besl(xhci, udev);
3931 temp = PORT_L1DS(udev->slot_id) | PORT_HIRD(hird);
3932 xhci_writel(xhci, temp, pm_addr);
3933
3934 /* Set port link state to U2(L1) */
3935 addr = port_array[port_num];
3936 xhci_set_link_state(xhci, port_array, port_num, XDEV_U2);
3937
3938 /* wait for ACK */
3939 spin_unlock_irqrestore(&xhci->lock, flags);
3940 msleep(10);
3941 spin_lock_irqsave(&xhci->lock, flags);
3942
3943 /* Check L1 Status */
3944 ret = xhci_handshake(xhci, pm_addr,
3945 PORT_L1S_MASK, PORT_L1S_SUCCESS, 125);
3946 if (ret != -ETIMEDOUT) {
3947 /* enter L1 successfully */
3948 temp = xhci_readl(xhci, addr);
3949 xhci_dbg(xhci, "port %d entered L1 state, port status 0x%x\n",
3950 port_num, temp);
3951 ret = 0;
3952 } else {
3953 temp = xhci_readl(xhci, pm_addr);
3954 xhci_dbg(xhci, "port %d software lpm failed, L1 status %d\n",
3955 port_num, temp & PORT_L1S_MASK);
3956 ret = -EINVAL;
3957 }
3958
3959 /* Resume the port */
3960 xhci_set_link_state(xhci, port_array, port_num, XDEV_U0);
3961
3962 spin_unlock_irqrestore(&xhci->lock, flags);
3963 msleep(10);
3964 spin_lock_irqsave(&xhci->lock, flags);
3965
3966 /* Clear PLC */
3967 xhci_test_and_clear_bit(xhci, port_array, port_num, PORT_PLC);
3968
3969 /* Check PORTSC to make sure the device is in the right state */
3970 if (!ret) {
3971 temp = xhci_readl(xhci, addr);
3972 xhci_dbg(xhci, "resumed port %d status 0x%x\n", port_num, temp);
3973 if (!(temp & PORT_CONNECT) || !(temp & PORT_PE) ||
3974 (temp & PORT_PLS_MASK) != XDEV_U0) {
3975 xhci_dbg(xhci, "port L1 resume fail\n");
3976 ret = -EINVAL;
3977 }
3978 }
3979
3980 if (ret) {
3981 /* Insert dev to lpm_failed_devs list */
3982 xhci_warn(xhci, "device LPM test failed, may disconnect and "
3983 "re-enumerate\n");
3984 dev_info = kzalloc(sizeof(struct dev_info), GFP_ATOMIC);
3985 if (!dev_info) {
3986 ret = -ENOMEM;
3987 goto finish;
3988 }
3989 dev_info->dev_id = dev_id;
3990 INIT_LIST_HEAD(&dev_info->list);
3991 list_add(&dev_info->list, &xhci->lpm_failed_devs);
3992 } else {
3993 xhci_ring_device(xhci, udev->slot_id);
3994 }
3995
3996 finish:
3997 spin_unlock_irqrestore(&xhci->lock, flags);
3998 return ret;
3999 }
4000
4001 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4002 struct usb_device *udev, int enable)
4003 {
4004 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4005 __le32 __iomem **port_array;
4006 __le32 __iomem *pm_addr;
4007 u32 temp;
4008 unsigned int port_num;
4009 unsigned long flags;
4010 int hird;
4011
4012 if (hcd->speed == HCD_USB3 || !xhci->hw_lpm_support ||
4013 !udev->lpm_capable)
4014 return -EPERM;
4015
4016 if (!udev->parent || udev->parent->parent ||
4017 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4018 return -EPERM;
4019
4020 if (udev->usb2_hw_lpm_capable != 1)
4021 return -EPERM;
4022
4023 spin_lock_irqsave(&xhci->lock, flags);
4024
4025 port_array = xhci->usb2_ports;
4026 port_num = udev->portnum - 1;
4027 pm_addr = port_array[port_num] + 1;
4028 temp = xhci_readl(xhci, pm_addr);
4029
4030 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4031 enable ? "enable" : "disable", port_num);
4032
4033 hird = xhci_calculate_hird_besl(xhci, udev);
4034
4035 if (enable) {
4036 temp &= ~PORT_HIRD_MASK;
4037 temp |= PORT_HIRD(hird) | PORT_RWE;
4038 xhci_writel(xhci, temp, pm_addr);
4039 temp = xhci_readl(xhci, pm_addr);
4040 temp |= PORT_HLE;
4041 xhci_writel(xhci, temp, pm_addr);
4042 } else {
4043 temp &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK);
4044 xhci_writel(xhci, temp, pm_addr);
4045 }
4046
4047 spin_unlock_irqrestore(&xhci->lock, flags);
4048 return 0;
4049 }
4050
4051 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4052 {
4053 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4054 int ret;
4055
4056 ret = xhci_usb2_software_lpm_test(hcd, udev);
4057 if (!ret) {
4058 xhci_dbg(xhci, "software LPM test succeed\n");
4059 if (xhci->hw_lpm_support == 1) {
4060 udev->usb2_hw_lpm_capable = 1;
4061 ret = xhci_set_usb2_hardware_lpm(hcd, udev, 1);
4062 if (!ret)
4063 udev->usb2_hw_lpm_enabled = 1;
4064 }
4065 }
4066
4067 return 0;
4068 }
4069
4070 #else
4071
4072 int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4073 struct usb_device *udev, int enable)
4074 {
4075 return 0;
4076 }
4077
4078 int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4079 {
4080 return 0;
4081 }
4082
4083 #endif /* CONFIG_PM_RUNTIME */
4084
4085 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4086
4087 #ifdef CONFIG_PM
4088 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4089 static unsigned long long xhci_service_interval_to_ns(
4090 struct usb_endpoint_descriptor *desc)
4091 {
4092 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4093 }
4094
4095 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4096 enum usb3_link_state state)
4097 {
4098 unsigned long long sel;
4099 unsigned long long pel;
4100 unsigned int max_sel_pel;
4101 char *state_name;
4102
4103 switch (state) {
4104 case USB3_LPM_U1:
4105 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4106 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4107 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4108 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4109 state_name = "U1";
4110 break;
4111 case USB3_LPM_U2:
4112 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4113 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4114 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4115 state_name = "U2";
4116 break;
4117 default:
4118 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4119 __func__);
4120 return USB3_LPM_DISABLED;
4121 }
4122
4123 if (sel <= max_sel_pel && pel <= max_sel_pel)
4124 return USB3_LPM_DEVICE_INITIATED;
4125
4126 if (sel > max_sel_pel)
4127 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4128 "due to long SEL %llu ms\n",
4129 state_name, sel);
4130 else
4131 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4132 "due to long PEL %llu\n ms",
4133 state_name, pel);
4134 return USB3_LPM_DISABLED;
4135 }
4136
4137 /* Returns the hub-encoded U1 timeout value.
4138 * The U1 timeout should be the maximum of the following values:
4139 * - For control endpoints, U1 system exit latency (SEL) * 3
4140 * - For bulk endpoints, U1 SEL * 5
4141 * - For interrupt endpoints:
4142 * - Notification EPs, U1 SEL * 3
4143 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4144 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4145 */
4146 static u16 xhci_calculate_intel_u1_timeout(struct usb_device *udev,
4147 struct usb_endpoint_descriptor *desc)
4148 {
4149 unsigned long long timeout_ns;
4150 int ep_type;
4151 int intr_type;
4152
4153 ep_type = usb_endpoint_type(desc);
4154 switch (ep_type) {
4155 case USB_ENDPOINT_XFER_CONTROL:
4156 timeout_ns = udev->u1_params.sel * 3;
4157 break;
4158 case USB_ENDPOINT_XFER_BULK:
4159 timeout_ns = udev->u1_params.sel * 5;
4160 break;
4161 case USB_ENDPOINT_XFER_INT:
4162 intr_type = usb_endpoint_interrupt_type(desc);
4163 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4164 timeout_ns = udev->u1_params.sel * 3;
4165 break;
4166 }
4167 /* Otherwise the calculation is the same as isoc eps */
4168 case USB_ENDPOINT_XFER_ISOC:
4169 timeout_ns = xhci_service_interval_to_ns(desc);
4170 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4171 if (timeout_ns < udev->u1_params.sel * 2)
4172 timeout_ns = udev->u1_params.sel * 2;
4173 break;
4174 default:
4175 return 0;
4176 }
4177
4178 /* The U1 timeout is encoded in 1us intervals. */
4179 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4180 /* Don't return a timeout of zero, because that's USB3_LPM_DISABLED. */
4181 if (timeout_ns == USB3_LPM_DISABLED)
4182 timeout_ns++;
4183
4184 /* If the necessary timeout value is bigger than what we can set in the
4185 * USB 3.0 hub, we have to disable hub-initiated U1.
4186 */
4187 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4188 return timeout_ns;
4189 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4190 "due to long timeout %llu ms\n", timeout_ns);
4191 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4192 }
4193
4194 /* Returns the hub-encoded U2 timeout value.
4195 * The U2 timeout should be the maximum of:
4196 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4197 * - largest bInterval of any active periodic endpoint (to avoid going
4198 * into lower power link states between intervals).
4199 * - the U2 Exit Latency of the device
4200 */
4201 static u16 xhci_calculate_intel_u2_timeout(struct usb_device *udev,
4202 struct usb_endpoint_descriptor *desc)
4203 {
4204 unsigned long long timeout_ns;
4205 unsigned long long u2_del_ns;
4206
4207 timeout_ns = 10 * 1000 * 1000;
4208
4209 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4210 (xhci_service_interval_to_ns(desc) > timeout_ns))
4211 timeout_ns = xhci_service_interval_to_ns(desc);
4212
4213 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4214 if (u2_del_ns > timeout_ns)
4215 timeout_ns = u2_del_ns;
4216
4217 /* The U2 timeout is encoded in 256us intervals */
4218 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4219 /* If the necessary timeout value is bigger than what we can set in the
4220 * USB 3.0 hub, we have to disable hub-initiated U2.
4221 */
4222 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4223 return timeout_ns;
4224 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4225 "due to long timeout %llu ms\n", timeout_ns);
4226 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4227 }
4228
4229 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4230 struct usb_device *udev,
4231 struct usb_endpoint_descriptor *desc,
4232 enum usb3_link_state state,
4233 u16 *timeout)
4234 {
4235 if (state == USB3_LPM_U1) {
4236 if (xhci->quirks & XHCI_INTEL_HOST)
4237 return xhci_calculate_intel_u1_timeout(udev, desc);
4238 } else {
4239 if (xhci->quirks & XHCI_INTEL_HOST)
4240 return xhci_calculate_intel_u2_timeout(udev, desc);
4241 }
4242
4243 return USB3_LPM_DISABLED;
4244 }
4245
4246 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4247 struct usb_device *udev,
4248 struct usb_endpoint_descriptor *desc,
4249 enum usb3_link_state state,
4250 u16 *timeout)
4251 {
4252 u16 alt_timeout;
4253
4254 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4255 desc, state, timeout);
4256
4257 /* If we found we can't enable hub-initiated LPM, or
4258 * the U1 or U2 exit latency was too high to allow
4259 * device-initiated LPM as well, just stop searching.
4260 */
4261 if (alt_timeout == USB3_LPM_DISABLED ||
4262 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4263 *timeout = alt_timeout;
4264 return -E2BIG;
4265 }
4266 if (alt_timeout > *timeout)
4267 *timeout = alt_timeout;
4268 return 0;
4269 }
4270
4271 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4272 struct usb_device *udev,
4273 struct usb_host_interface *alt,
4274 enum usb3_link_state state,
4275 u16 *timeout)
4276 {
4277 int j;
4278
4279 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4280 if (xhci_update_timeout_for_endpoint(xhci, udev,
4281 &alt->endpoint[j].desc, state, timeout))
4282 return -E2BIG;
4283 continue;
4284 }
4285 return 0;
4286 }
4287
4288 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4289 enum usb3_link_state state)
4290 {
4291 struct usb_device *parent;
4292 unsigned int num_hubs;
4293
4294 if (state == USB3_LPM_U2)
4295 return 0;
4296
4297 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4298 for (parent = udev->parent, num_hubs = 0; parent->parent;
4299 parent = parent->parent)
4300 num_hubs++;
4301
4302 if (num_hubs < 2)
4303 return 0;
4304
4305 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4306 " below second-tier hub.\n");
4307 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4308 "to decrease power consumption.\n");
4309 return -E2BIG;
4310 }
4311
4312 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4313 struct usb_device *udev,
4314 enum usb3_link_state state)
4315 {
4316 if (xhci->quirks & XHCI_INTEL_HOST)
4317 return xhci_check_intel_tier_policy(udev, state);
4318 return -EINVAL;
4319 }
4320
4321 /* Returns the U1 or U2 timeout that should be enabled.
4322 * If the tier check or timeout setting functions return with a non-zero exit
4323 * code, that means the timeout value has been finalized and we shouldn't look
4324 * at any more endpoints.
4325 */
4326 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4327 struct usb_device *udev, enum usb3_link_state state)
4328 {
4329 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4330 struct usb_host_config *config;
4331 char *state_name;
4332 int i;
4333 u16 timeout = USB3_LPM_DISABLED;
4334
4335 if (state == USB3_LPM_U1)
4336 state_name = "U1";
4337 else if (state == USB3_LPM_U2)
4338 state_name = "U2";
4339 else {
4340 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4341 state);
4342 return timeout;
4343 }
4344
4345 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4346 return timeout;
4347
4348 /* Gather some information about the currently installed configuration
4349 * and alternate interface settings.
4350 */
4351 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4352 state, &timeout))
4353 return timeout;
4354
4355 config = udev->actconfig;
4356 if (!config)
4357 return timeout;
4358
4359 for (i = 0; i < USB_MAXINTERFACES; i++) {
4360 struct usb_driver *driver;
4361 struct usb_interface *intf = config->interface[i];
4362
4363 if (!intf)
4364 continue;
4365
4366 /* Check if any currently bound drivers want hub-initiated LPM
4367 * disabled.
4368 */
4369 if (intf->dev.driver) {
4370 driver = to_usb_driver(intf->dev.driver);
4371 if (driver && driver->disable_hub_initiated_lpm) {
4372 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4373 "at request of driver %s\n",
4374 state_name, driver->name);
4375 return xhci_get_timeout_no_hub_lpm(udev, state);
4376 }
4377 }
4378
4379 /* Not sure how this could happen... */
4380 if (!intf->cur_altsetting)
4381 continue;
4382
4383 if (xhci_update_timeout_for_interface(xhci, udev,
4384 intf->cur_altsetting,
4385 state, &timeout))
4386 return timeout;
4387 }
4388 return timeout;
4389 }
4390
4391 /*
4392 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4393 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4394 */
4395 static int xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4396 struct usb_device *udev, u16 max_exit_latency)
4397 {
4398 struct xhci_virt_device *virt_dev;
4399 struct xhci_command *command;
4400 struct xhci_input_control_ctx *ctrl_ctx;
4401 struct xhci_slot_ctx *slot_ctx;
4402 unsigned long flags;
4403 int ret;
4404
4405 spin_lock_irqsave(&xhci->lock, flags);
4406 if (max_exit_latency == xhci->devs[udev->slot_id]->current_mel) {
4407 spin_unlock_irqrestore(&xhci->lock, flags);
4408 return 0;
4409 }
4410
4411 /* Attempt to issue an Evaluate Context command to change the MEL. */
4412 virt_dev = xhci->devs[udev->slot_id];
4413 command = xhci->lpm_command;
4414 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4415 spin_unlock_irqrestore(&xhci->lock, flags);
4416
4417 ctrl_ctx = xhci_get_input_control_ctx(xhci, command->in_ctx);
4418 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4419 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4420 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4421 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4422
4423 xhci_dbg(xhci, "Set up evaluate context for LPM MEL change.\n");
4424 xhci_dbg(xhci, "Slot %u Input Context:\n", udev->slot_id);
4425 xhci_dbg_ctx(xhci, command->in_ctx, 0);
4426
4427 /* Issue and wait for the evaluate context command. */
4428 ret = xhci_configure_endpoint(xhci, udev, command,
4429 true, true);
4430 xhci_dbg(xhci, "Slot %u Output Context:\n", udev->slot_id);
4431 xhci_dbg_ctx(xhci, virt_dev->out_ctx, 0);
4432
4433 if (!ret) {
4434 spin_lock_irqsave(&xhci->lock, flags);
4435 virt_dev->current_mel = max_exit_latency;
4436 spin_unlock_irqrestore(&xhci->lock, flags);
4437 }
4438 return ret;
4439 }
4440
4441 static int calculate_max_exit_latency(struct usb_device *udev,
4442 enum usb3_link_state state_changed,
4443 u16 hub_encoded_timeout)
4444 {
4445 unsigned long long u1_mel_us = 0;
4446 unsigned long long u2_mel_us = 0;
4447 unsigned long long mel_us = 0;
4448 bool disabling_u1;
4449 bool disabling_u2;
4450 bool enabling_u1;
4451 bool enabling_u2;
4452
4453 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4454 hub_encoded_timeout == USB3_LPM_DISABLED);
4455 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4456 hub_encoded_timeout == USB3_LPM_DISABLED);
4457
4458 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4459 hub_encoded_timeout != USB3_LPM_DISABLED);
4460 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4461 hub_encoded_timeout != USB3_LPM_DISABLED);
4462
4463 /* If U1 was already enabled and we're not disabling it,
4464 * or we're going to enable U1, account for the U1 max exit latency.
4465 */
4466 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4467 enabling_u1)
4468 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4469 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4470 enabling_u2)
4471 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4472
4473 if (u1_mel_us > u2_mel_us)
4474 mel_us = u1_mel_us;
4475 else
4476 mel_us = u2_mel_us;
4477 /* xHCI host controller max exit latency field is only 16 bits wide. */
4478 if (mel_us > MAX_EXIT) {
4479 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4480 "is too big.\n", mel_us);
4481 return -E2BIG;
4482 }
4483 return mel_us;
4484 }
4485
4486 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4487 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4488 struct usb_device *udev, enum usb3_link_state state)
4489 {
4490 struct xhci_hcd *xhci;
4491 u16 hub_encoded_timeout;
4492 int mel;
4493 int ret;
4494
4495 xhci = hcd_to_xhci(hcd);
4496 /* The LPM timeout values are pretty host-controller specific, so don't
4497 * enable hub-initiated timeouts unless the vendor has provided
4498 * information about their timeout algorithm.
4499 */
4500 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4501 !xhci->devs[udev->slot_id])
4502 return USB3_LPM_DISABLED;
4503
4504 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4505 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4506 if (mel < 0) {
4507 /* Max Exit Latency is too big, disable LPM. */
4508 hub_encoded_timeout = USB3_LPM_DISABLED;
4509 mel = 0;
4510 }
4511
4512 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4513 if (ret)
4514 return ret;
4515 return hub_encoded_timeout;
4516 }
4517
4518 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4519 struct usb_device *udev, enum usb3_link_state state)
4520 {
4521 struct xhci_hcd *xhci;
4522 u16 mel;
4523 int ret;
4524
4525 xhci = hcd_to_xhci(hcd);
4526 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4527 !xhci->devs[udev->slot_id])
4528 return 0;
4529
4530 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4531 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4532 if (ret)
4533 return ret;
4534 return 0;
4535 }
4536 #else /* CONFIG_PM */
4537
4538 int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4539 struct usb_device *udev, enum usb3_link_state state)
4540 {
4541 return USB3_LPM_DISABLED;
4542 }
4543
4544 int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4545 struct usb_device *udev, enum usb3_link_state state)
4546 {
4547 return 0;
4548 }
4549 #endif /* CONFIG_PM */
4550
4551 /*-------------------------------------------------------------------------*/
4552
4553 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4554 * internal data structures for the device.
4555 */
4556 int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4557 struct usb_tt *tt, gfp_t mem_flags)
4558 {
4559 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4560 struct xhci_virt_device *vdev;
4561 struct xhci_command *config_cmd;
4562 struct xhci_input_control_ctx *ctrl_ctx;
4563 struct xhci_slot_ctx *slot_ctx;
4564 unsigned long flags;
4565 unsigned think_time;
4566 int ret;
4567
4568 /* Ignore root hubs */
4569 if (!hdev->parent)
4570 return 0;
4571
4572 vdev = xhci->devs[hdev->slot_id];
4573 if (!vdev) {
4574 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4575 return -EINVAL;
4576 }
4577 config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
4578 if (!config_cmd) {
4579 xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
4580 return -ENOMEM;
4581 }
4582
4583 spin_lock_irqsave(&xhci->lock, flags);
4584 if (hdev->speed == USB_SPEED_HIGH &&
4585 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4586 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4587 xhci_free_command(xhci, config_cmd);
4588 spin_unlock_irqrestore(&xhci->lock, flags);
4589 return -ENOMEM;
4590 }
4591
4592 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4593 ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
4594 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4595 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4596 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4597 if (tt->multi)
4598 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4599 if (xhci->hci_version > 0x95) {
4600 xhci_dbg(xhci, "xHCI version %x needs hub "
4601 "TT think time and number of ports\n",
4602 (unsigned int) xhci->hci_version);
4603 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4604 /* Set TT think time - convert from ns to FS bit times.
4605 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4606 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4607 *
4608 * xHCI 1.0: this field shall be 0 if the device is not a
4609 * High-spped hub.
4610 */
4611 think_time = tt->think_time;
4612 if (think_time != 0)
4613 think_time = (think_time / 666) - 1;
4614 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4615 slot_ctx->tt_info |=
4616 cpu_to_le32(TT_THINK_TIME(think_time));
4617 } else {
4618 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4619 "TT think time or number of ports\n",
4620 (unsigned int) xhci->hci_version);
4621 }
4622 slot_ctx->dev_state = 0;
4623 spin_unlock_irqrestore(&xhci->lock, flags);
4624
4625 xhci_dbg(xhci, "Set up %s for hub device.\n",
4626 (xhci->hci_version > 0x95) ?
4627 "configure endpoint" : "evaluate context");
4628 xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
4629 xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
4630
4631 /* Issue and wait for the configure endpoint or
4632 * evaluate context command.
4633 */
4634 if (xhci->hci_version > 0x95)
4635 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4636 false, false);
4637 else
4638 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4639 true, false);
4640
4641 xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
4642 xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
4643
4644 xhci_free_command(xhci, config_cmd);
4645 return ret;
4646 }
4647
4648 int xhci_get_frame(struct usb_hcd *hcd)
4649 {
4650 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4651 /* EHCI mods by the periodic size. Why? */
4652 return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
4653 }
4654
4655 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4656 {
4657 struct xhci_hcd *xhci;
4658 struct device *dev = hcd->self.controller;
4659 int retval;
4660 u32 temp;
4661
4662 /* Accept arbitrarily long scatter-gather lists */
4663 hcd->self.sg_tablesize = ~0;
4664 /* XHCI controllers don't stop the ep queue on short packets :| */
4665 hcd->self.no_stop_on_short = 1;
4666
4667 if (usb_hcd_is_primary_hcd(hcd)) {
4668 xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
4669 if (!xhci)
4670 return -ENOMEM;
4671 *((struct xhci_hcd **) hcd->hcd_priv) = xhci;
4672 xhci->main_hcd = hcd;
4673 /* Mark the first roothub as being USB 2.0.
4674 * The xHCI driver will register the USB 3.0 roothub.
4675 */
4676 hcd->speed = HCD_USB2;
4677 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4678 /*
4679 * USB 2.0 roothub under xHCI has an integrated TT,
4680 * (rate matching hub) as opposed to having an OHCI/UHCI
4681 * companion controller.
4682 */
4683 hcd->has_tt = 1;
4684 } else {
4685 /* xHCI private pointer was set in xhci_pci_probe for the second
4686 * registered roothub.
4687 */
4688 xhci = hcd_to_xhci(hcd);
4689 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4690 if (HCC_64BIT_ADDR(temp)) {
4691 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4692 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4693 } else {
4694 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4695 }
4696 return 0;
4697 }
4698
4699 xhci->cap_regs = hcd->regs;
4700 xhci->op_regs = hcd->regs +
4701 HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
4702 xhci->run_regs = hcd->regs +
4703 (xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
4704 /* Cache read-only capability registers */
4705 xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
4706 xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
4707 xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
4708 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
4709 xhci->hci_version = HC_VERSION(xhci->hcc_params);
4710 xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4711 xhci_print_registers(xhci);
4712
4713 get_quirks(dev, xhci);
4714
4715 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
4716 * success event after a short transfer. This quirk will ignore such
4717 * spurious event.
4718 */
4719 if (xhci->hci_version > 0x96)
4720 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
4721
4722 /* Make sure the HC is halted. */
4723 retval = xhci_halt(xhci);
4724 if (retval)
4725 goto error;
4726
4727 xhci_dbg(xhci, "Resetting HCD\n");
4728 /* Reset the internal HC memory state and registers. */
4729 retval = xhci_reset(xhci);
4730 if (retval)
4731 goto error;
4732 xhci_dbg(xhci, "Reset complete\n");
4733
4734 temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
4735 if (HCC_64BIT_ADDR(temp)) {
4736 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
4737 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
4738 } else {
4739 dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
4740 }
4741
4742 xhci_dbg(xhci, "Calling HCD init\n");
4743 /* Initialize HCD and host controller data structures. */
4744 retval = xhci_init(hcd);
4745 if (retval)
4746 goto error;
4747 xhci_dbg(xhci, "Called HCD init\n");
4748 return 0;
4749 error:
4750 kfree(xhci);
4751 return retval;
4752 }
4753
4754 MODULE_DESCRIPTION(DRIVER_DESC);
4755 MODULE_AUTHOR(DRIVER_AUTHOR);
4756 MODULE_LICENSE("GPL");
4757
4758 static int __init xhci_hcd_init(void)
4759 {
4760 int retval;
4761
4762 retval = xhci_register_pci();
4763 if (retval < 0) {
4764 printk(KERN_DEBUG "Problem registering PCI driver.");
4765 return retval;
4766 }
4767 retval = xhci_register_plat();
4768 if (retval < 0) {
4769 printk(KERN_DEBUG "Problem registering platform driver.");
4770 goto unreg_pci;
4771 }
4772 /*
4773 * Check the compiler generated sizes of structures that must be laid
4774 * out in specific ways for hardware access.
4775 */
4776 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
4777 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
4778 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
4779 /* xhci_device_control has eight fields, and also
4780 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
4781 */
4782 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
4783 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
4784 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
4785 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
4786 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
4787 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
4788 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
4789 return 0;
4790 unreg_pci:
4791 xhci_unregister_pci();
4792 return retval;
4793 }
4794 module_init(xhci_hcd_init);
4795
4796 static void __exit xhci_hcd_cleanup(void)
4797 {
4798 xhci_unregister_pci();
4799 xhci_unregister_plat();
4800 }
4801 module_exit(xhci_hcd_cleanup);