2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
119 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
121 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
122 return TRB_TYPE_LINK_LE32(link
->control
);
125 union xhci_trb
*xhci_find_next_enqueue(struct xhci_ring
*ring
)
127 /* Enqueue pointer can be left pointing to the link TRB,
128 * we must handle that
130 if (TRB_TYPE_LINK_LE32(ring
->enqueue
->link
.control
))
131 return ring
->enq_seg
->next
->trbs
;
132 return ring
->enqueue
;
135 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
136 * TRB is in a new segment. This does not skip over link TRBs, and it does not
137 * effect the ring dequeue or enqueue pointers.
139 static void next_trb(struct xhci_hcd
*xhci
,
140 struct xhci_ring
*ring
,
141 struct xhci_segment
**seg
,
142 union xhci_trb
**trb
)
144 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
146 *trb
= ((*seg
)->trbs
);
153 * See Cycle bit rules. SW is the consumer for the event ring only.
154 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
156 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
158 unsigned long long addr
;
163 * If this is not event ring, and the dequeue pointer
164 * is not on a link TRB, there is one more usable TRB
166 if (ring
->type
!= TYPE_EVENT
&&
167 !last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
))
168 ring
->num_trbs_free
++;
172 * Update the dequeue pointer further if that was a link TRB or
173 * we're at the end of an event ring segment (which doesn't have
176 if (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
)) {
177 if (ring
->type
== TYPE_EVENT
&&
178 last_trb_on_last_seg(xhci
, ring
,
179 ring
->deq_seg
, ring
->dequeue
)) {
180 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
182 ring
->deq_seg
= ring
->deq_seg
->next
;
183 ring
->dequeue
= ring
->deq_seg
->trbs
;
187 } while (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
));
189 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
193 * See Cycle bit rules. SW is the consumer for the event ring only.
194 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
196 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
197 * chain bit is set), then set the chain bit in all the following link TRBs.
198 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
199 * have their chain bit cleared (so that each Link TRB is a separate TD).
201 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
202 * set, but other sections talk about dealing with the chain bit set. This was
203 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
204 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
206 * @more_trbs_coming: Will you enqueue more TRBs before calling
207 * prepare_transfer()?
209 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
210 bool more_trbs_coming
)
213 union xhci_trb
*next
;
214 unsigned long long addr
;
216 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
217 /* If this is not event ring, there is one less usable TRB */
218 if (ring
->type
!= TYPE_EVENT
&&
219 !last_trb(xhci
, ring
, ring
->enq_seg
, ring
->enqueue
))
220 ring
->num_trbs_free
--;
221 next
= ++(ring
->enqueue
);
224 /* Update the dequeue pointer further if that was a link TRB or we're at
225 * the end of an event ring segment (which doesn't have link TRBS)
227 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
228 if (ring
->type
!= TYPE_EVENT
) {
230 * If the caller doesn't plan on enqueueing more
231 * TDs before ringing the doorbell, then we
232 * don't want to give the link TRB to the
233 * hardware just yet. We'll give the link TRB
234 * back in prepare_ring() just before we enqueue
235 * the TD at the top of the ring.
237 if (!chain
&& !more_trbs_coming
)
240 /* If we're not dealing with 0.95 hardware or
241 * isoc rings on AMD 0.96 host,
242 * carry over the chain bit of the previous TRB
243 * (which may mean the chain bit is cleared).
245 if (!(ring
->type
== TYPE_ISOC
&&
246 (xhci
->quirks
& XHCI_AMD_0x96_HOST
))
247 && !xhci_link_trb_quirk(xhci
)) {
248 next
->link
.control
&=
249 cpu_to_le32(~TRB_CHAIN
);
250 next
->link
.control
|=
253 /* Give this link TRB to the hardware */
255 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
257 /* Toggle the cycle bit after the last ring segment. */
258 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
259 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
262 ring
->enq_seg
= ring
->enq_seg
->next
;
263 ring
->enqueue
= ring
->enq_seg
->trbs
;
264 next
= ring
->enqueue
;
266 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
270 * Check to see if there's room to enqueue num_trbs on the ring and make sure
271 * enqueue pointer will not advance into dequeue segment. See rules above.
273 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
274 unsigned int num_trbs
)
276 int num_trbs_in_deq_seg
;
278 if (ring
->num_trbs_free
< num_trbs
)
281 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
282 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
283 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
290 /* Ring the host controller doorbell after placing a command on the ring */
291 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
293 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
296 xhci_dbg(xhci
, "// Ding dong!\n");
297 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
298 /* Flush PCI posted writes */
299 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
302 static int xhci_abort_cmd_ring(struct xhci_hcd
*xhci
)
307 xhci_dbg(xhci
, "Abort command ring\n");
309 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
)) {
310 xhci_dbg(xhci
, "The command ring isn't running, "
311 "Have the command ring been stopped?\n");
315 temp_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
316 if (!(temp_64
& CMD_RING_RUNNING
)) {
317 xhci_dbg(xhci
, "Command ring had been stopped\n");
320 xhci
->cmd_ring_state
= CMD_RING_STATE_ABORTED
;
321 xhci_write_64(xhci
, temp_64
| CMD_RING_ABORT
,
322 &xhci
->op_regs
->cmd_ring
);
324 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
325 * time the completion od all xHCI commands, including
326 * the Command Abort operation. If software doesn't see
327 * CRR negated in a timely manner (e.g. longer than 5
328 * seconds), then it should assume that the there are
329 * larger problems with the xHC and assert HCRST.
331 ret
= xhci_handshake(xhci
, &xhci
->op_regs
->cmd_ring
,
332 CMD_RING_RUNNING
, 0, 5 * 1000 * 1000);
334 xhci_err(xhci
, "Stopped the command ring failed, "
335 "maybe the host is dead\n");
336 xhci
->xhc_state
|= XHCI_STATE_DYING
;
345 static int xhci_queue_cd(struct xhci_hcd
*xhci
,
346 struct xhci_command
*command
,
347 union xhci_trb
*cmd_trb
)
350 cd
= kzalloc(sizeof(struct xhci_cd
), GFP_ATOMIC
);
353 INIT_LIST_HEAD(&cd
->cancel_cmd_list
);
355 cd
->command
= command
;
356 cd
->cmd_trb
= cmd_trb
;
357 list_add_tail(&cd
->cancel_cmd_list
, &xhci
->cancel_cmd_list
);
363 * Cancel the command which has issue.
365 * Some commands may hang due to waiting for acknowledgement from
366 * usb device. It is outside of the xHC's ability to control and
367 * will cause the command ring is blocked. When it occurs software
368 * should intervene to recover the command ring.
369 * See Section 4.6.1.1 and 4.6.1.2
371 int xhci_cancel_cmd(struct xhci_hcd
*xhci
, struct xhci_command
*command
,
372 union xhci_trb
*cmd_trb
)
377 spin_lock_irqsave(&xhci
->lock
, flags
);
379 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
380 xhci_warn(xhci
, "Abort the command ring,"
381 " but the xHCI is dead.\n");
386 /* queue the cmd desriptor to cancel_cmd_list */
387 retval
= xhci_queue_cd(xhci
, command
, cmd_trb
);
389 xhci_warn(xhci
, "Queuing command descriptor failed.\n");
393 /* abort command ring */
394 retval
= xhci_abort_cmd_ring(xhci
);
396 xhci_err(xhci
, "Abort command ring failed\n");
397 if (unlikely(retval
== -ESHUTDOWN
)) {
398 spin_unlock_irqrestore(&xhci
->lock
, flags
);
399 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
400 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
406 spin_unlock_irqrestore(&xhci
->lock
, flags
);
410 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
411 unsigned int slot_id
,
412 unsigned int ep_index
,
413 unsigned int stream_id
)
415 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
416 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
417 unsigned int ep_state
= ep
->ep_state
;
419 /* Don't ring the doorbell for this endpoint if there are pending
420 * cancellations because we don't want to interrupt processing.
421 * We don't want to restart any stream rings if there's a set dequeue
422 * pointer command pending because the device can choose to start any
423 * stream once the endpoint is on the HW schedule.
424 * FIXME - check all the stream rings for pending cancellations.
426 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
427 (ep_state
& EP_HALTED
))
429 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
430 /* The CPU has better things to do at this point than wait for a
431 * write-posting flush. It'll get there soon enough.
435 /* Ring the doorbell for any rings with pending URBs */
436 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
437 unsigned int slot_id
,
438 unsigned int ep_index
)
440 unsigned int stream_id
;
441 struct xhci_virt_ep
*ep
;
443 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
445 /* A ring has pending URBs if its TD list is not empty */
446 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
447 if (ep
->ring
&& !(list_empty(&ep
->ring
->td_list
)))
448 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
452 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
454 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
455 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
456 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
462 * Find the segment that trb is in. Start searching in start_seg.
463 * If we must move past a segment that has a link TRB with a toggle cycle state
464 * bit set, then we will toggle the value pointed at by cycle_state.
466 static struct xhci_segment
*find_trb_seg(
467 struct xhci_segment
*start_seg
,
468 union xhci_trb
*trb
, int *cycle_state
)
470 struct xhci_segment
*cur_seg
= start_seg
;
471 struct xhci_generic_trb
*generic_trb
;
473 while (cur_seg
->trbs
> trb
||
474 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
475 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
476 if (generic_trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
))
478 cur_seg
= cur_seg
->next
;
479 if (cur_seg
== start_seg
)
480 /* Looped over the entire list. Oops! */
487 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
488 unsigned int slot_id
, unsigned int ep_index
,
489 unsigned int stream_id
)
491 struct xhci_virt_ep
*ep
;
493 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
494 /* Common case: no streams */
495 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
498 if (stream_id
== 0) {
500 "WARN: Slot ID %u, ep index %u has streams, "
501 "but URB has no stream ID.\n",
506 if (stream_id
< ep
->stream_info
->num_streams
)
507 return ep
->stream_info
->stream_rings
[stream_id
];
510 "WARN: Slot ID %u, ep index %u has "
511 "stream IDs 1 to %u allocated, "
512 "but stream ID %u is requested.\n",
514 ep
->stream_info
->num_streams
- 1,
519 /* Get the right ring for the given URB.
520 * If the endpoint supports streams, boundary check the URB's stream ID.
521 * If the endpoint doesn't support streams, return the singular endpoint ring.
523 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
526 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
527 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
531 * Move the xHC's endpoint ring dequeue pointer past cur_td.
532 * Record the new state of the xHC's endpoint ring dequeue segment,
533 * dequeue pointer, and new consumer cycle state in state.
534 * Update our internal representation of the ring's dequeue pointer.
536 * We do this in three jumps:
537 * - First we update our new ring state to be the same as when the xHC stopped.
538 * - Then we traverse the ring to find the segment that contains
539 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
540 * any link TRBs with the toggle cycle bit set.
541 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
542 * if we've moved it past a link TRB with the toggle cycle bit set.
544 * Some of the uses of xhci_generic_trb are grotty, but if they're done
545 * with correct __le32 accesses they should work fine. Only users of this are
548 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
549 unsigned int slot_id
, unsigned int ep_index
,
550 unsigned int stream_id
, struct xhci_td
*cur_td
,
551 struct xhci_dequeue_state
*state
)
553 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
554 struct xhci_ring
*ep_ring
;
555 struct xhci_generic_trb
*trb
;
556 struct xhci_ep_ctx
*ep_ctx
;
559 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
560 ep_index
, stream_id
);
562 xhci_warn(xhci
, "WARN can't find new dequeue state "
563 "for invalid stream ID %u.\n",
567 state
->new_cycle_state
= 0;
568 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
569 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
570 dev
->eps
[ep_index
].stopped_trb
,
571 &state
->new_cycle_state
);
572 if (!state
->new_deq_seg
) {
577 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
578 xhci_dbg(xhci
, "Finding endpoint context\n");
579 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
580 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
582 state
->new_deq_ptr
= cur_td
->last_trb
;
583 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
584 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
586 &state
->new_cycle_state
);
587 if (!state
->new_deq_seg
) {
592 trb
= &state
->new_deq_ptr
->generic
;
593 if (TRB_TYPE_LINK_LE32(trb
->field
[3]) &&
594 (trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
)))
595 state
->new_cycle_state
^= 0x1;
596 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
599 * If there is only one segment in a ring, find_trb_seg()'s while loop
600 * will not run, and it will return before it has a chance to see if it
601 * needs to toggle the cycle bit. It can't tell if the stalled transfer
602 * ended just before the link TRB on a one-segment ring, or if the TD
603 * wrapped around the top of the ring, because it doesn't have the TD in
604 * question. Look for the one-segment case where stalled TRB's address
605 * is greater than the new dequeue pointer address.
607 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
608 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
609 state
->new_cycle_state
^= 0x1;
610 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
612 /* Don't update the ring cycle state for the producer (us). */
613 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
615 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
616 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
617 (unsigned long long) addr
);
620 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
621 * (The last TRB actually points to the ring enqueue pointer, which is not part
622 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
624 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
625 struct xhci_td
*cur_td
, bool flip_cycle
)
627 struct xhci_segment
*cur_seg
;
628 union xhci_trb
*cur_trb
;
630 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
632 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
633 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
634 /* Unchain any chained Link TRBs, but
635 * leave the pointers intact.
637 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
638 /* Flip the cycle bit (link TRBs can't be the first
642 cur_trb
->generic
.field
[3] ^=
643 cpu_to_le32(TRB_CYCLE
);
644 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
645 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
646 "in seg %p (0x%llx dma)\n",
648 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
650 (unsigned long long)cur_seg
->dma
);
652 cur_trb
->generic
.field
[0] = 0;
653 cur_trb
->generic
.field
[1] = 0;
654 cur_trb
->generic
.field
[2] = 0;
655 /* Preserve only the cycle bit of this TRB */
656 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
657 /* Flip the cycle bit except on the first or last TRB */
658 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
659 cur_trb
!= cur_td
->last_trb
)
660 cur_trb
->generic
.field
[3] ^=
661 cpu_to_le32(TRB_CYCLE
);
662 cur_trb
->generic
.field
[3] |= cpu_to_le32(
663 TRB_TYPE(TRB_TR_NOOP
));
664 xhci_dbg(xhci
, "TRB to noop at offset 0x%llx\n",
666 xhci_trb_virt_to_dma(cur_seg
, cur_trb
));
668 if (cur_trb
== cur_td
->last_trb
)
673 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
674 unsigned int ep_index
, unsigned int stream_id
,
675 struct xhci_segment
*deq_seg
,
676 union xhci_trb
*deq_ptr
, u32 cycle_state
);
678 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
679 unsigned int slot_id
, unsigned int ep_index
,
680 unsigned int stream_id
,
681 struct xhci_dequeue_state
*deq_state
)
683 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
685 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
686 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
687 deq_state
->new_deq_seg
,
688 (unsigned long long)deq_state
->new_deq_seg
->dma
,
689 deq_state
->new_deq_ptr
,
690 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
691 deq_state
->new_cycle_state
);
692 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
693 deq_state
->new_deq_seg
,
694 deq_state
->new_deq_ptr
,
695 (u32
) deq_state
->new_cycle_state
);
696 /* Stop the TD queueing code from ringing the doorbell until
697 * this command completes. The HC won't set the dequeue pointer
698 * if the ring is running, and ringing the doorbell starts the
701 ep
->ep_state
|= SET_DEQ_PENDING
;
704 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
705 struct xhci_virt_ep
*ep
)
707 ep
->ep_state
&= ~EP_HALT_PENDING
;
708 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
709 * timer is running on another CPU, we don't decrement stop_cmds_pending
710 * (since we didn't successfully stop the watchdog timer).
712 if (del_timer(&ep
->stop_cmd_timer
))
713 ep
->stop_cmds_pending
--;
716 /* Must be called with xhci->lock held in interrupt context */
717 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
718 struct xhci_td
*cur_td
, int status
, char *adjective
)
722 struct urb_priv
*urb_priv
;
725 urb_priv
= urb
->hcpriv
;
727 hcd
= bus_to_hcd(urb
->dev
->bus
);
729 /* Only giveback urb when this is the last td in urb */
730 if (urb_priv
->td_cnt
== urb_priv
->length
) {
731 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
732 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
733 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
734 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
735 usb_amd_quirk_pll_enable();
738 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
740 spin_unlock(&xhci
->lock
);
741 usb_hcd_giveback_urb(hcd
, urb
, status
);
742 xhci_urb_free_priv(xhci
, urb_priv
);
743 spin_lock(&xhci
->lock
);
748 * When we get a command completion for a Stop Endpoint Command, we need to
749 * unlink any cancelled TDs from the ring. There are two ways to do that:
751 * 1. If the HW was in the middle of processing the TD that needs to be
752 * cancelled, then we must move the ring's dequeue pointer past the last TRB
753 * in the TD with a Set Dequeue Pointer Command.
754 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
755 * bit cleared) so that the HW will skip over them.
757 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
758 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
760 unsigned int slot_id
;
761 unsigned int ep_index
;
762 struct xhci_virt_device
*virt_dev
;
763 struct xhci_ring
*ep_ring
;
764 struct xhci_virt_ep
*ep
;
765 struct list_head
*entry
;
766 struct xhci_td
*cur_td
= NULL
;
767 struct xhci_td
*last_unlinked_td
;
769 struct xhci_dequeue_state deq_state
;
771 if (unlikely(TRB_TO_SUSPEND_PORT(
772 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
773 slot_id
= TRB_TO_SLOT_ID(
774 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
775 virt_dev
= xhci
->devs
[slot_id
];
777 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
780 xhci_warn(xhci
, "Stop endpoint command "
781 "completion for disabled slot %u\n",
786 memset(&deq_state
, 0, sizeof(deq_state
));
787 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
788 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
789 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
791 if (list_empty(&ep
->cancelled_td_list
)) {
792 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
793 ep
->stopped_td
= NULL
;
794 ep
->stopped_trb
= NULL
;
795 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
799 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
800 * We have the xHCI lock, so nothing can modify this list until we drop
801 * it. We're also in the event handler, so we can't get re-interrupted
802 * if another Stop Endpoint command completes
804 list_for_each(entry
, &ep
->cancelled_td_list
) {
805 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
806 xhci_dbg(xhci
, "Removing canceled TD starting at 0x%llx (dma).\n",
807 (unsigned long long)xhci_trb_virt_to_dma(
808 cur_td
->start_seg
, cur_td
->first_trb
));
809 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
811 /* This shouldn't happen unless a driver is mucking
812 * with the stream ID after submission. This will
813 * leave the TD on the hardware ring, and the hardware
814 * will try to execute it, and may access a buffer
815 * that has already been freed. In the best case, the
816 * hardware will execute it, and the event handler will
817 * ignore the completion event for that TD, since it was
818 * removed from the td_list for that endpoint. In
819 * short, don't muck with the stream ID after
822 xhci_warn(xhci
, "WARN Cancelled URB %p "
823 "has invalid stream ID %u.\n",
825 cur_td
->urb
->stream_id
);
826 goto remove_finished_td
;
829 * If we stopped on the TD we need to cancel, then we have to
830 * move the xHC endpoint ring dequeue pointer past this TD.
832 if (cur_td
== ep
->stopped_td
)
833 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
834 cur_td
->urb
->stream_id
,
837 td_to_noop(xhci
, ep_ring
, cur_td
, false);
840 * The event handler won't see a completion for this TD anymore,
841 * so remove it from the endpoint ring's TD list. Keep it in
842 * the cancelled TD list for URB completion later.
844 list_del_init(&cur_td
->td_list
);
846 last_unlinked_td
= cur_td
;
847 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
849 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
850 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
851 xhci_queue_new_dequeue_state(xhci
,
853 ep
->stopped_td
->urb
->stream_id
,
855 xhci_ring_cmd_db(xhci
);
857 /* Otherwise ring the doorbell(s) to restart queued transfers */
858 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
861 /* Clear stopped_td and stopped_trb if endpoint is not halted */
862 if (!(ep
->ep_state
& EP_HALTED
)) {
863 ep
->stopped_td
= NULL
;
864 ep
->stopped_trb
= NULL
;
868 * Drop the lock and complete the URBs in the cancelled TD list.
869 * New TDs to be cancelled might be added to the end of the list before
870 * we can complete all the URBs for the TDs we already unlinked.
871 * So stop when we've completed the URB for the last TD we unlinked.
874 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
875 struct xhci_td
, cancelled_td_list
);
876 list_del_init(&cur_td
->cancelled_td_list
);
878 /* Clean up the cancelled URB */
879 /* Doesn't matter what we pass for status, since the core will
880 * just overwrite it (because the URB has been unlinked).
882 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
884 /* Stop processing the cancelled list if the watchdog timer is
887 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
889 } while (cur_td
!= last_unlinked_td
);
891 /* Return to the event handler with xhci->lock re-acquired */
894 /* Watchdog timer function for when a stop endpoint command fails to complete.
895 * In this case, we assume the host controller is broken or dying or dead. The
896 * host may still be completing some other events, so we have to be careful to
897 * let the event ring handler and the URB dequeueing/enqueueing functions know
898 * through xhci->state.
900 * The timer may also fire if the host takes a very long time to respond to the
901 * command, and the stop endpoint command completion handler cannot delete the
902 * timer before the timer function is called. Another endpoint cancellation may
903 * sneak in before the timer function can grab the lock, and that may queue
904 * another stop endpoint command and add the timer back. So we cannot use a
905 * simple flag to say whether there is a pending stop endpoint command for a
906 * particular endpoint.
908 * Instead we use a combination of that flag and a counter for the number of
909 * pending stop endpoint commands. If the timer is the tail end of the last
910 * stop endpoint command, and the endpoint's command is still pending, we assume
913 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
915 struct xhci_hcd
*xhci
;
916 struct xhci_virt_ep
*ep
;
917 struct xhci_virt_ep
*temp_ep
;
918 struct xhci_ring
*ring
;
919 struct xhci_td
*cur_td
;
923 ep
= (struct xhci_virt_ep
*) arg
;
926 spin_lock_irqsave(&xhci
->lock
, flags
);
928 ep
->stop_cmds_pending
--;
929 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
930 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
931 "xHCI as DYING, exiting.\n");
932 spin_unlock_irqrestore(&xhci
->lock
, flags
);
935 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
936 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
938 spin_unlock_irqrestore(&xhci
->lock
, flags
);
942 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
943 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
944 /* Oops, HC is dead or dying or at least not responding to the stop
947 xhci
->xhc_state
|= XHCI_STATE_DYING
;
948 /* Disable interrupts from the host controller and start halting it */
950 spin_unlock_irqrestore(&xhci
->lock
, flags
);
952 ret
= xhci_halt(xhci
);
954 spin_lock_irqsave(&xhci
->lock
, flags
);
956 /* This is bad; the host is not responding to commands and it's
957 * not allowing itself to be halted. At least interrupts are
958 * disabled. If we call usb_hc_died(), it will attempt to
959 * disconnect all device drivers under this host. Those
960 * disconnect() methods will wait for all URBs to be unlinked,
961 * so we must complete them.
963 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
964 xhci_warn(xhci
, "Completing active URBs anyway.\n");
965 /* We could turn all TDs on the rings to no-ops. This won't
966 * help if the host has cached part of the ring, and is slow if
967 * we want to preserve the cycle bit. Skip it and hope the host
968 * doesn't touch the memory.
971 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
974 for (j
= 0; j
< 31; j
++) {
975 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
976 ring
= temp_ep
->ring
;
979 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
980 "ep index %u\n", i
, j
);
981 while (!list_empty(&ring
->td_list
)) {
982 cur_td
= list_first_entry(&ring
->td_list
,
985 list_del_init(&cur_td
->td_list
);
986 if (!list_empty(&cur_td
->cancelled_td_list
))
987 list_del_init(&cur_td
->cancelled_td_list
);
988 xhci_giveback_urb_in_irq(xhci
, cur_td
,
989 -ESHUTDOWN
, "killed");
991 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
992 cur_td
= list_first_entry(
993 &temp_ep
->cancelled_td_list
,
996 list_del_init(&cur_td
->cancelled_td_list
);
997 xhci_giveback_urb_in_irq(xhci
, cur_td
,
998 -ESHUTDOWN
, "killed");
1002 spin_unlock_irqrestore(&xhci
->lock
, flags
);
1003 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
1004 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
1005 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
1009 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
1010 struct xhci_virt_device
*dev
,
1011 struct xhci_ring
*ep_ring
,
1012 unsigned int ep_index
)
1014 union xhci_trb
*dequeue_temp
;
1015 int num_trbs_free_temp
;
1016 bool revert
= false;
1018 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
1019 dequeue_temp
= ep_ring
->dequeue
;
1021 /* If we get two back-to-back stalls, and the first stalled transfer
1022 * ends just before a link TRB, the dequeue pointer will be left on
1023 * the link TRB by the code in the while loop. So we have to update
1024 * the dequeue pointer one segment further, or we'll jump off
1025 * the segment into la-la-land.
1027 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
, ep_ring
->dequeue
)) {
1028 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1029 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1032 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
1033 /* We have more usable TRBs */
1034 ep_ring
->num_trbs_free
++;
1036 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
,
1037 ep_ring
->dequeue
)) {
1038 if (ep_ring
->dequeue
==
1039 dev
->eps
[ep_index
].queued_deq_ptr
)
1041 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
1042 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
1044 if (ep_ring
->dequeue
== dequeue_temp
) {
1051 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
1052 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
1057 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1058 * we need to clear the set deq pending flag in the endpoint ring state, so that
1059 * the TD queueing code can ring the doorbell again. We also need to ring the
1060 * endpoint doorbell to restart the ring, but only if there aren't more
1061 * cancellations pending.
1063 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
1064 struct xhci_event_cmd
*event
,
1065 union xhci_trb
*trb
)
1067 unsigned int slot_id
;
1068 unsigned int ep_index
;
1069 unsigned int stream_id
;
1070 struct xhci_ring
*ep_ring
;
1071 struct xhci_virt_device
*dev
;
1072 struct xhci_ep_ctx
*ep_ctx
;
1073 struct xhci_slot_ctx
*slot_ctx
;
1075 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1076 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1077 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
1078 dev
= xhci
->devs
[slot_id
];
1080 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
1082 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
1083 "freed stream ID %u\n",
1085 /* XXX: Harmless??? */
1086 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1090 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
1091 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
1093 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
1094 unsigned int ep_state
;
1095 unsigned int slot_state
;
1097 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
1099 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
1100 "of stream ID configuration\n");
1102 case COMP_CTX_STATE
:
1103 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
1104 "to incorrect slot or ep state.\n");
1105 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
1106 ep_state
&= EP_STATE_MASK
;
1107 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
1108 slot_state
= GET_SLOT_STATE(slot_state
);
1109 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
1110 slot_state
, ep_state
);
1113 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
1114 "slot %u was not enabled.\n", slot_id
);
1117 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
1118 "completion code of %u.\n",
1119 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1122 /* OK what do we do now? The endpoint state is hosed, and we
1123 * should never get to this point if the synchronization between
1124 * queueing, and endpoint state are correct. This might happen
1125 * if the device gets disconnected after we've finished
1126 * cancelling URBs, which might not be an error...
1129 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1130 le64_to_cpu(ep_ctx
->deq
));
1131 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
1132 dev
->eps
[ep_index
].queued_deq_ptr
) ==
1133 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
1134 /* Update the ring's dequeue segment and dequeue pointer
1135 * to reflect the new position.
1137 update_ring_for_set_deq_completion(xhci
, dev
,
1140 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
1141 "Ptr command & xHCI internal state.\n");
1142 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1143 dev
->eps
[ep_index
].queued_deq_seg
,
1144 dev
->eps
[ep_index
].queued_deq_ptr
);
1148 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1149 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1150 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1151 /* Restart any rings with pending URBs */
1152 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1155 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1156 struct xhci_event_cmd
*event
,
1157 union xhci_trb
*trb
)
1160 unsigned int ep_index
;
1162 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1163 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1164 /* This command will only fail if the endpoint wasn't halted,
1165 * but we don't care.
1167 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1168 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1170 /* HW with the reset endpoint quirk needs to have a configure endpoint
1171 * command complete before the endpoint can be used. Queue that here
1172 * because the HW can't handle two commands being queued in a row.
1174 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1175 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1176 xhci_queue_configure_endpoint(xhci
,
1177 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1179 xhci_ring_cmd_db(xhci
);
1181 /* Clear our internal halted state */
1182 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1186 /* Complete the command and detele it from the devcie's command queue.
1188 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1189 struct xhci_command
*command
, u32 status
)
1191 command
->status
= status
;
1192 list_del(&command
->cmd_list
);
1193 if (command
->completion
)
1194 complete(command
->completion
);
1196 xhci_free_command(xhci
, command
);
1200 /* Check to see if a command in the device's command queue matches this one.
1201 * Signal the completion or free the command, and return 1. Return 0 if the
1202 * completed command isn't at the head of the command list.
1204 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1205 struct xhci_virt_device
*virt_dev
,
1206 struct xhci_event_cmd
*event
)
1208 struct xhci_command
*command
;
1210 if (list_empty(&virt_dev
->cmd_list
))
1213 command
= list_entry(virt_dev
->cmd_list
.next
,
1214 struct xhci_command
, cmd_list
);
1215 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1218 xhci_complete_cmd_in_cmd_wait_list(xhci
, command
,
1219 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1224 * Finding the command trb need to be cancelled and modifying it to
1225 * NO OP command. And if the command is in device's command wait
1226 * list, finishing and freeing it.
1228 * If we can't find the command trb, we think it had already been
1231 static void xhci_cmd_to_noop(struct xhci_hcd
*xhci
, struct xhci_cd
*cur_cd
)
1233 struct xhci_segment
*cur_seg
;
1234 union xhci_trb
*cmd_trb
;
1237 if (xhci
->cmd_ring
->dequeue
== xhci
->cmd_ring
->enqueue
)
1240 /* find the current segment of command ring */
1241 cur_seg
= find_trb_seg(xhci
->cmd_ring
->first_seg
,
1242 xhci
->cmd_ring
->dequeue
, &cycle_state
);
1245 xhci_warn(xhci
, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1246 xhci
->cmd_ring
->dequeue
,
1247 (unsigned long long)
1248 xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1249 xhci
->cmd_ring
->dequeue
));
1250 xhci_debug_ring(xhci
, xhci
->cmd_ring
);
1251 xhci_dbg_ring_ptrs(xhci
, xhci
->cmd_ring
);
1255 /* find the command trb matched by cd from command ring */
1256 for (cmd_trb
= xhci
->cmd_ring
->dequeue
;
1257 cmd_trb
!= xhci
->cmd_ring
->enqueue
;
1258 next_trb(xhci
, xhci
->cmd_ring
, &cur_seg
, &cmd_trb
)) {
1259 /* If the trb is link trb, continue */
1260 if (TRB_TYPE_LINK_LE32(cmd_trb
->generic
.field
[3]))
1263 if (cur_cd
->cmd_trb
== cmd_trb
) {
1265 /* If the command in device's command list, we should
1266 * finish it and free the command structure.
1268 if (cur_cd
->command
)
1269 xhci_complete_cmd_in_cmd_wait_list(xhci
,
1270 cur_cd
->command
, COMP_CMD_STOP
);
1272 /* get cycle state from the origin command trb */
1273 cycle_state
= le32_to_cpu(cmd_trb
->generic
.field
[3])
1276 /* modify the command trb to NO OP command */
1277 cmd_trb
->generic
.field
[0] = 0;
1278 cmd_trb
->generic
.field
[1] = 0;
1279 cmd_trb
->generic
.field
[2] = 0;
1280 cmd_trb
->generic
.field
[3] = cpu_to_le32(
1281 TRB_TYPE(TRB_CMD_NOOP
) | cycle_state
);
1287 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd
*xhci
)
1289 struct xhci_cd
*cur_cd
, *next_cd
;
1291 if (list_empty(&xhci
->cancel_cmd_list
))
1294 list_for_each_entry_safe(cur_cd
, next_cd
,
1295 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1296 xhci_cmd_to_noop(xhci
, cur_cd
);
1297 list_del(&cur_cd
->cancel_cmd_list
);
1303 * traversing the cancel_cmd_list. If the command descriptor according
1304 * to cmd_trb is found, the function free it and return 1, otherwise
1307 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd
*xhci
,
1308 union xhci_trb
*cmd_trb
)
1310 struct xhci_cd
*cur_cd
, *next_cd
;
1312 if (list_empty(&xhci
->cancel_cmd_list
))
1315 list_for_each_entry_safe(cur_cd
, next_cd
,
1316 &xhci
->cancel_cmd_list
, cancel_cmd_list
) {
1317 if (cur_cd
->cmd_trb
== cmd_trb
) {
1318 if (cur_cd
->command
)
1319 xhci_complete_cmd_in_cmd_wait_list(xhci
,
1320 cur_cd
->command
, COMP_CMD_STOP
);
1321 list_del(&cur_cd
->cancel_cmd_list
);
1331 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1332 * trb pointed by the command ring dequeue pointer is the trb we want to
1333 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1334 * traverse the cancel_cmd_list to trun the all of the commands according
1335 * to command descriptor to NO-OP trb.
1337 static int handle_stopped_cmd_ring(struct xhci_hcd
*xhci
,
1338 int cmd_trb_comp_code
)
1340 int cur_trb_is_good
= 0;
1342 /* Searching the cmd trb pointed by the command ring dequeue
1343 * pointer in command descriptor list. If it is found, free it.
1345 cur_trb_is_good
= xhci_search_cmd_trb_in_cd_list(xhci
,
1346 xhci
->cmd_ring
->dequeue
);
1348 if (cmd_trb_comp_code
== COMP_CMD_ABORT
)
1349 xhci
->cmd_ring_state
= CMD_RING_STATE_STOPPED
;
1350 else if (cmd_trb_comp_code
== COMP_CMD_STOP
) {
1351 /* traversing the cancel_cmd_list and canceling
1352 * the command according to command descriptor
1354 xhci_cancel_cmd_in_cd_list(xhci
);
1356 xhci
->cmd_ring_state
= CMD_RING_STATE_RUNNING
;
1358 * ring command ring doorbell again to restart the
1361 if (xhci
->cmd_ring
->dequeue
!= xhci
->cmd_ring
->enqueue
)
1362 xhci_ring_cmd_db(xhci
);
1364 return cur_trb_is_good
;
1367 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1368 struct xhci_event_cmd
*event
)
1370 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1372 dma_addr_t cmd_dequeue_dma
;
1373 struct xhci_input_control_ctx
*ctrl_ctx
;
1374 struct xhci_virt_device
*virt_dev
;
1375 unsigned int ep_index
;
1376 struct xhci_ring
*ep_ring
;
1377 unsigned int ep_state
;
1379 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1380 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1381 xhci
->cmd_ring
->dequeue
);
1382 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1383 if (cmd_dequeue_dma
== 0) {
1384 xhci
->error_bitmask
|= 1 << 4;
1387 /* Does the DMA address match our internal dequeue pointer address? */
1388 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1389 xhci
->error_bitmask
|= 1 << 5;
1393 if ((GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_CMD_ABORT
) ||
1394 (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_CMD_STOP
)) {
1395 /* If the return value is 0, we think the trb pointed by
1396 * command ring dequeue pointer is a good trb. The good
1397 * trb means we don't want to cancel the trb, but it have
1398 * been stopped by host. So we should handle it normally.
1399 * Otherwise, driver should invoke inc_deq() and return.
1401 if (handle_stopped_cmd_ring(xhci
,
1402 GET_COMP_CODE(le32_to_cpu(event
->status
)))) {
1403 inc_deq(xhci
, xhci
->cmd_ring
);
1406 /* There is no command to handle if we get a stop event when the
1407 * command ring is empty, event->cmd_trb points to the next
1410 if (xhci
->cmd_ring
->dequeue
== xhci
->cmd_ring
->enqueue
)
1414 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1415 & TRB_TYPE_BITMASK
) {
1416 case TRB_TYPE(TRB_ENABLE_SLOT
):
1417 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1418 xhci
->slot_id
= slot_id
;
1421 complete(&xhci
->addr_dev
);
1423 case TRB_TYPE(TRB_DISABLE_SLOT
):
1424 if (xhci
->devs
[slot_id
]) {
1425 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1426 /* Delete default control endpoint resources */
1427 xhci_free_device_endpoint_resources(xhci
,
1428 xhci
->devs
[slot_id
], true);
1429 xhci_free_virt_device(xhci
, slot_id
);
1432 case TRB_TYPE(TRB_CONFIG_EP
):
1433 virt_dev
= xhci
->devs
[slot_id
];
1434 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1437 * Configure endpoint commands can come from the USB core
1438 * configuration or alt setting changes, or because the HW
1439 * needed an extra configure endpoint command after a reset
1440 * endpoint command or streams were being configured.
1441 * If the command was for a halted endpoint, the xHCI driver
1442 * is not waiting on the configure endpoint command.
1444 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1446 /* Input ctx add_flags are the endpoint index plus one */
1447 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1448 /* A usb_set_interface() call directly after clearing a halted
1449 * condition may race on this quirky hardware. Not worth
1450 * worrying about, since this is prototype hardware. Not sure
1451 * if this will work for streams, but streams support was
1452 * untested on this prototype.
1454 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1455 ep_index
!= (unsigned int) -1 &&
1456 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1457 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1458 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1459 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1460 if (!(ep_state
& EP_HALTED
))
1461 goto bandwidth_change
;
1462 xhci_dbg(xhci
, "Completed config ep cmd - "
1463 "last ep index = %d, state = %d\n",
1464 ep_index
, ep_state
);
1465 /* Clear internal halted state and restart ring(s) */
1466 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1468 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1472 xhci_dbg(xhci
, "Completed config ep cmd\n");
1473 xhci
->devs
[slot_id
]->cmd_status
=
1474 GET_COMP_CODE(le32_to_cpu(event
->status
));
1475 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1477 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1478 virt_dev
= xhci
->devs
[slot_id
];
1479 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1481 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1482 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1484 case TRB_TYPE(TRB_ADDR_DEV
):
1485 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1486 complete(&xhci
->addr_dev
);
1488 case TRB_TYPE(TRB_STOP_RING
):
1489 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1491 case TRB_TYPE(TRB_SET_DEQ
):
1492 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1494 case TRB_TYPE(TRB_CMD_NOOP
):
1496 case TRB_TYPE(TRB_RESET_EP
):
1497 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1499 case TRB_TYPE(TRB_RESET_DEV
):
1500 xhci_dbg(xhci
, "Completed reset device command.\n");
1501 slot_id
= TRB_TO_SLOT_ID(
1502 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1503 virt_dev
= xhci
->devs
[slot_id
];
1505 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1507 xhci_warn(xhci
, "Reset device command completion "
1508 "for disabled slot %u\n", slot_id
);
1510 case TRB_TYPE(TRB_NEC_GET_FW
):
1511 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1512 xhci
->error_bitmask
|= 1 << 6;
1515 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1516 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1517 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1520 /* Skip over unknown commands on the event ring */
1521 xhci
->error_bitmask
|= 1 << 6;
1524 inc_deq(xhci
, xhci
->cmd_ring
);
1527 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1528 union xhci_trb
*event
)
1532 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1533 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1534 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1535 handle_cmd_completion(xhci
, &event
->event_cmd
);
1538 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1539 * port registers -- USB 3.0 and USB 2.0).
1541 * Returns a zero-based port number, which is suitable for indexing into each of
1542 * the split roothubs' port arrays and bus state arrays.
1543 * Add one to it in order to call xhci_find_slot_id_by_port.
1545 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1546 struct xhci_hcd
*xhci
, u32 port_id
)
1549 unsigned int num_similar_speed_ports
= 0;
1551 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1552 * and usb2_ports are 0-based indexes. Count the number of similar
1553 * speed ports, up to 1 port before this port.
1555 for (i
= 0; i
< (port_id
- 1); i
++) {
1556 u8 port_speed
= xhci
->port_array
[i
];
1559 * Skip ports that don't have known speeds, or have duplicate
1560 * Extended Capabilities port speed entries.
1562 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1566 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1567 * 1.1 ports are under the USB 2.0 hub. If the port speed
1568 * matches the device speed, it's a similar speed port.
1570 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1571 num_similar_speed_ports
++;
1573 return num_similar_speed_ports
;
1576 static void handle_device_notification(struct xhci_hcd
*xhci
,
1577 union xhci_trb
*event
)
1580 struct usb_device
*udev
;
1582 slot_id
= TRB_TO_SLOT_ID(event
->generic
.field
[3]);
1583 if (!xhci
->devs
[slot_id
]) {
1584 xhci_warn(xhci
, "Device Notification event for "
1585 "unused slot %u\n", slot_id
);
1589 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1591 udev
= xhci
->devs
[slot_id
]->udev
;
1592 if (udev
&& udev
->parent
)
1593 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1596 static void handle_port_status(struct xhci_hcd
*xhci
,
1597 union xhci_trb
*event
)
1599 struct usb_hcd
*hcd
;
1604 unsigned int faked_port_index
;
1606 struct xhci_bus_state
*bus_state
;
1607 __le32 __iomem
**port_array
;
1608 bool bogus_port_status
= false;
1610 /* Port status change events always have a successful completion code */
1611 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1612 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1613 xhci
->error_bitmask
|= 1 << 8;
1615 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1616 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1618 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1619 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1620 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1621 inc_deq(xhci
, xhci
->event_ring
);
1625 /* Figure out which usb_hcd this port is attached to:
1626 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1628 major_revision
= xhci
->port_array
[port_id
- 1];
1630 /* Find the right roothub. */
1631 hcd
= xhci_to_hcd(xhci
);
1632 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1633 hcd
= xhci
->shared_hcd
;
1635 if (major_revision
== 0) {
1636 xhci_warn(xhci
, "Event for port %u not in "
1637 "Extended Capabilities, ignoring.\n",
1639 bogus_port_status
= true;
1642 if (major_revision
== DUPLICATE_ENTRY
) {
1643 xhci_warn(xhci
, "Event for port %u duplicated in"
1644 "Extended Capabilities, ignoring.\n",
1646 bogus_port_status
= true;
1651 * Hardware port IDs reported by a Port Status Change Event include USB
1652 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1653 * resume event, but we first need to translate the hardware port ID
1654 * into the index into the ports on the correct split roothub, and the
1655 * correct bus_state structure.
1657 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1658 if (hcd
->speed
== HCD_USB3
)
1659 port_array
= xhci
->usb3_ports
;
1661 port_array
= xhci
->usb2_ports
;
1662 /* Find the faked port hub number */
1663 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1666 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1667 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1668 xhci_dbg(xhci
, "resume root hub\n");
1669 usb_hcd_resume_root_hub(hcd
);
1672 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1673 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1675 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1676 if (!(temp1
& CMD_RUN
)) {
1677 xhci_warn(xhci
, "xHC is not running.\n");
1681 if (DEV_SUPERSPEED(temp
)) {
1682 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1683 /* Set a flag to say the port signaled remote wakeup,
1684 * so we can tell the difference between the end of
1685 * device and host initiated resume.
1687 bus_state
->port_remote_wakeup
|= 1 << faked_port_index
;
1688 xhci_test_and_clear_bit(xhci
, port_array
,
1689 faked_port_index
, PORT_PLC
);
1690 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1692 /* Need to wait until the next link state change
1693 * indicates the device is actually in U0.
1695 bogus_port_status
= true;
1698 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1699 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1700 msecs_to_jiffies(USB_RESUME_TIMEOUT
);
1701 set_bit(faked_port_index
, &bus_state
->resuming_ports
);
1702 mod_timer(&hcd
->rh_timer
,
1703 bus_state
->resume_done
[faked_port_index
]);
1704 /* Do the rest in GetPortStatus */
1708 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_U0
&&
1709 DEV_SUPERSPEED(temp
)) {
1710 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1711 /* We've just brought the device into U0 through either the
1712 * Resume state after a device remote wakeup, or through the
1713 * U3Exit state after a host-initiated resume. If it's a device
1714 * initiated remote wake, don't pass up the link state change,
1715 * so the roothub behavior is consistent with external
1716 * USB 3.0 hub behavior.
1718 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1719 faked_port_index
+ 1);
1720 if (slot_id
&& xhci
->devs
[slot_id
])
1721 xhci_ring_device(xhci
, slot_id
);
1722 if (bus_state
->port_remote_wakeup
& (1 << faked_port_index
)) {
1723 bus_state
->port_remote_wakeup
&=
1724 ~(1 << faked_port_index
);
1725 xhci_test_and_clear_bit(xhci
, port_array
,
1726 faked_port_index
, PORT_PLC
);
1727 usb_wakeup_notification(hcd
->self
.root_hub
,
1728 faked_port_index
+ 1);
1729 bogus_port_status
= true;
1734 if (hcd
->speed
!= HCD_USB3
)
1735 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1739 /* Update event ring dequeue pointer before dropping the lock */
1740 inc_deq(xhci
, xhci
->event_ring
);
1742 /* Don't make the USB core poll the roothub if we got a bad port status
1743 * change event. Besides, at that point we can't tell which roothub
1744 * (USB 2.0 or USB 3.0) to kick.
1746 if (bogus_port_status
)
1750 * xHCI port-status-change events occur when the "or" of all the
1751 * status-change bits in the portsc register changes from 0 to 1.
1752 * New status changes won't cause an event if any other change
1753 * bits are still set. When an event occurs, switch over to
1754 * polling to avoid losing status changes.
1756 xhci_dbg(xhci
, "%s: starting port polling.\n", __func__
);
1757 set_bit(HCD_FLAG_POLL_RH
, &hcd
->flags
);
1758 spin_unlock(&xhci
->lock
);
1759 /* Pass this up to the core */
1760 usb_hcd_poll_rh_status(hcd
);
1761 spin_lock(&xhci
->lock
);
1765 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1766 * at end_trb, which may be in another segment. If the suspect DMA address is a
1767 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1770 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1771 union xhci_trb
*start_trb
,
1772 union xhci_trb
*end_trb
,
1773 dma_addr_t suspect_dma
)
1775 dma_addr_t start_dma
;
1776 dma_addr_t end_seg_dma
;
1777 dma_addr_t end_trb_dma
;
1778 struct xhci_segment
*cur_seg
;
1780 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1781 cur_seg
= start_seg
;
1786 /* We may get an event for a Link TRB in the middle of a TD */
1787 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1788 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1789 /* If the end TRB isn't in this segment, this is set to 0 */
1790 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1792 if (end_trb_dma
> 0) {
1793 /* The end TRB is in this segment, so suspect should be here */
1794 if (start_dma
<= end_trb_dma
) {
1795 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1798 /* Case for one segment with
1799 * a TD wrapped around to the top
1801 if ((suspect_dma
>= start_dma
&&
1802 suspect_dma
<= end_seg_dma
) ||
1803 (suspect_dma
>= cur_seg
->dma
&&
1804 suspect_dma
<= end_trb_dma
))
1809 /* Might still be somewhere in this segment */
1810 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1813 cur_seg
= cur_seg
->next
;
1814 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1815 } while (cur_seg
!= start_seg
);
1820 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1821 unsigned int slot_id
, unsigned int ep_index
,
1822 unsigned int stream_id
,
1823 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1825 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1826 ep
->ep_state
|= EP_HALTED
;
1827 ep
->stopped_td
= td
;
1828 ep
->stopped_trb
= event_trb
;
1829 ep
->stopped_stream
= stream_id
;
1831 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1832 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1834 ep
->stopped_td
= NULL
;
1835 ep
->stopped_trb
= NULL
;
1836 ep
->stopped_stream
= 0;
1838 xhci_ring_cmd_db(xhci
);
1841 /* Check if an error has halted the endpoint ring. The class driver will
1842 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1843 * However, a babble and other errors also halt the endpoint ring, and the class
1844 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1845 * Ring Dequeue Pointer command manually.
1847 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1848 struct xhci_ep_ctx
*ep_ctx
,
1849 unsigned int trb_comp_code
)
1851 /* TRB completion codes that may require a manual halt cleanup */
1852 if (trb_comp_code
== COMP_TX_ERR
||
1853 trb_comp_code
== COMP_BABBLE
||
1854 trb_comp_code
== COMP_SPLIT_ERR
)
1855 /* The 0.96 spec says a babbling control endpoint
1856 * is not halted. The 0.96 spec says it is. Some HW
1857 * claims to be 0.95 compliant, but it halts the control
1858 * endpoint anyway. Check if a babble halted the
1861 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1862 cpu_to_le32(EP_STATE_HALTED
))
1868 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1870 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1871 /* Vendor defined "informational" completion code,
1872 * treat as not-an-error.
1874 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1876 xhci_dbg(xhci
, "Treating code as success.\n");
1883 * Finish the td processing, remove the td from td list;
1884 * Return 1 if the urb can be given back.
1886 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1887 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1888 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1890 struct xhci_virt_device
*xdev
;
1891 struct xhci_ring
*ep_ring
;
1892 unsigned int slot_id
;
1894 struct urb
*urb
= NULL
;
1895 struct xhci_ep_ctx
*ep_ctx
;
1897 struct urb_priv
*urb_priv
;
1900 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1901 xdev
= xhci
->devs
[slot_id
];
1902 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1903 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1904 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1905 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1910 if (trb_comp_code
== COMP_STOP_INVAL
||
1911 trb_comp_code
== COMP_STOP
) {
1912 /* The Endpoint Stop Command completion will take care of any
1913 * stopped TDs. A stopped TD may be restarted, so don't update
1914 * the ring dequeue pointer or take this TD off any lists yet.
1916 ep
->stopped_td
= td
;
1917 ep
->stopped_trb
= event_trb
;
1920 if (trb_comp_code
== COMP_STALL
) {
1921 /* The transfer is completed from the driver's
1922 * perspective, but we need to issue a set dequeue
1923 * command for this stalled endpoint to move the dequeue
1924 * pointer past the TD. We can't do that here because
1925 * the halt condition must be cleared first. Let the
1926 * USB class driver clear the stall later.
1928 ep
->stopped_td
= td
;
1929 ep
->stopped_trb
= event_trb
;
1930 ep
->stopped_stream
= ep_ring
->stream_id
;
1931 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1932 ep_ctx
, trb_comp_code
)) {
1933 /* Other types of errors halt the endpoint, but the
1934 * class driver doesn't call usb_reset_endpoint() unless
1935 * the error is -EPIPE. Clear the halted status in the
1936 * xHCI hardware manually.
1938 xhci_cleanup_halted_endpoint(xhci
,
1939 slot_id
, ep_index
, ep_ring
->stream_id
,
1942 /* Update ring dequeue pointer */
1943 while (ep_ring
->dequeue
!= td
->last_trb
)
1944 inc_deq(xhci
, ep_ring
);
1945 inc_deq(xhci
, ep_ring
);
1949 /* Clean up the endpoint's TD list */
1951 urb_priv
= urb
->hcpriv
;
1953 /* Do one last check of the actual transfer length.
1954 * If the host controller said we transferred more data than
1955 * the buffer length, urb->actual_length will be a very big
1956 * number (since it's unsigned). Play it safe and say we didn't
1957 * transfer anything.
1959 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1960 xhci_warn(xhci
, "URB transfer length is wrong, "
1961 "xHC issue? req. len = %u, "
1963 urb
->transfer_buffer_length
,
1964 urb
->actual_length
);
1965 urb
->actual_length
= 0;
1966 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1967 *status
= -EREMOTEIO
;
1971 list_del_init(&td
->td_list
);
1972 /* Was this TD slated to be cancelled but completed anyway? */
1973 if (!list_empty(&td
->cancelled_td_list
))
1974 list_del_init(&td
->cancelled_td_list
);
1977 /* Giveback the urb when all the tds are completed */
1978 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1980 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1981 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1982 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1984 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1985 usb_amd_quirk_pll_enable();
1995 * Process control tds, update urb status and actual_length.
1997 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1998 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1999 struct xhci_virt_ep
*ep
, int *status
)
2001 struct xhci_virt_device
*xdev
;
2002 struct xhci_ring
*ep_ring
;
2003 unsigned int slot_id
;
2005 struct xhci_ep_ctx
*ep_ctx
;
2008 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2009 xdev
= xhci
->devs
[slot_id
];
2010 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2011 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2012 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2013 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2015 switch (trb_comp_code
) {
2017 if (event_trb
== ep_ring
->dequeue
) {
2018 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
2019 "without IOC set??\n");
2020 *status
= -ESHUTDOWN
;
2021 } else if (event_trb
!= td
->last_trb
) {
2022 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
2023 "without IOC set??\n");
2024 *status
= -ESHUTDOWN
;
2030 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2031 *status
= -EREMOTEIO
;
2035 case COMP_STOP_INVAL
:
2037 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2039 if (!xhci_requires_manual_halt_cleanup(xhci
,
2040 ep_ctx
, trb_comp_code
))
2042 xhci_dbg(xhci
, "TRB error code %u, "
2043 "halted endpoint index = %u\n",
2044 trb_comp_code
, ep_index
);
2045 /* else fall through */
2047 /* Did we transfer part of the data (middle) phase? */
2048 if (event_trb
!= ep_ring
->dequeue
&&
2049 event_trb
!= td
->last_trb
)
2050 td
->urb
->actual_length
=
2051 td
->urb
->transfer_buffer_length
-
2052 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2054 td
->urb
->actual_length
= 0;
2056 xhci_cleanup_halted_endpoint(xhci
,
2057 slot_id
, ep_index
, 0, td
, event_trb
);
2058 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
2061 * Did we transfer any data, despite the errors that might have
2062 * happened? I.e. did we get past the setup stage?
2064 if (event_trb
!= ep_ring
->dequeue
) {
2065 /* The event was for the status stage */
2066 if (event_trb
== td
->last_trb
) {
2067 if (td
->urb_length_set
) {
2068 /* Don't overwrite a previously set error code
2070 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
2071 (td
->urb
->transfer_flags
2072 & URB_SHORT_NOT_OK
))
2073 /* Did we already see a short data
2075 *status
= -EREMOTEIO
;
2077 td
->urb
->actual_length
=
2078 td
->urb
->transfer_buffer_length
;
2082 * Maybe the event was for the data stage? If so, update
2083 * already the actual_length of the URB and flag it as
2084 * set, so that it is not overwritten in the event for
2087 td
->urb_length_set
= true;
2088 td
->urb
->actual_length
=
2089 td
->urb
->transfer_buffer_length
-
2090 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2091 xhci_dbg(xhci
, "Waiting for status "
2097 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2101 * Process isochronous tds, update urb packet status and actual_length.
2103 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2104 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2105 struct xhci_virt_ep
*ep
, int *status
)
2107 struct xhci_ring
*ep_ring
;
2108 struct urb_priv
*urb_priv
;
2111 union xhci_trb
*cur_trb
;
2112 struct xhci_segment
*cur_seg
;
2113 struct usb_iso_packet_descriptor
*frame
;
2115 bool skip_td
= false;
2117 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2118 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2119 urb_priv
= td
->urb
->hcpriv
;
2120 idx
= urb_priv
->td_cnt
;
2121 frame
= &td
->urb
->iso_frame_desc
[idx
];
2123 /* handle completion code */
2124 switch (trb_comp_code
) {
2126 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0) {
2130 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2131 trb_comp_code
= COMP_SHORT_TX
;
2133 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
2137 frame
->status
= -ECOMM
;
2140 case COMP_BUFF_OVER
:
2142 frame
->status
= -EOVERFLOW
;
2147 frame
->status
= -EPROTO
;
2151 frame
->status
= -EPROTO
;
2152 if (event_trb
!= td
->last_trb
)
2157 case COMP_STOP_INVAL
:
2164 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
2165 frame
->actual_length
= frame
->length
;
2166 td
->urb
->actual_length
+= frame
->length
;
2168 for (cur_trb
= ep_ring
->dequeue
,
2169 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
2170 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2171 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2172 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2173 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2175 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2176 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2178 if (trb_comp_code
!= COMP_STOP_INVAL
) {
2179 frame
->actual_length
= len
;
2180 td
->urb
->actual_length
+= len
;
2184 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2187 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2188 struct xhci_transfer_event
*event
,
2189 struct xhci_virt_ep
*ep
, int *status
)
2191 struct xhci_ring
*ep_ring
;
2192 struct urb_priv
*urb_priv
;
2193 struct usb_iso_packet_descriptor
*frame
;
2196 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2197 urb_priv
= td
->urb
->hcpriv
;
2198 idx
= urb_priv
->td_cnt
;
2199 frame
= &td
->urb
->iso_frame_desc
[idx
];
2201 /* The transfer is partly done. */
2202 frame
->status
= -EXDEV
;
2204 /* calc actual length */
2205 frame
->actual_length
= 0;
2207 /* Update ring dequeue pointer */
2208 while (ep_ring
->dequeue
!= td
->last_trb
)
2209 inc_deq(xhci
, ep_ring
);
2210 inc_deq(xhci
, ep_ring
);
2212 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
2216 * Process bulk and interrupt tds, update urb status and actual_length.
2218 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
2219 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
2220 struct xhci_virt_ep
*ep
, int *status
)
2222 struct xhci_ring
*ep_ring
;
2223 union xhci_trb
*cur_trb
;
2224 struct xhci_segment
*cur_seg
;
2227 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2228 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2230 switch (trb_comp_code
) {
2232 /* Double check that the HW transferred everything. */
2233 if (event_trb
!= td
->last_trb
||
2234 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2235 xhci_warn(xhci
, "WARN Successful completion "
2237 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2238 *status
= -EREMOTEIO
;
2241 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
2242 trb_comp_code
= COMP_SHORT_TX
;
2248 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2249 *status
= -EREMOTEIO
;
2254 /* Others already handled above */
2257 if (trb_comp_code
== COMP_SHORT_TX
)
2258 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
2259 "%d bytes untransferred\n",
2260 td
->urb
->ep
->desc
.bEndpointAddress
,
2261 td
->urb
->transfer_buffer_length
,
2262 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2263 /* Fast path - was this the last TRB in the TD for this URB? */
2264 if (event_trb
== td
->last_trb
) {
2265 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
2266 td
->urb
->actual_length
=
2267 td
->urb
->transfer_buffer_length
-
2268 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2269 if (td
->urb
->transfer_buffer_length
<
2270 td
->urb
->actual_length
) {
2271 xhci_warn(xhci
, "HC gave bad length "
2272 "of %d bytes left\n",
2273 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)));
2274 td
->urb
->actual_length
= 0;
2275 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2276 *status
= -EREMOTEIO
;
2280 /* Don't overwrite a previously set error code */
2281 if (*status
== -EINPROGRESS
) {
2282 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
2283 *status
= -EREMOTEIO
;
2288 td
->urb
->actual_length
=
2289 td
->urb
->transfer_buffer_length
;
2290 /* Ignore a short packet completion if the
2291 * untransferred length was zero.
2293 if (*status
== -EREMOTEIO
)
2297 /* Slow path - walk the list, starting from the dequeue
2298 * pointer, to get the actual length transferred.
2300 td
->urb
->actual_length
= 0;
2301 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
2302 cur_trb
!= event_trb
;
2303 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
2304 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
2305 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
2306 td
->urb
->actual_length
+=
2307 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
2309 /* If the ring didn't stop on a Link or No-op TRB, add
2310 * in the actual bytes transferred from the Normal TRB
2312 if (trb_comp_code
!= COMP_STOP_INVAL
)
2313 td
->urb
->actual_length
+=
2314 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
2315 EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
));
2318 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2322 * If this function returns an error condition, it means it got a Transfer
2323 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2324 * At this point, the host controller is probably hosed and should be reset.
2326 static int handle_tx_event(struct xhci_hcd
*xhci
,
2327 struct xhci_transfer_event
*event
)
2328 __releases(&xhci
->lock
)
2329 __acquires(&xhci
->lock
)
2331 struct xhci_virt_device
*xdev
;
2332 struct xhci_virt_ep
*ep
;
2333 struct xhci_ring
*ep_ring
;
2334 unsigned int slot_id
;
2336 struct xhci_td
*td
= NULL
;
2337 dma_addr_t event_dma
;
2338 struct xhci_segment
*event_seg
;
2339 union xhci_trb
*event_trb
;
2340 struct urb
*urb
= NULL
;
2341 int status
= -EINPROGRESS
;
2342 struct urb_priv
*urb_priv
;
2343 struct xhci_ep_ctx
*ep_ctx
;
2344 struct list_head
*tmp
;
2349 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2350 xdev
= xhci
->devs
[slot_id
];
2352 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
2353 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2354 (unsigned long long) xhci_trb_virt_to_dma(
2355 xhci
->event_ring
->deq_seg
,
2356 xhci
->event_ring
->dequeue
),
2357 lower_32_bits(le64_to_cpu(event
->buffer
)),
2358 upper_32_bits(le64_to_cpu(event
->buffer
)),
2359 le32_to_cpu(event
->transfer_len
),
2360 le32_to_cpu(event
->flags
));
2361 xhci_dbg(xhci
, "Event ring:\n");
2362 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2366 /* Endpoint ID is 1 based, our index is zero based */
2367 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2368 ep
= &xdev
->eps
[ep_index
];
2369 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2370 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2372 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
2373 EP_STATE_DISABLED
) {
2374 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
2375 "or incorrect stream ring\n");
2376 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2377 (unsigned long long) xhci_trb_virt_to_dma(
2378 xhci
->event_ring
->deq_seg
,
2379 xhci
->event_ring
->dequeue
),
2380 lower_32_bits(le64_to_cpu(event
->buffer
)),
2381 upper_32_bits(le64_to_cpu(event
->buffer
)),
2382 le32_to_cpu(event
->transfer_len
),
2383 le32_to_cpu(event
->flags
));
2384 xhci_dbg(xhci
, "Event ring:\n");
2385 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2389 /* Count current td numbers if ep->skip is set */
2391 list_for_each(tmp
, &ep_ring
->td_list
)
2395 event_dma
= le64_to_cpu(event
->buffer
);
2396 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2397 /* Look for common error cases */
2398 switch (trb_comp_code
) {
2399 /* Skip codes that require special handling depending on
2403 if (EVENT_TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2405 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2406 trb_comp_code
= COMP_SHORT_TX
;
2408 xhci_warn_ratelimited(xhci
,
2409 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2413 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
2415 case COMP_STOP_INVAL
:
2416 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
2419 xhci_dbg(xhci
, "Stalled endpoint\n");
2420 ep
->ep_state
|= EP_HALTED
;
2424 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
2427 case COMP_SPLIT_ERR
:
2429 xhci_dbg(xhci
, "Transfer error on endpoint\n");
2433 xhci_dbg(xhci
, "Babble error on endpoint\n");
2434 status
= -EOVERFLOW
;
2437 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2441 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2443 case COMP_BUFF_OVER
:
2444 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2448 * When the Isoch ring is empty, the xHC will generate
2449 * a Ring Overrun Event for IN Isoch endpoint or Ring
2450 * Underrun Event for OUT Isoch endpoint.
2452 xhci_dbg(xhci
, "underrun event on endpoint\n");
2453 if (!list_empty(&ep_ring
->td_list
))
2454 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2455 "still with TDs queued?\n",
2456 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2460 xhci_dbg(xhci
, "overrun event on endpoint\n");
2461 if (!list_empty(&ep_ring
->td_list
))
2462 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2463 "still with TDs queued?\n",
2464 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2468 xhci_warn(xhci
, "WARN: detect an incompatible device");
2471 case COMP_MISSED_INT
:
2473 * When encounter missed service error, one or more isoc tds
2474 * may be missed by xHC.
2475 * Set skip flag of the ep_ring; Complete the missed tds as
2476 * short transfer when process the ep_ring next time.
2479 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2482 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2486 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2492 /* This TRB should be in the TD at the head of this ring's
2495 if (list_empty(&ep_ring
->td_list
)) {
2497 * A stopped endpoint may generate an extra completion
2498 * event if the device was suspended. Don't print
2501 if (!(trb_comp_code
== COMP_STOP
||
2502 trb_comp_code
== COMP_STOP_INVAL
)) {
2503 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2504 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2506 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2507 (le32_to_cpu(event
->flags
) &
2508 TRB_TYPE_BITMASK
)>>10);
2509 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2513 xhci_dbg(xhci
, "td_list is empty while skip "
2514 "flag set. Clear skip flag.\n");
2520 /* We've skipped all the TDs on the ep ring when ep->skip set */
2521 if (ep
->skip
&& td_num
== 0) {
2523 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2524 "Clear skip flag.\n");
2529 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2533 /* Is this a TRB in the currently executing TD? */
2534 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2535 td
->last_trb
, event_dma
);
2538 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2539 * is not in the current TD pointed by ep_ring->dequeue because
2540 * that the hardware dequeue pointer still at the previous TRB
2541 * of the current TD. The previous TRB maybe a Link TD or the
2542 * last TRB of the previous TD. The command completion handle
2543 * will take care the rest.
2545 if (!event_seg
&& (trb_comp_code
== COMP_STOP
||
2546 trb_comp_code
== COMP_STOP_INVAL
)) {
2553 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2554 /* Some host controllers give a spurious
2555 * successful event after a short transfer.
2558 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2559 ep_ring
->last_td_was_short
) {
2560 ep_ring
->last_td_was_short
= false;
2564 /* HC is busted, give up! */
2566 "ERROR Transfer event TRB DMA ptr not "
2567 "part of current TD\n");
2571 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2574 if (trb_comp_code
== COMP_SHORT_TX
)
2575 ep_ring
->last_td_was_short
= true;
2577 ep_ring
->last_td_was_short
= false;
2580 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2584 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2585 sizeof(*event_trb
)];
2587 * No-op TRB should not trigger interrupts.
2588 * If event_trb is a no-op TRB, it means the
2589 * corresponding TD has been cancelled. Just ignore
2592 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2594 "event_trb is a no-op TRB. Skip it\n");
2598 /* Now update the urb's actual_length and give back to
2601 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2602 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2604 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2605 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2608 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2613 * Do not update event ring dequeue pointer if ep->skip is set.
2614 * Will roll back to continue process missed tds.
2616 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2617 inc_deq(xhci
, xhci
->event_ring
);
2622 urb_priv
= urb
->hcpriv
;
2623 /* Leave the TD around for the reset endpoint function
2624 * to use(but only if it's not a control endpoint,
2625 * since we already queued the Set TR dequeue pointer
2626 * command for stalled control endpoints).
2628 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2629 (trb_comp_code
!= COMP_STALL
&&
2630 trb_comp_code
!= COMP_BABBLE
))
2631 xhci_urb_free_priv(xhci
, urb_priv
);
2635 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2636 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2637 (urb
->transfer_flags
&
2638 URB_SHORT_NOT_OK
)) ||
2640 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2641 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2642 "expected = %d, status = %d\n",
2643 urb
, urb
->actual_length
,
2644 urb
->transfer_buffer_length
,
2646 spin_unlock(&xhci
->lock
);
2647 /* EHCI, UHCI, and OHCI always unconditionally set the
2648 * urb->status of an isochronous endpoint to 0.
2650 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2652 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2653 spin_lock(&xhci
->lock
);
2657 * If ep->skip is set, it means there are missed tds on the
2658 * endpoint ring need to take care of.
2659 * Process them as short transfer until reach the td pointed by
2662 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2668 * This function handles all OS-owned events on the event ring. It may drop
2669 * xhci->lock between event processing (e.g. to pass up port status changes).
2670 * Returns >0 for "possibly more events to process" (caller should call again),
2671 * otherwise 0 if done. In future, <0 returns should indicate error code.
2673 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2675 union xhci_trb
*event
;
2676 int update_ptrs
= 1;
2679 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2680 xhci
->error_bitmask
|= 1 << 1;
2684 event
= xhci
->event_ring
->dequeue
;
2685 /* Does the HC or OS own the TRB? */
2686 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2687 xhci
->event_ring
->cycle_state
) {
2688 xhci
->error_bitmask
|= 1 << 2;
2693 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2694 * speculative reads of the event's flags/data below.
2697 /* FIXME: Handle more event types. */
2698 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2699 case TRB_TYPE(TRB_COMPLETION
):
2700 handle_cmd_completion(xhci
, &event
->event_cmd
);
2702 case TRB_TYPE(TRB_PORT_STATUS
):
2703 handle_port_status(xhci
, event
);
2706 case TRB_TYPE(TRB_TRANSFER
):
2707 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2709 xhci
->error_bitmask
|= 1 << 9;
2713 case TRB_TYPE(TRB_DEV_NOTE
):
2714 handle_device_notification(xhci
, event
);
2717 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2719 handle_vendor_event(xhci
, event
);
2721 xhci
->error_bitmask
|= 1 << 3;
2723 /* Any of the above functions may drop and re-acquire the lock, so check
2724 * to make sure a watchdog timer didn't mark the host as non-responsive.
2726 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2727 xhci_dbg(xhci
, "xHCI host dying, returning from "
2728 "event handler.\n");
2733 /* Update SW event ring dequeue pointer */
2734 inc_deq(xhci
, xhci
->event_ring
);
2736 /* Are there more items on the event ring? Caller will call us again to
2743 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2744 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2745 * indicators of an event TRB error, but we check the status *first* to be safe.
2747 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2749 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2752 union xhci_trb
*event_ring_deq
;
2755 spin_lock(&xhci
->lock
);
2756 /* Check if the xHC generated the interrupt, or the irq is shared */
2757 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2758 if (status
== 0xffffffff)
2761 if (!(status
& STS_EINT
)) {
2762 spin_unlock(&xhci
->lock
);
2765 if (status
& STS_FATAL
) {
2766 xhci_warn(xhci
, "WARNING: Host System Error\n");
2769 spin_unlock(&xhci
->lock
);
2774 * Clear the op reg interrupt status first,
2775 * so we can receive interrupts from other MSI-X interrupters.
2776 * Write 1 to clear the interrupt status.
2779 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2780 /* FIXME when MSI-X is supported and there are multiple vectors */
2781 /* Clear the MSI-X event interrupt status */
2785 /* Acknowledge the PCI interrupt */
2786 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2787 irq_pending
|= IMAN_IP
;
2788 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2791 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2792 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2793 "Shouldn't IRQs be disabled?\n");
2794 /* Clear the event handler busy flag (RW1C);
2795 * the event ring should be empty.
2797 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2798 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2799 &xhci
->ir_set
->erst_dequeue
);
2800 spin_unlock(&xhci
->lock
);
2805 event_ring_deq
= xhci
->event_ring
->dequeue
;
2806 /* FIXME this should be a delayed service routine
2807 * that clears the EHB.
2809 while (xhci_handle_event(xhci
) > 0) {}
2811 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2812 /* If necessary, update the HW's version of the event ring deq ptr. */
2813 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2814 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2815 xhci
->event_ring
->dequeue
);
2817 xhci_warn(xhci
, "WARN something wrong with SW event "
2818 "ring dequeue ptr.\n");
2819 /* Update HC event ring dequeue pointer */
2820 temp_64
&= ERST_PTR_MASK
;
2821 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2824 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2825 temp_64
|= ERST_EHB
;
2826 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2828 spin_unlock(&xhci
->lock
);
2833 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2835 return xhci_irq(hcd
);
2838 /**** Endpoint Ring Operations ****/
2841 * Generic function for queueing a TRB on a ring.
2842 * The caller must have checked to make sure there's room on the ring.
2844 * @more_trbs_coming: Will you enqueue more TRBs before calling
2845 * prepare_transfer()?
2847 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2848 bool more_trbs_coming
,
2849 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2851 struct xhci_generic_trb
*trb
;
2853 trb
= &ring
->enqueue
->generic
;
2854 trb
->field
[0] = cpu_to_le32(field1
);
2855 trb
->field
[1] = cpu_to_le32(field2
);
2856 trb
->field
[2] = cpu_to_le32(field3
);
2857 trb
->field
[3] = cpu_to_le32(field4
);
2858 inc_enq(xhci
, ring
, more_trbs_coming
);
2862 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2863 * FIXME allocate segments if the ring is full.
2865 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2866 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2868 unsigned int num_trbs_needed
;
2870 /* Make sure the endpoint has been added to xHC schedule */
2872 case EP_STATE_DISABLED
:
2874 * USB core changed config/interfaces without notifying us,
2875 * or hardware is reporting the wrong state.
2877 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2879 case EP_STATE_ERROR
:
2880 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2881 /* FIXME event handling code for error needs to clear it */
2882 /* XXX not sure if this should be -ENOENT or not */
2884 case EP_STATE_HALTED
:
2885 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2886 case EP_STATE_STOPPED
:
2887 case EP_STATE_RUNNING
:
2890 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2892 * FIXME issue Configure Endpoint command to try to get the HC
2893 * back into a known state.
2899 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
2902 if (ep_ring
== xhci
->cmd_ring
) {
2903 xhci_err(xhci
, "Do not support expand command ring\n");
2907 xhci_dbg(xhci
, "ERROR no room on ep ring, "
2908 "try ring expansion\n");
2909 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
2910 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
2912 xhci_err(xhci
, "Ring expansion failed\n");
2917 if (enqueue_is_link_trb(ep_ring
)) {
2918 struct xhci_ring
*ring
= ep_ring
;
2919 union xhci_trb
*next
;
2921 next
= ring
->enqueue
;
2923 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2924 /* If we're not dealing with 0.95 hardware or isoc rings
2925 * on AMD 0.96 host, clear the chain bit.
2927 if (!xhci_link_trb_quirk(xhci
) &&
2928 !(ring
->type
== TYPE_ISOC
&&
2929 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2930 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2932 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2935 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2937 /* Toggle the cycle bit after the last ring segment. */
2938 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2939 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2941 ring
->enq_seg
= ring
->enq_seg
->next
;
2942 ring
->enqueue
= ring
->enq_seg
->trbs
;
2943 next
= ring
->enqueue
;
2950 static int prepare_transfer(struct xhci_hcd
*xhci
,
2951 struct xhci_virt_device
*xdev
,
2952 unsigned int ep_index
,
2953 unsigned int stream_id
,
2954 unsigned int num_trbs
,
2956 unsigned int td_index
,
2960 struct urb_priv
*urb_priv
;
2962 struct xhci_ring
*ep_ring
;
2963 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2965 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2967 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2972 ret
= prepare_ring(xhci
, ep_ring
,
2973 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2974 num_trbs
, mem_flags
);
2978 urb_priv
= urb
->hcpriv
;
2979 td
= urb_priv
->td
[td_index
];
2981 INIT_LIST_HEAD(&td
->td_list
);
2982 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2984 if (td_index
== 0) {
2985 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2991 /* Add this TD to the tail of the endpoint ring's TD list */
2992 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2993 td
->start_seg
= ep_ring
->enq_seg
;
2994 td
->first_trb
= ep_ring
->enqueue
;
2996 urb_priv
->td
[td_index
] = td
;
3001 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
3003 int num_sgs
, num_trbs
, running_total
, temp
, i
;
3004 struct scatterlist
*sg
;
3007 num_sgs
= urb
->num_mapped_sgs
;
3008 temp
= urb
->transfer_buffer_length
;
3011 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
3012 unsigned int len
= sg_dma_len(sg
);
3014 /* Scatter gather list entries may cross 64KB boundaries */
3015 running_total
= TRB_MAX_BUFF_SIZE
-
3016 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
3017 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3018 if (running_total
!= 0)
3021 /* How many more 64KB chunks to transfer, how many more TRBs? */
3022 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
3024 running_total
+= TRB_MAX_BUFF_SIZE
;
3026 len
= min_t(int, len
, temp
);
3034 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
3037 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
3038 "TRBs, %d left\n", __func__
,
3039 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
3040 if (running_total
!= urb
->transfer_buffer_length
)
3041 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
3042 "queued %#x (%d), asked for %#x (%d)\n",
3044 urb
->ep
->desc
.bEndpointAddress
,
3045 running_total
, running_total
,
3046 urb
->transfer_buffer_length
,
3047 urb
->transfer_buffer_length
);
3050 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
3051 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
3052 struct xhci_generic_trb
*start_trb
)
3055 * Pass all the TRBs to the hardware at once and make sure this write
3060 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
3062 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
3063 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
3067 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
3068 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
3069 * (comprised of sg list entries) can take several service intervals to
3072 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3073 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3075 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
3076 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
3080 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3081 ep_interval
= urb
->interval
;
3082 /* Convert to microframes */
3083 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3084 urb
->dev
->speed
== USB_SPEED_FULL
)
3086 /* FIXME change this to a warning and a suggestion to use the new API
3087 * to set the polling interval (once the API is added).
3089 if (xhci_interval
!= ep_interval
) {
3090 if (printk_ratelimit())
3091 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3092 " (%d microframe%s) than xHCI "
3093 "(%d microframe%s)\n",
3095 ep_interval
== 1 ? "" : "s",
3097 xhci_interval
== 1 ? "" : "s");
3098 urb
->interval
= xhci_interval
;
3099 /* Convert back to frames for LS/FS devices */
3100 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3101 urb
->dev
->speed
== USB_SPEED_FULL
)
3104 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3108 * The TD size is the number of bytes remaining in the TD (including this TRB),
3109 * right shifted by 10.
3110 * It must fit in bits 21:17, so it can't be bigger than 31.
3112 static u32
xhci_td_remainder(unsigned int remainder
)
3114 u32 max
= (1 << (21 - 17 + 1)) - 1;
3116 if ((remainder
>> 10) >= max
)
3119 return (remainder
>> 10) << 17;
3123 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3124 * packets remaining in the TD (*not* including this TRB).
3126 * Total TD packet count = total_packet_count =
3127 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3129 * Packets transferred up to and including this TRB = packets_transferred =
3130 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3132 * TD size = total_packet_count - packets_transferred
3134 * It must fit in bits 21:17, so it can't be bigger than 31.
3135 * The last TRB in a TD must have the TD size set to zero.
3137 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
3138 unsigned int total_packet_count
, struct urb
*urb
,
3139 unsigned int num_trbs_left
)
3141 int packets_transferred
;
3143 /* One TRB with a zero-length data packet. */
3144 if (num_trbs_left
== 0 || (running_total
== 0 && trb_buff_len
== 0))
3147 /* All the TRB queueing functions don't count the current TRB in
3150 packets_transferred
= (running_total
+ trb_buff_len
) /
3151 GET_MAX_PACKET(usb_endpoint_maxp(&urb
->ep
->desc
));
3153 if ((total_packet_count
- packets_transferred
) > 31)
3155 return (total_packet_count
- packets_transferred
) << 17;
3158 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3159 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3161 struct xhci_ring
*ep_ring
;
3162 unsigned int num_trbs
;
3163 struct urb_priv
*urb_priv
;
3165 struct scatterlist
*sg
;
3167 int trb_buff_len
, this_sg_len
, running_total
;
3168 unsigned int total_packet_count
;
3171 bool more_trbs_coming
;
3173 struct xhci_generic_trb
*start_trb
;
3176 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3180 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
3181 num_sgs
= urb
->num_mapped_sgs
;
3182 total_packet_count
= DIV_ROUND_UP(urb
->transfer_buffer_length
,
3183 usb_endpoint_maxp(&urb
->ep
->desc
));
3185 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3186 ep_index
, urb
->stream_id
,
3187 num_trbs
, urb
, 0, mem_flags
);
3188 if (trb_buff_len
< 0)
3189 return trb_buff_len
;
3191 urb_priv
= urb
->hcpriv
;
3192 td
= urb_priv
->td
[0];
3195 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3196 * until we've finished creating all the other TRBs. The ring's cycle
3197 * state may change as we enqueue the other TRBs, so save it too.
3199 start_trb
= &ep_ring
->enqueue
->generic
;
3200 start_cycle
= ep_ring
->cycle_state
;
3204 * How much data is in the first TRB?
3206 * There are three forces at work for TRB buffer pointers and lengths:
3207 * 1. We don't want to walk off the end of this sg-list entry buffer.
3208 * 2. The transfer length that the driver requested may be smaller than
3209 * the amount of memory allocated for this scatter-gather list.
3210 * 3. TRBs buffers can't cross 64KB boundaries.
3213 addr
= (u64
) sg_dma_address(sg
);
3214 this_sg_len
= sg_dma_len(sg
);
3215 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3216 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
3217 if (trb_buff_len
> urb
->transfer_buffer_length
)
3218 trb_buff_len
= urb
->transfer_buffer_length
;
3221 /* Queue the first TRB, even if it's zero-length */
3224 u32 length_field
= 0;
3227 /* Don't change the cycle bit of the first TRB until later */
3230 if (start_cycle
== 0)
3233 field
|= ep_ring
->cycle_state
;
3235 /* Chain all the TRBs together; clear the chain bit in the last
3236 * TRB to indicate it's the last TRB in the chain.
3241 /* FIXME - add check for ZERO_PACKET flag before this */
3242 td
->last_trb
= ep_ring
->enqueue
;
3246 /* Only set interrupt on short packet for IN endpoints */
3247 if (usb_urb_dir_in(urb
))
3250 if (TRB_MAX_BUFF_SIZE
-
3251 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
3252 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3253 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
3254 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
3255 (unsigned int) addr
+ trb_buff_len
);
3258 /* Set the TRB length, TD size, and interrupter fields. */
3259 if (xhci
->hci_version
< 0x100) {
3260 remainder
= xhci_td_remainder(
3261 urb
->transfer_buffer_length
-
3264 remainder
= xhci_v1_0_td_remainder(running_total
,
3265 trb_buff_len
, total_packet_count
, urb
,
3268 length_field
= TRB_LEN(trb_buff_len
) |
3273 more_trbs_coming
= true;
3275 more_trbs_coming
= false;
3276 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3277 lower_32_bits(addr
),
3278 upper_32_bits(addr
),
3280 field
| TRB_TYPE(TRB_NORMAL
));
3282 running_total
+= trb_buff_len
;
3284 /* Calculate length for next transfer --
3285 * Are we done queueing all the TRBs for this sg entry?
3287 this_sg_len
-= trb_buff_len
;
3288 if (this_sg_len
== 0) {
3293 addr
= (u64
) sg_dma_address(sg
);
3294 this_sg_len
= sg_dma_len(sg
);
3296 addr
+= trb_buff_len
;
3299 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3300 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
3301 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
3302 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
3304 urb
->transfer_buffer_length
- running_total
;
3305 } while (running_total
< urb
->transfer_buffer_length
);
3307 check_trb_math(urb
, num_trbs
, running_total
);
3308 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3309 start_cycle
, start_trb
);
3313 /* This is very similar to what ehci-q.c qtd_fill() does */
3314 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3315 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3317 struct xhci_ring
*ep_ring
;
3318 struct urb_priv
*urb_priv
;
3321 struct xhci_generic_trb
*start_trb
;
3323 bool more_trbs_coming
;
3325 u32 field
, length_field
;
3327 int running_total
, trb_buff_len
, ret
;
3328 unsigned int total_packet_count
;
3332 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3334 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3339 /* How much data is (potentially) left before the 64KB boundary? */
3340 running_total
= TRB_MAX_BUFF_SIZE
-
3341 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3342 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3344 /* If there's some data on this 64KB chunk, or we have to send a
3345 * zero-length transfer, we need at least one TRB
3347 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
3349 /* How many more 64KB chunks to transfer, how many more TRBs? */
3350 while (running_total
< urb
->transfer_buffer_length
) {
3352 running_total
+= TRB_MAX_BUFF_SIZE
;
3354 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3356 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3357 ep_index
, urb
->stream_id
,
3358 num_trbs
, urb
, 0, mem_flags
);
3362 urb_priv
= urb
->hcpriv
;
3363 td
= urb_priv
->td
[0];
3366 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3367 * until we've finished creating all the other TRBs. The ring's cycle
3368 * state may change as we enqueue the other TRBs, so save it too.
3370 start_trb
= &ep_ring
->enqueue
->generic
;
3371 start_cycle
= ep_ring
->cycle_state
;
3374 total_packet_count
= DIV_ROUND_UP(urb
->transfer_buffer_length
,
3375 usb_endpoint_maxp(&urb
->ep
->desc
));
3376 /* How much data is in the first TRB? */
3377 addr
= (u64
) urb
->transfer_dma
;
3378 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3379 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3380 if (trb_buff_len
> urb
->transfer_buffer_length
)
3381 trb_buff_len
= urb
->transfer_buffer_length
;
3385 /* Queue the first TRB, even if it's zero-length */
3390 /* Don't change the cycle bit of the first TRB until later */
3393 if (start_cycle
== 0)
3396 field
|= ep_ring
->cycle_state
;
3398 /* Chain all the TRBs together; clear the chain bit in the last
3399 * TRB to indicate it's the last TRB in the chain.
3404 /* FIXME - add check for ZERO_PACKET flag before this */
3405 td
->last_trb
= ep_ring
->enqueue
;
3409 /* Only set interrupt on short packet for IN endpoints */
3410 if (usb_urb_dir_in(urb
))
3413 /* Set the TRB length, TD size, and interrupter fields. */
3414 if (xhci
->hci_version
< 0x100) {
3415 remainder
= xhci_td_remainder(
3416 urb
->transfer_buffer_length
-
3419 remainder
= xhci_v1_0_td_remainder(running_total
,
3420 trb_buff_len
, total_packet_count
, urb
,
3423 length_field
= TRB_LEN(trb_buff_len
) |
3428 more_trbs_coming
= true;
3430 more_trbs_coming
= false;
3431 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3432 lower_32_bits(addr
),
3433 upper_32_bits(addr
),
3435 field
| TRB_TYPE(TRB_NORMAL
));
3437 running_total
+= trb_buff_len
;
3439 /* Calculate length for next transfer */
3440 addr
+= trb_buff_len
;
3441 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
3442 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
3443 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
3444 } while (running_total
< urb
->transfer_buffer_length
);
3446 check_trb_math(urb
, num_trbs
, running_total
);
3447 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3448 start_cycle
, start_trb
);
3452 /* Caller must have locked xhci->lock */
3453 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3454 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3456 struct xhci_ring
*ep_ring
;
3459 struct usb_ctrlrequest
*setup
;
3460 struct xhci_generic_trb
*start_trb
;
3462 u32 field
, length_field
;
3463 struct urb_priv
*urb_priv
;
3466 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3471 * Need to copy setup packet into setup TRB, so we can't use the setup
3474 if (!urb
->setup_packet
)
3477 /* 1 TRB for setup, 1 for status */
3480 * Don't need to check if we need additional event data and normal TRBs,
3481 * since data in control transfers will never get bigger than 16MB
3482 * XXX: can we get a buffer that crosses 64KB boundaries?
3484 if (urb
->transfer_buffer_length
> 0)
3486 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3487 ep_index
, urb
->stream_id
,
3488 num_trbs
, urb
, 0, mem_flags
);
3492 urb_priv
= urb
->hcpriv
;
3493 td
= urb_priv
->td
[0];
3496 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3497 * until we've finished creating all the other TRBs. The ring's cycle
3498 * state may change as we enqueue the other TRBs, so save it too.
3500 start_trb
= &ep_ring
->enqueue
->generic
;
3501 start_cycle
= ep_ring
->cycle_state
;
3503 /* Queue setup TRB - see section 6.4.1.2.1 */
3504 /* FIXME better way to translate setup_packet into two u32 fields? */
3505 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3507 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3508 if (start_cycle
== 0)
3511 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3512 if (xhci
->hci_version
== 0x100) {
3513 if (urb
->transfer_buffer_length
> 0) {
3514 if (setup
->bRequestType
& USB_DIR_IN
)
3515 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3517 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3521 queue_trb(xhci
, ep_ring
, true,
3522 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3523 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3524 TRB_LEN(8) | TRB_INTR_TARGET(0),
3525 /* Immediate data in pointer */
3528 /* If there's data, queue data TRBs */
3529 /* Only set interrupt on short packet for IN endpoints */
3530 if (usb_urb_dir_in(urb
))
3531 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3533 field
= TRB_TYPE(TRB_DATA
);
3535 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3536 xhci_td_remainder(urb
->transfer_buffer_length
) |
3538 if (urb
->transfer_buffer_length
> 0) {
3539 if (setup
->bRequestType
& USB_DIR_IN
)
3540 field
|= TRB_DIR_IN
;
3541 queue_trb(xhci
, ep_ring
, true,
3542 lower_32_bits(urb
->transfer_dma
),
3543 upper_32_bits(urb
->transfer_dma
),
3545 field
| ep_ring
->cycle_state
);
3548 /* Save the DMA address of the last TRB in the TD */
3549 td
->last_trb
= ep_ring
->enqueue
;
3551 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3552 /* If the device sent data, the status stage is an OUT transfer */
3553 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3557 queue_trb(xhci
, ep_ring
, false,
3561 /* Event on completion */
3562 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3564 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3565 start_cycle
, start_trb
);
3569 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3570 struct urb
*urb
, int i
)
3575 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3576 td_len
= urb
->iso_frame_desc
[i
].length
;
3578 num_trbs
= DIV_ROUND_UP(td_len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3587 * The transfer burst count field of the isochronous TRB defines the number of
3588 * bursts that are required to move all packets in this TD. Only SuperSpeed
3589 * devices can burst up to bMaxBurst number of packets per service interval.
3590 * This field is zero based, meaning a value of zero in the field means one
3591 * burst. Basically, for everything but SuperSpeed devices, this field will be
3592 * zero. Only xHCI 1.0 host controllers support this field.
3594 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3595 struct usb_device
*udev
,
3596 struct urb
*urb
, unsigned int total_packet_count
)
3598 unsigned int max_burst
;
3600 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3603 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3604 return DIV_ROUND_UP(total_packet_count
, max_burst
+ 1) - 1;
3608 * Returns the number of packets in the last "burst" of packets. This field is
3609 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3610 * the last burst packet count is equal to the total number of packets in the
3611 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3612 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3613 * contain 1 to (bMaxBurst + 1) packets.
3615 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3616 struct usb_device
*udev
,
3617 struct urb
*urb
, unsigned int total_packet_count
)
3619 unsigned int max_burst
;
3620 unsigned int residue
;
3622 if (xhci
->hci_version
< 0x100)
3625 switch (udev
->speed
) {
3626 case USB_SPEED_SUPER
:
3627 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3628 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3629 residue
= total_packet_count
% (max_burst
+ 1);
3630 /* If residue is zero, the last burst contains (max_burst + 1)
3631 * number of packets, but the TLBPC field is zero-based.
3637 if (total_packet_count
== 0)
3639 return total_packet_count
- 1;
3643 /* This is for isoc transfer */
3644 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3645 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3647 struct xhci_ring
*ep_ring
;
3648 struct urb_priv
*urb_priv
;
3650 int num_tds
, trbs_per_td
;
3651 struct xhci_generic_trb
*start_trb
;
3654 u32 field
, length_field
;
3655 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3656 u64 start_addr
, addr
;
3658 bool more_trbs_coming
;
3660 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3662 num_tds
= urb
->number_of_packets
;
3664 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3668 start_addr
= (u64
) urb
->transfer_dma
;
3669 start_trb
= &ep_ring
->enqueue
->generic
;
3670 start_cycle
= ep_ring
->cycle_state
;
3672 urb_priv
= urb
->hcpriv
;
3673 /* Queue the first TRB, even if it's zero-length */
3674 for (i
= 0; i
< num_tds
; i
++) {
3675 unsigned int total_packet_count
;
3676 unsigned int burst_count
;
3677 unsigned int residue
;
3681 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3682 td_len
= urb
->iso_frame_desc
[i
].length
;
3683 td_remain_len
= td_len
;
3684 total_packet_count
= DIV_ROUND_UP(td_len
,
3686 usb_endpoint_maxp(&urb
->ep
->desc
)));
3687 /* A zero-length transfer still involves at least one packet. */
3688 if (total_packet_count
== 0)
3689 total_packet_count
++;
3690 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3691 total_packet_count
);
3692 residue
= xhci_get_last_burst_packet_count(xhci
,
3693 urb
->dev
, urb
, total_packet_count
);
3695 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3697 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3698 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3705 td
= urb_priv
->td
[i
];
3706 for (j
= 0; j
< trbs_per_td
; j
++) {
3711 field
= TRB_TBC(burst_count
) |
3713 /* Queue the isoc TRB */
3714 field
|= TRB_TYPE(TRB_ISOC
);
3715 /* Assume URB_ISO_ASAP is set */
3718 if (start_cycle
== 0)
3721 field
|= ep_ring
->cycle_state
;
3724 /* Queue other normal TRBs */
3725 field
|= TRB_TYPE(TRB_NORMAL
);
3726 field
|= ep_ring
->cycle_state
;
3729 /* Only set interrupt on short packet for IN EPs */
3730 if (usb_urb_dir_in(urb
))
3733 /* Chain all the TRBs together; clear the chain bit in
3734 * the last TRB to indicate it's the last TRB in the
3737 if (j
< trbs_per_td
- 1) {
3739 more_trbs_coming
= true;
3741 td
->last_trb
= ep_ring
->enqueue
;
3743 if (xhci
->hci_version
== 0x100 &&
3746 /* Set BEI bit except for the last td */
3747 if (i
< num_tds
- 1)
3750 more_trbs_coming
= false;
3753 /* Calculate TRB length */
3754 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3755 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3756 if (trb_buff_len
> td_remain_len
)
3757 trb_buff_len
= td_remain_len
;
3759 /* Set the TRB length, TD size, & interrupter fields. */
3760 if (xhci
->hci_version
< 0x100) {
3761 remainder
= xhci_td_remainder(
3762 td_len
- running_total
);
3764 remainder
= xhci_v1_0_td_remainder(
3765 running_total
, trb_buff_len
,
3766 total_packet_count
, urb
,
3767 (trbs_per_td
- j
- 1));
3769 length_field
= TRB_LEN(trb_buff_len
) |
3773 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3774 lower_32_bits(addr
),
3775 upper_32_bits(addr
),
3778 running_total
+= trb_buff_len
;
3780 addr
+= trb_buff_len
;
3781 td_remain_len
-= trb_buff_len
;
3784 /* Check TD length */
3785 if (running_total
!= td_len
) {
3786 xhci_err(xhci
, "ISOC TD length unmatch\n");
3792 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3793 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3794 usb_amd_quirk_pll_disable();
3796 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3798 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3799 start_cycle
, start_trb
);
3802 /* Clean up a partially enqueued isoc transfer. */
3804 for (i
--; i
>= 0; i
--)
3805 list_del_init(&urb_priv
->td
[i
]->td_list
);
3807 /* Use the first TD as a temporary variable to turn the TDs we've queued
3808 * into No-ops with a software-owned cycle bit. That way the hardware
3809 * won't accidentally start executing bogus TDs when we partially
3810 * overwrite them. td->first_trb and td->start_seg are already set.
3812 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3813 /* Every TRB except the first & last will have its cycle bit flipped. */
3814 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3816 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3817 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3818 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3819 ep_ring
->cycle_state
= start_cycle
;
3820 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
3821 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3826 * Check transfer ring to guarantee there is enough room for the urb.
3827 * Update ISO URB start_frame and interval.
3828 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3829 * update the urb->start_frame by now.
3830 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3832 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3833 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3835 struct xhci_virt_device
*xdev
;
3836 struct xhci_ring
*ep_ring
;
3837 struct xhci_ep_ctx
*ep_ctx
;
3841 int num_tds
, num_trbs
, i
;
3844 xdev
= xhci
->devs
[slot_id
];
3845 ep_ring
= xdev
->eps
[ep_index
].ring
;
3846 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3849 num_tds
= urb
->number_of_packets
;
3850 for (i
= 0; i
< num_tds
; i
++)
3851 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3853 /* Check the ring to guarantee there is enough room for the whole urb.
3854 * Do not insert any td of the urb to the ring if the check failed.
3856 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3857 num_trbs
, mem_flags
);
3861 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3862 start_frame
&= 0x3fff;
3864 urb
->start_frame
= start_frame
;
3865 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3866 urb
->dev
->speed
== USB_SPEED_FULL
)
3867 urb
->start_frame
>>= 3;
3869 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3870 ep_interval
= urb
->interval
;
3871 /* Convert to microframes */
3872 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3873 urb
->dev
->speed
== USB_SPEED_FULL
)
3875 /* FIXME change this to a warning and a suggestion to use the new API
3876 * to set the polling interval (once the API is added).
3878 if (xhci_interval
!= ep_interval
) {
3879 if (printk_ratelimit())
3880 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3881 " (%d microframe%s) than xHCI "
3882 "(%d microframe%s)\n",
3884 ep_interval
== 1 ? "" : "s",
3886 xhci_interval
== 1 ? "" : "s");
3887 urb
->interval
= xhci_interval
;
3888 /* Convert back to frames for LS/FS devices */
3889 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3890 urb
->dev
->speed
== USB_SPEED_FULL
)
3893 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
3895 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3898 /**** Command Ring Operations ****/
3900 /* Generic function for queueing a command TRB on the command ring.
3901 * Check to make sure there's room on the command ring for one command TRB.
3902 * Also check that there's room reserved for commands that must not fail.
3903 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3904 * then only check for the number of reserved spots.
3905 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3906 * because the command event handler may want to resubmit a failed command.
3908 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3909 u32 field3
, u32 field4
, bool command_must_succeed
)
3911 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3914 if (!command_must_succeed
)
3917 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3918 reserved_trbs
, GFP_ATOMIC
);
3920 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3921 if (command_must_succeed
)
3922 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3923 "unfailable commands failed.\n");
3926 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
3927 field4
| xhci
->cmd_ring
->cycle_state
);
3931 /* Queue a slot enable or disable request on the command ring */
3932 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3934 return queue_command(xhci
, 0, 0, 0,
3935 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3938 /* Queue an address device command TRB */
3939 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3942 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3943 upper_32_bits(in_ctx_ptr
), 0,
3944 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3948 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3949 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3951 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3954 /* Queue a reset device command TRB */
3955 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3957 return queue_command(xhci
, 0, 0, 0,
3958 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3962 /* Queue a configure endpoint command TRB */
3963 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3964 u32 slot_id
, bool command_must_succeed
)
3966 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3967 upper_32_bits(in_ctx_ptr
), 0,
3968 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3969 command_must_succeed
);
3972 /* Queue an evaluate context command TRB */
3973 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3974 u32 slot_id
, bool command_must_succeed
)
3976 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3977 upper_32_bits(in_ctx_ptr
), 0,
3978 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3979 command_must_succeed
);
3983 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3984 * activity on an endpoint that is about to be suspended.
3986 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3987 unsigned int ep_index
, int suspend
)
3989 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3990 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3991 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3992 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3994 return queue_command(xhci
, 0, 0, 0,
3995 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3998 /* Set Transfer Ring Dequeue Pointer command.
3999 * This should not be used for endpoints that have streams enabled.
4001 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
4002 unsigned int ep_index
, unsigned int stream_id
,
4003 struct xhci_segment
*deq_seg
,
4004 union xhci_trb
*deq_ptr
, u32 cycle_state
)
4007 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4008 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4009 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
4010 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
4011 struct xhci_virt_ep
*ep
;
4013 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
4015 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4016 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
4020 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
4021 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
4022 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
4023 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
4026 ep
->queued_deq_seg
= deq_seg
;
4027 ep
->queued_deq_ptr
= deq_ptr
;
4028 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
4029 upper_32_bits(addr
), trb_stream_id
,
4030 trb_slot_id
| trb_ep_index
| type
, false);
4033 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
4034 unsigned int ep_index
)
4036 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
4037 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
4038 u32 type
= TRB_TYPE(TRB_RESET_EP
);
4040 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,