2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
119 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
121 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
122 return TRB_TYPE_LINK_LE32(link
->control
);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd
*xhci
,
130 struct xhci_ring
*ring
,
131 struct xhci_segment
**seg
,
132 union xhci_trb
**trb
)
134 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
136 *trb
= ((*seg
)->trbs
);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
148 unsigned long long addr
;
153 * If this is not event ring, and the dequeue pointer
154 * is not on a link TRB, there is one more usable TRB
156 if (ring
->type
!= TYPE_EVENT
&&
157 !last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
))
158 ring
->num_trbs_free
++;
162 * Update the dequeue pointer further if that was a link TRB or
163 * we're at the end of an event ring segment (which doesn't have
166 if (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
)) {
167 if (ring
->type
== TYPE_EVENT
&&
168 last_trb_on_last_seg(xhci
, ring
,
169 ring
->deq_seg
, ring
->dequeue
)) {
170 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
172 ring
->deq_seg
= ring
->deq_seg
->next
;
173 ring
->dequeue
= ring
->deq_seg
->trbs
;
177 } while (last_trb(xhci
, ring
, ring
->deq_seg
, ring
->dequeue
));
179 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
183 * See Cycle bit rules. SW is the consumer for the event ring only.
184 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
186 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
187 * chain bit is set), then set the chain bit in all the following link TRBs.
188 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
189 * have their chain bit cleared (so that each Link TRB is a separate TD).
191 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
192 * set, but other sections talk about dealing with the chain bit set. This was
193 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
194 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
196 * @more_trbs_coming: Will you enqueue more TRBs before calling
197 * prepare_transfer()?
199 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
200 bool more_trbs_coming
)
203 union xhci_trb
*next
;
204 unsigned long long addr
;
206 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
207 /* If this is not event ring, there is one less usable TRB */
208 if (ring
->type
!= TYPE_EVENT
&&
209 !last_trb(xhci
, ring
, ring
->enq_seg
, ring
->enqueue
))
210 ring
->num_trbs_free
--;
211 next
= ++(ring
->enqueue
);
214 /* Update the dequeue pointer further if that was a link TRB or we're at
215 * the end of an event ring segment (which doesn't have link TRBS)
217 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
218 if (ring
->type
!= TYPE_EVENT
) {
220 * If the caller doesn't plan on enqueueing more
221 * TDs before ringing the doorbell, then we
222 * don't want to give the link TRB to the
223 * hardware just yet. We'll give the link TRB
224 * back in prepare_ring() just before we enqueue
225 * the TD at the top of the ring.
227 if (!chain
&& !more_trbs_coming
)
230 /* If we're not dealing with 0.95 hardware or
231 * isoc rings on AMD 0.96 host,
232 * carry over the chain bit of the previous TRB
233 * (which may mean the chain bit is cleared).
235 if (!(ring
->type
== TYPE_ISOC
&&
236 (xhci
->quirks
& XHCI_AMD_0x96_HOST
))
237 && !xhci_link_trb_quirk(xhci
)) {
238 next
->link
.control
&=
239 cpu_to_le32(~TRB_CHAIN
);
240 next
->link
.control
|=
243 /* Give this link TRB to the hardware */
245 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
247 /* Toggle the cycle bit after the last ring segment. */
248 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
249 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
252 ring
->enq_seg
= ring
->enq_seg
->next
;
253 ring
->enqueue
= ring
->enq_seg
->trbs
;
254 next
= ring
->enqueue
;
256 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
260 * Check to see if there's room to enqueue num_trbs on the ring and make sure
261 * enqueue pointer will not advance into dequeue segment. See rules above.
263 static inline int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
264 unsigned int num_trbs
)
266 int num_trbs_in_deq_seg
;
268 if (ring
->num_trbs_free
< num_trbs
)
271 if (ring
->type
!= TYPE_COMMAND
&& ring
->type
!= TYPE_EVENT
) {
272 num_trbs_in_deq_seg
= ring
->dequeue
- ring
->deq_seg
->trbs
;
273 if (ring
->num_trbs_free
< num_trbs
+ num_trbs_in_deq_seg
)
280 /* Ring the host controller doorbell after placing a command on the ring */
281 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
283 if (!(xhci
->cmd_ring_state
& CMD_RING_STATE_RUNNING
))
286 xhci_dbg(xhci
, "// Ding dong!\n");
287 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
288 /* Flush PCI posted writes */
289 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
292 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
293 unsigned int slot_id
,
294 unsigned int ep_index
,
295 unsigned int stream_id
)
297 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
298 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
299 unsigned int ep_state
= ep
->ep_state
;
301 /* Don't ring the doorbell for this endpoint if there are pending
302 * cancellations because we don't want to interrupt processing.
303 * We don't want to restart any stream rings if there's a set dequeue
304 * pointer command pending because the device can choose to start any
305 * stream once the endpoint is on the HW schedule.
306 * FIXME - check all the stream rings for pending cancellations.
308 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
309 (ep_state
& EP_HALTED
))
311 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
312 /* The CPU has better things to do at this point than wait for a
313 * write-posting flush. It'll get there soon enough.
317 /* Ring the doorbell for any rings with pending URBs */
318 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
319 unsigned int slot_id
,
320 unsigned int ep_index
)
322 unsigned int stream_id
;
323 struct xhci_virt_ep
*ep
;
325 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
327 /* A ring has pending URBs if its TD list is not empty */
328 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
329 if (!(list_empty(&ep
->ring
->td_list
)))
330 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
334 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
336 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
337 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
338 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
344 * Find the segment that trb is in. Start searching in start_seg.
345 * If we must move past a segment that has a link TRB with a toggle cycle state
346 * bit set, then we will toggle the value pointed at by cycle_state.
348 static struct xhci_segment
*find_trb_seg(
349 struct xhci_segment
*start_seg
,
350 union xhci_trb
*trb
, int *cycle_state
)
352 struct xhci_segment
*cur_seg
= start_seg
;
353 struct xhci_generic_trb
*generic_trb
;
355 while (cur_seg
->trbs
> trb
||
356 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
357 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
358 if (generic_trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
))
360 cur_seg
= cur_seg
->next
;
361 if (cur_seg
== start_seg
)
362 /* Looped over the entire list. Oops! */
369 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
370 unsigned int slot_id
, unsigned int ep_index
,
371 unsigned int stream_id
)
373 struct xhci_virt_ep
*ep
;
375 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
376 /* Common case: no streams */
377 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
380 if (stream_id
== 0) {
382 "WARN: Slot ID %u, ep index %u has streams, "
383 "but URB has no stream ID.\n",
388 if (stream_id
< ep
->stream_info
->num_streams
)
389 return ep
->stream_info
->stream_rings
[stream_id
];
392 "WARN: Slot ID %u, ep index %u has "
393 "stream IDs 1 to %u allocated, "
394 "but stream ID %u is requested.\n",
396 ep
->stream_info
->num_streams
- 1,
401 /* Get the right ring for the given URB.
402 * If the endpoint supports streams, boundary check the URB's stream ID.
403 * If the endpoint doesn't support streams, return the singular endpoint ring.
405 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
408 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
409 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
413 * Move the xHC's endpoint ring dequeue pointer past cur_td.
414 * Record the new state of the xHC's endpoint ring dequeue segment,
415 * dequeue pointer, and new consumer cycle state in state.
416 * Update our internal representation of the ring's dequeue pointer.
418 * We do this in three jumps:
419 * - First we update our new ring state to be the same as when the xHC stopped.
420 * - Then we traverse the ring to find the segment that contains
421 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
422 * any link TRBs with the toggle cycle bit set.
423 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
424 * if we've moved it past a link TRB with the toggle cycle bit set.
426 * Some of the uses of xhci_generic_trb are grotty, but if they're done
427 * with correct __le32 accesses they should work fine. Only users of this are
430 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
431 unsigned int slot_id
, unsigned int ep_index
,
432 unsigned int stream_id
, struct xhci_td
*cur_td
,
433 struct xhci_dequeue_state
*state
)
435 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
436 struct xhci_ring
*ep_ring
;
437 struct xhci_generic_trb
*trb
;
438 struct xhci_ep_ctx
*ep_ctx
;
441 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
442 ep_index
, stream_id
);
444 xhci_warn(xhci
, "WARN can't find new dequeue state "
445 "for invalid stream ID %u.\n",
449 state
->new_cycle_state
= 0;
450 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
451 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
452 dev
->eps
[ep_index
].stopped_trb
,
453 &state
->new_cycle_state
);
454 if (!state
->new_deq_seg
) {
459 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
460 xhci_dbg(xhci
, "Finding endpoint context\n");
461 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
462 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
464 state
->new_deq_ptr
= cur_td
->last_trb
;
465 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
466 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
468 &state
->new_cycle_state
);
469 if (!state
->new_deq_seg
) {
474 trb
= &state
->new_deq_ptr
->generic
;
475 if (TRB_TYPE_LINK_LE32(trb
->field
[3]) &&
476 (trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
)))
477 state
->new_cycle_state
^= 0x1;
478 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
481 * If there is only one segment in a ring, find_trb_seg()'s while loop
482 * will not run, and it will return before it has a chance to see if it
483 * needs to toggle the cycle bit. It can't tell if the stalled transfer
484 * ended just before the link TRB on a one-segment ring, or if the TD
485 * wrapped around the top of the ring, because it doesn't have the TD in
486 * question. Look for the one-segment case where stalled TRB's address
487 * is greater than the new dequeue pointer address.
489 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
490 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
491 state
->new_cycle_state
^= 0x1;
492 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
494 /* Don't update the ring cycle state for the producer (us). */
495 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
497 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
498 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
499 (unsigned long long) addr
);
502 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
503 * (The last TRB actually points to the ring enqueue pointer, which is not part
504 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
506 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
507 struct xhci_td
*cur_td
, bool flip_cycle
)
509 struct xhci_segment
*cur_seg
;
510 union xhci_trb
*cur_trb
;
512 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
514 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
515 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
516 /* Unchain any chained Link TRBs, but
517 * leave the pointers intact.
519 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
520 /* Flip the cycle bit (link TRBs can't be the first
524 cur_trb
->generic
.field
[3] ^=
525 cpu_to_le32(TRB_CYCLE
);
526 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
527 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
528 "in seg %p (0x%llx dma)\n",
530 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
532 (unsigned long long)cur_seg
->dma
);
534 cur_trb
->generic
.field
[0] = 0;
535 cur_trb
->generic
.field
[1] = 0;
536 cur_trb
->generic
.field
[2] = 0;
537 /* Preserve only the cycle bit of this TRB */
538 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
539 /* Flip the cycle bit except on the first or last TRB */
540 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
541 cur_trb
!= cur_td
->last_trb
)
542 cur_trb
->generic
.field
[3] ^=
543 cpu_to_le32(TRB_CYCLE
);
544 cur_trb
->generic
.field
[3] |= cpu_to_le32(
545 TRB_TYPE(TRB_TR_NOOP
));
546 xhci_dbg(xhci
, "TRB to noop at offset 0x%llx\n",
548 xhci_trb_virt_to_dma(cur_seg
, cur_trb
));
550 if (cur_trb
== cur_td
->last_trb
)
555 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
556 unsigned int ep_index
, unsigned int stream_id
,
557 struct xhci_segment
*deq_seg
,
558 union xhci_trb
*deq_ptr
, u32 cycle_state
);
560 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
561 unsigned int slot_id
, unsigned int ep_index
,
562 unsigned int stream_id
,
563 struct xhci_dequeue_state
*deq_state
)
565 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
567 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
568 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
569 deq_state
->new_deq_seg
,
570 (unsigned long long)deq_state
->new_deq_seg
->dma
,
571 deq_state
->new_deq_ptr
,
572 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
573 deq_state
->new_cycle_state
);
574 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
575 deq_state
->new_deq_seg
,
576 deq_state
->new_deq_ptr
,
577 (u32
) deq_state
->new_cycle_state
);
578 /* Stop the TD queueing code from ringing the doorbell until
579 * this command completes. The HC won't set the dequeue pointer
580 * if the ring is running, and ringing the doorbell starts the
583 ep
->ep_state
|= SET_DEQ_PENDING
;
586 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
587 struct xhci_virt_ep
*ep
)
589 ep
->ep_state
&= ~EP_HALT_PENDING
;
590 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
591 * timer is running on another CPU, we don't decrement stop_cmds_pending
592 * (since we didn't successfully stop the watchdog timer).
594 if (del_timer(&ep
->stop_cmd_timer
))
595 ep
->stop_cmds_pending
--;
598 /* Must be called with xhci->lock held in interrupt context */
599 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
600 struct xhci_td
*cur_td
, int status
, char *adjective
)
604 struct urb_priv
*urb_priv
;
607 urb_priv
= urb
->hcpriv
;
609 hcd
= bus_to_hcd(urb
->dev
->bus
);
611 /* Only giveback urb when this is the last td in urb */
612 if (urb_priv
->td_cnt
== urb_priv
->length
) {
613 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
614 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
615 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
616 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
617 usb_amd_quirk_pll_enable();
620 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
622 spin_unlock(&xhci
->lock
);
623 usb_hcd_giveback_urb(hcd
, urb
, status
);
624 xhci_urb_free_priv(xhci
, urb_priv
);
625 spin_lock(&xhci
->lock
);
630 * When we get a command completion for a Stop Endpoint Command, we need to
631 * unlink any cancelled TDs from the ring. There are two ways to do that:
633 * 1. If the HW was in the middle of processing the TD that needs to be
634 * cancelled, then we must move the ring's dequeue pointer past the last TRB
635 * in the TD with a Set Dequeue Pointer Command.
636 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
637 * bit cleared) so that the HW will skip over them.
639 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
640 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
642 unsigned int slot_id
;
643 unsigned int ep_index
;
644 struct xhci_virt_device
*virt_dev
;
645 struct xhci_ring
*ep_ring
;
646 struct xhci_virt_ep
*ep
;
647 struct list_head
*entry
;
648 struct xhci_td
*cur_td
= NULL
;
649 struct xhci_td
*last_unlinked_td
;
651 struct xhci_dequeue_state deq_state
;
653 if (unlikely(TRB_TO_SUSPEND_PORT(
654 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
655 slot_id
= TRB_TO_SLOT_ID(
656 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
657 virt_dev
= xhci
->devs
[slot_id
];
659 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
662 xhci_warn(xhci
, "Stop endpoint command "
663 "completion for disabled slot %u\n",
668 memset(&deq_state
, 0, sizeof(deq_state
));
669 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
670 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
671 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
673 if (list_empty(&ep
->cancelled_td_list
)) {
674 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
675 ep
->stopped_td
= NULL
;
676 ep
->stopped_trb
= NULL
;
677 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
681 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
682 * We have the xHCI lock, so nothing can modify this list until we drop
683 * it. We're also in the event handler, so we can't get re-interrupted
684 * if another Stop Endpoint command completes
686 list_for_each(entry
, &ep
->cancelled_td_list
) {
687 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
688 xhci_dbg(xhci
, "Removing canceled TD starting at 0x%llx (dma).\n",
689 (unsigned long long)xhci_trb_virt_to_dma(
690 cur_td
->start_seg
, cur_td
->first_trb
));
691 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
693 /* This shouldn't happen unless a driver is mucking
694 * with the stream ID after submission. This will
695 * leave the TD on the hardware ring, and the hardware
696 * will try to execute it, and may access a buffer
697 * that has already been freed. In the best case, the
698 * hardware will execute it, and the event handler will
699 * ignore the completion event for that TD, since it was
700 * removed from the td_list for that endpoint. In
701 * short, don't muck with the stream ID after
704 xhci_warn(xhci
, "WARN Cancelled URB %p "
705 "has invalid stream ID %u.\n",
707 cur_td
->urb
->stream_id
);
708 goto remove_finished_td
;
711 * If we stopped on the TD we need to cancel, then we have to
712 * move the xHC endpoint ring dequeue pointer past this TD.
714 if (cur_td
== ep
->stopped_td
)
715 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
716 cur_td
->urb
->stream_id
,
719 td_to_noop(xhci
, ep_ring
, cur_td
, false);
722 * The event handler won't see a completion for this TD anymore,
723 * so remove it from the endpoint ring's TD list. Keep it in
724 * the cancelled TD list for URB completion later.
726 list_del_init(&cur_td
->td_list
);
728 last_unlinked_td
= cur_td
;
729 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
731 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
732 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
733 xhci_queue_new_dequeue_state(xhci
,
735 ep
->stopped_td
->urb
->stream_id
,
737 xhci_ring_cmd_db(xhci
);
739 /* Otherwise ring the doorbell(s) to restart queued transfers */
740 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
742 ep
->stopped_td
= NULL
;
743 ep
->stopped_trb
= NULL
;
746 * Drop the lock and complete the URBs in the cancelled TD list.
747 * New TDs to be cancelled might be added to the end of the list before
748 * we can complete all the URBs for the TDs we already unlinked.
749 * So stop when we've completed the URB for the last TD we unlinked.
752 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
753 struct xhci_td
, cancelled_td_list
);
754 list_del_init(&cur_td
->cancelled_td_list
);
756 /* Clean up the cancelled URB */
757 /* Doesn't matter what we pass for status, since the core will
758 * just overwrite it (because the URB has been unlinked).
760 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
762 /* Stop processing the cancelled list if the watchdog timer is
765 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
767 } while (cur_td
!= last_unlinked_td
);
769 /* Return to the event handler with xhci->lock re-acquired */
772 /* Watchdog timer function for when a stop endpoint command fails to complete.
773 * In this case, we assume the host controller is broken or dying or dead. The
774 * host may still be completing some other events, so we have to be careful to
775 * let the event ring handler and the URB dequeueing/enqueueing functions know
776 * through xhci->state.
778 * The timer may also fire if the host takes a very long time to respond to the
779 * command, and the stop endpoint command completion handler cannot delete the
780 * timer before the timer function is called. Another endpoint cancellation may
781 * sneak in before the timer function can grab the lock, and that may queue
782 * another stop endpoint command and add the timer back. So we cannot use a
783 * simple flag to say whether there is a pending stop endpoint command for a
784 * particular endpoint.
786 * Instead we use a combination of that flag and a counter for the number of
787 * pending stop endpoint commands. If the timer is the tail end of the last
788 * stop endpoint command, and the endpoint's command is still pending, we assume
791 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
793 struct xhci_hcd
*xhci
;
794 struct xhci_virt_ep
*ep
;
795 struct xhci_virt_ep
*temp_ep
;
796 struct xhci_ring
*ring
;
797 struct xhci_td
*cur_td
;
801 ep
= (struct xhci_virt_ep
*) arg
;
804 spin_lock_irqsave(&xhci
->lock
, flags
);
806 ep
->stop_cmds_pending
--;
807 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
808 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
809 "xHCI as DYING, exiting.\n");
810 spin_unlock_irqrestore(&xhci
->lock
, flags
);
813 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
814 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
816 spin_unlock_irqrestore(&xhci
->lock
, flags
);
820 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
821 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
822 /* Oops, HC is dead or dying or at least not responding to the stop
825 xhci
->xhc_state
|= XHCI_STATE_DYING
;
826 /* Disable interrupts from the host controller and start halting it */
828 spin_unlock_irqrestore(&xhci
->lock
, flags
);
830 ret
= xhci_halt(xhci
);
832 spin_lock_irqsave(&xhci
->lock
, flags
);
834 /* This is bad; the host is not responding to commands and it's
835 * not allowing itself to be halted. At least interrupts are
836 * disabled. If we call usb_hc_died(), it will attempt to
837 * disconnect all device drivers under this host. Those
838 * disconnect() methods will wait for all URBs to be unlinked,
839 * so we must complete them.
841 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
842 xhci_warn(xhci
, "Completing active URBs anyway.\n");
843 /* We could turn all TDs on the rings to no-ops. This won't
844 * help if the host has cached part of the ring, and is slow if
845 * we want to preserve the cycle bit. Skip it and hope the host
846 * doesn't touch the memory.
849 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
852 for (j
= 0; j
< 31; j
++) {
853 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
854 ring
= temp_ep
->ring
;
857 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
858 "ep index %u\n", i
, j
);
859 while (!list_empty(&ring
->td_list
)) {
860 cur_td
= list_first_entry(&ring
->td_list
,
863 list_del_init(&cur_td
->td_list
);
864 if (!list_empty(&cur_td
->cancelled_td_list
))
865 list_del_init(&cur_td
->cancelled_td_list
);
866 xhci_giveback_urb_in_irq(xhci
, cur_td
,
867 -ESHUTDOWN
, "killed");
869 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
870 cur_td
= list_first_entry(
871 &temp_ep
->cancelled_td_list
,
874 list_del_init(&cur_td
->cancelled_td_list
);
875 xhci_giveback_urb_in_irq(xhci
, cur_td
,
876 -ESHUTDOWN
, "killed");
880 spin_unlock_irqrestore(&xhci
->lock
, flags
);
881 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
882 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
883 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
887 static void update_ring_for_set_deq_completion(struct xhci_hcd
*xhci
,
888 struct xhci_virt_device
*dev
,
889 struct xhci_ring
*ep_ring
,
890 unsigned int ep_index
)
892 union xhci_trb
*dequeue_temp
;
893 int num_trbs_free_temp
;
896 num_trbs_free_temp
= ep_ring
->num_trbs_free
;
897 dequeue_temp
= ep_ring
->dequeue
;
899 /* If we get two back-to-back stalls, and the first stalled transfer
900 * ends just before a link TRB, the dequeue pointer will be left on
901 * the link TRB by the code in the while loop. So we have to update
902 * the dequeue pointer one segment further, or we'll jump off
903 * the segment into la-la-land.
905 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
, ep_ring
->dequeue
)) {
906 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
907 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
910 while (ep_ring
->dequeue
!= dev
->eps
[ep_index
].queued_deq_ptr
) {
911 /* We have more usable TRBs */
912 ep_ring
->num_trbs_free
++;
914 if (last_trb(xhci
, ep_ring
, ep_ring
->deq_seg
,
916 if (ep_ring
->dequeue
==
917 dev
->eps
[ep_index
].queued_deq_ptr
)
919 ep_ring
->deq_seg
= ep_ring
->deq_seg
->next
;
920 ep_ring
->dequeue
= ep_ring
->deq_seg
->trbs
;
922 if (ep_ring
->dequeue
== dequeue_temp
) {
929 xhci_dbg(xhci
, "Unable to find new dequeue pointer\n");
930 ep_ring
->num_trbs_free
= num_trbs_free_temp
;
935 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
936 * we need to clear the set deq pending flag in the endpoint ring state, so that
937 * the TD queueing code can ring the doorbell again. We also need to ring the
938 * endpoint doorbell to restart the ring, but only if there aren't more
939 * cancellations pending.
941 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
942 struct xhci_event_cmd
*event
,
945 unsigned int slot_id
;
946 unsigned int ep_index
;
947 unsigned int stream_id
;
948 struct xhci_ring
*ep_ring
;
949 struct xhci_virt_device
*dev
;
950 struct xhci_ep_ctx
*ep_ctx
;
951 struct xhci_slot_ctx
*slot_ctx
;
953 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
954 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
955 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
956 dev
= xhci
->devs
[slot_id
];
958 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
960 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
961 "freed stream ID %u\n",
963 /* XXX: Harmless??? */
964 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
968 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
969 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
971 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
972 unsigned int ep_state
;
973 unsigned int slot_state
;
975 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
977 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
978 "of stream ID configuration\n");
981 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
982 "to incorrect slot or ep state.\n");
983 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
984 ep_state
&= EP_STATE_MASK
;
985 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
986 slot_state
= GET_SLOT_STATE(slot_state
);
987 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
988 slot_state
, ep_state
);
991 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
992 "slot %u was not enabled.\n", slot_id
);
995 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
996 "completion code of %u.\n",
997 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1000 /* OK what do we do now? The endpoint state is hosed, and we
1001 * should never get to this point if the synchronization between
1002 * queueing, and endpoint state are correct. This might happen
1003 * if the device gets disconnected after we've finished
1004 * cancelling URBs, which might not be an error...
1007 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1008 le64_to_cpu(ep_ctx
->deq
));
1009 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
1010 dev
->eps
[ep_index
].queued_deq_ptr
) ==
1011 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
1012 /* Update the ring's dequeue segment and dequeue pointer
1013 * to reflect the new position.
1015 update_ring_for_set_deq_completion(xhci
, dev
,
1018 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
1019 "Ptr command & xHCI internal state.\n");
1020 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
1021 dev
->eps
[ep_index
].queued_deq_seg
,
1022 dev
->eps
[ep_index
].queued_deq_ptr
);
1026 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
1027 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1028 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1029 /* Restart any rings with pending URBs */
1030 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1033 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1034 struct xhci_event_cmd
*event
,
1035 union xhci_trb
*trb
)
1038 unsigned int ep_index
;
1040 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1041 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1042 /* This command will only fail if the endpoint wasn't halted,
1043 * but we don't care.
1045 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1046 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1048 /* HW with the reset endpoint quirk needs to have a configure endpoint
1049 * command complete before the endpoint can be used. Queue that here
1050 * because the HW can't handle two commands being queued in a row.
1052 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1053 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1054 xhci_queue_configure_endpoint(xhci
,
1055 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1057 xhci_ring_cmd_db(xhci
);
1059 /* Clear our internal halted state and restart the ring(s) */
1060 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1061 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1065 /* Check to see if a command in the device's command queue matches this one.
1066 * Signal the completion or free the command, and return 1. Return 0 if the
1067 * completed command isn't at the head of the command list.
1069 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1070 struct xhci_virt_device
*virt_dev
,
1071 struct xhci_event_cmd
*event
)
1073 struct xhci_command
*command
;
1075 if (list_empty(&virt_dev
->cmd_list
))
1078 command
= list_entry(virt_dev
->cmd_list
.next
,
1079 struct xhci_command
, cmd_list
);
1080 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1083 command
->status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1084 list_del(&command
->cmd_list
);
1085 if (command
->completion
)
1086 complete(command
->completion
);
1088 xhci_free_command(xhci
, command
);
1092 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1093 struct xhci_event_cmd
*event
)
1095 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1097 dma_addr_t cmd_dequeue_dma
;
1098 struct xhci_input_control_ctx
*ctrl_ctx
;
1099 struct xhci_virt_device
*virt_dev
;
1100 unsigned int ep_index
;
1101 struct xhci_ring
*ep_ring
;
1102 unsigned int ep_state
;
1104 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1105 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1106 xhci
->cmd_ring
->dequeue
);
1107 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1108 if (cmd_dequeue_dma
== 0) {
1109 xhci
->error_bitmask
|= 1 << 4;
1112 /* Does the DMA address match our internal dequeue pointer address? */
1113 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1114 xhci
->error_bitmask
|= 1 << 5;
1117 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1118 & TRB_TYPE_BITMASK
) {
1119 case TRB_TYPE(TRB_ENABLE_SLOT
):
1120 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1121 xhci
->slot_id
= slot_id
;
1124 complete(&xhci
->addr_dev
);
1126 case TRB_TYPE(TRB_DISABLE_SLOT
):
1127 if (xhci
->devs
[slot_id
]) {
1128 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1129 /* Delete default control endpoint resources */
1130 xhci_free_device_endpoint_resources(xhci
,
1131 xhci
->devs
[slot_id
], true);
1132 xhci_free_virt_device(xhci
, slot_id
);
1135 case TRB_TYPE(TRB_CONFIG_EP
):
1136 virt_dev
= xhci
->devs
[slot_id
];
1137 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1140 * Configure endpoint commands can come from the USB core
1141 * configuration or alt setting changes, or because the HW
1142 * needed an extra configure endpoint command after a reset
1143 * endpoint command or streams were being configured.
1144 * If the command was for a halted endpoint, the xHCI driver
1145 * is not waiting on the configure endpoint command.
1147 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1149 /* Input ctx add_flags are the endpoint index plus one */
1150 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1151 /* A usb_set_interface() call directly after clearing a halted
1152 * condition may race on this quirky hardware. Not worth
1153 * worrying about, since this is prototype hardware. Not sure
1154 * if this will work for streams, but streams support was
1155 * untested on this prototype.
1157 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1158 ep_index
!= (unsigned int) -1 &&
1159 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1160 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1161 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1162 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1163 if (!(ep_state
& EP_HALTED
))
1164 goto bandwidth_change
;
1165 xhci_dbg(xhci
, "Completed config ep cmd - "
1166 "last ep index = %d, state = %d\n",
1167 ep_index
, ep_state
);
1168 /* Clear internal halted state and restart ring(s) */
1169 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1171 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1175 xhci_dbg(xhci
, "Completed config ep cmd\n");
1176 xhci
->devs
[slot_id
]->cmd_status
=
1177 GET_COMP_CODE(le32_to_cpu(event
->status
));
1178 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1180 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1181 virt_dev
= xhci
->devs
[slot_id
];
1182 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1184 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1185 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1187 case TRB_TYPE(TRB_ADDR_DEV
):
1188 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1189 complete(&xhci
->addr_dev
);
1191 case TRB_TYPE(TRB_STOP_RING
):
1192 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1194 case TRB_TYPE(TRB_SET_DEQ
):
1195 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1197 case TRB_TYPE(TRB_CMD_NOOP
):
1199 case TRB_TYPE(TRB_RESET_EP
):
1200 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1202 case TRB_TYPE(TRB_RESET_DEV
):
1203 xhci_dbg(xhci
, "Completed reset device command.\n");
1204 slot_id
= TRB_TO_SLOT_ID(
1205 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1206 virt_dev
= xhci
->devs
[slot_id
];
1208 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1210 xhci_warn(xhci
, "Reset device command completion "
1211 "for disabled slot %u\n", slot_id
);
1213 case TRB_TYPE(TRB_NEC_GET_FW
):
1214 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1215 xhci
->error_bitmask
|= 1 << 6;
1218 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1219 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1220 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1223 /* Skip over unknown commands on the event ring */
1224 xhci
->error_bitmask
|= 1 << 6;
1227 inc_deq(xhci
, xhci
->cmd_ring
);
1230 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1231 union xhci_trb
*event
)
1235 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1236 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1237 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1238 handle_cmd_completion(xhci
, &event
->event_cmd
);
1241 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1242 * port registers -- USB 3.0 and USB 2.0).
1244 * Returns a zero-based port number, which is suitable for indexing into each of
1245 * the split roothubs' port arrays and bus state arrays.
1246 * Add one to it in order to call xhci_find_slot_id_by_port.
1248 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1249 struct xhci_hcd
*xhci
, u32 port_id
)
1252 unsigned int num_similar_speed_ports
= 0;
1254 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1255 * and usb2_ports are 0-based indexes. Count the number of similar
1256 * speed ports, up to 1 port before this port.
1258 for (i
= 0; i
< (port_id
- 1); i
++) {
1259 u8 port_speed
= xhci
->port_array
[i
];
1262 * Skip ports that don't have known speeds, or have duplicate
1263 * Extended Capabilities port speed entries.
1265 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1269 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1270 * 1.1 ports are under the USB 2.0 hub. If the port speed
1271 * matches the device speed, it's a similar speed port.
1273 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1274 num_similar_speed_ports
++;
1276 return num_similar_speed_ports
;
1279 static void handle_device_notification(struct xhci_hcd
*xhci
,
1280 union xhci_trb
*event
)
1283 struct usb_device
*udev
;
1285 slot_id
= TRB_TO_SLOT_ID(event
->generic
.field
[3]);
1286 if (!xhci
->devs
[slot_id
]) {
1287 xhci_warn(xhci
, "Device Notification event for "
1288 "unused slot %u\n", slot_id
);
1292 xhci_dbg(xhci
, "Device Wake Notification event for slot ID %u\n",
1294 udev
= xhci
->devs
[slot_id
]->udev
;
1295 if (udev
&& udev
->parent
)
1296 usb_wakeup_notification(udev
->parent
, udev
->portnum
);
1299 static void handle_port_status(struct xhci_hcd
*xhci
,
1300 union xhci_trb
*event
)
1302 struct usb_hcd
*hcd
;
1307 unsigned int faked_port_index
;
1309 struct xhci_bus_state
*bus_state
;
1310 __le32 __iomem
**port_array
;
1311 bool bogus_port_status
= false;
1313 /* Port status change events always have a successful completion code */
1314 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1315 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1316 xhci
->error_bitmask
|= 1 << 8;
1318 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1319 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1321 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1322 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1323 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1324 bogus_port_status
= true;
1328 /* Figure out which usb_hcd this port is attached to:
1329 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1331 major_revision
= xhci
->port_array
[port_id
- 1];
1332 if (major_revision
== 0) {
1333 xhci_warn(xhci
, "Event for port %u not in "
1334 "Extended Capabilities, ignoring.\n",
1336 bogus_port_status
= true;
1339 if (major_revision
== DUPLICATE_ENTRY
) {
1340 xhci_warn(xhci
, "Event for port %u duplicated in"
1341 "Extended Capabilities, ignoring.\n",
1343 bogus_port_status
= true;
1348 * Hardware port IDs reported by a Port Status Change Event include USB
1349 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1350 * resume event, but we first need to translate the hardware port ID
1351 * into the index into the ports on the correct split roothub, and the
1352 * correct bus_state structure.
1354 /* Find the right roothub. */
1355 hcd
= xhci_to_hcd(xhci
);
1356 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1357 hcd
= xhci
->shared_hcd
;
1358 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1359 if (hcd
->speed
== HCD_USB3
)
1360 port_array
= xhci
->usb3_ports
;
1362 port_array
= xhci
->usb2_ports
;
1363 /* Find the faked port hub number */
1364 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1367 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1368 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1369 xhci_dbg(xhci
, "resume root hub\n");
1370 usb_hcd_resume_root_hub(hcd
);
1373 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1374 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1376 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1377 if (!(temp1
& CMD_RUN
)) {
1378 xhci_warn(xhci
, "xHC is not running.\n");
1382 if (DEV_SUPERSPEED(temp
)) {
1383 xhci_dbg(xhci
, "remote wake SS port %d\n", port_id
);
1384 /* Set a flag to say the port signaled remote wakeup,
1385 * so we can tell the difference between the end of
1386 * device and host initiated resume.
1388 bus_state
->port_remote_wakeup
|= 1 << faked_port_index
;
1389 xhci_test_and_clear_bit(xhci
, port_array
,
1390 faked_port_index
, PORT_PLC
);
1391 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1393 /* Need to wait until the next link state change
1394 * indicates the device is actually in U0.
1396 bogus_port_status
= true;
1399 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1400 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1401 msecs_to_jiffies(20);
1402 set_bit(faked_port_index
, &bus_state
->resuming_ports
);
1403 mod_timer(&hcd
->rh_timer
,
1404 bus_state
->resume_done
[faked_port_index
]);
1405 /* Do the rest in GetPortStatus */
1409 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_U0
&&
1410 DEV_SUPERSPEED(temp
)) {
1411 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1412 /* We've just brought the device into U0 through either the
1413 * Resume state after a device remote wakeup, or through the
1414 * U3Exit state after a host-initiated resume. If it's a device
1415 * initiated remote wake, don't pass up the link state change,
1416 * so the roothub behavior is consistent with external
1417 * USB 3.0 hub behavior.
1419 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1420 faked_port_index
+ 1);
1421 if (slot_id
&& xhci
->devs
[slot_id
])
1422 xhci_ring_device(xhci
, slot_id
);
1423 if (bus_state
->port_remote_wakeup
&& (1 << faked_port_index
)) {
1424 bus_state
->port_remote_wakeup
&=
1425 ~(1 << faked_port_index
);
1426 xhci_test_and_clear_bit(xhci
, port_array
,
1427 faked_port_index
, PORT_PLC
);
1428 usb_wakeup_notification(hcd
->self
.root_hub
,
1429 faked_port_index
+ 1);
1430 bogus_port_status
= true;
1435 if (hcd
->speed
!= HCD_USB3
)
1436 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1440 /* Update event ring dequeue pointer before dropping the lock */
1441 inc_deq(xhci
, xhci
->event_ring
);
1443 /* Don't make the USB core poll the roothub if we got a bad port status
1444 * change event. Besides, at that point we can't tell which roothub
1445 * (USB 2.0 or USB 3.0) to kick.
1447 if (bogus_port_status
)
1450 spin_unlock(&xhci
->lock
);
1451 /* Pass this up to the core */
1452 usb_hcd_poll_rh_status(hcd
);
1453 spin_lock(&xhci
->lock
);
1457 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1458 * at end_trb, which may be in another segment. If the suspect DMA address is a
1459 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1462 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1463 union xhci_trb
*start_trb
,
1464 union xhci_trb
*end_trb
,
1465 dma_addr_t suspect_dma
)
1467 dma_addr_t start_dma
;
1468 dma_addr_t end_seg_dma
;
1469 dma_addr_t end_trb_dma
;
1470 struct xhci_segment
*cur_seg
;
1472 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1473 cur_seg
= start_seg
;
1478 /* We may get an event for a Link TRB in the middle of a TD */
1479 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1480 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1481 /* If the end TRB isn't in this segment, this is set to 0 */
1482 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1484 if (end_trb_dma
> 0) {
1485 /* The end TRB is in this segment, so suspect should be here */
1486 if (start_dma
<= end_trb_dma
) {
1487 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1490 /* Case for one segment with
1491 * a TD wrapped around to the top
1493 if ((suspect_dma
>= start_dma
&&
1494 suspect_dma
<= end_seg_dma
) ||
1495 (suspect_dma
>= cur_seg
->dma
&&
1496 suspect_dma
<= end_trb_dma
))
1501 /* Might still be somewhere in this segment */
1502 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1505 cur_seg
= cur_seg
->next
;
1506 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1507 } while (cur_seg
!= start_seg
);
1512 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1513 unsigned int slot_id
, unsigned int ep_index
,
1514 unsigned int stream_id
,
1515 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1517 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1518 ep
->ep_state
|= EP_HALTED
;
1519 ep
->stopped_td
= td
;
1520 ep
->stopped_trb
= event_trb
;
1521 ep
->stopped_stream
= stream_id
;
1523 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1524 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1526 ep
->stopped_td
= NULL
;
1527 ep
->stopped_trb
= NULL
;
1528 ep
->stopped_stream
= 0;
1530 xhci_ring_cmd_db(xhci
);
1533 /* Check if an error has halted the endpoint ring. The class driver will
1534 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1535 * However, a babble and other errors also halt the endpoint ring, and the class
1536 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1537 * Ring Dequeue Pointer command manually.
1539 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1540 struct xhci_ep_ctx
*ep_ctx
,
1541 unsigned int trb_comp_code
)
1543 /* TRB completion codes that may require a manual halt cleanup */
1544 if (trb_comp_code
== COMP_TX_ERR
||
1545 trb_comp_code
== COMP_BABBLE
||
1546 trb_comp_code
== COMP_SPLIT_ERR
)
1547 /* The 0.96 spec says a babbling control endpoint
1548 * is not halted. The 0.96 spec says it is. Some HW
1549 * claims to be 0.95 compliant, but it halts the control
1550 * endpoint anyway. Check if a babble halted the
1553 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1554 cpu_to_le32(EP_STATE_HALTED
))
1560 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1562 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1563 /* Vendor defined "informational" completion code,
1564 * treat as not-an-error.
1566 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1568 xhci_dbg(xhci
, "Treating code as success.\n");
1575 * Finish the td processing, remove the td from td list;
1576 * Return 1 if the urb can be given back.
1578 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1579 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1580 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1582 struct xhci_virt_device
*xdev
;
1583 struct xhci_ring
*ep_ring
;
1584 unsigned int slot_id
;
1586 struct urb
*urb
= NULL
;
1587 struct xhci_ep_ctx
*ep_ctx
;
1589 struct urb_priv
*urb_priv
;
1592 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1593 xdev
= xhci
->devs
[slot_id
];
1594 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1595 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1596 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1597 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1602 if (trb_comp_code
== COMP_STOP_INVAL
||
1603 trb_comp_code
== COMP_STOP
) {
1604 /* The Endpoint Stop Command completion will take care of any
1605 * stopped TDs. A stopped TD may be restarted, so don't update
1606 * the ring dequeue pointer or take this TD off any lists yet.
1608 ep
->stopped_td
= td
;
1609 ep
->stopped_trb
= event_trb
;
1612 if (trb_comp_code
== COMP_STALL
) {
1613 /* The transfer is completed from the driver's
1614 * perspective, but we need to issue a set dequeue
1615 * command for this stalled endpoint to move the dequeue
1616 * pointer past the TD. We can't do that here because
1617 * the halt condition must be cleared first. Let the
1618 * USB class driver clear the stall later.
1620 ep
->stopped_td
= td
;
1621 ep
->stopped_trb
= event_trb
;
1622 ep
->stopped_stream
= ep_ring
->stream_id
;
1623 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1624 ep_ctx
, trb_comp_code
)) {
1625 /* Other types of errors halt the endpoint, but the
1626 * class driver doesn't call usb_reset_endpoint() unless
1627 * the error is -EPIPE. Clear the halted status in the
1628 * xHCI hardware manually.
1630 xhci_cleanup_halted_endpoint(xhci
,
1631 slot_id
, ep_index
, ep_ring
->stream_id
,
1634 /* Update ring dequeue pointer */
1635 while (ep_ring
->dequeue
!= td
->last_trb
)
1636 inc_deq(xhci
, ep_ring
);
1637 inc_deq(xhci
, ep_ring
);
1641 /* Clean up the endpoint's TD list */
1643 urb_priv
= urb
->hcpriv
;
1645 /* Do one last check of the actual transfer length.
1646 * If the host controller said we transferred more data than
1647 * the buffer length, urb->actual_length will be a very big
1648 * number (since it's unsigned). Play it safe and say we didn't
1649 * transfer anything.
1651 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1652 xhci_warn(xhci
, "URB transfer length is wrong, "
1653 "xHC issue? req. len = %u, "
1655 urb
->transfer_buffer_length
,
1656 urb
->actual_length
);
1657 urb
->actual_length
= 0;
1658 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1659 *status
= -EREMOTEIO
;
1663 list_del_init(&td
->td_list
);
1664 /* Was this TD slated to be cancelled but completed anyway? */
1665 if (!list_empty(&td
->cancelled_td_list
))
1666 list_del_init(&td
->cancelled_td_list
);
1669 /* Giveback the urb when all the tds are completed */
1670 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1672 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1673 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1674 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1676 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1677 usb_amd_quirk_pll_enable();
1687 * Process control tds, update urb status and actual_length.
1689 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1690 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1691 struct xhci_virt_ep
*ep
, int *status
)
1693 struct xhci_virt_device
*xdev
;
1694 struct xhci_ring
*ep_ring
;
1695 unsigned int slot_id
;
1697 struct xhci_ep_ctx
*ep_ctx
;
1700 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1701 xdev
= xhci
->devs
[slot_id
];
1702 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1703 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1704 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1705 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1707 switch (trb_comp_code
) {
1709 if (event_trb
== ep_ring
->dequeue
) {
1710 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1711 "without IOC set??\n");
1712 *status
= -ESHUTDOWN
;
1713 } else if (event_trb
!= td
->last_trb
) {
1714 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1715 "without IOC set??\n");
1716 *status
= -ESHUTDOWN
;
1722 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1723 *status
= -EREMOTEIO
;
1727 case COMP_STOP_INVAL
:
1729 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1731 if (!xhci_requires_manual_halt_cleanup(xhci
,
1732 ep_ctx
, trb_comp_code
))
1734 xhci_dbg(xhci
, "TRB error code %u, "
1735 "halted endpoint index = %u\n",
1736 trb_comp_code
, ep_index
);
1737 /* else fall through */
1739 /* Did we transfer part of the data (middle) phase? */
1740 if (event_trb
!= ep_ring
->dequeue
&&
1741 event_trb
!= td
->last_trb
)
1742 td
->urb
->actual_length
=
1743 td
->urb
->transfer_buffer_length
1744 - TRB_LEN(le32_to_cpu(event
->transfer_len
));
1746 td
->urb
->actual_length
= 0;
1748 xhci_cleanup_halted_endpoint(xhci
,
1749 slot_id
, ep_index
, 0, td
, event_trb
);
1750 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1753 * Did we transfer any data, despite the errors that might have
1754 * happened? I.e. did we get past the setup stage?
1756 if (event_trb
!= ep_ring
->dequeue
) {
1757 /* The event was for the status stage */
1758 if (event_trb
== td
->last_trb
) {
1759 if (td
->urb
->actual_length
!= 0) {
1760 /* Don't overwrite a previously set error code
1762 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1763 (td
->urb
->transfer_flags
1764 & URB_SHORT_NOT_OK
))
1765 /* Did we already see a short data
1767 *status
= -EREMOTEIO
;
1769 td
->urb
->actual_length
=
1770 td
->urb
->transfer_buffer_length
;
1773 /* Maybe the event was for the data stage? */
1774 td
->urb
->actual_length
=
1775 td
->urb
->transfer_buffer_length
-
1776 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1777 xhci_dbg(xhci
, "Waiting for status "
1783 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1787 * Process isochronous tds, update urb packet status and actual_length.
1789 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1790 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1791 struct xhci_virt_ep
*ep
, int *status
)
1793 struct xhci_ring
*ep_ring
;
1794 struct urb_priv
*urb_priv
;
1797 union xhci_trb
*cur_trb
;
1798 struct xhci_segment
*cur_seg
;
1799 struct usb_iso_packet_descriptor
*frame
;
1801 bool skip_td
= false;
1803 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1804 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1805 urb_priv
= td
->urb
->hcpriv
;
1806 idx
= urb_priv
->td_cnt
;
1807 frame
= &td
->urb
->iso_frame_desc
[idx
];
1809 /* handle completion code */
1810 switch (trb_comp_code
) {
1812 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0) {
1816 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
1817 trb_comp_code
= COMP_SHORT_TX
;
1819 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
1823 frame
->status
= -ECOMM
;
1826 case COMP_BUFF_OVER
:
1828 frame
->status
= -EOVERFLOW
;
1834 frame
->status
= -EPROTO
;
1838 case COMP_STOP_INVAL
:
1845 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
1846 frame
->actual_length
= frame
->length
;
1847 td
->urb
->actual_length
+= frame
->length
;
1849 for (cur_trb
= ep_ring
->dequeue
,
1850 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
1851 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1852 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1853 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1854 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1856 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1857 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1859 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1860 frame
->actual_length
= len
;
1861 td
->urb
->actual_length
+= len
;
1865 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1868 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1869 struct xhci_transfer_event
*event
,
1870 struct xhci_virt_ep
*ep
, int *status
)
1872 struct xhci_ring
*ep_ring
;
1873 struct urb_priv
*urb_priv
;
1874 struct usb_iso_packet_descriptor
*frame
;
1877 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1878 urb_priv
= td
->urb
->hcpriv
;
1879 idx
= urb_priv
->td_cnt
;
1880 frame
= &td
->urb
->iso_frame_desc
[idx
];
1882 /* The transfer is partly done. */
1883 frame
->status
= -EXDEV
;
1885 /* calc actual length */
1886 frame
->actual_length
= 0;
1888 /* Update ring dequeue pointer */
1889 while (ep_ring
->dequeue
!= td
->last_trb
)
1890 inc_deq(xhci
, ep_ring
);
1891 inc_deq(xhci
, ep_ring
);
1893 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
1897 * Process bulk and interrupt tds, update urb status and actual_length.
1899 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1900 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1901 struct xhci_virt_ep
*ep
, int *status
)
1903 struct xhci_ring
*ep_ring
;
1904 union xhci_trb
*cur_trb
;
1905 struct xhci_segment
*cur_seg
;
1908 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1909 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1911 switch (trb_comp_code
) {
1913 /* Double check that the HW transferred everything. */
1914 if (event_trb
!= td
->last_trb
||
1915 TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1916 xhci_warn(xhci
, "WARN Successful completion "
1918 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1919 *status
= -EREMOTEIO
;
1922 if ((xhci
->quirks
& XHCI_TRUST_TX_LENGTH
))
1923 trb_comp_code
= COMP_SHORT_TX
;
1929 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1930 *status
= -EREMOTEIO
;
1935 /* Others already handled above */
1938 if (trb_comp_code
== COMP_SHORT_TX
)
1939 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
1940 "%d bytes untransferred\n",
1941 td
->urb
->ep
->desc
.bEndpointAddress
,
1942 td
->urb
->transfer_buffer_length
,
1943 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1944 /* Fast path - was this the last TRB in the TD for this URB? */
1945 if (event_trb
== td
->last_trb
) {
1946 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1947 td
->urb
->actual_length
=
1948 td
->urb
->transfer_buffer_length
-
1949 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1950 if (td
->urb
->transfer_buffer_length
<
1951 td
->urb
->actual_length
) {
1952 xhci_warn(xhci
, "HC gave bad length "
1953 "of %d bytes left\n",
1954 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1955 td
->urb
->actual_length
= 0;
1956 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1957 *status
= -EREMOTEIO
;
1961 /* Don't overwrite a previously set error code */
1962 if (*status
== -EINPROGRESS
) {
1963 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1964 *status
= -EREMOTEIO
;
1969 td
->urb
->actual_length
=
1970 td
->urb
->transfer_buffer_length
;
1971 /* Ignore a short packet completion if the
1972 * untransferred length was zero.
1974 if (*status
== -EREMOTEIO
)
1978 /* Slow path - walk the list, starting from the dequeue
1979 * pointer, to get the actual length transferred.
1981 td
->urb
->actual_length
= 0;
1982 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1983 cur_trb
!= event_trb
;
1984 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1985 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1986 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1987 td
->urb
->actual_length
+=
1988 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1990 /* If the ring didn't stop on a Link or No-op TRB, add
1991 * in the actual bytes transferred from the Normal TRB
1993 if (trb_comp_code
!= COMP_STOP_INVAL
)
1994 td
->urb
->actual_length
+=
1995 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1996 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1999 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
2003 * If this function returns an error condition, it means it got a Transfer
2004 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2005 * At this point, the host controller is probably hosed and should be reset.
2007 static int handle_tx_event(struct xhci_hcd
*xhci
,
2008 struct xhci_transfer_event
*event
)
2010 struct xhci_virt_device
*xdev
;
2011 struct xhci_virt_ep
*ep
;
2012 struct xhci_ring
*ep_ring
;
2013 unsigned int slot_id
;
2015 struct xhci_td
*td
= NULL
;
2016 dma_addr_t event_dma
;
2017 struct xhci_segment
*event_seg
;
2018 union xhci_trb
*event_trb
;
2019 struct urb
*urb
= NULL
;
2020 int status
= -EINPROGRESS
;
2021 struct urb_priv
*urb_priv
;
2022 struct xhci_ep_ctx
*ep_ctx
;
2023 struct list_head
*tmp
;
2028 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
2029 xdev
= xhci
->devs
[slot_id
];
2031 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
2032 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2033 (unsigned long long) xhci_trb_virt_to_dma(
2034 xhci
->event_ring
->deq_seg
,
2035 xhci
->event_ring
->dequeue
),
2036 lower_32_bits(le64_to_cpu(event
->buffer
)),
2037 upper_32_bits(le64_to_cpu(event
->buffer
)),
2038 le32_to_cpu(event
->transfer_len
),
2039 le32_to_cpu(event
->flags
));
2040 xhci_dbg(xhci
, "Event ring:\n");
2041 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2045 /* Endpoint ID is 1 based, our index is zero based */
2046 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
2047 ep
= &xdev
->eps
[ep_index
];
2048 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
2049 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2051 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
2052 EP_STATE_DISABLED
) {
2053 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
2054 "or incorrect stream ring\n");
2055 xhci_err(xhci
, "@%016llx %08x %08x %08x %08x\n",
2056 (unsigned long long) xhci_trb_virt_to_dma(
2057 xhci
->event_ring
->deq_seg
,
2058 xhci
->event_ring
->dequeue
),
2059 lower_32_bits(le64_to_cpu(event
->buffer
)),
2060 upper_32_bits(le64_to_cpu(event
->buffer
)),
2061 le32_to_cpu(event
->transfer_len
),
2062 le32_to_cpu(event
->flags
));
2063 xhci_dbg(xhci
, "Event ring:\n");
2064 xhci_debug_segment(xhci
, xhci
->event_ring
->deq_seg
);
2068 /* Count current td numbers if ep->skip is set */
2070 list_for_each(tmp
, &ep_ring
->td_list
)
2074 event_dma
= le64_to_cpu(event
->buffer
);
2075 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
2076 /* Look for common error cases */
2077 switch (trb_comp_code
) {
2078 /* Skip codes that require special handling depending on
2082 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) == 0)
2084 if (xhci
->quirks
& XHCI_TRUST_TX_LENGTH
)
2085 trb_comp_code
= COMP_SHORT_TX
;
2087 xhci_warn_ratelimited(xhci
,
2088 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2092 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
2094 case COMP_STOP_INVAL
:
2095 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
2098 xhci_dbg(xhci
, "Stalled endpoint\n");
2099 ep
->ep_state
|= EP_HALTED
;
2103 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
2106 case COMP_SPLIT_ERR
:
2108 xhci_dbg(xhci
, "Transfer error on endpoint\n");
2112 xhci_dbg(xhci
, "Babble error on endpoint\n");
2113 status
= -EOVERFLOW
;
2116 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2120 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2122 case COMP_BUFF_OVER
:
2123 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2127 * When the Isoch ring is empty, the xHC will generate
2128 * a Ring Overrun Event for IN Isoch endpoint or Ring
2129 * Underrun Event for OUT Isoch endpoint.
2131 xhci_dbg(xhci
, "underrun event on endpoint\n");
2132 if (!list_empty(&ep_ring
->td_list
))
2133 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2134 "still with TDs queued?\n",
2135 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2139 xhci_dbg(xhci
, "overrun event on endpoint\n");
2140 if (!list_empty(&ep_ring
->td_list
))
2141 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2142 "still with TDs queued?\n",
2143 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2147 xhci_warn(xhci
, "WARN: detect an incompatible device");
2150 case COMP_MISSED_INT
:
2152 * When encounter missed service error, one or more isoc tds
2153 * may be missed by xHC.
2154 * Set skip flag of the ep_ring; Complete the missed tds as
2155 * short transfer when process the ep_ring next time.
2158 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2161 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2165 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2171 /* This TRB should be in the TD at the head of this ring's
2174 if (list_empty(&ep_ring
->td_list
)) {
2175 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d "
2176 "with no TDs queued?\n",
2177 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2179 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2180 (le32_to_cpu(event
->flags
) &
2181 TRB_TYPE_BITMASK
)>>10);
2182 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2185 xhci_dbg(xhci
, "td_list is empty while skip "
2186 "flag set. Clear skip flag.\n");
2192 /* We've skipped all the TDs on the ep ring when ep->skip set */
2193 if (ep
->skip
&& td_num
== 0) {
2195 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2196 "Clear skip flag.\n");
2201 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2205 /* Is this a TRB in the currently executing TD? */
2206 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2207 td
->last_trb
, event_dma
);
2210 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2211 * is not in the current TD pointed by ep_ring->dequeue because
2212 * that the hardware dequeue pointer still at the previous TRB
2213 * of the current TD. The previous TRB maybe a Link TD or the
2214 * last TRB of the previous TD. The command completion handle
2215 * will take care the rest.
2217 if (!event_seg
&& trb_comp_code
== COMP_STOP_INVAL
) {
2224 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2225 /* Some host controllers give a spurious
2226 * successful event after a short transfer.
2229 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2230 ep_ring
->last_td_was_short
) {
2231 ep_ring
->last_td_was_short
= false;
2235 /* HC is busted, give up! */
2237 "ERROR Transfer event TRB DMA ptr not "
2238 "part of current TD\n");
2242 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2245 if (trb_comp_code
== COMP_SHORT_TX
)
2246 ep_ring
->last_td_was_short
= true;
2248 ep_ring
->last_td_was_short
= false;
2251 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2255 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2256 sizeof(*event_trb
)];
2258 * No-op TRB should not trigger interrupts.
2259 * If event_trb is a no-op TRB, it means the
2260 * corresponding TD has been cancelled. Just ignore
2263 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2265 "event_trb is a no-op TRB. Skip it\n");
2269 /* Now update the urb's actual_length and give back to
2272 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2273 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2275 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2276 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2279 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2284 * Do not update event ring dequeue pointer if ep->skip is set.
2285 * Will roll back to continue process missed tds.
2287 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2288 inc_deq(xhci
, xhci
->event_ring
);
2293 urb_priv
= urb
->hcpriv
;
2294 /* Leave the TD around for the reset endpoint function
2295 * to use(but only if it's not a control endpoint,
2296 * since we already queued the Set TR dequeue pointer
2297 * command for stalled control endpoints).
2299 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2300 (trb_comp_code
!= COMP_STALL
&&
2301 trb_comp_code
!= COMP_BABBLE
))
2302 xhci_urb_free_priv(xhci
, urb_priv
);
2304 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2305 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2306 (urb
->transfer_flags
&
2307 URB_SHORT_NOT_OK
)) ||
2309 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2310 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2311 "expected = %d, status = %d\n",
2312 urb
, urb
->actual_length
,
2313 urb
->transfer_buffer_length
,
2315 spin_unlock(&xhci
->lock
);
2316 /* EHCI, UHCI, and OHCI always unconditionally set the
2317 * urb->status of an isochronous endpoint to 0.
2319 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2321 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2322 spin_lock(&xhci
->lock
);
2326 * If ep->skip is set, it means there are missed tds on the
2327 * endpoint ring need to take care of.
2328 * Process them as short transfer until reach the td pointed by
2331 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2337 * This function handles all OS-owned events on the event ring. It may drop
2338 * xhci->lock between event processing (e.g. to pass up port status changes).
2339 * Returns >0 for "possibly more events to process" (caller should call again),
2340 * otherwise 0 if done. In future, <0 returns should indicate error code.
2342 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2344 union xhci_trb
*event
;
2345 int update_ptrs
= 1;
2348 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2349 xhci
->error_bitmask
|= 1 << 1;
2353 event
= xhci
->event_ring
->dequeue
;
2354 /* Does the HC or OS own the TRB? */
2355 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2356 xhci
->event_ring
->cycle_state
) {
2357 xhci
->error_bitmask
|= 1 << 2;
2362 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2363 * speculative reads of the event's flags/data below.
2366 /* FIXME: Handle more event types. */
2367 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2368 case TRB_TYPE(TRB_COMPLETION
):
2369 handle_cmd_completion(xhci
, &event
->event_cmd
);
2371 case TRB_TYPE(TRB_PORT_STATUS
):
2372 handle_port_status(xhci
, event
);
2375 case TRB_TYPE(TRB_TRANSFER
):
2376 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2378 xhci
->error_bitmask
|= 1 << 9;
2382 case TRB_TYPE(TRB_DEV_NOTE
):
2383 handle_device_notification(xhci
, event
);
2386 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2388 handle_vendor_event(xhci
, event
);
2390 xhci
->error_bitmask
|= 1 << 3;
2392 /* Any of the above functions may drop and re-acquire the lock, so check
2393 * to make sure a watchdog timer didn't mark the host as non-responsive.
2395 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2396 xhci_dbg(xhci
, "xHCI host dying, returning from "
2397 "event handler.\n");
2402 /* Update SW event ring dequeue pointer */
2403 inc_deq(xhci
, xhci
->event_ring
);
2405 /* Are there more items on the event ring? Caller will call us again to
2412 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2413 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2414 * indicators of an event TRB error, but we check the status *first* to be safe.
2416 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2418 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2420 union xhci_trb
*trb
;
2422 union xhci_trb
*event_ring_deq
;
2425 spin_lock(&xhci
->lock
);
2426 trb
= xhci
->event_ring
->dequeue
;
2427 /* Check if the xHC generated the interrupt, or the irq is shared */
2428 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2429 if (status
== 0xffffffff)
2432 if (!(status
& STS_EINT
)) {
2433 spin_unlock(&xhci
->lock
);
2436 if (status
& STS_FATAL
) {
2437 xhci_warn(xhci
, "WARNING: Host System Error\n");
2440 spin_unlock(&xhci
->lock
);
2445 * Clear the op reg interrupt status first,
2446 * so we can receive interrupts from other MSI-X interrupters.
2447 * Write 1 to clear the interrupt status.
2450 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2451 /* FIXME when MSI-X is supported and there are multiple vectors */
2452 /* Clear the MSI-X event interrupt status */
2456 /* Acknowledge the PCI interrupt */
2457 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2458 irq_pending
|= IMAN_IP
;
2459 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2462 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2463 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2464 "Shouldn't IRQs be disabled?\n");
2465 /* Clear the event handler busy flag (RW1C);
2466 * the event ring should be empty.
2468 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2469 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2470 &xhci
->ir_set
->erst_dequeue
);
2471 spin_unlock(&xhci
->lock
);
2476 event_ring_deq
= xhci
->event_ring
->dequeue
;
2477 /* FIXME this should be a delayed service routine
2478 * that clears the EHB.
2480 while (xhci_handle_event(xhci
) > 0) {}
2482 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2483 /* If necessary, update the HW's version of the event ring deq ptr. */
2484 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2485 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2486 xhci
->event_ring
->dequeue
);
2488 xhci_warn(xhci
, "WARN something wrong with SW event "
2489 "ring dequeue ptr.\n");
2490 /* Update HC event ring dequeue pointer */
2491 temp_64
&= ERST_PTR_MASK
;
2492 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2495 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2496 temp_64
|= ERST_EHB
;
2497 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2499 spin_unlock(&xhci
->lock
);
2504 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2506 return xhci_irq(hcd
);
2509 /**** Endpoint Ring Operations ****/
2512 * Generic function for queueing a TRB on a ring.
2513 * The caller must have checked to make sure there's room on the ring.
2515 * @more_trbs_coming: Will you enqueue more TRBs before calling
2516 * prepare_transfer()?
2518 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2519 bool more_trbs_coming
,
2520 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2522 struct xhci_generic_trb
*trb
;
2524 trb
= &ring
->enqueue
->generic
;
2525 trb
->field
[0] = cpu_to_le32(field1
);
2526 trb
->field
[1] = cpu_to_le32(field2
);
2527 trb
->field
[2] = cpu_to_le32(field3
);
2528 trb
->field
[3] = cpu_to_le32(field4
);
2529 inc_enq(xhci
, ring
, more_trbs_coming
);
2533 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2534 * FIXME allocate segments if the ring is full.
2536 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2537 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
2539 unsigned int num_trbs_needed
;
2541 /* Make sure the endpoint has been added to xHC schedule */
2543 case EP_STATE_DISABLED
:
2545 * USB core changed config/interfaces without notifying us,
2546 * or hardware is reporting the wrong state.
2548 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2550 case EP_STATE_ERROR
:
2551 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2552 /* FIXME event handling code for error needs to clear it */
2553 /* XXX not sure if this should be -ENOENT or not */
2555 case EP_STATE_HALTED
:
2556 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2557 case EP_STATE_STOPPED
:
2558 case EP_STATE_RUNNING
:
2561 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2563 * FIXME issue Configure Endpoint command to try to get the HC
2564 * back into a known state.
2570 if (room_on_ring(xhci
, ep_ring
, num_trbs
))
2573 if (ep_ring
== xhci
->cmd_ring
) {
2574 xhci_err(xhci
, "Do not support expand command ring\n");
2578 xhci_dbg(xhci
, "ERROR no room on ep ring, "
2579 "try ring expansion\n");
2580 num_trbs_needed
= num_trbs
- ep_ring
->num_trbs_free
;
2581 if (xhci_ring_expansion(xhci
, ep_ring
, num_trbs_needed
,
2583 xhci_err(xhci
, "Ring expansion failed\n");
2588 if (enqueue_is_link_trb(ep_ring
)) {
2589 struct xhci_ring
*ring
= ep_ring
;
2590 union xhci_trb
*next
;
2592 next
= ring
->enqueue
;
2594 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2595 /* If we're not dealing with 0.95 hardware or isoc rings
2596 * on AMD 0.96 host, clear the chain bit.
2598 if (!xhci_link_trb_quirk(xhci
) &&
2599 !(ring
->type
== TYPE_ISOC
&&
2600 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2601 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2603 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2606 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2608 /* Toggle the cycle bit after the last ring segment. */
2609 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2610 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2612 ring
->enq_seg
= ring
->enq_seg
->next
;
2613 ring
->enqueue
= ring
->enq_seg
->trbs
;
2614 next
= ring
->enqueue
;
2621 static int prepare_transfer(struct xhci_hcd
*xhci
,
2622 struct xhci_virt_device
*xdev
,
2623 unsigned int ep_index
,
2624 unsigned int stream_id
,
2625 unsigned int num_trbs
,
2627 unsigned int td_index
,
2631 struct urb_priv
*urb_priv
;
2633 struct xhci_ring
*ep_ring
;
2634 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2636 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2638 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2643 ret
= prepare_ring(xhci
, ep_ring
,
2644 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2645 num_trbs
, mem_flags
);
2649 urb_priv
= urb
->hcpriv
;
2650 td
= urb_priv
->td
[td_index
];
2652 INIT_LIST_HEAD(&td
->td_list
);
2653 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2655 if (td_index
== 0) {
2656 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2662 /* Add this TD to the tail of the endpoint ring's TD list */
2663 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2664 td
->start_seg
= ep_ring
->enq_seg
;
2665 td
->first_trb
= ep_ring
->enqueue
;
2667 urb_priv
->td
[td_index
] = td
;
2672 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
2674 int num_sgs
, num_trbs
, running_total
, temp
, i
;
2675 struct scatterlist
*sg
;
2678 num_sgs
= urb
->num_mapped_sgs
;
2679 temp
= urb
->transfer_buffer_length
;
2682 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
2683 unsigned int len
= sg_dma_len(sg
);
2685 /* Scatter gather list entries may cross 64KB boundaries */
2686 running_total
= TRB_MAX_BUFF_SIZE
-
2687 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
2688 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2689 if (running_total
!= 0)
2692 /* How many more 64KB chunks to transfer, how many more TRBs? */
2693 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
2695 running_total
+= TRB_MAX_BUFF_SIZE
;
2697 len
= min_t(int, len
, temp
);
2705 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
2708 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
2709 "TRBs, %d left\n", __func__
,
2710 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
2711 if (running_total
!= urb
->transfer_buffer_length
)
2712 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2713 "queued %#x (%d), asked for %#x (%d)\n",
2715 urb
->ep
->desc
.bEndpointAddress
,
2716 running_total
, running_total
,
2717 urb
->transfer_buffer_length
,
2718 urb
->transfer_buffer_length
);
2721 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2722 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2723 struct xhci_generic_trb
*start_trb
)
2726 * Pass all the TRBs to the hardware at once and make sure this write
2731 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
2733 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
2734 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
2738 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2739 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2740 * (comprised of sg list entries) can take several service intervals to
2743 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2744 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2746 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
2747 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2751 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
2752 ep_interval
= urb
->interval
;
2753 /* Convert to microframes */
2754 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2755 urb
->dev
->speed
== USB_SPEED_FULL
)
2757 /* FIXME change this to a warning and a suggestion to use the new API
2758 * to set the polling interval (once the API is added).
2760 if (xhci_interval
!= ep_interval
) {
2761 if (printk_ratelimit())
2762 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2763 " (%d microframe%s) than xHCI "
2764 "(%d microframe%s)\n",
2766 ep_interval
== 1 ? "" : "s",
2768 xhci_interval
== 1 ? "" : "s");
2769 urb
->interval
= xhci_interval
;
2770 /* Convert back to frames for LS/FS devices */
2771 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2772 urb
->dev
->speed
== USB_SPEED_FULL
)
2775 return xhci_queue_bulk_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2779 * The TD size is the number of bytes remaining in the TD (including this TRB),
2780 * right shifted by 10.
2781 * It must fit in bits 21:17, so it can't be bigger than 31.
2783 static u32
xhci_td_remainder(unsigned int remainder
)
2785 u32 max
= (1 << (21 - 17 + 1)) - 1;
2787 if ((remainder
>> 10) >= max
)
2790 return (remainder
>> 10) << 17;
2794 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2795 * the TD (*not* including this TRB).
2797 * Total TD packet count = total_packet_count =
2798 * roundup(TD size in bytes / wMaxPacketSize)
2800 * Packets transferred up to and including this TRB = packets_transferred =
2801 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2803 * TD size = total_packet_count - packets_transferred
2805 * It must fit in bits 21:17, so it can't be bigger than 31.
2808 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
2809 unsigned int total_packet_count
, struct urb
*urb
)
2811 int packets_transferred
;
2813 /* One TRB with a zero-length data packet. */
2814 if (running_total
== 0 && trb_buff_len
== 0)
2817 /* All the TRB queueing functions don't count the current TRB in
2820 packets_transferred
= (running_total
+ trb_buff_len
) /
2821 usb_endpoint_maxp(&urb
->ep
->desc
);
2823 return xhci_td_remainder(total_packet_count
- packets_transferred
);
2826 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2827 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2829 struct xhci_ring
*ep_ring
;
2830 unsigned int num_trbs
;
2831 struct urb_priv
*urb_priv
;
2833 struct scatterlist
*sg
;
2835 int trb_buff_len
, this_sg_len
, running_total
;
2836 unsigned int total_packet_count
;
2839 bool more_trbs_coming
;
2841 struct xhci_generic_trb
*start_trb
;
2844 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2848 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2849 num_sgs
= urb
->num_mapped_sgs
;
2850 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2851 usb_endpoint_maxp(&urb
->ep
->desc
));
2853 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2854 ep_index
, urb
->stream_id
,
2855 num_trbs
, urb
, 0, mem_flags
);
2856 if (trb_buff_len
< 0)
2857 return trb_buff_len
;
2859 urb_priv
= urb
->hcpriv
;
2860 td
= urb_priv
->td
[0];
2863 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2864 * until we've finished creating all the other TRBs. The ring's cycle
2865 * state may change as we enqueue the other TRBs, so save it too.
2867 start_trb
= &ep_ring
->enqueue
->generic
;
2868 start_cycle
= ep_ring
->cycle_state
;
2872 * How much data is in the first TRB?
2874 * There are three forces at work for TRB buffer pointers and lengths:
2875 * 1. We don't want to walk off the end of this sg-list entry buffer.
2876 * 2. The transfer length that the driver requested may be smaller than
2877 * the amount of memory allocated for this scatter-gather list.
2878 * 3. TRBs buffers can't cross 64KB boundaries.
2881 addr
= (u64
) sg_dma_address(sg
);
2882 this_sg_len
= sg_dma_len(sg
);
2883 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2884 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2885 if (trb_buff_len
> urb
->transfer_buffer_length
)
2886 trb_buff_len
= urb
->transfer_buffer_length
;
2889 /* Queue the first TRB, even if it's zero-length */
2892 u32 length_field
= 0;
2895 /* Don't change the cycle bit of the first TRB until later */
2898 if (start_cycle
== 0)
2901 field
|= ep_ring
->cycle_state
;
2903 /* Chain all the TRBs together; clear the chain bit in the last
2904 * TRB to indicate it's the last TRB in the chain.
2909 /* FIXME - add check for ZERO_PACKET flag before this */
2910 td
->last_trb
= ep_ring
->enqueue
;
2914 /* Only set interrupt on short packet for IN endpoints */
2915 if (usb_urb_dir_in(urb
))
2918 if (TRB_MAX_BUFF_SIZE
-
2919 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
2920 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2921 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2922 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2923 (unsigned int) addr
+ trb_buff_len
);
2926 /* Set the TRB length, TD size, and interrupter fields. */
2927 if (xhci
->hci_version
< 0x100) {
2928 remainder
= xhci_td_remainder(
2929 urb
->transfer_buffer_length
-
2932 remainder
= xhci_v1_0_td_remainder(running_total
,
2933 trb_buff_len
, total_packet_count
, urb
);
2935 length_field
= TRB_LEN(trb_buff_len
) |
2940 more_trbs_coming
= true;
2942 more_trbs_coming
= false;
2943 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
2944 lower_32_bits(addr
),
2945 upper_32_bits(addr
),
2947 field
| TRB_TYPE(TRB_NORMAL
));
2949 running_total
+= trb_buff_len
;
2951 /* Calculate length for next transfer --
2952 * Are we done queueing all the TRBs for this sg entry?
2954 this_sg_len
-= trb_buff_len
;
2955 if (this_sg_len
== 0) {
2960 addr
= (u64
) sg_dma_address(sg
);
2961 this_sg_len
= sg_dma_len(sg
);
2963 addr
+= trb_buff_len
;
2966 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2967 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2968 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2969 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2971 urb
->transfer_buffer_length
- running_total
;
2972 } while (running_total
< urb
->transfer_buffer_length
);
2974 check_trb_math(urb
, num_trbs
, running_total
);
2975 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2976 start_cycle
, start_trb
);
2980 /* This is very similar to what ehci-q.c qtd_fill() does */
2981 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2982 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2984 struct xhci_ring
*ep_ring
;
2985 struct urb_priv
*urb_priv
;
2988 struct xhci_generic_trb
*start_trb
;
2990 bool more_trbs_coming
;
2992 u32 field
, length_field
;
2994 int running_total
, trb_buff_len
, ret
;
2995 unsigned int total_packet_count
;
2999 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3001 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3006 /* How much data is (potentially) left before the 64KB boundary? */
3007 running_total
= TRB_MAX_BUFF_SIZE
-
3008 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3009 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
3011 /* If there's some data on this 64KB chunk, or we have to send a
3012 * zero-length transfer, we need at least one TRB
3014 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
3016 /* How many more 64KB chunks to transfer, how many more TRBs? */
3017 while (running_total
< urb
->transfer_buffer_length
) {
3019 running_total
+= TRB_MAX_BUFF_SIZE
;
3021 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3023 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3024 ep_index
, urb
->stream_id
,
3025 num_trbs
, urb
, 0, mem_flags
);
3029 urb_priv
= urb
->hcpriv
;
3030 td
= urb_priv
->td
[0];
3033 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3034 * until we've finished creating all the other TRBs. The ring's cycle
3035 * state may change as we enqueue the other TRBs, so save it too.
3037 start_trb
= &ep_ring
->enqueue
->generic
;
3038 start_cycle
= ep_ring
->cycle_state
;
3041 total_packet_count
= roundup(urb
->transfer_buffer_length
,
3042 usb_endpoint_maxp(&urb
->ep
->desc
));
3043 /* How much data is in the first TRB? */
3044 addr
= (u64
) urb
->transfer_dma
;
3045 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3046 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
3047 if (trb_buff_len
> urb
->transfer_buffer_length
)
3048 trb_buff_len
= urb
->transfer_buffer_length
;
3052 /* Queue the first TRB, even if it's zero-length */
3057 /* Don't change the cycle bit of the first TRB until later */
3060 if (start_cycle
== 0)
3063 field
|= ep_ring
->cycle_state
;
3065 /* Chain all the TRBs together; clear the chain bit in the last
3066 * TRB to indicate it's the last TRB in the chain.
3071 /* FIXME - add check for ZERO_PACKET flag before this */
3072 td
->last_trb
= ep_ring
->enqueue
;
3076 /* Only set interrupt on short packet for IN endpoints */
3077 if (usb_urb_dir_in(urb
))
3080 /* Set the TRB length, TD size, and interrupter fields. */
3081 if (xhci
->hci_version
< 0x100) {
3082 remainder
= xhci_td_remainder(
3083 urb
->transfer_buffer_length
-
3086 remainder
= xhci_v1_0_td_remainder(running_total
,
3087 trb_buff_len
, total_packet_count
, urb
);
3089 length_field
= TRB_LEN(trb_buff_len
) |
3094 more_trbs_coming
= true;
3096 more_trbs_coming
= false;
3097 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3098 lower_32_bits(addr
),
3099 upper_32_bits(addr
),
3101 field
| TRB_TYPE(TRB_NORMAL
));
3103 running_total
+= trb_buff_len
;
3105 /* Calculate length for next transfer */
3106 addr
+= trb_buff_len
;
3107 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
3108 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
3109 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
3110 } while (running_total
< urb
->transfer_buffer_length
);
3112 check_trb_math(urb
, num_trbs
, running_total
);
3113 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3114 start_cycle
, start_trb
);
3118 /* Caller must have locked xhci->lock */
3119 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3120 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3122 struct xhci_ring
*ep_ring
;
3125 struct usb_ctrlrequest
*setup
;
3126 struct xhci_generic_trb
*start_trb
;
3128 u32 field
, length_field
;
3129 struct urb_priv
*urb_priv
;
3132 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3137 * Need to copy setup packet into setup TRB, so we can't use the setup
3140 if (!urb
->setup_packet
)
3143 /* 1 TRB for setup, 1 for status */
3146 * Don't need to check if we need additional event data and normal TRBs,
3147 * since data in control transfers will never get bigger than 16MB
3148 * XXX: can we get a buffer that crosses 64KB boundaries?
3150 if (urb
->transfer_buffer_length
> 0)
3152 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3153 ep_index
, urb
->stream_id
,
3154 num_trbs
, urb
, 0, mem_flags
);
3158 urb_priv
= urb
->hcpriv
;
3159 td
= urb_priv
->td
[0];
3162 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3163 * until we've finished creating all the other TRBs. The ring's cycle
3164 * state may change as we enqueue the other TRBs, so save it too.
3166 start_trb
= &ep_ring
->enqueue
->generic
;
3167 start_cycle
= ep_ring
->cycle_state
;
3169 /* Queue setup TRB - see section 6.4.1.2.1 */
3170 /* FIXME better way to translate setup_packet into two u32 fields? */
3171 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3173 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3174 if (start_cycle
== 0)
3177 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3178 if (xhci
->hci_version
== 0x100) {
3179 if (urb
->transfer_buffer_length
> 0) {
3180 if (setup
->bRequestType
& USB_DIR_IN
)
3181 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3183 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3187 queue_trb(xhci
, ep_ring
, true,
3188 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3189 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3190 TRB_LEN(8) | TRB_INTR_TARGET(0),
3191 /* Immediate data in pointer */
3194 /* If there's data, queue data TRBs */
3195 /* Only set interrupt on short packet for IN endpoints */
3196 if (usb_urb_dir_in(urb
))
3197 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3199 field
= TRB_TYPE(TRB_DATA
);
3201 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3202 xhci_td_remainder(urb
->transfer_buffer_length
) |
3204 if (urb
->transfer_buffer_length
> 0) {
3205 if (setup
->bRequestType
& USB_DIR_IN
)
3206 field
|= TRB_DIR_IN
;
3207 queue_trb(xhci
, ep_ring
, true,
3208 lower_32_bits(urb
->transfer_dma
),
3209 upper_32_bits(urb
->transfer_dma
),
3211 field
| ep_ring
->cycle_state
);
3214 /* Save the DMA address of the last TRB in the TD */
3215 td
->last_trb
= ep_ring
->enqueue
;
3217 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3218 /* If the device sent data, the status stage is an OUT transfer */
3219 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3223 queue_trb(xhci
, ep_ring
, false,
3227 /* Event on completion */
3228 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3230 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3231 start_cycle
, start_trb
);
3235 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3236 struct urb
*urb
, int i
)
3241 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3242 td_len
= urb
->iso_frame_desc
[i
].length
;
3244 num_trbs
= DIV_ROUND_UP(td_len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3253 * The transfer burst count field of the isochronous TRB defines the number of
3254 * bursts that are required to move all packets in this TD. Only SuperSpeed
3255 * devices can burst up to bMaxBurst number of packets per service interval.
3256 * This field is zero based, meaning a value of zero in the field means one
3257 * burst. Basically, for everything but SuperSpeed devices, this field will be
3258 * zero. Only xHCI 1.0 host controllers support this field.
3260 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3261 struct usb_device
*udev
,
3262 struct urb
*urb
, unsigned int total_packet_count
)
3264 unsigned int max_burst
;
3266 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3269 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3270 return roundup(total_packet_count
, max_burst
+ 1) - 1;
3274 * Returns the number of packets in the last "burst" of packets. This field is
3275 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3276 * the last burst packet count is equal to the total number of packets in the
3277 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3278 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3279 * contain 1 to (bMaxBurst + 1) packets.
3281 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3282 struct usb_device
*udev
,
3283 struct urb
*urb
, unsigned int total_packet_count
)
3285 unsigned int max_burst
;
3286 unsigned int residue
;
3288 if (xhci
->hci_version
< 0x100)
3291 switch (udev
->speed
) {
3292 case USB_SPEED_SUPER
:
3293 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3294 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3295 residue
= total_packet_count
% (max_burst
+ 1);
3296 /* If residue is zero, the last burst contains (max_burst + 1)
3297 * number of packets, but the TLBPC field is zero-based.
3303 if (total_packet_count
== 0)
3305 return total_packet_count
- 1;
3309 /* This is for isoc transfer */
3310 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3311 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3313 struct xhci_ring
*ep_ring
;
3314 struct urb_priv
*urb_priv
;
3316 int num_tds
, trbs_per_td
;
3317 struct xhci_generic_trb
*start_trb
;
3320 u32 field
, length_field
;
3321 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3322 u64 start_addr
, addr
;
3324 bool more_trbs_coming
;
3326 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3328 num_tds
= urb
->number_of_packets
;
3330 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3334 start_addr
= (u64
) urb
->transfer_dma
;
3335 start_trb
= &ep_ring
->enqueue
->generic
;
3336 start_cycle
= ep_ring
->cycle_state
;
3338 urb_priv
= urb
->hcpriv
;
3339 /* Queue the first TRB, even if it's zero-length */
3340 for (i
= 0; i
< num_tds
; i
++) {
3341 unsigned int total_packet_count
;
3342 unsigned int burst_count
;
3343 unsigned int residue
;
3347 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3348 td_len
= urb
->iso_frame_desc
[i
].length
;
3349 td_remain_len
= td_len
;
3350 total_packet_count
= roundup(td_len
,
3351 usb_endpoint_maxp(&urb
->ep
->desc
));
3352 /* A zero-length transfer still involves at least one packet. */
3353 if (total_packet_count
== 0)
3354 total_packet_count
++;
3355 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3356 total_packet_count
);
3357 residue
= xhci_get_last_burst_packet_count(xhci
,
3358 urb
->dev
, urb
, total_packet_count
);
3360 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3362 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3363 urb
->stream_id
, trbs_per_td
, urb
, i
, mem_flags
);
3370 td
= urb_priv
->td
[i
];
3371 for (j
= 0; j
< trbs_per_td
; j
++) {
3373 field
= TRB_TBC(burst_count
) | TRB_TLBPC(residue
);
3376 /* Queue the isoc TRB */
3377 field
|= TRB_TYPE(TRB_ISOC
);
3378 /* Assume URB_ISO_ASAP is set */
3381 if (start_cycle
== 0)
3384 field
|= ep_ring
->cycle_state
;
3387 /* Queue other normal TRBs */
3388 field
|= TRB_TYPE(TRB_NORMAL
);
3389 field
|= ep_ring
->cycle_state
;
3392 /* Only set interrupt on short packet for IN EPs */
3393 if (usb_urb_dir_in(urb
))
3396 /* Chain all the TRBs together; clear the chain bit in
3397 * the last TRB to indicate it's the last TRB in the
3400 if (j
< trbs_per_td
- 1) {
3402 more_trbs_coming
= true;
3404 td
->last_trb
= ep_ring
->enqueue
;
3406 if (xhci
->hci_version
== 0x100) {
3407 /* Set BEI bit except for the last td */
3408 if (i
< num_tds
- 1)
3411 more_trbs_coming
= false;
3414 /* Calculate TRB length */
3415 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3416 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3417 if (trb_buff_len
> td_remain_len
)
3418 trb_buff_len
= td_remain_len
;
3420 /* Set the TRB length, TD size, & interrupter fields. */
3421 if (xhci
->hci_version
< 0x100) {
3422 remainder
= xhci_td_remainder(
3423 td_len
- running_total
);
3425 remainder
= xhci_v1_0_td_remainder(
3426 running_total
, trb_buff_len
,
3427 total_packet_count
, urb
);
3429 length_field
= TRB_LEN(trb_buff_len
) |
3433 queue_trb(xhci
, ep_ring
, more_trbs_coming
,
3434 lower_32_bits(addr
),
3435 upper_32_bits(addr
),
3438 running_total
+= trb_buff_len
;
3440 addr
+= trb_buff_len
;
3441 td_remain_len
-= trb_buff_len
;
3444 /* Check TD length */
3445 if (running_total
!= td_len
) {
3446 xhci_err(xhci
, "ISOC TD length unmatch\n");
3452 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3453 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3454 usb_amd_quirk_pll_disable();
3456 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3458 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3459 start_cycle
, start_trb
);
3462 /* Clean up a partially enqueued isoc transfer. */
3464 for (i
--; i
>= 0; i
--)
3465 list_del_init(&urb_priv
->td
[i
]->td_list
);
3467 /* Use the first TD as a temporary variable to turn the TDs we've queued
3468 * into No-ops with a software-owned cycle bit. That way the hardware
3469 * won't accidentally start executing bogus TDs when we partially
3470 * overwrite them. td->first_trb and td->start_seg are already set.
3472 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3473 /* Every TRB except the first & last will have its cycle bit flipped. */
3474 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3476 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3477 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3478 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3479 ep_ring
->cycle_state
= start_cycle
;
3480 ep_ring
->num_trbs_free
= ep_ring
->num_trbs_free_temp
;
3481 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3486 * Check transfer ring to guarantee there is enough room for the urb.
3487 * Update ISO URB start_frame and interval.
3488 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3489 * update the urb->start_frame by now.
3490 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3492 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3493 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3495 struct xhci_virt_device
*xdev
;
3496 struct xhci_ring
*ep_ring
;
3497 struct xhci_ep_ctx
*ep_ctx
;
3501 int num_tds
, num_trbs
, i
;
3504 xdev
= xhci
->devs
[slot_id
];
3505 ep_ring
= xdev
->eps
[ep_index
].ring
;
3506 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3509 num_tds
= urb
->number_of_packets
;
3510 for (i
= 0; i
< num_tds
; i
++)
3511 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3513 /* Check the ring to guarantee there is enough room for the whole urb.
3514 * Do not insert any td of the urb to the ring if the check failed.
3516 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3517 num_trbs
, mem_flags
);
3521 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3522 start_frame
&= 0x3fff;
3524 urb
->start_frame
= start_frame
;
3525 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3526 urb
->dev
->speed
== USB_SPEED_FULL
)
3527 urb
->start_frame
>>= 3;
3529 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3530 ep_interval
= urb
->interval
;
3531 /* Convert to microframes */
3532 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3533 urb
->dev
->speed
== USB_SPEED_FULL
)
3535 /* FIXME change this to a warning and a suggestion to use the new API
3536 * to set the polling interval (once the API is added).
3538 if (xhci_interval
!= ep_interval
) {
3539 if (printk_ratelimit())
3540 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3541 " (%d microframe%s) than xHCI "
3542 "(%d microframe%s)\n",
3544 ep_interval
== 1 ? "" : "s",
3546 xhci_interval
== 1 ? "" : "s");
3547 urb
->interval
= xhci_interval
;
3548 /* Convert back to frames for LS/FS devices */
3549 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3550 urb
->dev
->speed
== USB_SPEED_FULL
)
3553 ep_ring
->num_trbs_free_temp
= ep_ring
->num_trbs_free
;
3555 return xhci_queue_isoc_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
3558 /**** Command Ring Operations ****/
3560 /* Generic function for queueing a command TRB on the command ring.
3561 * Check to make sure there's room on the command ring for one command TRB.
3562 * Also check that there's room reserved for commands that must not fail.
3563 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3564 * then only check for the number of reserved spots.
3565 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3566 * because the command event handler may want to resubmit a failed command.
3568 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3569 u32 field3
, u32 field4
, bool command_must_succeed
)
3571 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3574 if (!command_must_succeed
)
3577 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3578 reserved_trbs
, GFP_ATOMIC
);
3580 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3581 if (command_must_succeed
)
3582 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3583 "unfailable commands failed.\n");
3586 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
3587 field4
| xhci
->cmd_ring
->cycle_state
);
3591 /* Queue a slot enable or disable request on the command ring */
3592 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3594 return queue_command(xhci
, 0, 0, 0,
3595 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3598 /* Queue an address device command TRB */
3599 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3602 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3603 upper_32_bits(in_ctx_ptr
), 0,
3604 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3608 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3609 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3611 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3614 /* Queue a reset device command TRB */
3615 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3617 return queue_command(xhci
, 0, 0, 0,
3618 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3622 /* Queue a configure endpoint command TRB */
3623 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3624 u32 slot_id
, bool command_must_succeed
)
3626 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3627 upper_32_bits(in_ctx_ptr
), 0,
3628 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3629 command_must_succeed
);
3632 /* Queue an evaluate context command TRB */
3633 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3634 u32 slot_id
, bool command_must_succeed
)
3636 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3637 upper_32_bits(in_ctx_ptr
), 0,
3638 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3639 command_must_succeed
);
3643 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3644 * activity on an endpoint that is about to be suspended.
3646 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3647 unsigned int ep_index
, int suspend
)
3649 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3650 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3651 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3652 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3654 return queue_command(xhci
, 0, 0, 0,
3655 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3658 /* Set Transfer Ring Dequeue Pointer command.
3659 * This should not be used for endpoints that have streams enabled.
3661 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
3662 unsigned int ep_index
, unsigned int stream_id
,
3663 struct xhci_segment
*deq_seg
,
3664 union xhci_trb
*deq_ptr
, u32 cycle_state
)
3667 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3668 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3669 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3670 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3671 struct xhci_virt_ep
*ep
;
3673 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
3675 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3676 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3680 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3681 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
3682 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3683 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
3686 ep
->queued_deq_seg
= deq_seg
;
3687 ep
->queued_deq_ptr
= deq_ptr
;
3688 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
3689 upper_32_bits(addr
), trb_stream_id
,
3690 trb_slot_id
| trb_ep_index
| type
, false);
3693 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
3694 unsigned int ep_index
)
3696 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3697 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3698 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3700 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,