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module_param: make bool parameters really bool (drivers & misc)
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / usb / gadget / omap_udc.c
1 /*
2 * omap_udc.c -- for OMAP full speed udc; most chips support OTG.
3 *
4 * Copyright (C) 2004 Texas Instruments, Inc.
5 * Copyright (C) 2004-2005 David Brownell
6 *
7 * OMAP2 & DMA support by Kyungmin Park <kyungmin.park@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15 #undef DEBUG
16 #undef VERBOSE
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/timer.h>
27 #include <linux/list.h>
28 #include <linux/interrupt.h>
29 #include <linux/proc_fs.h>
30 #include <linux/mm.h>
31 #include <linux/moduleparam.h>
32 #include <linux/platform_device.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/clk.h>
38 #include <linux/prefetch.h>
39
40 #include <asm/byteorder.h>
41 #include <asm/io.h>
42 #include <asm/irq.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
45 #include <asm/mach-types.h>
46
47 #include <plat/dma.h>
48 #include <plat/usb.h>
49
50 #include "omap_udc.h"
51
52 #undef USB_TRACE
53
54 /* bulk DMA seems to be behaving for both IN and OUT */
55 #define USE_DMA
56
57 /* ISO too */
58 #define USE_ISO
59
60 #define DRIVER_DESC "OMAP UDC driver"
61 #define DRIVER_VERSION "4 October 2004"
62
63 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
64
65 #define OMAP2_DMA_CH(ch) (((ch) - 1) << 1)
66 #define OMAP24XX_DMA(name, ch) (OMAP24XX_DMA_##name + OMAP2_DMA_CH(ch))
67
68 /*
69 * The OMAP UDC needs _very_ early endpoint setup: before enabling the
70 * D+ pullup to allow enumeration. That's too early for the gadget
71 * framework to use from usb_endpoint_enable(), which happens after
72 * enumeration as part of activating an interface. (But if we add an
73 * optional new "UDC not yet running" state to the gadget driver model,
74 * even just during driver binding, the endpoint autoconfig logic is the
75 * natural spot to manufacture new endpoints.)
76 *
77 * So instead of using endpoint enable calls to control the hardware setup,
78 * this driver defines a "fifo mode" parameter. It's used during driver
79 * initialization to choose among a set of pre-defined endpoint configs.
80 * See omap_udc_setup() for available modes, or to add others. That code
81 * lives in an init section, so use this driver as a module if you need
82 * to change the fifo mode after the kernel boots.
83 *
84 * Gadget drivers normally ignore endpoints they don't care about, and
85 * won't include them in configuration descriptors. That means only
86 * misbehaving hosts would even notice they exist.
87 */
88 #ifdef USE_ISO
89 static unsigned fifo_mode = 3;
90 #else
91 static unsigned fifo_mode = 0;
92 #endif
93
94 /* "modprobe omap_udc fifo_mode=42", or else as a kernel
95 * boot parameter "omap_udc:fifo_mode=42"
96 */
97 module_param (fifo_mode, uint, 0);
98 MODULE_PARM_DESC (fifo_mode, "endpoint configuration");
99
100 #ifdef USE_DMA
101 static bool use_dma = 1;
102
103 /* "modprobe omap_udc use_dma=y", or else as a kernel
104 * boot parameter "omap_udc:use_dma=y"
105 */
106 module_param (use_dma, bool, 0);
107 MODULE_PARM_DESC (use_dma, "enable/disable DMA");
108 #else /* !USE_DMA */
109
110 /* save a bit of code */
111 #define use_dma 0
112 #endif /* !USE_DMA */
113
114
115 static const char driver_name [] = "omap_udc";
116 static const char driver_desc [] = DRIVER_DESC;
117
118 /*-------------------------------------------------------------------------*/
119
120 /* there's a notion of "current endpoint" for modifying endpoint
121 * state, and PIO access to its FIFO.
122 */
123
124 static void use_ep(struct omap_ep *ep, u16 select)
125 {
126 u16 num = ep->bEndpointAddress & 0x0f;
127
128 if (ep->bEndpointAddress & USB_DIR_IN)
129 num |= UDC_EP_DIR;
130 omap_writew(num | select, UDC_EP_NUM);
131 /* when select, MUST deselect later !! */
132 }
133
134 static inline void deselect_ep(void)
135 {
136 u16 w;
137
138 w = omap_readw(UDC_EP_NUM);
139 w &= ~UDC_EP_SEL;
140 omap_writew(w, UDC_EP_NUM);
141 /* 6 wait states before TX will happen */
142 }
143
144 static void dma_channel_claim(struct omap_ep *ep, unsigned preferred);
145
146 /*-------------------------------------------------------------------------*/
147
148 static int omap_ep_enable(struct usb_ep *_ep,
149 const struct usb_endpoint_descriptor *desc)
150 {
151 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
152 struct omap_udc *udc;
153 unsigned long flags;
154 u16 maxp;
155
156 /* catch various bogus parameters */
157 if (!_ep || !desc || ep->desc
158 || desc->bDescriptorType != USB_DT_ENDPOINT
159 || ep->bEndpointAddress != desc->bEndpointAddress
160 || ep->maxpacket < usb_endpoint_maxp(desc)) {
161 DBG("%s, bad ep or descriptor\n", __func__);
162 return -EINVAL;
163 }
164 maxp = usb_endpoint_maxp(desc);
165 if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
166 && maxp != ep->maxpacket)
167 || usb_endpoint_maxp(desc) > ep->maxpacket
168 || !desc->wMaxPacketSize) {
169 DBG("%s, bad %s maxpacket\n", __func__, _ep->name);
170 return -ERANGE;
171 }
172
173 #ifdef USE_ISO
174 if ((desc->bmAttributes == USB_ENDPOINT_XFER_ISOC
175 && desc->bInterval != 1)) {
176 /* hardware wants period = 1; USB allows 2^(Interval-1) */
177 DBG("%s, unsupported ISO period %dms\n", _ep->name,
178 1 << (desc->bInterval - 1));
179 return -EDOM;
180 }
181 #else
182 if (desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
183 DBG("%s, ISO nyet\n", _ep->name);
184 return -EDOM;
185 }
186 #endif
187
188 /* xfer types must match, except that interrupt ~= bulk */
189 if (ep->bmAttributes != desc->bmAttributes
190 && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
191 && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
192 DBG("%s, %s type mismatch\n", __func__, _ep->name);
193 return -EINVAL;
194 }
195
196 udc = ep->udc;
197 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN) {
198 DBG("%s, bogus device state\n", __func__);
199 return -ESHUTDOWN;
200 }
201
202 spin_lock_irqsave(&udc->lock, flags);
203
204 ep->desc = desc;
205 ep->irqs = 0;
206 ep->stopped = 0;
207 ep->ep.maxpacket = maxp;
208
209 /* set endpoint to initial state */
210 ep->dma_channel = 0;
211 ep->has_dma = 0;
212 ep->lch = -1;
213 use_ep(ep, UDC_EP_SEL);
214 omap_writew(udc->clr_halt, UDC_CTRL);
215 ep->ackwait = 0;
216 deselect_ep();
217
218 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
219 list_add(&ep->iso, &udc->iso);
220
221 /* maybe assign a DMA channel to this endpoint */
222 if (use_dma && desc->bmAttributes == USB_ENDPOINT_XFER_BULK)
223 /* FIXME ISO can dma, but prefers first channel */
224 dma_channel_claim(ep, 0);
225
226 /* PIO OUT may RX packets */
227 if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
228 && !ep->has_dma
229 && !(ep->bEndpointAddress & USB_DIR_IN)) {
230 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
231 ep->ackwait = 1 + ep->double_buf;
232 }
233
234 spin_unlock_irqrestore(&udc->lock, flags);
235 VDBG("%s enabled\n", _ep->name);
236 return 0;
237 }
238
239 static void nuke(struct omap_ep *, int status);
240
241 static int omap_ep_disable(struct usb_ep *_ep)
242 {
243 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
244 unsigned long flags;
245
246 if (!_ep || !ep->desc) {
247 DBG("%s, %s not enabled\n", __func__,
248 _ep ? ep->ep.name : NULL);
249 return -EINVAL;
250 }
251
252 spin_lock_irqsave(&ep->udc->lock, flags);
253 ep->desc = NULL;
254 nuke (ep, -ESHUTDOWN);
255 ep->ep.maxpacket = ep->maxpacket;
256 ep->has_dma = 0;
257 omap_writew(UDC_SET_HALT, UDC_CTRL);
258 list_del_init(&ep->iso);
259 del_timer(&ep->timer);
260
261 spin_unlock_irqrestore(&ep->udc->lock, flags);
262
263 VDBG("%s disabled\n", _ep->name);
264 return 0;
265 }
266
267 /*-------------------------------------------------------------------------*/
268
269 static struct usb_request *
270 omap_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
271 {
272 struct omap_req *req;
273
274 req = kzalloc(sizeof(*req), gfp_flags);
275 if (req) {
276 req->req.dma = DMA_ADDR_INVALID;
277 INIT_LIST_HEAD (&req->queue);
278 }
279 return &req->req;
280 }
281
282 static void
283 omap_free_request(struct usb_ep *ep, struct usb_request *_req)
284 {
285 struct omap_req *req = container_of(_req, struct omap_req, req);
286
287 if (_req)
288 kfree (req);
289 }
290
291 /*-------------------------------------------------------------------------*/
292
293 static void
294 done(struct omap_ep *ep, struct omap_req *req, int status)
295 {
296 unsigned stopped = ep->stopped;
297
298 list_del_init(&req->queue);
299
300 if (req->req.status == -EINPROGRESS)
301 req->req.status = status;
302 else
303 status = req->req.status;
304
305 if (use_dma && ep->has_dma) {
306 if (req->mapped) {
307 dma_unmap_single(ep->udc->gadget.dev.parent,
308 req->req.dma, req->req.length,
309 (ep->bEndpointAddress & USB_DIR_IN)
310 ? DMA_TO_DEVICE
311 : DMA_FROM_DEVICE);
312 req->req.dma = DMA_ADDR_INVALID;
313 req->mapped = 0;
314 } else
315 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
316 req->req.dma, req->req.length,
317 (ep->bEndpointAddress & USB_DIR_IN)
318 ? DMA_TO_DEVICE
319 : DMA_FROM_DEVICE);
320 }
321
322 #ifndef USB_TRACE
323 if (status && status != -ESHUTDOWN)
324 #endif
325 VDBG("complete %s req %p stat %d len %u/%u\n",
326 ep->ep.name, &req->req, status,
327 req->req.actual, req->req.length);
328
329 /* don't modify queue heads during completion callback */
330 ep->stopped = 1;
331 spin_unlock(&ep->udc->lock);
332 req->req.complete(&ep->ep, &req->req);
333 spin_lock(&ep->udc->lock);
334 ep->stopped = stopped;
335 }
336
337 /*-------------------------------------------------------------------------*/
338
339 #define UDC_FIFO_FULL (UDC_NON_ISO_FIFO_FULL | UDC_ISO_FIFO_FULL)
340 #define UDC_FIFO_UNWRITABLE (UDC_EP_HALTED | UDC_FIFO_FULL)
341
342 #define FIFO_EMPTY (UDC_NON_ISO_FIFO_EMPTY | UDC_ISO_FIFO_EMPTY)
343 #define FIFO_UNREADABLE (UDC_EP_HALTED | FIFO_EMPTY)
344
345 static inline int
346 write_packet(u8 *buf, struct omap_req *req, unsigned max)
347 {
348 unsigned len;
349 u16 *wp;
350
351 len = min(req->req.length - req->req.actual, max);
352 req->req.actual += len;
353
354 max = len;
355 if (likely((((int)buf) & 1) == 0)) {
356 wp = (u16 *)buf;
357 while (max >= 2) {
358 omap_writew(*wp++, UDC_DATA);
359 max -= 2;
360 }
361 buf = (u8 *)wp;
362 }
363 while (max--)
364 omap_writeb(*buf++, UDC_DATA);
365 return len;
366 }
367
368 // FIXME change r/w fifo calling convention
369
370
371 // return: 0 = still running, 1 = completed, negative = errno
372 static int write_fifo(struct omap_ep *ep, struct omap_req *req)
373 {
374 u8 *buf;
375 unsigned count;
376 int is_last;
377 u16 ep_stat;
378
379 buf = req->req.buf + req->req.actual;
380 prefetch(buf);
381
382 /* PIO-IN isn't double buffered except for iso */
383 ep_stat = omap_readw(UDC_STAT_FLG);
384 if (ep_stat & UDC_FIFO_UNWRITABLE)
385 return 0;
386
387 count = ep->ep.maxpacket;
388 count = write_packet(buf, req, count);
389 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
390 ep->ackwait = 1;
391
392 /* last packet is often short (sometimes a zlp) */
393 if (count != ep->ep.maxpacket)
394 is_last = 1;
395 else if (req->req.length == req->req.actual
396 && !req->req.zero)
397 is_last = 1;
398 else
399 is_last = 0;
400
401 /* NOTE: requests complete when all IN data is in a
402 * FIFO (or sometimes later, if a zlp was needed).
403 * Use usb_ep_fifo_status() where needed.
404 */
405 if (is_last)
406 done(ep, req, 0);
407 return is_last;
408 }
409
410 static inline int
411 read_packet(u8 *buf, struct omap_req *req, unsigned avail)
412 {
413 unsigned len;
414 u16 *wp;
415
416 len = min(req->req.length - req->req.actual, avail);
417 req->req.actual += len;
418 avail = len;
419
420 if (likely((((int)buf) & 1) == 0)) {
421 wp = (u16 *)buf;
422 while (avail >= 2) {
423 *wp++ = omap_readw(UDC_DATA);
424 avail -= 2;
425 }
426 buf = (u8 *)wp;
427 }
428 while (avail--)
429 *buf++ = omap_readb(UDC_DATA);
430 return len;
431 }
432
433 // return: 0 = still running, 1 = queue empty, negative = errno
434 static int read_fifo(struct omap_ep *ep, struct omap_req *req)
435 {
436 u8 *buf;
437 unsigned count, avail;
438 int is_last;
439
440 buf = req->req.buf + req->req.actual;
441 prefetchw(buf);
442
443 for (;;) {
444 u16 ep_stat = omap_readw(UDC_STAT_FLG);
445
446 is_last = 0;
447 if (ep_stat & FIFO_EMPTY) {
448 if (!ep->double_buf)
449 break;
450 ep->fnf = 1;
451 }
452 if (ep_stat & UDC_EP_HALTED)
453 break;
454
455 if (ep_stat & UDC_FIFO_FULL)
456 avail = ep->ep.maxpacket;
457 else {
458 avail = omap_readw(UDC_RXFSTAT);
459 ep->fnf = ep->double_buf;
460 }
461 count = read_packet(buf, req, avail);
462
463 /* partial packet reads may not be errors */
464 if (count < ep->ep.maxpacket) {
465 is_last = 1;
466 /* overflowed this request? flush extra data */
467 if (count != avail) {
468 req->req.status = -EOVERFLOW;
469 avail -= count;
470 while (avail--)
471 omap_readw(UDC_DATA);
472 }
473 } else if (req->req.length == req->req.actual)
474 is_last = 1;
475 else
476 is_last = 0;
477
478 if (!ep->bEndpointAddress)
479 break;
480 if (is_last)
481 done(ep, req, 0);
482 break;
483 }
484 return is_last;
485 }
486
487 /*-------------------------------------------------------------------------*/
488
489 static u16 dma_src_len(struct omap_ep *ep, dma_addr_t start)
490 {
491 dma_addr_t end;
492
493 /* IN-DMA needs this on fault/cancel paths, so 15xx misreports
494 * the last transfer's bytecount by more than a FIFO's worth.
495 */
496 if (cpu_is_omap15xx())
497 return 0;
498
499 end = omap_get_dma_src_pos(ep->lch);
500 if (end == ep->dma_counter)
501 return 0;
502
503 end |= start & (0xffff << 16);
504 if (end < start)
505 end += 0x10000;
506 return end - start;
507 }
508
509 static u16 dma_dest_len(struct omap_ep *ep, dma_addr_t start)
510 {
511 dma_addr_t end;
512
513 end = omap_get_dma_dst_pos(ep->lch);
514 if (end == ep->dma_counter)
515 return 0;
516
517 end |= start & (0xffff << 16);
518 if (cpu_is_omap15xx())
519 end++;
520 if (end < start)
521 end += 0x10000;
522 return end - start;
523 }
524
525
526 /* Each USB transfer request using DMA maps to one or more DMA transfers.
527 * When DMA completion isn't request completion, the UDC continues with
528 * the next DMA transfer for that USB transfer.
529 */
530
531 static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
532 {
533 u16 txdma_ctrl, w;
534 unsigned length = req->req.length - req->req.actual;
535 const int sync_mode = cpu_is_omap15xx()
536 ? OMAP_DMA_SYNC_FRAME
537 : OMAP_DMA_SYNC_ELEMENT;
538 int dma_trigger = 0;
539
540 if (cpu_is_omap24xx())
541 dma_trigger = OMAP24XX_DMA(USB_W2FC_TX0, ep->dma_channel);
542
543 /* measure length in either bytes or packets */
544 if ((cpu_is_omap16xx() && length <= UDC_TXN_TSC)
545 || (cpu_is_omap24xx() && length < ep->maxpacket)
546 || (cpu_is_omap15xx() && length < ep->maxpacket)) {
547 txdma_ctrl = UDC_TXN_EOT | length;
548 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
549 length, 1, sync_mode, dma_trigger, 0);
550 } else {
551 length = min(length / ep->maxpacket,
552 (unsigned) UDC_TXN_TSC + 1);
553 txdma_ctrl = length;
554 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
555 ep->ep.maxpacket >> 1, length, sync_mode,
556 dma_trigger, 0);
557 length *= ep->maxpacket;
558 }
559 omap_set_dma_src_params(ep->lch, OMAP_DMA_PORT_EMIFF,
560 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
561 0, 0);
562
563 omap_start_dma(ep->lch);
564 ep->dma_counter = omap_get_dma_src_pos(ep->lch);
565 w = omap_readw(UDC_DMA_IRQ_EN);
566 w |= UDC_TX_DONE_IE(ep->dma_channel);
567 omap_writew(w, UDC_DMA_IRQ_EN);
568 omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
569 req->dma_bytes = length;
570 }
571
572 static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
573 {
574 u16 w;
575
576 if (status == 0) {
577 req->req.actual += req->dma_bytes;
578
579 /* return if this request needs to send data or zlp */
580 if (req->req.actual < req->req.length)
581 return;
582 if (req->req.zero
583 && req->dma_bytes != 0
584 && (req->req.actual % ep->maxpacket) == 0)
585 return;
586 } else
587 req->req.actual += dma_src_len(ep, req->req.dma
588 + req->req.actual);
589
590 /* tx completion */
591 omap_stop_dma(ep->lch);
592 w = omap_readw(UDC_DMA_IRQ_EN);
593 w &= ~UDC_TX_DONE_IE(ep->dma_channel);
594 omap_writew(w, UDC_DMA_IRQ_EN);
595 done(ep, req, status);
596 }
597
598 static void next_out_dma(struct omap_ep *ep, struct omap_req *req)
599 {
600 unsigned packets = req->req.length - req->req.actual;
601 int dma_trigger = 0;
602 u16 w;
603
604 if (cpu_is_omap24xx())
605 dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
606
607 /* NOTE: we filtered out "short reads" before, so we know
608 * the buffer has only whole numbers of packets.
609 * except MODE SELECT(6) sent the 24 bytes data in OMAP24XX DMA mode
610 */
611 if (cpu_is_omap24xx() && packets < ep->maxpacket) {
612 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S8,
613 packets, 1, OMAP_DMA_SYNC_ELEMENT,
614 dma_trigger, 0);
615 req->dma_bytes = packets;
616 } else {
617 /* set up this DMA transfer, enable the fifo, start */
618 packets /= ep->ep.maxpacket;
619 packets = min(packets, (unsigned)UDC_RXN_TC + 1);
620 req->dma_bytes = packets * ep->ep.maxpacket;
621 omap_set_dma_transfer_params(ep->lch, OMAP_DMA_DATA_TYPE_S16,
622 ep->ep.maxpacket >> 1, packets,
623 OMAP_DMA_SYNC_ELEMENT,
624 dma_trigger, 0);
625 }
626 omap_set_dma_dest_params(ep->lch, OMAP_DMA_PORT_EMIFF,
627 OMAP_DMA_AMODE_POST_INC, req->req.dma + req->req.actual,
628 0, 0);
629 ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
630
631 omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
632 w = omap_readw(UDC_DMA_IRQ_EN);
633 w |= UDC_RX_EOT_IE(ep->dma_channel);
634 omap_writew(w, UDC_DMA_IRQ_EN);
635 omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
636 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
637
638 omap_start_dma(ep->lch);
639 }
640
641 static void
642 finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
643 {
644 u16 count, w;
645
646 if (status == 0)
647 ep->dma_counter = (u16) (req->req.dma + req->req.actual);
648 count = dma_dest_len(ep, req->req.dma + req->req.actual);
649 count += req->req.actual;
650 if (one)
651 count--;
652 if (count <= req->req.length)
653 req->req.actual = count;
654
655 if (count != req->dma_bytes || status)
656 omap_stop_dma(ep->lch);
657
658 /* if this wasn't short, request may need another transfer */
659 else if (req->req.actual < req->req.length)
660 return;
661
662 /* rx completion */
663 w = omap_readw(UDC_DMA_IRQ_EN);
664 w &= ~UDC_RX_EOT_IE(ep->dma_channel);
665 omap_writew(w, UDC_DMA_IRQ_EN);
666 done(ep, req, status);
667 }
668
669 static void dma_irq(struct omap_udc *udc, u16 irq_src)
670 {
671 u16 dman_stat = omap_readw(UDC_DMAN_STAT);
672 struct omap_ep *ep;
673 struct omap_req *req;
674
675 /* IN dma: tx to host */
676 if (irq_src & UDC_TXN_DONE) {
677 ep = &udc->ep[16 + UDC_DMA_TX_SRC(dman_stat)];
678 ep->irqs++;
679 /* can see TXN_DONE after dma abort */
680 if (!list_empty(&ep->queue)) {
681 req = container_of(ep->queue.next,
682 struct omap_req, queue);
683 finish_in_dma(ep, req, 0);
684 }
685 omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
686
687 if (!list_empty (&ep->queue)) {
688 req = container_of(ep->queue.next,
689 struct omap_req, queue);
690 next_in_dma(ep, req);
691 }
692 }
693
694 /* OUT dma: rx from host */
695 if (irq_src & UDC_RXN_EOT) {
696 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
697 ep->irqs++;
698 /* can see RXN_EOT after dma abort */
699 if (!list_empty(&ep->queue)) {
700 req = container_of(ep->queue.next,
701 struct omap_req, queue);
702 finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
703 }
704 omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
705
706 if (!list_empty (&ep->queue)) {
707 req = container_of(ep->queue.next,
708 struct omap_req, queue);
709 next_out_dma(ep, req);
710 }
711 }
712
713 if (irq_src & UDC_RXN_CNT) {
714 ep = &udc->ep[UDC_DMA_RX_SRC(dman_stat)];
715 ep->irqs++;
716 /* omap15xx does this unasked... */
717 VDBG("%s, RX_CNT irq?\n", ep->ep.name);
718 omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
719 }
720 }
721
722 static void dma_error(int lch, u16 ch_status, void *data)
723 {
724 struct omap_ep *ep = data;
725
726 /* if ch_status & OMAP_DMA_DROP_IRQ ... */
727 /* if ch_status & OMAP1_DMA_TOUT_IRQ ... */
728 ERR("%s dma error, lch %d status %02x\n", ep->ep.name, lch, ch_status);
729
730 /* complete current transfer ... */
731 }
732
733 static void dma_channel_claim(struct omap_ep *ep, unsigned channel)
734 {
735 u16 reg;
736 int status, restart, is_in;
737 int dma_channel;
738
739 is_in = ep->bEndpointAddress & USB_DIR_IN;
740 if (is_in)
741 reg = omap_readw(UDC_TXDMA_CFG);
742 else
743 reg = omap_readw(UDC_RXDMA_CFG);
744 reg |= UDC_DMA_REQ; /* "pulse" activated */
745
746 ep->dma_channel = 0;
747 ep->lch = -1;
748 if (channel == 0 || channel > 3) {
749 if ((reg & 0x0f00) == 0)
750 channel = 3;
751 else if ((reg & 0x00f0) == 0)
752 channel = 2;
753 else if ((reg & 0x000f) == 0) /* preferred for ISO */
754 channel = 1;
755 else {
756 status = -EMLINK;
757 goto just_restart;
758 }
759 }
760 reg |= (0x0f & ep->bEndpointAddress) << (4 * (channel - 1));
761 ep->dma_channel = channel;
762
763 if (is_in) {
764 if (cpu_is_omap24xx())
765 dma_channel = OMAP24XX_DMA(USB_W2FC_TX0, channel);
766 else
767 dma_channel = OMAP_DMA_USB_W2FC_TX0 - 1 + channel;
768 status = omap_request_dma(dma_channel,
769 ep->ep.name, dma_error, ep, &ep->lch);
770 if (status == 0) {
771 omap_writew(reg, UDC_TXDMA_CFG);
772 /* EMIFF or SDRC */
773 omap_set_dma_src_burst_mode(ep->lch,
774 OMAP_DMA_DATA_BURST_4);
775 omap_set_dma_src_data_pack(ep->lch, 1);
776 /* TIPB */
777 omap_set_dma_dest_params(ep->lch,
778 OMAP_DMA_PORT_TIPB,
779 OMAP_DMA_AMODE_CONSTANT,
780 UDC_DATA_DMA,
781 0, 0);
782 }
783 } else {
784 if (cpu_is_omap24xx())
785 dma_channel = OMAP24XX_DMA(USB_W2FC_RX0, channel);
786 else
787 dma_channel = OMAP_DMA_USB_W2FC_RX0 - 1 + channel;
788
789 status = omap_request_dma(dma_channel,
790 ep->ep.name, dma_error, ep, &ep->lch);
791 if (status == 0) {
792 omap_writew(reg, UDC_RXDMA_CFG);
793 /* TIPB */
794 omap_set_dma_src_params(ep->lch,
795 OMAP_DMA_PORT_TIPB,
796 OMAP_DMA_AMODE_CONSTANT,
797 UDC_DATA_DMA,
798 0, 0);
799 /* EMIFF or SDRC */
800 omap_set_dma_dest_burst_mode(ep->lch,
801 OMAP_DMA_DATA_BURST_4);
802 omap_set_dma_dest_data_pack(ep->lch, 1);
803 }
804 }
805 if (status)
806 ep->dma_channel = 0;
807 else {
808 ep->has_dma = 1;
809 omap_disable_dma_irq(ep->lch, OMAP_DMA_BLOCK_IRQ);
810
811 /* channel type P: hw synch (fifo) */
812 if (cpu_class_is_omap1() && !cpu_is_omap15xx())
813 omap_set_dma_channel_mode(ep->lch, OMAP_DMA_LCH_P);
814 }
815
816 just_restart:
817 /* restart any queue, even if the claim failed */
818 restart = !ep->stopped && !list_empty(&ep->queue);
819
820 if (status)
821 DBG("%s no dma channel: %d%s\n", ep->ep.name, status,
822 restart ? " (restart)" : "");
823 else
824 DBG("%s claimed %cxdma%d lch %d%s\n", ep->ep.name,
825 is_in ? 't' : 'r',
826 ep->dma_channel - 1, ep->lch,
827 restart ? " (restart)" : "");
828
829 if (restart) {
830 struct omap_req *req;
831 req = container_of(ep->queue.next, struct omap_req, queue);
832 if (ep->has_dma)
833 (is_in ? next_in_dma : next_out_dma)(ep, req);
834 else {
835 use_ep(ep, UDC_EP_SEL);
836 (is_in ? write_fifo : read_fifo)(ep, req);
837 deselect_ep();
838 if (!is_in) {
839 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
840 ep->ackwait = 1 + ep->double_buf;
841 }
842 /* IN: 6 wait states before it'll tx */
843 }
844 }
845 }
846
847 static void dma_channel_release(struct omap_ep *ep)
848 {
849 int shift = 4 * (ep->dma_channel - 1);
850 u16 mask = 0x0f << shift;
851 struct omap_req *req;
852 int active;
853
854 /* abort any active usb transfer request */
855 if (!list_empty(&ep->queue))
856 req = container_of(ep->queue.next, struct omap_req, queue);
857 else
858 req = NULL;
859
860 active = omap_get_dma_active_status(ep->lch);
861
862 DBG("%s release %s %cxdma%d %p\n", ep->ep.name,
863 active ? "active" : "idle",
864 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
865 ep->dma_channel - 1, req);
866
867 /* NOTE: re-setting RX_REQ/TX_REQ because of a chip bug (before
868 * OMAP 1710 ES2.0) where reading the DMA_CFG can clear them.
869 */
870
871 /* wait till current packet DMA finishes, and fifo empties */
872 if (ep->bEndpointAddress & USB_DIR_IN) {
873 omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
874 UDC_TXDMA_CFG);
875
876 if (req) {
877 finish_in_dma(ep, req, -ECONNRESET);
878
879 /* clear FIFO; hosts probably won't empty it */
880 use_ep(ep, UDC_EP_SEL);
881 omap_writew(UDC_CLR_EP, UDC_CTRL);
882 deselect_ep();
883 }
884 while (omap_readw(UDC_TXDMA_CFG) & mask)
885 udelay(10);
886 } else {
887 omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
888 UDC_RXDMA_CFG);
889
890 /* dma empties the fifo */
891 while (omap_readw(UDC_RXDMA_CFG) & mask)
892 udelay(10);
893 if (req)
894 finish_out_dma(ep, req, -ECONNRESET, 0);
895 }
896 omap_free_dma(ep->lch);
897 ep->dma_channel = 0;
898 ep->lch = -1;
899 /* has_dma still set, till endpoint is fully quiesced */
900 }
901
902
903 /*-------------------------------------------------------------------------*/
904
905 static int
906 omap_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
907 {
908 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
909 struct omap_req *req = container_of(_req, struct omap_req, req);
910 struct omap_udc *udc;
911 unsigned long flags;
912 int is_iso = 0;
913
914 /* catch various bogus parameters */
915 if (!_req || !req->req.complete || !req->req.buf
916 || !list_empty(&req->queue)) {
917 DBG("%s, bad params\n", __func__);
918 return -EINVAL;
919 }
920 if (!_ep || (!ep->desc && ep->bEndpointAddress)) {
921 DBG("%s, bad ep\n", __func__);
922 return -EINVAL;
923 }
924 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
925 if (req->req.length > ep->ep.maxpacket)
926 return -EMSGSIZE;
927 is_iso = 1;
928 }
929
930 /* this isn't bogus, but OMAP DMA isn't the only hardware to
931 * have a hard time with partial packet reads... reject it.
932 * Except OMAP2 can handle the small packets.
933 */
934 if (use_dma
935 && ep->has_dma
936 && ep->bEndpointAddress != 0
937 && (ep->bEndpointAddress & USB_DIR_IN) == 0
938 && !cpu_class_is_omap2()
939 && (req->req.length % ep->ep.maxpacket) != 0) {
940 DBG("%s, no partial packet OUT reads\n", __func__);
941 return -EMSGSIZE;
942 }
943
944 udc = ep->udc;
945 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
946 return -ESHUTDOWN;
947
948 if (use_dma && ep->has_dma) {
949 if (req->req.dma == DMA_ADDR_INVALID) {
950 req->req.dma = dma_map_single(
951 ep->udc->gadget.dev.parent,
952 req->req.buf,
953 req->req.length,
954 (ep->bEndpointAddress & USB_DIR_IN)
955 ? DMA_TO_DEVICE
956 : DMA_FROM_DEVICE);
957 req->mapped = 1;
958 } else {
959 dma_sync_single_for_device(
960 ep->udc->gadget.dev.parent,
961 req->req.dma, req->req.length,
962 (ep->bEndpointAddress & USB_DIR_IN)
963 ? DMA_TO_DEVICE
964 : DMA_FROM_DEVICE);
965 req->mapped = 0;
966 }
967 }
968
969 VDBG("%s queue req %p, len %d buf %p\n",
970 ep->ep.name, _req, _req->length, _req->buf);
971
972 spin_lock_irqsave(&udc->lock, flags);
973
974 req->req.status = -EINPROGRESS;
975 req->req.actual = 0;
976
977 /* maybe kickstart non-iso i/o queues */
978 if (is_iso) {
979 u16 w;
980
981 w = omap_readw(UDC_IRQ_EN);
982 w |= UDC_SOF_IE;
983 omap_writew(w, UDC_IRQ_EN);
984 } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
985 int is_in;
986
987 if (ep->bEndpointAddress == 0) {
988 if (!udc->ep0_pending || !list_empty (&ep->queue)) {
989 spin_unlock_irqrestore(&udc->lock, flags);
990 return -EL2HLT;
991 }
992
993 /* empty DATA stage? */
994 is_in = udc->ep0_in;
995 if (!req->req.length) {
996
997 /* chip became CONFIGURED or ADDRESSED
998 * earlier; drivers may already have queued
999 * requests to non-control endpoints
1000 */
1001 if (udc->ep0_set_config) {
1002 u16 irq_en = omap_readw(UDC_IRQ_EN);
1003
1004 irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
1005 if (!udc->ep0_reset_config)
1006 irq_en |= UDC_EPN_RX_IE
1007 | UDC_EPN_TX_IE;
1008 omap_writew(irq_en, UDC_IRQ_EN);
1009 }
1010
1011 /* STATUS for zero length DATA stages is
1012 * always an IN ... even for IN transfers,
1013 * a weird case which seem to stall OMAP.
1014 */
1015 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1016 omap_writew(UDC_CLR_EP, UDC_CTRL);
1017 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1018 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1019
1020 /* cleanup */
1021 udc->ep0_pending = 0;
1022 done(ep, req, 0);
1023 req = NULL;
1024
1025 /* non-empty DATA stage */
1026 } else if (is_in) {
1027 omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
1028 } else {
1029 if (udc->ep0_setup)
1030 goto irq_wait;
1031 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1032 }
1033 } else {
1034 is_in = ep->bEndpointAddress & USB_DIR_IN;
1035 if (!ep->has_dma)
1036 use_ep(ep, UDC_EP_SEL);
1037 /* if ISO: SOF IRQs must be enabled/disabled! */
1038 }
1039
1040 if (ep->has_dma)
1041 (is_in ? next_in_dma : next_out_dma)(ep, req);
1042 else if (req) {
1043 if ((is_in ? write_fifo : read_fifo)(ep, req) == 1)
1044 req = NULL;
1045 deselect_ep();
1046 if (!is_in) {
1047 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1048 ep->ackwait = 1 + ep->double_buf;
1049 }
1050 /* IN: 6 wait states before it'll tx */
1051 }
1052 }
1053
1054 irq_wait:
1055 /* irq handler advances the queue */
1056 if (req != NULL)
1057 list_add_tail(&req->queue, &ep->queue);
1058 spin_unlock_irqrestore(&udc->lock, flags);
1059
1060 return 0;
1061 }
1062
1063 static int omap_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1064 {
1065 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1066 struct omap_req *req;
1067 unsigned long flags;
1068
1069 if (!_ep || !_req)
1070 return -EINVAL;
1071
1072 spin_lock_irqsave(&ep->udc->lock, flags);
1073
1074 /* make sure it's actually queued on this endpoint */
1075 list_for_each_entry (req, &ep->queue, queue) {
1076 if (&req->req == _req)
1077 break;
1078 }
1079 if (&req->req != _req) {
1080 spin_unlock_irqrestore(&ep->udc->lock, flags);
1081 return -EINVAL;
1082 }
1083
1084 if (use_dma && ep->dma_channel && ep->queue.next == &req->queue) {
1085 int channel = ep->dma_channel;
1086
1087 /* releasing the channel cancels the request,
1088 * reclaiming the channel restarts the queue
1089 */
1090 dma_channel_release(ep);
1091 dma_channel_claim(ep, channel);
1092 } else
1093 done(ep, req, -ECONNRESET);
1094 spin_unlock_irqrestore(&ep->udc->lock, flags);
1095 return 0;
1096 }
1097
1098 /*-------------------------------------------------------------------------*/
1099
1100 static int omap_ep_set_halt(struct usb_ep *_ep, int value)
1101 {
1102 struct omap_ep *ep = container_of(_ep, struct omap_ep, ep);
1103 unsigned long flags;
1104 int status = -EOPNOTSUPP;
1105
1106 spin_lock_irqsave(&ep->udc->lock, flags);
1107
1108 /* just use protocol stalls for ep0; real halts are annoying */
1109 if (ep->bEndpointAddress == 0) {
1110 if (!ep->udc->ep0_pending)
1111 status = -EINVAL;
1112 else if (value) {
1113 if (ep->udc->ep0_set_config) {
1114 WARNING("error changing config?\n");
1115 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1116 }
1117 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1118 ep->udc->ep0_pending = 0;
1119 status = 0;
1120 } else /* NOP */
1121 status = 0;
1122
1123 /* otherwise, all active non-ISO endpoints can halt */
1124 } else if (ep->bmAttributes != USB_ENDPOINT_XFER_ISOC && ep->desc) {
1125
1126 /* IN endpoints must already be idle */
1127 if ((ep->bEndpointAddress & USB_DIR_IN)
1128 && !list_empty(&ep->queue)) {
1129 status = -EAGAIN;
1130 goto done;
1131 }
1132
1133 if (value) {
1134 int channel;
1135
1136 if (use_dma && ep->dma_channel
1137 && !list_empty(&ep->queue)) {
1138 channel = ep->dma_channel;
1139 dma_channel_release(ep);
1140 } else
1141 channel = 0;
1142
1143 use_ep(ep, UDC_EP_SEL);
1144 if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
1145 omap_writew(UDC_SET_HALT, UDC_CTRL);
1146 status = 0;
1147 } else
1148 status = -EAGAIN;
1149 deselect_ep();
1150
1151 if (channel)
1152 dma_channel_claim(ep, channel);
1153 } else {
1154 use_ep(ep, 0);
1155 omap_writew(ep->udc->clr_halt, UDC_CTRL);
1156 ep->ackwait = 0;
1157 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1158 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1159 ep->ackwait = 1 + ep->double_buf;
1160 }
1161 }
1162 }
1163 done:
1164 VDBG("%s %s halt stat %d\n", ep->ep.name,
1165 value ? "set" : "clear", status);
1166
1167 spin_unlock_irqrestore(&ep->udc->lock, flags);
1168 return status;
1169 }
1170
1171 static struct usb_ep_ops omap_ep_ops = {
1172 .enable = omap_ep_enable,
1173 .disable = omap_ep_disable,
1174
1175 .alloc_request = omap_alloc_request,
1176 .free_request = omap_free_request,
1177
1178 .queue = omap_ep_queue,
1179 .dequeue = omap_ep_dequeue,
1180
1181 .set_halt = omap_ep_set_halt,
1182 // fifo_status ... report bytes in fifo
1183 // fifo_flush ... flush fifo
1184 };
1185
1186 /*-------------------------------------------------------------------------*/
1187
1188 static int omap_get_frame(struct usb_gadget *gadget)
1189 {
1190 u16 sof = omap_readw(UDC_SOF);
1191 return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
1192 }
1193
1194 static int omap_wakeup(struct usb_gadget *gadget)
1195 {
1196 struct omap_udc *udc;
1197 unsigned long flags;
1198 int retval = -EHOSTUNREACH;
1199
1200 udc = container_of(gadget, struct omap_udc, gadget);
1201
1202 spin_lock_irqsave(&udc->lock, flags);
1203 if (udc->devstat & UDC_SUS) {
1204 /* NOTE: OTG spec erratum says that OTG devices may
1205 * issue wakeups without host enable.
1206 */
1207 if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
1208 DBG("remote wakeup...\n");
1209 omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
1210 retval = 0;
1211 }
1212
1213 /* NOTE: non-OTG systems may use SRP TOO... */
1214 } else if (!(udc->devstat & UDC_ATT)) {
1215 if (udc->transceiver)
1216 retval = otg_start_srp(udc->transceiver);
1217 }
1218 spin_unlock_irqrestore(&udc->lock, flags);
1219
1220 return retval;
1221 }
1222
1223 static int
1224 omap_set_selfpowered(struct usb_gadget *gadget, int is_selfpowered)
1225 {
1226 struct omap_udc *udc;
1227 unsigned long flags;
1228 u16 syscon1;
1229
1230 udc = container_of(gadget, struct omap_udc, gadget);
1231 spin_lock_irqsave(&udc->lock, flags);
1232 syscon1 = omap_readw(UDC_SYSCON1);
1233 if (is_selfpowered)
1234 syscon1 |= UDC_SELF_PWR;
1235 else
1236 syscon1 &= ~UDC_SELF_PWR;
1237 omap_writew(syscon1, UDC_SYSCON1);
1238 spin_unlock_irqrestore(&udc->lock, flags);
1239
1240 return 0;
1241 }
1242
1243 static int can_pullup(struct omap_udc *udc)
1244 {
1245 return udc->driver && udc->softconnect && udc->vbus_active;
1246 }
1247
1248 static void pullup_enable(struct omap_udc *udc)
1249 {
1250 u16 w;
1251
1252 w = omap_readw(UDC_SYSCON1);
1253 w |= UDC_PULLUP_EN;
1254 omap_writew(w, UDC_SYSCON1);
1255 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1256 u32 l;
1257
1258 l = omap_readl(OTG_CTRL);
1259 l |= OTG_BSESSVLD;
1260 omap_writel(l, OTG_CTRL);
1261 }
1262 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1263 }
1264
1265 static void pullup_disable(struct omap_udc *udc)
1266 {
1267 u16 w;
1268
1269 if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
1270 u32 l;
1271
1272 l = omap_readl(OTG_CTRL);
1273 l &= ~OTG_BSESSVLD;
1274 omap_writel(l, OTG_CTRL);
1275 }
1276 omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
1277 w = omap_readw(UDC_SYSCON1);
1278 w &= ~UDC_PULLUP_EN;
1279 omap_writew(w, UDC_SYSCON1);
1280 }
1281
1282 static struct omap_udc *udc;
1283
1284 static void omap_udc_enable_clock(int enable)
1285 {
1286 if (udc == NULL || udc->dc_clk == NULL || udc->hhc_clk == NULL)
1287 return;
1288
1289 if (enable) {
1290 clk_enable(udc->dc_clk);
1291 clk_enable(udc->hhc_clk);
1292 udelay(100);
1293 } else {
1294 clk_disable(udc->hhc_clk);
1295 clk_disable(udc->dc_clk);
1296 }
1297 }
1298
1299 /*
1300 * Called by whatever detects VBUS sessions: external transceiver
1301 * driver, or maybe GPIO0 VBUS IRQ. May request 48 MHz clock.
1302 */
1303 static int omap_vbus_session(struct usb_gadget *gadget, int is_active)
1304 {
1305 struct omap_udc *udc;
1306 unsigned long flags;
1307 u32 l;
1308
1309 udc = container_of(gadget, struct omap_udc, gadget);
1310 spin_lock_irqsave(&udc->lock, flags);
1311 VDBG("VBUS %s\n", is_active ? "on" : "off");
1312 udc->vbus_active = (is_active != 0);
1313 if (cpu_is_omap15xx()) {
1314 /* "software" detect, ignored if !VBUS_MODE_1510 */
1315 l = omap_readl(FUNC_MUX_CTRL_0);
1316 if (is_active)
1317 l |= VBUS_CTRL_1510;
1318 else
1319 l &= ~VBUS_CTRL_1510;
1320 omap_writel(l, FUNC_MUX_CTRL_0);
1321 }
1322 if (udc->dc_clk != NULL && is_active) {
1323 if (!udc->clk_requested) {
1324 omap_udc_enable_clock(1);
1325 udc->clk_requested = 1;
1326 }
1327 }
1328 if (can_pullup(udc))
1329 pullup_enable(udc);
1330 else
1331 pullup_disable(udc);
1332 if (udc->dc_clk != NULL && !is_active) {
1333 if (udc->clk_requested) {
1334 omap_udc_enable_clock(0);
1335 udc->clk_requested = 0;
1336 }
1337 }
1338 spin_unlock_irqrestore(&udc->lock, flags);
1339 return 0;
1340 }
1341
1342 static int omap_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1343 {
1344 struct omap_udc *udc;
1345
1346 udc = container_of(gadget, struct omap_udc, gadget);
1347 if (udc->transceiver)
1348 return otg_set_power(udc->transceiver, mA);
1349 return -EOPNOTSUPP;
1350 }
1351
1352 static int omap_pullup(struct usb_gadget *gadget, int is_on)
1353 {
1354 struct omap_udc *udc;
1355 unsigned long flags;
1356
1357 udc = container_of(gadget, struct omap_udc, gadget);
1358 spin_lock_irqsave(&udc->lock, flags);
1359 udc->softconnect = (is_on != 0);
1360 if (can_pullup(udc))
1361 pullup_enable(udc);
1362 else
1363 pullup_disable(udc);
1364 spin_unlock_irqrestore(&udc->lock, flags);
1365 return 0;
1366 }
1367
1368 static int omap_udc_start(struct usb_gadget_driver *driver,
1369 int (*bind)(struct usb_gadget *));
1370 static int omap_udc_stop(struct usb_gadget_driver *driver);
1371
1372 static struct usb_gadget_ops omap_gadget_ops = {
1373 .get_frame = omap_get_frame,
1374 .wakeup = omap_wakeup,
1375 .set_selfpowered = omap_set_selfpowered,
1376 .vbus_session = omap_vbus_session,
1377 .vbus_draw = omap_vbus_draw,
1378 .pullup = omap_pullup,
1379 .start = omap_udc_start,
1380 .stop = omap_udc_stop,
1381 };
1382
1383 /*-------------------------------------------------------------------------*/
1384
1385 /* dequeue ALL requests; caller holds udc->lock */
1386 static void nuke(struct omap_ep *ep, int status)
1387 {
1388 struct omap_req *req;
1389
1390 ep->stopped = 1;
1391
1392 if (use_dma && ep->dma_channel)
1393 dma_channel_release(ep);
1394
1395 use_ep(ep, 0);
1396 omap_writew(UDC_CLR_EP, UDC_CTRL);
1397 if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
1398 omap_writew(UDC_SET_HALT, UDC_CTRL);
1399
1400 while (!list_empty(&ep->queue)) {
1401 req = list_entry(ep->queue.next, struct omap_req, queue);
1402 done(ep, req, status);
1403 }
1404 }
1405
1406 /* caller holds udc->lock */
1407 static void udc_quiesce(struct omap_udc *udc)
1408 {
1409 struct omap_ep *ep;
1410
1411 udc->gadget.speed = USB_SPEED_UNKNOWN;
1412 nuke(&udc->ep[0], -ESHUTDOWN);
1413 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list)
1414 nuke(ep, -ESHUTDOWN);
1415 }
1416
1417 /*-------------------------------------------------------------------------*/
1418
1419 static void update_otg(struct omap_udc *udc)
1420 {
1421 u16 devstat;
1422
1423 if (!gadget_is_otg(&udc->gadget))
1424 return;
1425
1426 if (omap_readl(OTG_CTRL) & OTG_ID)
1427 devstat = omap_readw(UDC_DEVSTAT);
1428 else
1429 devstat = 0;
1430
1431 udc->gadget.b_hnp_enable = !!(devstat & UDC_B_HNP_ENABLE);
1432 udc->gadget.a_hnp_support = !!(devstat & UDC_A_HNP_SUPPORT);
1433 udc->gadget.a_alt_hnp_support = !!(devstat & UDC_A_ALT_HNP_SUPPORT);
1434
1435 /* Enable HNP early, avoiding races on suspend irq path.
1436 * ASSUMES OTG state machine B_BUS_REQ input is true.
1437 */
1438 if (udc->gadget.b_hnp_enable) {
1439 u32 l;
1440
1441 l = omap_readl(OTG_CTRL);
1442 l |= OTG_B_HNPEN | OTG_B_BUSREQ;
1443 l &= ~OTG_PULLUP;
1444 omap_writel(l, OTG_CTRL);
1445 }
1446 }
1447
1448 static void ep0_irq(struct omap_udc *udc, u16 irq_src)
1449 {
1450 struct omap_ep *ep0 = &udc->ep[0];
1451 struct omap_req *req = NULL;
1452
1453 ep0->irqs++;
1454
1455 /* Clear any pending requests and then scrub any rx/tx state
1456 * before starting to handle the SETUP request.
1457 */
1458 if (irq_src & UDC_SETUP) {
1459 u16 ack = irq_src & (UDC_EP0_TX|UDC_EP0_RX);
1460
1461 nuke(ep0, 0);
1462 if (ack) {
1463 omap_writew(ack, UDC_IRQ_SRC);
1464 irq_src = UDC_SETUP;
1465 }
1466 }
1467
1468 /* IN/OUT packets mean we're in the DATA or STATUS stage.
1469 * This driver uses only uses protocol stalls (ep0 never halts),
1470 * and if we got this far the gadget driver already had a
1471 * chance to stall. Tries to be forgiving of host oddities.
1472 *
1473 * NOTE: the last chance gadget drivers have to stall control
1474 * requests is during their request completion callback.
1475 */
1476 if (!list_empty(&ep0->queue))
1477 req = container_of(ep0->queue.next, struct omap_req, queue);
1478
1479 /* IN == TX to host */
1480 if (irq_src & UDC_EP0_TX) {
1481 int stat;
1482
1483 omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
1484 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1485 stat = omap_readw(UDC_STAT_FLG);
1486 if (stat & UDC_ACK) {
1487 if (udc->ep0_in) {
1488 /* write next IN packet from response,
1489 * or set up the status stage.
1490 */
1491 if (req)
1492 stat = write_fifo(ep0, req);
1493 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1494 if (!req && udc->ep0_pending) {
1495 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1496 omap_writew(UDC_CLR_EP, UDC_CTRL);
1497 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1498 omap_writew(0, UDC_EP_NUM);
1499 udc->ep0_pending = 0;
1500 } /* else: 6 wait states before it'll tx */
1501 } else {
1502 /* ack status stage of OUT transfer */
1503 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1504 if (req)
1505 done(ep0, req, 0);
1506 }
1507 req = NULL;
1508 } else if (stat & UDC_STALL) {
1509 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1510 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1511 } else {
1512 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1513 }
1514 }
1515
1516 /* OUT == RX from host */
1517 if (irq_src & UDC_EP0_RX) {
1518 int stat;
1519
1520 omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
1521 omap_writew(UDC_EP_SEL, UDC_EP_NUM);
1522 stat = omap_readw(UDC_STAT_FLG);
1523 if (stat & UDC_ACK) {
1524 if (!udc->ep0_in) {
1525 stat = 0;
1526 /* read next OUT packet of request, maybe
1527 * reactiviting the fifo; stall on errors.
1528 */
1529 if (!req || (stat = read_fifo(ep0, req)) < 0) {
1530 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1531 udc->ep0_pending = 0;
1532 stat = 0;
1533 } else if (stat == 0)
1534 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1535 omap_writew(0, UDC_EP_NUM);
1536
1537 /* activate status stage */
1538 if (stat == 1) {
1539 done(ep0, req, 0);
1540 /* that may have STALLed ep0... */
1541 omap_writew(UDC_EP_SEL | UDC_EP_DIR,
1542 UDC_EP_NUM);
1543 omap_writew(UDC_CLR_EP, UDC_CTRL);
1544 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1545 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1546 udc->ep0_pending = 0;
1547 }
1548 } else {
1549 /* ack status stage of IN transfer */
1550 omap_writew(0, UDC_EP_NUM);
1551 if (req)
1552 done(ep0, req, 0);
1553 }
1554 } else if (stat & UDC_STALL) {
1555 omap_writew(UDC_CLR_HALT, UDC_CTRL);
1556 omap_writew(0, UDC_EP_NUM);
1557 } else {
1558 omap_writew(0, UDC_EP_NUM);
1559 }
1560 }
1561
1562 /* SETUP starts all control transfers */
1563 if (irq_src & UDC_SETUP) {
1564 union u {
1565 u16 word[4];
1566 struct usb_ctrlrequest r;
1567 } u;
1568 int status = -EINVAL;
1569 struct omap_ep *ep;
1570
1571 /* read the (latest) SETUP message */
1572 do {
1573 omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
1574 /* two bytes at a time */
1575 u.word[0] = omap_readw(UDC_DATA);
1576 u.word[1] = omap_readw(UDC_DATA);
1577 u.word[2] = omap_readw(UDC_DATA);
1578 u.word[3] = omap_readw(UDC_DATA);
1579 omap_writew(0, UDC_EP_NUM);
1580 } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
1581
1582 #define w_value le16_to_cpu(u.r.wValue)
1583 #define w_index le16_to_cpu(u.r.wIndex)
1584 #define w_length le16_to_cpu(u.r.wLength)
1585
1586 /* Delegate almost all control requests to the gadget driver,
1587 * except for a handful of ch9 status/feature requests that
1588 * hardware doesn't autodecode _and_ the gadget API hides.
1589 */
1590 udc->ep0_in = (u.r.bRequestType & USB_DIR_IN) != 0;
1591 udc->ep0_set_config = 0;
1592 udc->ep0_pending = 1;
1593 ep0->stopped = 0;
1594 ep0->ackwait = 0;
1595 switch (u.r.bRequest) {
1596 case USB_REQ_SET_CONFIGURATION:
1597 /* udc needs to know when ep != 0 is valid */
1598 if (u.r.bRequestType != USB_RECIP_DEVICE)
1599 goto delegate;
1600 if (w_length != 0)
1601 goto do_stall;
1602 udc->ep0_set_config = 1;
1603 udc->ep0_reset_config = (w_value == 0);
1604 VDBG("set config %d\n", w_value);
1605
1606 /* update udc NOW since gadget driver may start
1607 * queueing requests immediately; clear config
1608 * later if it fails the request.
1609 */
1610 if (udc->ep0_reset_config)
1611 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1612 else
1613 omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
1614 update_otg(udc);
1615 goto delegate;
1616 case USB_REQ_CLEAR_FEATURE:
1617 /* clear endpoint halt */
1618 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1619 goto delegate;
1620 if (w_value != USB_ENDPOINT_HALT
1621 || w_length != 0)
1622 goto do_stall;
1623 ep = &udc->ep[w_index & 0xf];
1624 if (ep != ep0) {
1625 if (w_index & USB_DIR_IN)
1626 ep += 16;
1627 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1628 || !ep->desc)
1629 goto do_stall;
1630 use_ep(ep, 0);
1631 omap_writew(udc->clr_halt, UDC_CTRL);
1632 ep->ackwait = 0;
1633 if (!(ep->bEndpointAddress & USB_DIR_IN)) {
1634 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1635 ep->ackwait = 1 + ep->double_buf;
1636 }
1637 /* NOTE: assumes the host behaves sanely,
1638 * only clearing real halts. Else we may
1639 * need to kill pending transfers and then
1640 * restart the queue... very messy for DMA!
1641 */
1642 }
1643 VDBG("%s halt cleared by host\n", ep->name);
1644 goto ep0out_status_stage;
1645 case USB_REQ_SET_FEATURE:
1646 /* set endpoint halt */
1647 if (u.r.bRequestType != USB_RECIP_ENDPOINT)
1648 goto delegate;
1649 if (w_value != USB_ENDPOINT_HALT
1650 || w_length != 0)
1651 goto do_stall;
1652 ep = &udc->ep[w_index & 0xf];
1653 if (w_index & USB_DIR_IN)
1654 ep += 16;
1655 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
1656 || ep == ep0 || !ep->desc)
1657 goto do_stall;
1658 if (use_dma && ep->has_dma) {
1659 /* this has rude side-effects (aborts) and
1660 * can't really work if DMA-IN is active
1661 */
1662 DBG("%s host set_halt, NYET \n", ep->name);
1663 goto do_stall;
1664 }
1665 use_ep(ep, 0);
1666 /* can't halt if fifo isn't empty... */
1667 omap_writew(UDC_CLR_EP, UDC_CTRL);
1668 omap_writew(UDC_SET_HALT, UDC_CTRL);
1669 VDBG("%s halted by host\n", ep->name);
1670 ep0out_status_stage:
1671 status = 0;
1672 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1673 omap_writew(UDC_CLR_EP, UDC_CTRL);
1674 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1675 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1676 udc->ep0_pending = 0;
1677 break;
1678 case USB_REQ_GET_STATUS:
1679 /* USB_ENDPOINT_HALT status? */
1680 if (u.r.bRequestType != (USB_DIR_IN|USB_RECIP_ENDPOINT))
1681 goto intf_status;
1682
1683 /* ep0 never stalls */
1684 if (!(w_index & 0xf))
1685 goto zero_status;
1686
1687 /* only active endpoints count */
1688 ep = &udc->ep[w_index & 0xf];
1689 if (w_index & USB_DIR_IN)
1690 ep += 16;
1691 if (!ep->desc)
1692 goto do_stall;
1693
1694 /* iso never stalls */
1695 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
1696 goto zero_status;
1697
1698 /* FIXME don't assume non-halted endpoints!! */
1699 ERR("%s status, can't report\n", ep->ep.name);
1700 goto do_stall;
1701
1702 intf_status:
1703 /* return interface status. if we were pedantic,
1704 * we'd detect non-existent interfaces, and stall.
1705 */
1706 if (u.r.bRequestType
1707 != (USB_DIR_IN|USB_RECIP_INTERFACE))
1708 goto delegate;
1709
1710 zero_status:
1711 /* return two zero bytes */
1712 omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
1713 omap_writew(0, UDC_DATA);
1714 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1715 omap_writew(UDC_EP_DIR, UDC_EP_NUM);
1716 status = 0;
1717 VDBG("GET_STATUS, interface %d\n", w_index);
1718 /* next, status stage */
1719 break;
1720 default:
1721 delegate:
1722 /* activate the ep0out fifo right away */
1723 if (!udc->ep0_in && w_length) {
1724 omap_writew(0, UDC_EP_NUM);
1725 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1726 }
1727
1728 /* gadget drivers see class/vendor specific requests,
1729 * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1730 * and more
1731 */
1732 VDBG("SETUP %02x.%02x v%04x i%04x l%04x\n",
1733 u.r.bRequestType, u.r.bRequest,
1734 w_value, w_index, w_length);
1735
1736 #undef w_value
1737 #undef w_index
1738 #undef w_length
1739
1740 /* The gadget driver may return an error here,
1741 * causing an immediate protocol stall.
1742 *
1743 * Else it must issue a response, either queueing a
1744 * response buffer for the DATA stage, or halting ep0
1745 * (causing a protocol stall, not a real halt). A
1746 * zero length buffer means no DATA stage.
1747 *
1748 * It's fine to issue that response after the setup()
1749 * call returns, and this IRQ was handled.
1750 */
1751 udc->ep0_setup = 1;
1752 spin_unlock(&udc->lock);
1753 status = udc->driver->setup (&udc->gadget, &u.r);
1754 spin_lock(&udc->lock);
1755 udc->ep0_setup = 0;
1756 }
1757
1758 if (status < 0) {
1759 do_stall:
1760 VDBG("req %02x.%02x protocol STALL; stat %d\n",
1761 u.r.bRequestType, u.r.bRequest, status);
1762 if (udc->ep0_set_config) {
1763 if (udc->ep0_reset_config)
1764 WARNING("error resetting config?\n");
1765 else
1766 omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
1767 }
1768 omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
1769 udc->ep0_pending = 0;
1770 }
1771 }
1772 }
1773
1774 /*-------------------------------------------------------------------------*/
1775
1776 #define OTG_FLAGS (UDC_B_HNP_ENABLE|UDC_A_HNP_SUPPORT|UDC_A_ALT_HNP_SUPPORT)
1777
1778 static void devstate_irq(struct omap_udc *udc, u16 irq_src)
1779 {
1780 u16 devstat, change;
1781
1782 devstat = omap_readw(UDC_DEVSTAT);
1783 change = devstat ^ udc->devstat;
1784 udc->devstat = devstat;
1785
1786 if (change & (UDC_USB_RESET|UDC_ATT)) {
1787 udc_quiesce(udc);
1788
1789 if (change & UDC_ATT) {
1790 /* driver for any external transceiver will
1791 * have called omap_vbus_session() already
1792 */
1793 if (devstat & UDC_ATT) {
1794 udc->gadget.speed = USB_SPEED_FULL;
1795 VDBG("connect\n");
1796 if (!udc->transceiver)
1797 pullup_enable(udc);
1798 // if (driver->connect) call it
1799 } else if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1800 udc->gadget.speed = USB_SPEED_UNKNOWN;
1801 if (!udc->transceiver)
1802 pullup_disable(udc);
1803 DBG("disconnect, gadget %s\n",
1804 udc->driver->driver.name);
1805 if (udc->driver->disconnect) {
1806 spin_unlock(&udc->lock);
1807 udc->driver->disconnect(&udc->gadget);
1808 spin_lock(&udc->lock);
1809 }
1810 }
1811 change &= ~UDC_ATT;
1812 }
1813
1814 if (change & UDC_USB_RESET) {
1815 if (devstat & UDC_USB_RESET) {
1816 VDBG("RESET=1\n");
1817 } else {
1818 udc->gadget.speed = USB_SPEED_FULL;
1819 INFO("USB reset done, gadget %s\n",
1820 udc->driver->driver.name);
1821 /* ep0 traffic is legal from now on */
1822 omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
1823 UDC_IRQ_EN);
1824 }
1825 change &= ~UDC_USB_RESET;
1826 }
1827 }
1828 if (change & UDC_SUS) {
1829 if (udc->gadget.speed != USB_SPEED_UNKNOWN) {
1830 // FIXME tell isp1301 to suspend/resume (?)
1831 if (devstat & UDC_SUS) {
1832 VDBG("suspend\n");
1833 update_otg(udc);
1834 /* HNP could be under way already */
1835 if (udc->gadget.speed == USB_SPEED_FULL
1836 && udc->driver->suspend) {
1837 spin_unlock(&udc->lock);
1838 udc->driver->suspend(&udc->gadget);
1839 spin_lock(&udc->lock);
1840 }
1841 if (udc->transceiver)
1842 otg_set_suspend(udc->transceiver, 1);
1843 } else {
1844 VDBG("resume\n");
1845 if (udc->transceiver)
1846 otg_set_suspend(udc->transceiver, 0);
1847 if (udc->gadget.speed == USB_SPEED_FULL
1848 && udc->driver->resume) {
1849 spin_unlock(&udc->lock);
1850 udc->driver->resume(&udc->gadget);
1851 spin_lock(&udc->lock);
1852 }
1853 }
1854 }
1855 change &= ~UDC_SUS;
1856 }
1857 if (!cpu_is_omap15xx() && (change & OTG_FLAGS)) {
1858 update_otg(udc);
1859 change &= ~OTG_FLAGS;
1860 }
1861
1862 change &= ~(UDC_CFG|UDC_DEF|UDC_ADD);
1863 if (change)
1864 VDBG("devstat %03x, ignore change %03x\n",
1865 devstat, change);
1866
1867 omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
1868 }
1869
1870 static irqreturn_t omap_udc_irq(int irq, void *_udc)
1871 {
1872 struct omap_udc *udc = _udc;
1873 u16 irq_src;
1874 irqreturn_t status = IRQ_NONE;
1875 unsigned long flags;
1876
1877 spin_lock_irqsave(&udc->lock, flags);
1878 irq_src = omap_readw(UDC_IRQ_SRC);
1879
1880 /* Device state change (usb ch9 stuff) */
1881 if (irq_src & UDC_DS_CHG) {
1882 devstate_irq(_udc, irq_src);
1883 status = IRQ_HANDLED;
1884 irq_src &= ~UDC_DS_CHG;
1885 }
1886
1887 /* EP0 control transfers */
1888 if (irq_src & (UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX)) {
1889 ep0_irq(_udc, irq_src);
1890 status = IRQ_HANDLED;
1891 irq_src &= ~(UDC_EP0_RX|UDC_SETUP|UDC_EP0_TX);
1892 }
1893
1894 /* DMA transfer completion */
1895 if (use_dma && (irq_src & (UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT))) {
1896 dma_irq(_udc, irq_src);
1897 status = IRQ_HANDLED;
1898 irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
1899 }
1900
1901 irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
1902 if (irq_src)
1903 DBG("udc_irq, unhandled %03x\n", irq_src);
1904 spin_unlock_irqrestore(&udc->lock, flags);
1905
1906 return status;
1907 }
1908
1909 /* workaround for seemingly-lost IRQs for RX ACKs... */
1910 #define PIO_OUT_TIMEOUT (jiffies + HZ/3)
1911 #define HALF_FULL(f) (!((f)&(UDC_NON_ISO_FIFO_FULL|UDC_NON_ISO_FIFO_EMPTY)))
1912
1913 static void pio_out_timer(unsigned long _ep)
1914 {
1915 struct omap_ep *ep = (void *) _ep;
1916 unsigned long flags;
1917 u16 stat_flg;
1918
1919 spin_lock_irqsave(&ep->udc->lock, flags);
1920 if (!list_empty(&ep->queue) && ep->ackwait) {
1921 use_ep(ep, UDC_EP_SEL);
1922 stat_flg = omap_readw(UDC_STAT_FLG);
1923
1924 if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
1925 || (ep->double_buf && HALF_FULL(stat_flg)))) {
1926 struct omap_req *req;
1927
1928 VDBG("%s: lose, %04x\n", ep->ep.name, stat_flg);
1929 req = container_of(ep->queue.next,
1930 struct omap_req, queue);
1931 (void) read_fifo(ep, req);
1932 omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
1933 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1934 ep->ackwait = 1 + ep->double_buf;
1935 } else
1936 deselect_ep();
1937 }
1938 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1939 spin_unlock_irqrestore(&ep->udc->lock, flags);
1940 }
1941
1942 static irqreturn_t omap_udc_pio_irq(int irq, void *_dev)
1943 {
1944 u16 epn_stat, irq_src;
1945 irqreturn_t status = IRQ_NONE;
1946 struct omap_ep *ep;
1947 int epnum;
1948 struct omap_udc *udc = _dev;
1949 struct omap_req *req;
1950 unsigned long flags;
1951
1952 spin_lock_irqsave(&udc->lock, flags);
1953 epn_stat = omap_readw(UDC_EPN_STAT);
1954 irq_src = omap_readw(UDC_IRQ_SRC);
1955
1956 /* handle OUT first, to avoid some wasteful NAKs */
1957 if (irq_src & UDC_EPN_RX) {
1958 epnum = (epn_stat >> 8) & 0x0f;
1959 omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
1960 status = IRQ_HANDLED;
1961 ep = &udc->ep[epnum];
1962 ep->irqs++;
1963
1964 omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
1965 ep->fnf = 0;
1966 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
1967 ep->ackwait--;
1968 if (!list_empty(&ep->queue)) {
1969 int stat;
1970 req = container_of(ep->queue.next,
1971 struct omap_req, queue);
1972 stat = read_fifo(ep, req);
1973 if (!ep->double_buf)
1974 ep->fnf = 1;
1975 }
1976 }
1977 /* min 6 clock delay before clearing EP_SEL ... */
1978 epn_stat = omap_readw(UDC_EPN_STAT);
1979 epn_stat = omap_readw(UDC_EPN_STAT);
1980 omap_writew(epnum, UDC_EP_NUM);
1981
1982 /* enabling fifo _after_ clearing ACK, contrary to docs,
1983 * reduces lossage; timer still needed though (sigh).
1984 */
1985 if (ep->fnf) {
1986 omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
1987 ep->ackwait = 1 + ep->double_buf;
1988 }
1989 mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
1990 }
1991
1992 /* then IN transfers */
1993 else if (irq_src & UDC_EPN_TX) {
1994 epnum = epn_stat & 0x0f;
1995 omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
1996 status = IRQ_HANDLED;
1997 ep = &udc->ep[16 + epnum];
1998 ep->irqs++;
1999
2000 omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
2001 if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
2002 ep->ackwait = 0;
2003 if (!list_empty(&ep->queue)) {
2004 req = container_of(ep->queue.next,
2005 struct omap_req, queue);
2006 (void) write_fifo(ep, req);
2007 }
2008 }
2009 /* min 6 clock delay before clearing EP_SEL ... */
2010 epn_stat = omap_readw(UDC_EPN_STAT);
2011 epn_stat = omap_readw(UDC_EPN_STAT);
2012 omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
2013 /* then 6 clocks before it'd tx */
2014 }
2015
2016 spin_unlock_irqrestore(&udc->lock, flags);
2017 return status;
2018 }
2019
2020 #ifdef USE_ISO
2021 static irqreturn_t omap_udc_iso_irq(int irq, void *_dev)
2022 {
2023 struct omap_udc *udc = _dev;
2024 struct omap_ep *ep;
2025 int pending = 0;
2026 unsigned long flags;
2027
2028 spin_lock_irqsave(&udc->lock, flags);
2029
2030 /* handle all non-DMA ISO transfers */
2031 list_for_each_entry (ep, &udc->iso, iso) {
2032 u16 stat;
2033 struct omap_req *req;
2034
2035 if (ep->has_dma || list_empty(&ep->queue))
2036 continue;
2037 req = list_entry(ep->queue.next, struct omap_req, queue);
2038
2039 use_ep(ep, UDC_EP_SEL);
2040 stat = omap_readw(UDC_STAT_FLG);
2041
2042 /* NOTE: like the other controller drivers, this isn't
2043 * currently reporting lost or damaged frames.
2044 */
2045 if (ep->bEndpointAddress & USB_DIR_IN) {
2046 if (stat & UDC_MISS_IN)
2047 /* done(ep, req, -EPROTO) */;
2048 else
2049 write_fifo(ep, req);
2050 } else {
2051 int status = 0;
2052
2053 if (stat & UDC_NO_RXPACKET)
2054 status = -EREMOTEIO;
2055 else if (stat & UDC_ISO_ERR)
2056 status = -EILSEQ;
2057 else if (stat & UDC_DATA_FLUSH)
2058 status = -ENOSR;
2059
2060 if (status)
2061 /* done(ep, req, status) */;
2062 else
2063 read_fifo(ep, req);
2064 }
2065 deselect_ep();
2066 /* 6 wait states before next EP */
2067
2068 ep->irqs++;
2069 if (!list_empty(&ep->queue))
2070 pending = 1;
2071 }
2072 if (!pending) {
2073 u16 w;
2074
2075 w = omap_readw(UDC_IRQ_EN);
2076 w &= ~UDC_SOF_IE;
2077 omap_writew(w, UDC_IRQ_EN);
2078 }
2079 omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
2080
2081 spin_unlock_irqrestore(&udc->lock, flags);
2082 return IRQ_HANDLED;
2083 }
2084 #endif
2085
2086 /*-------------------------------------------------------------------------*/
2087
2088 static inline int machine_without_vbus_sense(void)
2089 {
2090 return (machine_is_omap_innovator()
2091 || machine_is_omap_osk()
2092 || machine_is_omap_apollon()
2093 #ifndef CONFIG_MACH_OMAP_H4_OTG
2094 || machine_is_omap_h4()
2095 #endif
2096 || machine_is_sx1()
2097 || cpu_is_omap7xx() /* No known omap7xx boards with vbus sense */
2098 );
2099 }
2100
2101 static int omap_udc_start(struct usb_gadget_driver *driver,
2102 int (*bind)(struct usb_gadget *))
2103 {
2104 int status = -ENODEV;
2105 struct omap_ep *ep;
2106 unsigned long flags;
2107
2108 /* basic sanity tests */
2109 if (!udc)
2110 return -ENODEV;
2111 if (!driver
2112 // FIXME if otg, check: driver->is_otg
2113 || driver->max_speed < USB_SPEED_FULL
2114 || !bind || !driver->setup)
2115 return -EINVAL;
2116
2117 spin_lock_irqsave(&udc->lock, flags);
2118 if (udc->driver) {
2119 spin_unlock_irqrestore(&udc->lock, flags);
2120 return -EBUSY;
2121 }
2122
2123 /* reset state */
2124 list_for_each_entry (ep, &udc->gadget.ep_list, ep.ep_list) {
2125 ep->irqs = 0;
2126 if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
2127 continue;
2128 use_ep(ep, 0);
2129 omap_writew(UDC_SET_HALT, UDC_CTRL);
2130 }
2131 udc->ep0_pending = 0;
2132 udc->ep[0].irqs = 0;
2133 udc->softconnect = 1;
2134
2135 /* hook up the driver */
2136 driver->driver.bus = NULL;
2137 udc->driver = driver;
2138 udc->gadget.dev.driver = &driver->driver;
2139 spin_unlock_irqrestore(&udc->lock, flags);
2140
2141 if (udc->dc_clk != NULL)
2142 omap_udc_enable_clock(1);
2143
2144 status = bind(&udc->gadget);
2145 if (status) {
2146 DBG("bind to %s --> %d\n", driver->driver.name, status);
2147 udc->gadget.dev.driver = NULL;
2148 udc->driver = NULL;
2149 goto done;
2150 }
2151 DBG("bound to driver %s\n", driver->driver.name);
2152
2153 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2154
2155 /* connect to bus through transceiver */
2156 if (udc->transceiver) {
2157 status = otg_set_peripheral(udc->transceiver, &udc->gadget);
2158 if (status < 0) {
2159 ERR("can't bind to transceiver\n");
2160 if (driver->unbind) {
2161 driver->unbind (&udc->gadget);
2162 udc->gadget.dev.driver = NULL;
2163 udc->driver = NULL;
2164 }
2165 goto done;
2166 }
2167 } else {
2168 if (can_pullup(udc))
2169 pullup_enable (udc);
2170 else
2171 pullup_disable (udc);
2172 }
2173
2174 /* boards that don't have VBUS sensing can't autogate 48MHz;
2175 * can't enter deep sleep while a gadget driver is active.
2176 */
2177 if (machine_without_vbus_sense())
2178 omap_vbus_session(&udc->gadget, 1);
2179
2180 done:
2181 if (udc->dc_clk != NULL)
2182 omap_udc_enable_clock(0);
2183 return status;
2184 }
2185
2186 static int omap_udc_stop(struct usb_gadget_driver *driver)
2187 {
2188 unsigned long flags;
2189 int status = -ENODEV;
2190
2191 if (!udc)
2192 return -ENODEV;
2193 if (!driver || driver != udc->driver || !driver->unbind)
2194 return -EINVAL;
2195
2196 if (udc->dc_clk != NULL)
2197 omap_udc_enable_clock(1);
2198
2199 if (machine_without_vbus_sense())
2200 omap_vbus_session(&udc->gadget, 0);
2201
2202 if (udc->transceiver)
2203 (void) otg_set_peripheral(udc->transceiver, NULL);
2204 else
2205 pullup_disable(udc);
2206
2207 spin_lock_irqsave(&udc->lock, flags);
2208 udc_quiesce(udc);
2209 spin_unlock_irqrestore(&udc->lock, flags);
2210
2211 driver->unbind(&udc->gadget);
2212 udc->gadget.dev.driver = NULL;
2213 udc->driver = NULL;
2214
2215 if (udc->dc_clk != NULL)
2216 omap_udc_enable_clock(0);
2217 DBG("unregistered driver '%s'\n", driver->driver.name);
2218 return status;
2219 }
2220
2221 /*-------------------------------------------------------------------------*/
2222
2223 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2224
2225 #include <linux/seq_file.h>
2226
2227 static const char proc_filename[] = "driver/udc";
2228
2229 #define FOURBITS "%s%s%s%s"
2230 #define EIGHTBITS FOURBITS FOURBITS
2231
2232 static void proc_ep_show(struct seq_file *s, struct omap_ep *ep)
2233 {
2234 u16 stat_flg;
2235 struct omap_req *req;
2236 char buf[20];
2237
2238 use_ep(ep, 0);
2239
2240 if (use_dma && ep->has_dma)
2241 snprintf(buf, sizeof buf, "(%cxdma%d lch%d) ",
2242 (ep->bEndpointAddress & USB_DIR_IN) ? 't' : 'r',
2243 ep->dma_channel - 1, ep->lch);
2244 else
2245 buf[0] = 0;
2246
2247 stat_flg = omap_readw(UDC_STAT_FLG);
2248 seq_printf(s,
2249 "\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
2250 ep->name, buf,
2251 ep->double_buf ? "dbuf " : "",
2252 ({char *s; switch(ep->ackwait){
2253 case 0: s = ""; break;
2254 case 1: s = "(ackw) "; break;
2255 case 2: s = "(ackw2) "; break;
2256 default: s = "(?) "; break;
2257 } s;}),
2258 ep->irqs, stat_flg,
2259 (stat_flg & UDC_NO_RXPACKET) ? "no_rxpacket " : "",
2260 (stat_flg & UDC_MISS_IN) ? "miss_in " : "",
2261 (stat_flg & UDC_DATA_FLUSH) ? "data_flush " : "",
2262 (stat_flg & UDC_ISO_ERR) ? "iso_err " : "",
2263 (stat_flg & UDC_ISO_FIFO_EMPTY) ? "iso_fifo_empty " : "",
2264 (stat_flg & UDC_ISO_FIFO_FULL) ? "iso_fifo_full " : "",
2265 (stat_flg & UDC_EP_HALTED) ? "HALT " : "",
2266 (stat_flg & UDC_STALL) ? "STALL " : "",
2267 (stat_flg & UDC_NAK) ? "NAK " : "",
2268 (stat_flg & UDC_ACK) ? "ACK " : "",
2269 (stat_flg & UDC_FIFO_EN) ? "fifo_en " : "",
2270 (stat_flg & UDC_NON_ISO_FIFO_EMPTY) ? "fifo_empty " : "",
2271 (stat_flg & UDC_NON_ISO_FIFO_FULL) ? "fifo_full " : "");
2272
2273 if (list_empty (&ep->queue))
2274 seq_printf(s, "\t(queue empty)\n");
2275 else
2276 list_for_each_entry (req, &ep->queue, queue) {
2277 unsigned length = req->req.actual;
2278
2279 if (use_dma && buf[0]) {
2280 length += ((ep->bEndpointAddress & USB_DIR_IN)
2281 ? dma_src_len : dma_dest_len)
2282 (ep, req->req.dma + length);
2283 buf[0] = 0;
2284 }
2285 seq_printf(s, "\treq %p len %d/%d buf %p\n",
2286 &req->req, length,
2287 req->req.length, req->req.buf);
2288 }
2289 }
2290
2291 static char *trx_mode(unsigned m, int enabled)
2292 {
2293 switch (m) {
2294 case 0: return enabled ? "*6wire" : "unused";
2295 case 1: return "4wire";
2296 case 2: return "3wire";
2297 case 3: return "6wire";
2298 default: return "unknown";
2299 }
2300 }
2301
2302 static int proc_otg_show(struct seq_file *s)
2303 {
2304 u32 tmp;
2305 u32 trans = 0;
2306 char *ctrl_name = "(UNKNOWN)";
2307
2308 /* XXX This needs major revision for OMAP2+ */
2309 tmp = omap_readl(OTG_REV);
2310 if (cpu_class_is_omap1()) {
2311 ctrl_name = "tranceiver_ctrl";
2312 trans = omap_readw(USB_TRANSCEIVER_CTRL);
2313 }
2314 seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
2315 tmp >> 4, tmp & 0xf, ctrl_name, trans);
2316 tmp = omap_readw(OTG_SYSCON_1);
2317 seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
2318 FOURBITS "\n", tmp,
2319 trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
2320 trx_mode(USB1_TRX_MODE(tmp), trans & CONF_USB1_UNI_R),
2321 (USB0_TRX_MODE(tmp) == 0 && !cpu_is_omap1710())
2322 ? "internal"
2323 : trx_mode(USB0_TRX_MODE(tmp), 1),
2324 (tmp & OTG_IDLE_EN) ? " !otg" : "",
2325 (tmp & HST_IDLE_EN) ? " !host" : "",
2326 (tmp & DEV_IDLE_EN) ? " !dev" : "",
2327 (tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
2328 tmp = omap_readl(OTG_SYSCON_2);
2329 seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
2330 " b_ase_brst=%d hmc=%d\n", tmp,
2331 (tmp & OTG_EN) ? " otg_en" : "",
2332 (tmp & USBX_SYNCHRO) ? " synchro" : "",
2333 // much more SRP stuff
2334 (tmp & SRP_DATA) ? " srp_data" : "",
2335 (tmp & SRP_VBUS) ? " srp_vbus" : "",
2336 (tmp & OTG_PADEN) ? " otg_paden" : "",
2337 (tmp & HMC_PADEN) ? " hmc_paden" : "",
2338 (tmp & UHOST_EN) ? " uhost_en" : "",
2339 (tmp & HMC_TLLSPEED) ? " tllspeed" : "",
2340 (tmp & HMC_TLLATTACH) ? " tllattach" : "",
2341 B_ASE_BRST(tmp),
2342 OTG_HMC(tmp));
2343 tmp = omap_readl(OTG_CTRL);
2344 seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
2345 (tmp & OTG_ASESSVLD) ? " asess" : "",
2346 (tmp & OTG_BSESSEND) ? " bsess_end" : "",
2347 (tmp & OTG_BSESSVLD) ? " bsess" : "",
2348 (tmp & OTG_VBUSVLD) ? " vbus" : "",
2349 (tmp & OTG_ID) ? " id" : "",
2350 (tmp & OTG_DRIVER_SEL) ? " DEVICE" : " HOST",
2351 (tmp & OTG_A_SETB_HNPEN) ? " a_setb_hnpen" : "",
2352 (tmp & OTG_A_BUSREQ) ? " a_bus" : "",
2353 (tmp & OTG_B_HNPEN) ? " b_hnpen" : "",
2354 (tmp & OTG_B_BUSREQ) ? " b_bus" : "",
2355 (tmp & OTG_BUSDROP) ? " busdrop" : "",
2356 (tmp & OTG_PULLDOWN) ? " down" : "",
2357 (tmp & OTG_PULLUP) ? " up" : "",
2358 (tmp & OTG_DRV_VBUS) ? " drv" : "",
2359 (tmp & OTG_PD_VBUS) ? " pd_vb" : "",
2360 (tmp & OTG_PU_VBUS) ? " pu_vb" : "",
2361 (tmp & OTG_PU_ID) ? " pu_id" : ""
2362 );
2363 tmp = omap_readw(OTG_IRQ_EN);
2364 seq_printf(s, "otg_irq_en %04x" "\n", tmp);
2365 tmp = omap_readw(OTG_IRQ_SRC);
2366 seq_printf(s, "otg_irq_src %04x" "\n", tmp);
2367 tmp = omap_readw(OTG_OUTCTRL);
2368 seq_printf(s, "otg_outctrl %04x" "\n", tmp);
2369 tmp = omap_readw(OTG_TEST);
2370 seq_printf(s, "otg_test %04x" "\n", tmp);
2371 return 0;
2372 }
2373
2374 static int proc_udc_show(struct seq_file *s, void *_)
2375 {
2376 u32 tmp;
2377 struct omap_ep *ep;
2378 unsigned long flags;
2379
2380 spin_lock_irqsave(&udc->lock, flags);
2381
2382 seq_printf(s, "%s, version: " DRIVER_VERSION
2383 #ifdef USE_ISO
2384 " (iso)"
2385 #endif
2386 "%s\n",
2387 driver_desc,
2388 use_dma ? " (dma)" : "");
2389
2390 tmp = omap_readw(UDC_REV) & 0xff;
2391 seq_printf(s,
2392 "UDC rev %d.%d, fifo mode %d, gadget %s\n"
2393 "hmc %d, transceiver %s\n",
2394 tmp >> 4, tmp & 0xf,
2395 fifo_mode,
2396 udc->driver ? udc->driver->driver.name : "(none)",
2397 HMC,
2398 udc->transceiver
2399 ? udc->transceiver->label
2400 : ((cpu_is_omap1710() || cpu_is_omap24xx())
2401 ? "external" : "(none)"));
2402 if (cpu_class_is_omap1()) {
2403 seq_printf(s, "ULPD control %04x req %04x status %04x\n",
2404 omap_readw(ULPD_CLOCK_CTRL),
2405 omap_readw(ULPD_SOFT_REQ),
2406 omap_readw(ULPD_STATUS_REQ));
2407 }
2408
2409 /* OTG controller registers */
2410 if (!cpu_is_omap15xx())
2411 proc_otg_show(s);
2412
2413 tmp = omap_readw(UDC_SYSCON1);
2414 seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
2415 (tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
2416 (tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
2417 (tmp & UDC_DMA_ENDIAN) ? " dma_endian" : "",
2418 (tmp & UDC_NAK_EN) ? " nak" : "",
2419 (tmp & UDC_AUTODECODE_DIS) ? " autodecode_dis" : "",
2420 (tmp & UDC_SELF_PWR) ? " self_pwr" : "",
2421 (tmp & UDC_SOFF_DIS) ? " soff_dis" : "",
2422 (tmp & UDC_PULLUP_EN) ? " PULLUP" : "");
2423 // syscon2 is write-only
2424
2425 /* UDC controller registers */
2426 if (!(tmp & UDC_PULLUP_EN)) {
2427 seq_printf(s, "(suspended)\n");
2428 spin_unlock_irqrestore(&udc->lock, flags);
2429 return 0;
2430 }
2431
2432 tmp = omap_readw(UDC_DEVSTAT);
2433 seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
2434 (tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
2435 (tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
2436 (tmp & UDC_A_ALT_HNP_SUPPORT) ? " a_alt_hnp" : "",
2437 (tmp & UDC_R_WK_OK) ? " r_wk_ok" : "",
2438 (tmp & UDC_USB_RESET) ? " usb_reset" : "",
2439 (tmp & UDC_SUS) ? " SUS" : "",
2440 (tmp & UDC_CFG) ? " CFG" : "",
2441 (tmp & UDC_ADD) ? " ADD" : "",
2442 (tmp & UDC_DEF) ? " DEF" : "",
2443 (tmp & UDC_ATT) ? " ATT" : "");
2444 seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
2445 tmp = omap_readw(UDC_IRQ_EN);
2446 seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
2447 (tmp & UDC_SOF_IE) ? " sof" : "",
2448 (tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
2449 (tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
2450 (tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
2451 (tmp & UDC_EP0_IE) ? " ep0" : "");
2452 tmp = omap_readw(UDC_IRQ_SRC);
2453 seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
2454 (tmp & UDC_TXN_DONE) ? " txn_done" : "",
2455 (tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
2456 (tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
2457 (tmp & UDC_IRQ_SOF) ? " sof" : "",
2458 (tmp & UDC_EPN_RX) ? " epn_rx" : "",
2459 (tmp & UDC_EPN_TX) ? " epn_tx" : "",
2460 (tmp & UDC_DS_CHG) ? " ds_chg" : "",
2461 (tmp & UDC_SETUP) ? " setup" : "",
2462 (tmp & UDC_EP0_RX) ? " ep0out" : "",
2463 (tmp & UDC_EP0_TX) ? " ep0in" : "");
2464 if (use_dma) {
2465 unsigned i;
2466
2467 tmp = omap_readw(UDC_DMA_IRQ_EN);
2468 seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
2469 (tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
2470 (tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
2471 (tmp & UDC_RX_EOT_IE(3)) ? " rx2_eot" : "",
2472
2473 (tmp & UDC_TX_DONE_IE(2)) ? " tx1_done" : "",
2474 (tmp & UDC_RX_CNT_IE(2)) ? " rx1_cnt" : "",
2475 (tmp & UDC_RX_EOT_IE(2)) ? " rx1_eot" : "",
2476
2477 (tmp & UDC_TX_DONE_IE(1)) ? " tx0_done" : "",
2478 (tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
2479 (tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
2480
2481 tmp = omap_readw(UDC_RXDMA_CFG);
2482 seq_printf(s, "rxdma_cfg %04x\n", tmp);
2483 if (tmp) {
2484 for (i = 0; i < 3; i++) {
2485 if ((tmp & (0x0f << (i * 4))) == 0)
2486 continue;
2487 seq_printf(s, "rxdma[%d] %04x\n", i,
2488 omap_readw(UDC_RXDMA(i + 1)));
2489 }
2490 }
2491 tmp = omap_readw(UDC_TXDMA_CFG);
2492 seq_printf(s, "txdma_cfg %04x\n", tmp);
2493 if (tmp) {
2494 for (i = 0; i < 3; i++) {
2495 if (!(tmp & (0x0f << (i * 4))))
2496 continue;
2497 seq_printf(s, "txdma[%d] %04x\n", i,
2498 omap_readw(UDC_TXDMA(i + 1)));
2499 }
2500 }
2501 }
2502
2503 tmp = omap_readw(UDC_DEVSTAT);
2504 if (tmp & UDC_ATT) {
2505 proc_ep_show(s, &udc->ep[0]);
2506 if (tmp & UDC_ADD) {
2507 list_for_each_entry (ep, &udc->gadget.ep_list,
2508 ep.ep_list) {
2509 if (ep->desc)
2510 proc_ep_show(s, ep);
2511 }
2512 }
2513 }
2514 spin_unlock_irqrestore(&udc->lock, flags);
2515 return 0;
2516 }
2517
2518 static int proc_udc_open(struct inode *inode, struct file *file)
2519 {
2520 return single_open(file, proc_udc_show, NULL);
2521 }
2522
2523 static const struct file_operations proc_ops = {
2524 .owner = THIS_MODULE,
2525 .open = proc_udc_open,
2526 .read = seq_read,
2527 .llseek = seq_lseek,
2528 .release = single_release,
2529 };
2530
2531 static void create_proc_file(void)
2532 {
2533 proc_create(proc_filename, 0, NULL, &proc_ops);
2534 }
2535
2536 static void remove_proc_file(void)
2537 {
2538 remove_proc_entry(proc_filename, NULL);
2539 }
2540
2541 #else
2542
2543 static inline void create_proc_file(void) {}
2544 static inline void remove_proc_file(void) {}
2545
2546 #endif
2547
2548 /*-------------------------------------------------------------------------*/
2549
2550 /* Before this controller can enumerate, we need to pick an endpoint
2551 * configuration, or "fifo_mode" That involves allocating 2KB of packet
2552 * buffer space among the endpoints we'll be operating.
2553 *
2554 * NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
2555 * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
2556 * capability yet though.
2557 */
2558 static unsigned __init
2559 omap_ep_setup(char *name, u8 addr, u8 type,
2560 unsigned buf, unsigned maxp, int dbuf)
2561 {
2562 struct omap_ep *ep;
2563 u16 epn_rxtx = 0;
2564
2565 /* OUT endpoints first, then IN */
2566 ep = &udc->ep[addr & 0xf];
2567 if (addr & USB_DIR_IN)
2568 ep += 16;
2569
2570 /* in case of ep init table bugs */
2571 BUG_ON(ep->name[0]);
2572
2573 /* chip setup ... bit values are same for IN, OUT */
2574 if (type == USB_ENDPOINT_XFER_ISOC) {
2575 switch (maxp) {
2576 case 8: epn_rxtx = 0 << 12; break;
2577 case 16: epn_rxtx = 1 << 12; break;
2578 case 32: epn_rxtx = 2 << 12; break;
2579 case 64: epn_rxtx = 3 << 12; break;
2580 case 128: epn_rxtx = 4 << 12; break;
2581 case 256: epn_rxtx = 5 << 12; break;
2582 case 512: epn_rxtx = 6 << 12; break;
2583 default: BUG();
2584 }
2585 epn_rxtx |= UDC_EPN_RX_ISO;
2586 dbuf = 1;
2587 } else {
2588 /* double-buffering "not supported" on 15xx,
2589 * and ignored for PIO-IN on newer chips
2590 * (for more reliable behavior)
2591 */
2592 if (!use_dma || cpu_is_omap15xx() || cpu_is_omap24xx())
2593 dbuf = 0;
2594
2595 switch (maxp) {
2596 case 8: epn_rxtx = 0 << 12; break;
2597 case 16: epn_rxtx = 1 << 12; break;
2598 case 32: epn_rxtx = 2 << 12; break;
2599 case 64: epn_rxtx = 3 << 12; break;
2600 default: BUG();
2601 }
2602 if (dbuf && addr)
2603 epn_rxtx |= UDC_EPN_RX_DB;
2604 init_timer(&ep->timer);
2605 ep->timer.function = pio_out_timer;
2606 ep->timer.data = (unsigned long) ep;
2607 }
2608 if (addr)
2609 epn_rxtx |= UDC_EPN_RX_VALID;
2610 BUG_ON(buf & 0x07);
2611 epn_rxtx |= buf >> 3;
2612
2613 DBG("%s addr %02x rxtx %04x maxp %d%s buf %d\n",
2614 name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
2615
2616 if (addr & USB_DIR_IN)
2617 omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
2618 else
2619 omap_writew(epn_rxtx, UDC_EP_RX(addr));
2620
2621 /* next endpoint's buffer starts after this one's */
2622 buf += maxp;
2623 if (dbuf)
2624 buf += maxp;
2625 BUG_ON(buf > 2048);
2626
2627 /* set up driver data structures */
2628 BUG_ON(strlen(name) >= sizeof ep->name);
2629 strlcpy(ep->name, name, sizeof ep->name);
2630 INIT_LIST_HEAD(&ep->queue);
2631 INIT_LIST_HEAD(&ep->iso);
2632 ep->bEndpointAddress = addr;
2633 ep->bmAttributes = type;
2634 ep->double_buf = dbuf;
2635 ep->udc = udc;
2636
2637 ep->ep.name = ep->name;
2638 ep->ep.ops = &omap_ep_ops;
2639 ep->ep.maxpacket = ep->maxpacket = maxp;
2640 list_add_tail (&ep->ep.ep_list, &udc->gadget.ep_list);
2641
2642 return buf;
2643 }
2644
2645 static void omap_udc_release(struct device *dev)
2646 {
2647 complete(udc->done);
2648 kfree (udc);
2649 udc = NULL;
2650 }
2651
2652 static int __init
2653 omap_udc_setup(struct platform_device *odev, struct otg_transceiver *xceiv)
2654 {
2655 unsigned tmp, buf;
2656
2657 /* abolish any previous hardware state */
2658 omap_writew(0, UDC_SYSCON1);
2659 omap_writew(0, UDC_IRQ_EN);
2660 omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
2661 omap_writew(0, UDC_DMA_IRQ_EN);
2662 omap_writew(0, UDC_RXDMA_CFG);
2663 omap_writew(0, UDC_TXDMA_CFG);
2664
2665 /* UDC_PULLUP_EN gates the chip clock */
2666 // OTG_SYSCON_1 |= DEV_IDLE_EN;
2667
2668 udc = kzalloc(sizeof(*udc), GFP_KERNEL);
2669 if (!udc)
2670 return -ENOMEM;
2671
2672 spin_lock_init (&udc->lock);
2673
2674 udc->gadget.ops = &omap_gadget_ops;
2675 udc->gadget.ep0 = &udc->ep[0].ep;
2676 INIT_LIST_HEAD(&udc->gadget.ep_list);
2677 INIT_LIST_HEAD(&udc->iso);
2678 udc->gadget.speed = USB_SPEED_UNKNOWN;
2679 udc->gadget.max_speed = USB_SPEED_FULL;
2680 udc->gadget.name = driver_name;
2681
2682 device_initialize(&udc->gadget.dev);
2683 dev_set_name(&udc->gadget.dev, "gadget");
2684 udc->gadget.dev.release = omap_udc_release;
2685 udc->gadget.dev.parent = &odev->dev;
2686 if (use_dma)
2687 udc->gadget.dev.dma_mask = odev->dev.dma_mask;
2688
2689 udc->transceiver = xceiv;
2690
2691 /* ep0 is special; put it right after the SETUP buffer */
2692 buf = omap_ep_setup("ep0", 0, USB_ENDPOINT_XFER_CONTROL,
2693 8 /* after SETUP */, 64 /* maxpacket */, 0);
2694 list_del_init(&udc->ep[0].ep.ep_list);
2695
2696 /* initially disable all non-ep0 endpoints */
2697 for (tmp = 1; tmp < 15; tmp++) {
2698 omap_writew(0, UDC_EP_RX(tmp));
2699 omap_writew(0, UDC_EP_TX(tmp));
2700 }
2701
2702 #define OMAP_BULK_EP(name,addr) \
2703 buf = omap_ep_setup(name "-bulk", addr, \
2704 USB_ENDPOINT_XFER_BULK, buf, 64, 1);
2705 #define OMAP_INT_EP(name,addr, maxp) \
2706 buf = omap_ep_setup(name "-int", addr, \
2707 USB_ENDPOINT_XFER_INT, buf, maxp, 0);
2708 #define OMAP_ISO_EP(name,addr, maxp) \
2709 buf = omap_ep_setup(name "-iso", addr, \
2710 USB_ENDPOINT_XFER_ISOC, buf, maxp, 1);
2711
2712 switch (fifo_mode) {
2713 case 0:
2714 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2715 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2716 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2717 break;
2718 case 1:
2719 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2720 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2721 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2722
2723 OMAP_BULK_EP("ep3in", USB_DIR_IN | 3);
2724 OMAP_BULK_EP("ep4out", USB_DIR_OUT | 4);
2725 OMAP_INT_EP("ep10in", USB_DIR_IN | 10, 16);
2726
2727 OMAP_BULK_EP("ep5in", USB_DIR_IN | 5);
2728 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2729 OMAP_INT_EP("ep11in", USB_DIR_IN | 11, 16);
2730
2731 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2732 OMAP_BULK_EP("ep6out", USB_DIR_OUT | 6);
2733 OMAP_INT_EP("ep12in", USB_DIR_IN | 12, 16);
2734
2735 OMAP_BULK_EP("ep7in", USB_DIR_IN | 7);
2736 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2737 OMAP_INT_EP("ep13in", USB_DIR_IN | 13, 16);
2738 OMAP_INT_EP("ep13out", USB_DIR_OUT | 13, 16);
2739
2740 OMAP_BULK_EP("ep8in", USB_DIR_IN | 8);
2741 OMAP_BULK_EP("ep8out", USB_DIR_OUT | 8);
2742 OMAP_INT_EP("ep14in", USB_DIR_IN | 14, 16);
2743 OMAP_INT_EP("ep14out", USB_DIR_OUT | 14, 16);
2744
2745 OMAP_BULK_EP("ep15in", USB_DIR_IN | 15);
2746 OMAP_BULK_EP("ep15out", USB_DIR_OUT | 15);
2747
2748 break;
2749
2750 #ifdef USE_ISO
2751 case 2: /* mixed iso/bulk */
2752 OMAP_ISO_EP("ep1in", USB_DIR_IN | 1, 256);
2753 OMAP_ISO_EP("ep2out", USB_DIR_OUT | 2, 256);
2754 OMAP_ISO_EP("ep3in", USB_DIR_IN | 3, 128);
2755 OMAP_ISO_EP("ep4out", USB_DIR_OUT | 4, 128);
2756
2757 OMAP_INT_EP("ep5in", USB_DIR_IN | 5, 16);
2758
2759 OMAP_BULK_EP("ep6in", USB_DIR_IN | 6);
2760 OMAP_BULK_EP("ep7out", USB_DIR_OUT | 7);
2761 OMAP_INT_EP("ep8in", USB_DIR_IN | 8, 16);
2762 break;
2763 case 3: /* mixed bulk/iso */
2764 OMAP_BULK_EP("ep1in", USB_DIR_IN | 1);
2765 OMAP_BULK_EP("ep2out", USB_DIR_OUT | 2);
2766 OMAP_INT_EP("ep3in", USB_DIR_IN | 3, 16);
2767
2768 OMAP_BULK_EP("ep4in", USB_DIR_IN | 4);
2769 OMAP_BULK_EP("ep5out", USB_DIR_OUT | 5);
2770 OMAP_INT_EP("ep6in", USB_DIR_IN | 6, 16);
2771
2772 OMAP_ISO_EP("ep7in", USB_DIR_IN | 7, 256);
2773 OMAP_ISO_EP("ep8out", USB_DIR_OUT | 8, 256);
2774 OMAP_INT_EP("ep9in", USB_DIR_IN | 9, 16);
2775 break;
2776 #endif
2777
2778 /* add more modes as needed */
2779
2780 default:
2781 ERR("unsupported fifo_mode #%d\n", fifo_mode);
2782 return -ENODEV;
2783 }
2784 omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
2785 INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
2786 return 0;
2787 }
2788
2789 static int __init omap_udc_probe(struct platform_device *pdev)
2790 {
2791 int status = -ENODEV;
2792 int hmc;
2793 struct otg_transceiver *xceiv = NULL;
2794 const char *type = NULL;
2795 struct omap_usb_config *config = pdev->dev.platform_data;
2796 struct clk *dc_clk;
2797 struct clk *hhc_clk;
2798
2799 /* NOTE: "knows" the order of the resources! */
2800 if (!request_mem_region(pdev->resource[0].start,
2801 pdev->resource[0].end - pdev->resource[0].start + 1,
2802 driver_name)) {
2803 DBG("request_mem_region failed\n");
2804 return -EBUSY;
2805 }
2806
2807 if (cpu_is_omap16xx()) {
2808 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2809 hhc_clk = clk_get(&pdev->dev, "usb_hhc_ck");
2810 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2811 /* can't use omap_udc_enable_clock yet */
2812 clk_enable(dc_clk);
2813 clk_enable(hhc_clk);
2814 udelay(100);
2815 }
2816
2817 if (cpu_is_omap24xx()) {
2818 dc_clk = clk_get(&pdev->dev, "usb_fck");
2819 hhc_clk = clk_get(&pdev->dev, "usb_l4_ick");
2820 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2821 /* can't use omap_udc_enable_clock yet */
2822 clk_enable(dc_clk);
2823 clk_enable(hhc_clk);
2824 udelay(100);
2825 }
2826
2827 if (cpu_is_omap7xx()) {
2828 dc_clk = clk_get(&pdev->dev, "usb_dc_ck");
2829 hhc_clk = clk_get(&pdev->dev, "l3_ocpi_ck");
2830 BUG_ON(IS_ERR(dc_clk) || IS_ERR(hhc_clk));
2831 /* can't use omap_udc_enable_clock yet */
2832 clk_enable(dc_clk);
2833 clk_enable(hhc_clk);
2834 udelay(100);
2835 }
2836
2837 INFO("OMAP UDC rev %d.%d%s\n",
2838 omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
2839 config->otg ? ", Mini-AB" : "");
2840
2841 /* use the mode given to us by board init code */
2842 if (cpu_is_omap15xx()) {
2843 hmc = HMC_1510;
2844 type = "(unknown)";
2845
2846 if (machine_without_vbus_sense()) {
2847 /* just set up software VBUS detect, and then
2848 * later rig it so we always report VBUS.
2849 * FIXME without really sensing VBUS, we can't
2850 * know when to turn PULLUP_EN on/off; and that
2851 * means we always "need" the 48MHz clock.
2852 */
2853 u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
2854 tmp &= ~VBUS_CTRL_1510;
2855 omap_writel(tmp, FUNC_MUX_CTRL_0);
2856 tmp |= VBUS_MODE_1510;
2857 tmp &= ~VBUS_CTRL_1510;
2858 omap_writel(tmp, FUNC_MUX_CTRL_0);
2859 }
2860 } else {
2861 /* The transceiver may package some GPIO logic or handle
2862 * loopback and/or transceiverless setup; if we find one,
2863 * use it. Except for OTG, we don't _need_ to talk to one;
2864 * but not having one probably means no VBUS detection.
2865 */
2866 xceiv = otg_get_transceiver();
2867 if (xceiv)
2868 type = xceiv->label;
2869 else if (config->otg) {
2870 DBG("OTG requires external transceiver!\n");
2871 goto cleanup0;
2872 }
2873
2874 hmc = HMC_1610;
2875
2876 if (cpu_is_omap24xx()) {
2877 /* this could be transceiverless in one of the
2878 * "we don't need to know" modes.
2879 */
2880 type = "external";
2881 goto known;
2882 }
2883
2884 switch (hmc) {
2885 case 0: /* POWERUP DEFAULT == 0 */
2886 case 4:
2887 case 12:
2888 case 20:
2889 if (!cpu_is_omap1710()) {
2890 type = "integrated";
2891 break;
2892 }
2893 /* FALL THROUGH */
2894 case 3:
2895 case 11:
2896 case 16:
2897 case 19:
2898 case 25:
2899 if (!xceiv) {
2900 DBG("external transceiver not registered!\n");
2901 type = "unknown";
2902 }
2903 break;
2904 case 21: /* internal loopback */
2905 type = "loopback";
2906 break;
2907 case 14: /* transceiverless */
2908 if (cpu_is_omap1710())
2909 goto bad_on_1710;
2910 /* FALL THROUGH */
2911 case 13:
2912 case 15:
2913 type = "no";
2914 break;
2915
2916 default:
2917 bad_on_1710:
2918 ERR("unrecognized UDC HMC mode %d\n", hmc);
2919 goto cleanup0;
2920 }
2921 }
2922 known:
2923 INFO("hmc mode %d, %s transceiver\n", hmc, type);
2924
2925 /* a "gadget" abstracts/virtualizes the controller */
2926 status = omap_udc_setup(pdev, xceiv);
2927 if (status) {
2928 goto cleanup0;
2929 }
2930 xceiv = NULL;
2931 // "udc" is now valid
2932 pullup_disable(udc);
2933 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
2934 udc->gadget.is_otg = (config->otg != 0);
2935 #endif
2936
2937 /* starting with omap1710 es2.0, clear toggle is a separate bit */
2938 if (omap_readw(UDC_REV) >= 0x61)
2939 udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
2940 else
2941 udc->clr_halt = UDC_RESET_EP;
2942
2943 /* USB general purpose IRQ: ep0, state changes, dma, etc */
2944 status = request_irq(pdev->resource[1].start, omap_udc_irq,
2945 IRQF_SAMPLE_RANDOM, driver_name, udc);
2946 if (status != 0) {
2947 ERR("can't get irq %d, err %d\n",
2948 (int) pdev->resource[1].start, status);
2949 goto cleanup1;
2950 }
2951
2952 /* USB "non-iso" IRQ (PIO for all but ep0) */
2953 status = request_irq(pdev->resource[2].start, omap_udc_pio_irq,
2954 IRQF_SAMPLE_RANDOM, "omap_udc pio", udc);
2955 if (status != 0) {
2956 ERR("can't get irq %d, err %d\n",
2957 (int) pdev->resource[2].start, status);
2958 goto cleanup2;
2959 }
2960 #ifdef USE_ISO
2961 status = request_irq(pdev->resource[3].start, omap_udc_iso_irq,
2962 0, "omap_udc iso", udc);
2963 if (status != 0) {
2964 ERR("can't get irq %d, err %d\n",
2965 (int) pdev->resource[3].start, status);
2966 goto cleanup3;
2967 }
2968 #endif
2969 if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
2970 udc->dc_clk = dc_clk;
2971 udc->hhc_clk = hhc_clk;
2972 clk_disable(hhc_clk);
2973 clk_disable(dc_clk);
2974 }
2975
2976 if (cpu_is_omap24xx()) {
2977 udc->dc_clk = dc_clk;
2978 udc->hhc_clk = hhc_clk;
2979 /* FIXME OMAP2 don't release hhc & dc clock */
2980 #if 0
2981 clk_disable(hhc_clk);
2982 clk_disable(dc_clk);
2983 #endif
2984 }
2985
2986 create_proc_file();
2987 status = device_add(&udc->gadget.dev);
2988 if (status)
2989 goto cleanup4;
2990
2991 status = usb_add_gadget_udc(&pdev->dev, &udc->gadget);
2992 if (!status)
2993 return status;
2994 /* If fail, fall through */
2995 cleanup4:
2996 remove_proc_file();
2997
2998 #ifdef USE_ISO
2999 cleanup3:
3000 free_irq(pdev->resource[2].start, udc);
3001 #endif
3002
3003 cleanup2:
3004 free_irq(pdev->resource[1].start, udc);
3005
3006 cleanup1:
3007 kfree (udc);
3008 udc = NULL;
3009
3010 cleanup0:
3011 if (xceiv)
3012 otg_put_transceiver(xceiv);
3013
3014 if (cpu_is_omap16xx() || cpu_is_omap24xx() || cpu_is_omap7xx()) {
3015 clk_disable(hhc_clk);
3016 clk_disable(dc_clk);
3017 clk_put(hhc_clk);
3018 clk_put(dc_clk);
3019 }
3020
3021 release_mem_region(pdev->resource[0].start,
3022 pdev->resource[0].end - pdev->resource[0].start + 1);
3023
3024 return status;
3025 }
3026
3027 static int __exit omap_udc_remove(struct platform_device *pdev)
3028 {
3029 DECLARE_COMPLETION_ONSTACK(done);
3030
3031 if (!udc)
3032 return -ENODEV;
3033
3034 usb_del_gadget_udc(&udc->gadget);
3035 if (udc->driver)
3036 return -EBUSY;
3037
3038 udc->done = &done;
3039
3040 pullup_disable(udc);
3041 if (udc->transceiver) {
3042 otg_put_transceiver(udc->transceiver);
3043 udc->transceiver = NULL;
3044 }
3045 omap_writew(0, UDC_SYSCON1);
3046
3047 remove_proc_file();
3048
3049 #ifdef USE_ISO
3050 free_irq(pdev->resource[3].start, udc);
3051 #endif
3052 free_irq(pdev->resource[2].start, udc);
3053 free_irq(pdev->resource[1].start, udc);
3054
3055 if (udc->dc_clk) {
3056 if (udc->clk_requested)
3057 omap_udc_enable_clock(0);
3058 clk_put(udc->hhc_clk);
3059 clk_put(udc->dc_clk);
3060 }
3061
3062 release_mem_region(pdev->resource[0].start,
3063 pdev->resource[0].end - pdev->resource[0].start + 1);
3064
3065 device_unregister(&udc->gadget.dev);
3066 wait_for_completion(&done);
3067
3068 return 0;
3069 }
3070
3071 /* suspend/resume/wakeup from sysfs (echo > power/state) or when the
3072 * system is forced into deep sleep
3073 *
3074 * REVISIT we should probably reject suspend requests when there's a host
3075 * session active, rather than disconnecting, at least on boards that can
3076 * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
3077 * make host resumes and VBUS detection trigger OMAP wakeup events; that
3078 * may involve talking to an external transceiver (e.g. isp1301).
3079 */
3080
3081 static int omap_udc_suspend(struct platform_device *dev, pm_message_t message)
3082 {
3083 u32 devstat;
3084
3085 devstat = omap_readw(UDC_DEVSTAT);
3086
3087 /* we're requesting 48 MHz clock if the pullup is enabled
3088 * (== we're attached to the host) and we're not suspended,
3089 * which would prevent entry to deep sleep...
3090 */
3091 if ((devstat & UDC_ATT) != 0 && (devstat & UDC_SUS) == 0) {
3092 WARNING("session active; suspend requires disconnect\n");
3093 omap_pullup(&udc->gadget, 0);
3094 }
3095
3096 return 0;
3097 }
3098
3099 static int omap_udc_resume(struct platform_device *dev)
3100 {
3101 DBG("resume + wakeup/SRP\n");
3102 omap_pullup(&udc->gadget, 1);
3103
3104 /* maybe the host would enumerate us if we nudged it */
3105 msleep(100);
3106 return omap_wakeup(&udc->gadget);
3107 }
3108
3109 /*-------------------------------------------------------------------------*/
3110
3111 static struct platform_driver udc_driver = {
3112 .remove = __exit_p(omap_udc_remove),
3113 .suspend = omap_udc_suspend,
3114 .resume = omap_udc_resume,
3115 .driver = {
3116 .owner = THIS_MODULE,
3117 .name = (char *) driver_name,
3118 },
3119 };
3120
3121 static int __init udc_init(void)
3122 {
3123 /* Disable DMA for omap7xx -- it doesn't work right. */
3124 if (cpu_is_omap7xx())
3125 use_dma = 0;
3126
3127 INFO("%s, version: " DRIVER_VERSION
3128 #ifdef USE_ISO
3129 " (iso)"
3130 #endif
3131 "%s\n", driver_desc,
3132 use_dma ? " (dma)" : "");
3133 return platform_driver_probe(&udc_driver, omap_udc_probe);
3134 }
3135 module_init(udc_init);
3136
3137 static void __exit udc_exit(void)
3138 {
3139 platform_driver_unregister(&udc_driver);
3140 }
3141 module_exit(udc_exit);
3142
3143 MODULE_DESCRIPTION(DRIVER_DESC);
3144 MODULE_LICENSE("GPL");
3145 MODULE_ALIAS("platform:omap_udc");
kernel source for telekom puls (alcatel/mediatek)