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Fix common misspellings
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / ip22zilog.c
1 /*
2 * Driver for Zilog serial chips found on SGI workstations and
3 * servers. This driver could actually be made more generic.
4 *
5 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
6 * old drivers/sgi/char/sgiserial.c code which itself is based of the original
7 * drivers/sbus/char/zs.c code. A lot of code has been simply moved over
8 * directly from there but much has been rewritten. Credits therefore go out
9 * to David S. Miller, Eddie C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell
10 * for their work there.
11 *
12 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
14 */
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #include <linux/init.h>
32
33 #include <asm/io.h>
34 #include <asm/irq.h>
35 #include <asm/sgialib.h>
36 #include <asm/sgi/ioc.h>
37 #include <asm/sgi/hpc3.h>
38 #include <asm/sgi/ip22.h>
39
40 #if defined(CONFIG_SERIAL_IP22_ZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
41 #define SUPPORT_SYSRQ
42 #endif
43
44 #include <linux/serial_core.h>
45
46 #include "ip22zilog.h"
47
48 /*
49 * On IP22 we need to delay after register accesses but we do not need to
50 * flush writes.
51 */
52 #define ZSDELAY() udelay(5)
53 #define ZSDELAY_LONG() udelay(20)
54 #define ZS_WSYNC(channel) do { } while (0)
55
56 #define NUM_IP22ZILOG 1
57 #define NUM_CHANNELS (NUM_IP22ZILOG * 2)
58
59 #define ZS_CLOCK 3672000 /* Zilog input clock rate. */
60 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
61
62 /*
63 * We wrap our port structure around the generic uart_port.
64 */
65 struct uart_ip22zilog_port {
66 struct uart_port port;
67
68 /* IRQ servicing chain. */
69 struct uart_ip22zilog_port *next;
70
71 /* Current values of Zilog write registers. */
72 unsigned char curregs[NUM_ZSREGS];
73
74 unsigned int flags;
75 #define IP22ZILOG_FLAG_IS_CONS 0x00000004
76 #define IP22ZILOG_FLAG_IS_KGDB 0x00000008
77 #define IP22ZILOG_FLAG_MODEM_STATUS 0x00000010
78 #define IP22ZILOG_FLAG_IS_CHANNEL_A 0x00000020
79 #define IP22ZILOG_FLAG_REGS_HELD 0x00000040
80 #define IP22ZILOG_FLAG_TX_STOPPED 0x00000080
81 #define IP22ZILOG_FLAG_TX_ACTIVE 0x00000100
82 #define IP22ZILOG_FLAG_RESET_DONE 0x00000200
83
84 unsigned int tty_break;
85
86 unsigned char parity_mask;
87 unsigned char prev_status;
88 };
89
90 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
91 #define UART_ZILOG(PORT) ((struct uart_ip22zilog_port *)(PORT))
92 #define IP22ZILOG_GET_CURR_REG(PORT, REGNUM) \
93 (UART_ZILOG(PORT)->curregs[REGNUM])
94 #define IP22ZILOG_SET_CURR_REG(PORT, REGNUM, REGVAL) \
95 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
96 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
97 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
98 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
99 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
100 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
101 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
102 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
103
104 /* Reading and writing Zilog8530 registers. The delays are to make this
105 * driver work on the IP22 which needs a settling delay after each chip
106 * register access, other machines handle this in hardware via auxiliary
107 * flip-flops which implement the settle time we do in software.
108 *
109 * The port lock must be held and local IRQs must be disabled
110 * when {read,write}_zsreg is invoked.
111 */
112 static unsigned char read_zsreg(struct zilog_channel *channel,
113 unsigned char reg)
114 {
115 unsigned char retval;
116
117 writeb(reg, &channel->control);
118 ZSDELAY();
119 retval = readb(&channel->control);
120 ZSDELAY();
121
122 return retval;
123 }
124
125 static void write_zsreg(struct zilog_channel *channel,
126 unsigned char reg, unsigned char value)
127 {
128 writeb(reg, &channel->control);
129 ZSDELAY();
130 writeb(value, &channel->control);
131 ZSDELAY();
132 }
133
134 static void ip22zilog_clear_fifo(struct zilog_channel *channel)
135 {
136 int i;
137
138 for (i = 0; i < 32; i++) {
139 unsigned char regval;
140
141 regval = readb(&channel->control);
142 ZSDELAY();
143 if (regval & Rx_CH_AV)
144 break;
145
146 regval = read_zsreg(channel, R1);
147 readb(&channel->data);
148 ZSDELAY();
149
150 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
151 writeb(ERR_RES, &channel->control);
152 ZSDELAY();
153 ZS_WSYNC(channel);
154 }
155 }
156 }
157
158 /* This function must only be called when the TX is not busy. The UART
159 * port lock must be held and local interrupts disabled.
160 */
161 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs)
162 {
163 int i;
164
165 /* Let pending transmits finish. */
166 for (i = 0; i < 1000; i++) {
167 unsigned char stat = read_zsreg(channel, R1);
168 if (stat & ALL_SNT)
169 break;
170 udelay(100);
171 }
172
173 writeb(ERR_RES, &channel->control);
174 ZSDELAY();
175 ZS_WSYNC(channel);
176
177 ip22zilog_clear_fifo(channel);
178
179 /* Disable all interrupts. */
180 write_zsreg(channel, R1,
181 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
182
183 /* Set parity, sync config, stop bits, and clock divisor. */
184 write_zsreg(channel, R4, regs[R4]);
185
186 /* Set misc. TX/RX control bits. */
187 write_zsreg(channel, R10, regs[R10]);
188
189 /* Set TX/RX controls sans the enable bits. */
190 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
191 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
192
193 /* Synchronous mode config. */
194 write_zsreg(channel, R6, regs[R6]);
195 write_zsreg(channel, R7, regs[R7]);
196
197 /* Don't mess with the interrupt vector (R2, unused by us) and
198 * master interrupt control (R9). We make sure this is setup
199 * properly at probe time then never touch it again.
200 */
201
202 /* Disable baud generator. */
203 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
204
205 /* Clock mode control. */
206 write_zsreg(channel, R11, regs[R11]);
207
208 /* Lower and upper byte of baud rate generator divisor. */
209 write_zsreg(channel, R12, regs[R12]);
210 write_zsreg(channel, R13, regs[R13]);
211
212 /* Now rewrite R14, with BRENAB (if set). */
213 write_zsreg(channel, R14, regs[R14]);
214
215 /* External status interrupt control. */
216 write_zsreg(channel, R15, regs[R15]);
217
218 /* Reset external status interrupts. */
219 write_zsreg(channel, R0, RES_EXT_INT);
220 write_zsreg(channel, R0, RES_EXT_INT);
221
222 /* Rewrite R3/R5, this time without enables masked. */
223 write_zsreg(channel, R3, regs[R3]);
224 write_zsreg(channel, R5, regs[R5]);
225
226 /* Rewrite R1, this time without IRQ enabled masked. */
227 write_zsreg(channel, R1, regs[R1]);
228 }
229
230 /* Reprogram the Zilog channel HW registers with the copies found in the
231 * software state struct. If the transmitter is busy, we defer this update
232 * until the next TX complete interrupt. Else, we do it right now.
233 *
234 * The UART port lock must be held and local interrupts disabled.
235 */
236 static void ip22zilog_maybe_update_regs(struct uart_ip22zilog_port *up,
237 struct zilog_channel *channel)
238 {
239 if (!ZS_REGS_HELD(up)) {
240 if (ZS_TX_ACTIVE(up)) {
241 up->flags |= IP22ZILOG_FLAG_REGS_HELD;
242 } else {
243 __load_zsregs(channel, up->curregs);
244 }
245 }
246 }
247
248 #define Rx_BRK 0x0100 /* BREAK event software flag. */
249 #define Rx_SYS 0x0200 /* SysRq event software flag. */
250
251 static struct tty_struct *ip22zilog_receive_chars(struct uart_ip22zilog_port *up,
252 struct zilog_channel *channel)
253 {
254 struct tty_struct *tty;
255 unsigned char ch, flag;
256 unsigned int r1;
257
258 tty = NULL;
259 if (up->port.state != NULL &&
260 up->port.state->port.tty != NULL)
261 tty = up->port.state->port.tty;
262
263 for (;;) {
264 ch = readb(&channel->control);
265 ZSDELAY();
266 if (!(ch & Rx_CH_AV))
267 break;
268
269 r1 = read_zsreg(channel, R1);
270 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
271 writeb(ERR_RES, &channel->control);
272 ZSDELAY();
273 ZS_WSYNC(channel);
274 }
275
276 ch = readb(&channel->data);
277 ZSDELAY();
278
279 ch &= up->parity_mask;
280
281 /* Handle the null char got when BREAK is removed. */
282 if (!ch)
283 r1 |= up->tty_break;
284
285 /* A real serial line, record the character and status. */
286 flag = TTY_NORMAL;
287 up->port.icount.rx++;
288 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | Rx_SYS | Rx_BRK)) {
289 up->tty_break = 0;
290
291 if (r1 & (Rx_SYS | Rx_BRK)) {
292 up->port.icount.brk++;
293 if (r1 & Rx_SYS)
294 continue;
295 r1 &= ~(PAR_ERR | CRC_ERR);
296 }
297 else if (r1 & PAR_ERR)
298 up->port.icount.parity++;
299 else if (r1 & CRC_ERR)
300 up->port.icount.frame++;
301 if (r1 & Rx_OVR)
302 up->port.icount.overrun++;
303 r1 &= up->port.read_status_mask;
304 if (r1 & Rx_BRK)
305 flag = TTY_BREAK;
306 else if (r1 & PAR_ERR)
307 flag = TTY_PARITY;
308 else if (r1 & CRC_ERR)
309 flag = TTY_FRAME;
310 }
311
312 if (uart_handle_sysrq_char(&up->port, ch))
313 continue;
314
315 if (tty)
316 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag);
317 }
318 return tty;
319 }
320
321 static void ip22zilog_status_handle(struct uart_ip22zilog_port *up,
322 struct zilog_channel *channel)
323 {
324 unsigned char status;
325
326 status = readb(&channel->control);
327 ZSDELAY();
328
329 writeb(RES_EXT_INT, &channel->control);
330 ZSDELAY();
331 ZS_WSYNC(channel);
332
333 if (up->curregs[R15] & BRKIE) {
334 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) {
335 if (uart_handle_break(&up->port))
336 up->tty_break = Rx_SYS;
337 else
338 up->tty_break = Rx_BRK;
339 }
340 }
341
342 if (ZS_WANTS_MODEM_STATUS(up)) {
343 if (status & SYNC)
344 up->port.icount.dsr++;
345
346 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
347 * But it does not tell us which bit has changed, we have to keep
348 * track of this ourselves.
349 */
350 if ((status ^ up->prev_status) ^ DCD)
351 uart_handle_dcd_change(&up->port,
352 (status & DCD));
353 if ((status ^ up->prev_status) ^ CTS)
354 uart_handle_cts_change(&up->port,
355 (status & CTS));
356
357 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
358 }
359
360 up->prev_status = status;
361 }
362
363 static void ip22zilog_transmit_chars(struct uart_ip22zilog_port *up,
364 struct zilog_channel *channel)
365 {
366 struct circ_buf *xmit;
367
368 if (ZS_IS_CONS(up)) {
369 unsigned char status = readb(&channel->control);
370 ZSDELAY();
371
372 /* TX still busy? Just wait for the next TX done interrupt.
373 *
374 * It can occur because of how we do serial console writes. It would
375 * be nice to transmit console writes just like we normally would for
376 * a TTY line. (ie. buffered and TX interrupt driven). That is not
377 * easy because console writes cannot sleep. One solution might be
378 * to poll on enough port->xmit space becoming free. -DaveM
379 */
380 if (!(status & Tx_BUF_EMP))
381 return;
382 }
383
384 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE;
385
386 if (ZS_REGS_HELD(up)) {
387 __load_zsregs(channel, up->curregs);
388 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD;
389 }
390
391 if (ZS_TX_STOPPED(up)) {
392 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
393 goto ack_tx_int;
394 }
395
396 if (up->port.x_char) {
397 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
398 writeb(up->port.x_char, &channel->data);
399 ZSDELAY();
400 ZS_WSYNC(channel);
401
402 up->port.icount.tx++;
403 up->port.x_char = 0;
404 return;
405 }
406
407 if (up->port.state == NULL)
408 goto ack_tx_int;
409 xmit = &up->port.state->xmit;
410 if (uart_circ_empty(xmit))
411 goto ack_tx_int;
412 if (uart_tx_stopped(&up->port))
413 goto ack_tx_int;
414
415 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
416 writeb(xmit->buf[xmit->tail], &channel->data);
417 ZSDELAY();
418 ZS_WSYNC(channel);
419
420 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
421 up->port.icount.tx++;
422
423 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
424 uart_write_wakeup(&up->port);
425
426 return;
427
428 ack_tx_int:
429 writeb(RES_Tx_P, &channel->control);
430 ZSDELAY();
431 ZS_WSYNC(channel);
432 }
433
434 static irqreturn_t ip22zilog_interrupt(int irq, void *dev_id)
435 {
436 struct uart_ip22zilog_port *up = dev_id;
437
438 while (up) {
439 struct zilog_channel *channel
440 = ZILOG_CHANNEL_FROM_PORT(&up->port);
441 struct tty_struct *tty;
442 unsigned char r3;
443
444 spin_lock(&up->port.lock);
445 r3 = read_zsreg(channel, R3);
446
447 /* Channel A */
448 tty = NULL;
449 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
450 writeb(RES_H_IUS, &channel->control);
451 ZSDELAY();
452 ZS_WSYNC(channel);
453
454 if (r3 & CHARxIP)
455 tty = ip22zilog_receive_chars(up, channel);
456 if (r3 & CHAEXT)
457 ip22zilog_status_handle(up, channel);
458 if (r3 & CHATxIP)
459 ip22zilog_transmit_chars(up, channel);
460 }
461 spin_unlock(&up->port.lock);
462
463 if (tty)
464 tty_flip_buffer_push(tty);
465
466 /* Channel B */
467 up = up->next;
468 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
469
470 spin_lock(&up->port.lock);
471 tty = NULL;
472 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
473 writeb(RES_H_IUS, &channel->control);
474 ZSDELAY();
475 ZS_WSYNC(channel);
476
477 if (r3 & CHBRxIP)
478 tty = ip22zilog_receive_chars(up, channel);
479 if (r3 & CHBEXT)
480 ip22zilog_status_handle(up, channel);
481 if (r3 & CHBTxIP)
482 ip22zilog_transmit_chars(up, channel);
483 }
484 spin_unlock(&up->port.lock);
485
486 if (tty)
487 tty_flip_buffer_push(tty);
488
489 up = up->next;
490 }
491
492 return IRQ_HANDLED;
493 }
494
495 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
496 * port lock, it is acquired here.
497 */
498 static __inline__ unsigned char ip22zilog_read_channel_status(struct uart_port *port)
499 {
500 struct zilog_channel *channel;
501 unsigned char status;
502
503 channel = ZILOG_CHANNEL_FROM_PORT(port);
504 status = readb(&channel->control);
505 ZSDELAY();
506
507 return status;
508 }
509
510 /* The port lock is not held. */
511 static unsigned int ip22zilog_tx_empty(struct uart_port *port)
512 {
513 unsigned long flags;
514 unsigned char status;
515 unsigned int ret;
516
517 spin_lock_irqsave(&port->lock, flags);
518
519 status = ip22zilog_read_channel_status(port);
520
521 spin_unlock_irqrestore(&port->lock, flags);
522
523 if (status & Tx_BUF_EMP)
524 ret = TIOCSER_TEMT;
525 else
526 ret = 0;
527
528 return ret;
529 }
530
531 /* The port lock is held and interrupts are disabled. */
532 static unsigned int ip22zilog_get_mctrl(struct uart_port *port)
533 {
534 unsigned char status;
535 unsigned int ret;
536
537 status = ip22zilog_read_channel_status(port);
538
539 ret = 0;
540 if (status & DCD)
541 ret |= TIOCM_CAR;
542 if (status & SYNC)
543 ret |= TIOCM_DSR;
544 if (status & CTS)
545 ret |= TIOCM_CTS;
546
547 return ret;
548 }
549
550 /* The port lock is held and interrupts are disabled. */
551 static void ip22zilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
552 {
553 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
554 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
555 unsigned char set_bits, clear_bits;
556
557 set_bits = clear_bits = 0;
558
559 if (mctrl & TIOCM_RTS)
560 set_bits |= RTS;
561 else
562 clear_bits |= RTS;
563 if (mctrl & TIOCM_DTR)
564 set_bits |= DTR;
565 else
566 clear_bits |= DTR;
567
568 /* NOTE: Not subject to 'transmitter active' rule. */
569 up->curregs[R5] |= set_bits;
570 up->curregs[R5] &= ~clear_bits;
571 write_zsreg(channel, R5, up->curregs[R5]);
572 }
573
574 /* The port lock is held and interrupts are disabled. */
575 static void ip22zilog_stop_tx(struct uart_port *port)
576 {
577 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
578
579 up->flags |= IP22ZILOG_FLAG_TX_STOPPED;
580 }
581
582 /* The port lock is held and interrupts are disabled. */
583 static void ip22zilog_start_tx(struct uart_port *port)
584 {
585 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
586 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
587 unsigned char status;
588
589 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE;
590 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED;
591
592 status = readb(&channel->control);
593 ZSDELAY();
594
595 /* TX busy? Just wait for the TX done interrupt. */
596 if (!(status & Tx_BUF_EMP))
597 return;
598
599 /* Send the first character to jump-start the TX done
600 * IRQ sending engine.
601 */
602 if (port->x_char) {
603 writeb(port->x_char, &channel->data);
604 ZSDELAY();
605 ZS_WSYNC(channel);
606
607 port->icount.tx++;
608 port->x_char = 0;
609 } else {
610 struct circ_buf *xmit = &port->state->xmit;
611
612 writeb(xmit->buf[xmit->tail], &channel->data);
613 ZSDELAY();
614 ZS_WSYNC(channel);
615
616 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
617 port->icount.tx++;
618
619 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
620 uart_write_wakeup(&up->port);
621 }
622 }
623
624 /* The port lock is held and interrupts are disabled. */
625 static void ip22zilog_stop_rx(struct uart_port *port)
626 {
627 struct uart_ip22zilog_port *up = UART_ZILOG(port);
628 struct zilog_channel *channel;
629
630 if (ZS_IS_CONS(up))
631 return;
632
633 channel = ZILOG_CHANNEL_FROM_PORT(port);
634
635 /* Disable all RX interrupts. */
636 up->curregs[R1] &= ~RxINT_MASK;
637 ip22zilog_maybe_update_regs(up, channel);
638 }
639
640 /* The port lock is held. */
641 static void ip22zilog_enable_ms(struct uart_port *port)
642 {
643 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
644 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
645 unsigned char new_reg;
646
647 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
648 if (new_reg != up->curregs[R15]) {
649 up->curregs[R15] = new_reg;
650
651 /* NOTE: Not subject to 'transmitter active' rule. */
652 write_zsreg(channel, R15, up->curregs[R15]);
653 }
654 }
655
656 /* The port lock is not held. */
657 static void ip22zilog_break_ctl(struct uart_port *port, int break_state)
658 {
659 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
660 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
661 unsigned char set_bits, clear_bits, new_reg;
662 unsigned long flags;
663
664 set_bits = clear_bits = 0;
665
666 if (break_state)
667 set_bits |= SND_BRK;
668 else
669 clear_bits |= SND_BRK;
670
671 spin_lock_irqsave(&port->lock, flags);
672
673 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
674 if (new_reg != up->curregs[R5]) {
675 up->curregs[R5] = new_reg;
676
677 /* NOTE: Not subject to 'transmitter active' rule. */
678 write_zsreg(channel, R5, up->curregs[R5]);
679 }
680
681 spin_unlock_irqrestore(&port->lock, flags);
682 }
683
684 static void __ip22zilog_reset(struct uart_ip22zilog_port *up)
685 {
686 struct zilog_channel *channel;
687 int i;
688
689 if (up->flags & IP22ZILOG_FLAG_RESET_DONE)
690 return;
691
692 /* Let pending transmits finish. */
693 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
694 for (i = 0; i < 1000; i++) {
695 unsigned char stat = read_zsreg(channel, R1);
696 if (stat & ALL_SNT)
697 break;
698 udelay(100);
699 }
700
701 if (!ZS_IS_CHANNEL_A(up)) {
702 up++;
703 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
704 }
705 write_zsreg(channel, R9, FHWRES);
706 ZSDELAY_LONG();
707 (void) read_zsreg(channel, R0);
708
709 up->flags |= IP22ZILOG_FLAG_RESET_DONE;
710 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE;
711 }
712
713 static void __ip22zilog_startup(struct uart_ip22zilog_port *up)
714 {
715 struct zilog_channel *channel;
716
717 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
718
719 __ip22zilog_reset(up);
720
721 __load_zsregs(channel, up->curregs);
722 /* set master interrupt enable */
723 write_zsreg(channel, R9, up->curregs[R9]);
724 up->prev_status = readb(&channel->control);
725
726 /* Enable receiver and transmitter. */
727 up->curregs[R3] |= RxENAB;
728 up->curregs[R5] |= TxENAB;
729
730 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
731 ip22zilog_maybe_update_regs(up, channel);
732 }
733
734 static int ip22zilog_startup(struct uart_port *port)
735 {
736 struct uart_ip22zilog_port *up = UART_ZILOG(port);
737 unsigned long flags;
738
739 if (ZS_IS_CONS(up))
740 return 0;
741
742 spin_lock_irqsave(&port->lock, flags);
743 __ip22zilog_startup(up);
744 spin_unlock_irqrestore(&port->lock, flags);
745 return 0;
746 }
747
748 /*
749 * The test for ZS_IS_CONS is explained by the following e-mail:
750 *****
751 * From: Russell King <rmk@arm.linux.org.uk>
752 * Date: Sun, 8 Dec 2002 10:18:38 +0000
753 *
754 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
755 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
756 * > and I noticed that something is not right with reference
757 * > counting in this case. It seems that when the console
758 * > is open by kernel initially, this is not accounted
759 * > as an open, and uart_startup is not called.
760 *
761 * That is correct. We are unable to call uart_startup when the serial
762 * console is initialised because it may need to allocate memory (as
763 * request_irq does) and the memory allocators may not have been
764 * initialised.
765 *
766 * 1. initialise the port into a state where it can send characters in the
767 * console write method.
768 *
769 * 2. don't do the actual hardware shutdown in your shutdown() method (but
770 * do the normal software shutdown - ie, free irqs etc)
771 *****
772 */
773 static void ip22zilog_shutdown(struct uart_port *port)
774 {
775 struct uart_ip22zilog_port *up = UART_ZILOG(port);
776 struct zilog_channel *channel;
777 unsigned long flags;
778
779 if (ZS_IS_CONS(up))
780 return;
781
782 spin_lock_irqsave(&port->lock, flags);
783
784 channel = ZILOG_CHANNEL_FROM_PORT(port);
785
786 /* Disable receiver and transmitter. */
787 up->curregs[R3] &= ~RxENAB;
788 up->curregs[R5] &= ~TxENAB;
789
790 /* Disable all interrupts and BRK assertion. */
791 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
792 up->curregs[R5] &= ~SND_BRK;
793 ip22zilog_maybe_update_regs(up, channel);
794
795 spin_unlock_irqrestore(&port->lock, flags);
796 }
797
798 /* Shared by TTY driver and serial console setup. The port lock is held
799 * and local interrupts are disabled.
800 */
801 static void
802 ip22zilog_convert_to_zs(struct uart_ip22zilog_port *up, unsigned int cflag,
803 unsigned int iflag, int brg)
804 {
805
806 up->curregs[R10] = NRZ;
807 up->curregs[R11] = TCBR | RCBR;
808
809 /* Program BAUD and clock source. */
810 up->curregs[R4] &= ~XCLK_MASK;
811 up->curregs[R4] |= X16CLK;
812 up->curregs[R12] = brg & 0xff;
813 up->curregs[R13] = (brg >> 8) & 0xff;
814 up->curregs[R14] = BRENAB;
815
816 /* Character size, stop bits, and parity. */
817 up->curregs[3] &= ~RxN_MASK;
818 up->curregs[5] &= ~TxN_MASK;
819 switch (cflag & CSIZE) {
820 case CS5:
821 up->curregs[3] |= Rx5;
822 up->curregs[5] |= Tx5;
823 up->parity_mask = 0x1f;
824 break;
825 case CS6:
826 up->curregs[3] |= Rx6;
827 up->curregs[5] |= Tx6;
828 up->parity_mask = 0x3f;
829 break;
830 case CS7:
831 up->curregs[3] |= Rx7;
832 up->curregs[5] |= Tx7;
833 up->parity_mask = 0x7f;
834 break;
835 case CS8:
836 default:
837 up->curregs[3] |= Rx8;
838 up->curregs[5] |= Tx8;
839 up->parity_mask = 0xff;
840 break;
841 };
842 up->curregs[4] &= ~0x0c;
843 if (cflag & CSTOPB)
844 up->curregs[4] |= SB2;
845 else
846 up->curregs[4] |= SB1;
847 if (cflag & PARENB)
848 up->curregs[4] |= PAR_ENAB;
849 else
850 up->curregs[4] &= ~PAR_ENAB;
851 if (!(cflag & PARODD))
852 up->curregs[4] |= PAR_EVEN;
853 else
854 up->curregs[4] &= ~PAR_EVEN;
855
856 up->port.read_status_mask = Rx_OVR;
857 if (iflag & INPCK)
858 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
859 if (iflag & (BRKINT | PARMRK))
860 up->port.read_status_mask |= BRK_ABRT;
861
862 up->port.ignore_status_mask = 0;
863 if (iflag & IGNPAR)
864 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
865 if (iflag & IGNBRK) {
866 up->port.ignore_status_mask |= BRK_ABRT;
867 if (iflag & IGNPAR)
868 up->port.ignore_status_mask |= Rx_OVR;
869 }
870
871 if ((cflag & CREAD) == 0)
872 up->port.ignore_status_mask = 0xff;
873 }
874
875 /* The port lock is not held. */
876 static void
877 ip22zilog_set_termios(struct uart_port *port, struct ktermios *termios,
878 struct ktermios *old)
879 {
880 struct uart_ip22zilog_port *up = (struct uart_ip22zilog_port *) port;
881 unsigned long flags;
882 int baud, brg;
883
884 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
885
886 spin_lock_irqsave(&up->port.lock, flags);
887
888 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
889
890 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
891
892 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
893 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS;
894 else
895 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS;
896
897 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
898 uart_update_timeout(port, termios->c_cflag, baud);
899
900 spin_unlock_irqrestore(&up->port.lock, flags);
901 }
902
903 static const char *ip22zilog_type(struct uart_port *port)
904 {
905 return "IP22-Zilog";
906 }
907
908 /* We do not request/release mappings of the registers here, this
909 * happens at early serial probe time.
910 */
911 static void ip22zilog_release_port(struct uart_port *port)
912 {
913 }
914
915 static int ip22zilog_request_port(struct uart_port *port)
916 {
917 return 0;
918 }
919
920 /* These do not need to do anything interesting either. */
921 static void ip22zilog_config_port(struct uart_port *port, int flags)
922 {
923 }
924
925 /* We do not support letting the user mess with the divisor, IRQ, etc. */
926 static int ip22zilog_verify_port(struct uart_port *port, struct serial_struct *ser)
927 {
928 return -EINVAL;
929 }
930
931 static struct uart_ops ip22zilog_pops = {
932 .tx_empty = ip22zilog_tx_empty,
933 .set_mctrl = ip22zilog_set_mctrl,
934 .get_mctrl = ip22zilog_get_mctrl,
935 .stop_tx = ip22zilog_stop_tx,
936 .start_tx = ip22zilog_start_tx,
937 .stop_rx = ip22zilog_stop_rx,
938 .enable_ms = ip22zilog_enable_ms,
939 .break_ctl = ip22zilog_break_ctl,
940 .startup = ip22zilog_startup,
941 .shutdown = ip22zilog_shutdown,
942 .set_termios = ip22zilog_set_termios,
943 .type = ip22zilog_type,
944 .release_port = ip22zilog_release_port,
945 .request_port = ip22zilog_request_port,
946 .config_port = ip22zilog_config_port,
947 .verify_port = ip22zilog_verify_port,
948 };
949
950 static struct uart_ip22zilog_port *ip22zilog_port_table;
951 static struct zilog_layout **ip22zilog_chip_regs;
952
953 static struct uart_ip22zilog_port *ip22zilog_irq_chain;
954 static int zilog_irq = -1;
955
956 static void * __init alloc_one_table(unsigned long size)
957 {
958 return kzalloc(size, GFP_KERNEL);
959 }
960
961 static void __init ip22zilog_alloc_tables(void)
962 {
963 ip22zilog_port_table = (struct uart_ip22zilog_port *)
964 alloc_one_table(NUM_CHANNELS * sizeof(struct uart_ip22zilog_port));
965 ip22zilog_chip_regs = (struct zilog_layout **)
966 alloc_one_table(NUM_IP22ZILOG * sizeof(struct zilog_layout *));
967
968 if (ip22zilog_port_table == NULL || ip22zilog_chip_regs == NULL) {
969 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables.");
970 }
971 }
972
973 /* Get the address of the registers for IP22-Zilog instance CHIP. */
974 static struct zilog_layout * __init get_zs(int chip)
975 {
976 unsigned long base;
977
978 if (chip < 0 || chip >= NUM_IP22ZILOG) {
979 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip);
980 }
981
982 /* Not probe-able, hard code it. */
983 base = (unsigned long) &sgioc->uart;
984
985 zilog_irq = SGI_SERIAL_IRQ;
986 request_mem_region(base, 8, "IP22-Zilog");
987
988 return (struct zilog_layout *) base;
989 }
990
991 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
992
993 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
994 static void ip22zilog_put_char(struct uart_port *port, int ch)
995 {
996 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port);
997 int loops = ZS_PUT_CHAR_MAX_DELAY;
998
999 /* This is a timed polling loop so do not switch the explicit
1000 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1001 */
1002 do {
1003 unsigned char val = readb(&channel->control);
1004 if (val & Tx_BUF_EMP) {
1005 ZSDELAY();
1006 break;
1007 }
1008 udelay(5);
1009 } while (--loops);
1010
1011 writeb(ch, &channel->data);
1012 ZSDELAY();
1013 ZS_WSYNC(channel);
1014 }
1015
1016 static void
1017 ip22zilog_console_write(struct console *con, const char *s, unsigned int count)
1018 {
1019 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1020 unsigned long flags;
1021
1022 spin_lock_irqsave(&up->port.lock, flags);
1023 uart_console_write(&up->port, s, count, ip22zilog_put_char);
1024 udelay(2);
1025 spin_unlock_irqrestore(&up->port.lock, flags);
1026 }
1027
1028 static int __init ip22zilog_console_setup(struct console *con, char *options)
1029 {
1030 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index];
1031 unsigned long flags;
1032 int baud = 9600, bits = 8;
1033 int parity = 'n';
1034 int flow = 'n';
1035
1036 up->flags |= IP22ZILOG_FLAG_IS_CONS;
1037
1038 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index);
1039
1040 spin_lock_irqsave(&up->port.lock, flags);
1041
1042 up->curregs[R15] |= BRKIE;
1043
1044 __ip22zilog_startup(up);
1045
1046 spin_unlock_irqrestore(&up->port.lock, flags);
1047
1048 if (options)
1049 uart_parse_options(options, &baud, &parity, &bits, &flow);
1050 return uart_set_options(&up->port, con, baud, parity, bits, flow);
1051 }
1052
1053 static struct uart_driver ip22zilog_reg;
1054
1055 static struct console ip22zilog_console = {
1056 .name = "ttyS",
1057 .write = ip22zilog_console_write,
1058 .device = uart_console_device,
1059 .setup = ip22zilog_console_setup,
1060 .flags = CON_PRINTBUFFER,
1061 .index = -1,
1062 .data = &ip22zilog_reg,
1063 };
1064 #endif /* CONFIG_SERIAL_IP22_ZILOG_CONSOLE */
1065
1066 static struct uart_driver ip22zilog_reg = {
1067 .owner = THIS_MODULE,
1068 .driver_name = "serial",
1069 .dev_name = "ttyS",
1070 .major = TTY_MAJOR,
1071 .minor = 64,
1072 .nr = NUM_CHANNELS,
1073 #ifdef CONFIG_SERIAL_IP22_ZILOG_CONSOLE
1074 .cons = &ip22zilog_console,
1075 #endif
1076 };
1077
1078 static void __init ip22zilog_prepare(void)
1079 {
1080 struct uart_ip22zilog_port *up;
1081 struct zilog_layout *rp;
1082 int channel, chip;
1083
1084 /*
1085 * Temporary fix.
1086 */
1087 for (channel = 0; channel < NUM_CHANNELS; channel++)
1088 spin_lock_init(&ip22zilog_port_table[channel].port.lock);
1089
1090 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1];
1091 up = &ip22zilog_port_table[0];
1092 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--)
1093 up[channel].next = &up[channel - 1];
1094 up[channel].next = NULL;
1095
1096 for (chip = 0; chip < NUM_IP22ZILOG; chip++) {
1097 if (!ip22zilog_chip_regs[chip]) {
1098 ip22zilog_chip_regs[chip] = rp = get_zs(chip);
1099
1100 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB;
1101 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA;
1102
1103 /* In theory mapbase is the physical address ... */
1104 up[(chip * 2) + 0].port.mapbase =
1105 (unsigned long) ioremap((unsigned long) &rp->channelB, 8);
1106 up[(chip * 2) + 1].port.mapbase =
1107 (unsigned long) ioremap((unsigned long) &rp->channelA, 8);
1108 }
1109
1110 /* Channel A */
1111 up[(chip * 2) + 0].port.iotype = UPIO_MEM;
1112 up[(chip * 2) + 0].port.irq = zilog_irq;
1113 up[(chip * 2) + 0].port.uartclk = ZS_CLOCK;
1114 up[(chip * 2) + 0].port.fifosize = 1;
1115 up[(chip * 2) + 0].port.ops = &ip22zilog_pops;
1116 up[(chip * 2) + 0].port.type = PORT_IP22ZILOG;
1117 up[(chip * 2) + 0].port.flags = 0;
1118 up[(chip * 2) + 0].port.line = (chip * 2) + 0;
1119 up[(chip * 2) + 0].flags = 0;
1120
1121 /* Channel B */
1122 up[(chip * 2) + 1].port.iotype = UPIO_MEM;
1123 up[(chip * 2) + 1].port.irq = zilog_irq;
1124 up[(chip * 2) + 1].port.uartclk = ZS_CLOCK;
1125 up[(chip * 2) + 1].port.fifosize = 1;
1126 up[(chip * 2) + 1].port.ops = &ip22zilog_pops;
1127 up[(chip * 2) + 1].port.type = PORT_IP22ZILOG;
1128 up[(chip * 2) + 1].port.line = (chip * 2) + 1;
1129 up[(chip * 2) + 1].flags |= IP22ZILOG_FLAG_IS_CHANNEL_A;
1130 }
1131
1132 for (channel = 0; channel < NUM_CHANNELS; channel++) {
1133 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel];
1134 int brg;
1135
1136 /* Normal serial TTY. */
1137 up->parity_mask = 0xff;
1138 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1139 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1140 up->curregs[R3] = RxENAB | Rx8;
1141 up->curregs[R5] = TxENAB | Tx8;
1142 up->curregs[R9] = NV | MIE;
1143 up->curregs[R10] = NRZ;
1144 up->curregs[R11] = TCBR | RCBR;
1145 brg = BPS_TO_BRG(9600, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1146 up->curregs[R12] = (brg & 0xff);
1147 up->curregs[R13] = (brg >> 8) & 0xff;
1148 up->curregs[R14] = BRENAB;
1149 }
1150 }
1151
1152 static int __init ip22zilog_ports_init(void)
1153 {
1154 int ret;
1155
1156 printk(KERN_INFO "Serial: IP22 Zilog driver (%d chips).\n", NUM_IP22ZILOG);
1157
1158 ip22zilog_prepare();
1159
1160 if (request_irq(zilog_irq, ip22zilog_interrupt, 0,
1161 "IP22-Zilog", ip22zilog_irq_chain)) {
1162 panic("IP22-Zilog: Unable to register zs interrupt handler.\n");
1163 }
1164
1165 ret = uart_register_driver(&ip22zilog_reg);
1166 if (ret == 0) {
1167 int i;
1168
1169 for (i = 0; i < NUM_CHANNELS; i++) {
1170 struct uart_ip22zilog_port *up = &ip22zilog_port_table[i];
1171
1172 uart_add_one_port(&ip22zilog_reg, &up->port);
1173 }
1174 }
1175
1176 return ret;
1177 }
1178
1179 static int __init ip22zilog_init(void)
1180 {
1181 /* IP22 Zilog setup is hard coded, no probing to do. */
1182 ip22zilog_alloc_tables();
1183 ip22zilog_ports_init();
1184
1185 return 0;
1186 }
1187
1188 static void __exit ip22zilog_exit(void)
1189 {
1190 int i;
1191 struct uart_ip22zilog_port *up;
1192
1193 for (i = 0; i < NUM_CHANNELS; i++) {
1194 up = &ip22zilog_port_table[i];
1195
1196 uart_remove_one_port(&ip22zilog_reg, &up->port);
1197 }
1198
1199 /* Free IO mem */
1200 up = &ip22zilog_port_table[0];
1201 for (i = 0; i < NUM_IP22ZILOG; i++) {
1202 if (up[(i * 2) + 0].port.mapbase) {
1203 iounmap((void*)up[(i * 2) + 0].port.mapbase);
1204 up[(i * 2) + 0].port.mapbase = 0;
1205 }
1206 if (up[(i * 2) + 1].port.mapbase) {
1207 iounmap((void*)up[(i * 2) + 1].port.mapbase);
1208 up[(i * 2) + 1].port.mapbase = 0;
1209 }
1210 }
1211
1212 uart_unregister_driver(&ip22zilog_reg);
1213 }
1214
1215 module_init(ip22zilog_init);
1216 module_exit(ip22zilog_exit);
1217
1218 /* David wrote it but I'm to blame for the bugs ... */
1219 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1220 MODULE_DESCRIPTION("SGI Zilog serial port driver");
1221 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)