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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/pinctrl/consumer.h>
51 #include <linux/io.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55
56 /* Register definitions */
57 #define URXD0 0x0 /* Receiver Register */
58 #define URTX0 0x40 /* Transmitter Register */
59 #define UCR1 0x80 /* Control Register 1 */
60 #define UCR2 0x84 /* Control Register 2 */
61 #define UCR3 0x88 /* Control Register 3 */
62 #define UCR4 0x8c /* Control Register 4 */
63 #define UFCR 0x90 /* FIFO Control Register */
64 #define USR1 0x94 /* Status Register 1 */
65 #define USR2 0x98 /* Status Register 2 */
66 #define UESC 0x9c /* Escape Character Register */
67 #define UTIM 0xa0 /* Escape Timer Register */
68 #define UBIR 0xa4 /* BRM Incremental Register */
69 #define UBMR 0xa8 /* BRM Modulator Register */
70 #define UBRC 0xac /* Baud Rate Count Register */
71 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
72 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
73 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
74
75 /* UART Control Register Bit Fields.*/
76 #define URXD_CHARRDY (1<<15)
77 #define URXD_ERR (1<<14)
78 #define URXD_OVRRUN (1<<13)
79 #define URXD_FRMERR (1<<12)
80 #define URXD_BRK (1<<11)
81 #define URXD_PRERR (1<<10)
82 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
83 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
84 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
85 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
86 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
87 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
88 #define UCR1_IREN (1<<7) /* Infrared interface enable */
89 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
90 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
91 #define UCR1_SNDBRK (1<<4) /* Send break */
92 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
93 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
94 #define UCR1_DOZE (1<<1) /* Doze */
95 #define UCR1_UARTEN (1<<0) /* UART enabled */
96 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
97 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
98 #define UCR2_CTSC (1<<13) /* CTS pin control */
99 #define UCR2_CTS (1<<12) /* Clear to send */
100 #define UCR2_ESCEN (1<<11) /* Escape enable */
101 #define UCR2_PREN (1<<8) /* Parity enable */
102 #define UCR2_PROE (1<<7) /* Parity odd/even */
103 #define UCR2_STPB (1<<6) /* Stop */
104 #define UCR2_WS (1<<5) /* Word size */
105 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
106 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
107 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
108 #define UCR2_RXEN (1<<1) /* Receiver enabled */
109 #define UCR2_SRST (1<<0) /* SW reset */
110 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
111 #define UCR3_PARERREN (1<<12) /* Parity enable */
112 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
113 #define UCR3_DSR (1<<10) /* Data set ready */
114 #define UCR3_DCD (1<<9) /* Data carrier detect */
115 #define UCR3_RI (1<<8) /* Ring indicator */
116 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
117 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
118 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
119 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
120 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
121 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
122 #define UCR3_BPEN (1<<0) /* Preset registers enable */
123 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
124 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
125 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
126 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
127 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
128 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
129 #define UCR4_IRSC (1<<5) /* IR special case */
130 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
131 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
132 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
133 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
134 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
135 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
136 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
137 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
138 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
139 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
140 #define USR1_RTSS (1<<14) /* RTS pin status */
141 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
142 #define USR1_RTSD (1<<12) /* RTS delta */
143 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
144 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
145 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
146 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE (1<<12) /* Idle condition */
154 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
155 #define USR2_WAKE (1<<7) /* Wake */
156 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
157 #define USR2_TXDC (1<<3) /* Transmitter complete */
158 #define USR2_BRCD (1<<2) /* Break condition */
159 #define USR2_ORE (1<<1) /* Overrun error */
160 #define USR2_RDR (1<<0) /* Recv data ready */
161 #define UTS_FRCPERR (1<<13) /* Force parity error */
162 #define UTS_LOOP (1<<12) /* Loop tx and rx */
163 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
164 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
165 #define UTS_TXFULL (1<<4) /* TxFIFO full */
166 #define UTS_RXFULL (1<<3) /* RxFIFO full */
167 #define UTS_SOFTRST (1<<0) /* Software reset */
168
169 /* We've been assigned a range on the "Low-density serial ports" major */
170 #define SERIAL_IMX_MAJOR 207
171 #define MINOR_START 16
172 #define DEV_NAME "ttymxc"
173
174 /*
175 * This determines how often we check the modem status signals
176 * for any change. They generally aren't connected to an IRQ
177 * so we have to poll them. We also check immediately before
178 * filling the TX fifo incase CTS has been dropped.
179 */
180 #define MCTRL_TIMEOUT (250*HZ/1000)
181
182 #define DRIVER_NAME "IMX-uart"
183
184 #define UART_NR 8
185
186 /* i.mx21 type uart runs on all i.mx except i.mx1 */
187 enum imx_uart_type {
188 IMX1_UART,
189 IMX21_UART,
190 };
191
192 /* device type dependent stuff */
193 struct imx_uart_data {
194 unsigned uts_reg;
195 enum imx_uart_type devtype;
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 int txirq, rxirq, rtsirq;
203 unsigned int have_rtscts:1;
204 unsigned int use_irda:1;
205 unsigned int irda_inv_rx:1;
206 unsigned int irda_inv_tx:1;
207 unsigned short trcv_delay; /* transceiver delay */
208 struct clk *clk_ipg;
209 struct clk *clk_per;
210 const struct imx_uart_data *devdata;
211 };
212
213 struct imx_port_ucrs {
214 unsigned int ucr1;
215 unsigned int ucr2;
216 unsigned int ucr3;
217 };
218
219 #ifdef CONFIG_IRDA
220 #define USE_IRDA(sport) ((sport)->use_irda)
221 #else
222 #define USE_IRDA(sport) (0)
223 #endif
224
225 static struct imx_uart_data imx_uart_devdata[] = {
226 [IMX1_UART] = {
227 .uts_reg = IMX1_UTS,
228 .devtype = IMX1_UART,
229 },
230 [IMX21_UART] = {
231 .uts_reg = IMX21_UTS,
232 .devtype = IMX21_UART,
233 },
234 };
235
236 static struct platform_device_id imx_uart_devtype[] = {
237 {
238 .name = "imx1-uart",
239 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
240 }, {
241 .name = "imx21-uart",
242 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
243 }, {
244 /* sentinel */
245 }
246 };
247 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
248
249 static struct of_device_id imx_uart_dt_ids[] = {
250 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
251 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
252 { /* sentinel */ }
253 };
254 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
255
256 static inline unsigned uts_reg(struct imx_port *sport)
257 {
258 return sport->devdata->uts_reg;
259 }
260
261 static inline int is_imx1_uart(struct imx_port *sport)
262 {
263 return sport->devdata->devtype == IMX1_UART;
264 }
265
266 static inline int is_imx21_uart(struct imx_port *sport)
267 {
268 return sport->devdata->devtype == IMX21_UART;
269 }
270
271 /*
272 * Save and restore functions for UCR1, UCR2 and UCR3 registers
273 */
274 static void imx_port_ucrs_save(struct uart_port *port,
275 struct imx_port_ucrs *ucr)
276 {
277 /* save control registers */
278 ucr->ucr1 = readl(port->membase + UCR1);
279 ucr->ucr2 = readl(port->membase + UCR2);
280 ucr->ucr3 = readl(port->membase + UCR3);
281 }
282
283 static void imx_port_ucrs_restore(struct uart_port *port,
284 struct imx_port_ucrs *ucr)
285 {
286 /* restore control registers */
287 writel(ucr->ucr1, port->membase + UCR1);
288 writel(ucr->ucr2, port->membase + UCR2);
289 writel(ucr->ucr3, port->membase + UCR3);
290 }
291
292 /*
293 * Handle any change of modem status signal since we were last called.
294 */
295 static void imx_mctrl_check(struct imx_port *sport)
296 {
297 unsigned int status, changed;
298
299 status = sport->port.ops->get_mctrl(&sport->port);
300 changed = status ^ sport->old_status;
301
302 if (changed == 0)
303 return;
304
305 sport->old_status = status;
306
307 if (changed & TIOCM_RI)
308 sport->port.icount.rng++;
309 if (changed & TIOCM_DSR)
310 sport->port.icount.dsr++;
311 if (changed & TIOCM_CAR)
312 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
313 if (changed & TIOCM_CTS)
314 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
315
316 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
317 }
318
319 /*
320 * This is our per-port timeout handler, for checking the
321 * modem status signals.
322 */
323 static void imx_timeout(unsigned long data)
324 {
325 struct imx_port *sport = (struct imx_port *)data;
326 unsigned long flags;
327
328 if (sport->port.state) {
329 spin_lock_irqsave(&sport->port.lock, flags);
330 imx_mctrl_check(sport);
331 spin_unlock_irqrestore(&sport->port.lock, flags);
332
333 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
334 }
335 }
336
337 /*
338 * interrupts disabled on entry
339 */
340 static void imx_stop_tx(struct uart_port *port)
341 {
342 struct imx_port *sport = (struct imx_port *)port;
343 unsigned long temp;
344
345 if (USE_IRDA(sport)) {
346 /* half duplex - wait for end of transmission */
347 int n = 256;
348 while ((--n > 0) &&
349 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
350 udelay(5);
351 barrier();
352 }
353 /*
354 * irda transceiver - wait a bit more to avoid
355 * cutoff, hardware dependent
356 */
357 udelay(sport->trcv_delay);
358
359 /*
360 * half duplex - reactivate receive mode,
361 * flush receive pipe echo crap
362 */
363 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
364 temp = readl(sport->port.membase + UCR1);
365 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
366 writel(temp, sport->port.membase + UCR1);
367
368 temp = readl(sport->port.membase + UCR4);
369 temp &= ~(UCR4_TCEN);
370 writel(temp, sport->port.membase + UCR4);
371
372 while (readl(sport->port.membase + URXD0) &
373 URXD_CHARRDY)
374 barrier();
375
376 temp = readl(sport->port.membase + UCR1);
377 temp |= UCR1_RRDYEN;
378 writel(temp, sport->port.membase + UCR1);
379
380 temp = readl(sport->port.membase + UCR4);
381 temp |= UCR4_DREN;
382 writel(temp, sport->port.membase + UCR4);
383 }
384 return;
385 }
386
387 temp = readl(sport->port.membase + UCR1);
388 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
389 }
390
391 /*
392 * interrupts disabled on entry
393 */
394 static void imx_stop_rx(struct uart_port *port)
395 {
396 struct imx_port *sport = (struct imx_port *)port;
397 unsigned long temp;
398
399 temp = readl(sport->port.membase + UCR2);
400 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
401 }
402
403 /*
404 * Set the modem control timer to fire immediately.
405 */
406 static void imx_enable_ms(struct uart_port *port)
407 {
408 struct imx_port *sport = (struct imx_port *)port;
409
410 mod_timer(&sport->timer, jiffies);
411 }
412
413 static inline void imx_transmit_buffer(struct imx_port *sport)
414 {
415 struct circ_buf *xmit = &sport->port.state->xmit;
416
417 while (!uart_circ_empty(xmit) &&
418 !(readl(sport->port.membase + uts_reg(sport))
419 & UTS_TXFULL)) {
420 /* send xmit->buf[xmit->tail]
421 * out the port here */
422 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
423 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
424 sport->port.icount.tx++;
425 }
426
427 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
428 uart_write_wakeup(&sport->port);
429
430 if (uart_circ_empty(xmit))
431 imx_stop_tx(&sport->port);
432 }
433
434 /*
435 * interrupts disabled on entry
436 */
437 static void imx_start_tx(struct uart_port *port)
438 {
439 struct imx_port *sport = (struct imx_port *)port;
440 unsigned long temp;
441
442 if (USE_IRDA(sport)) {
443 /* half duplex in IrDA mode; have to disable receive mode */
444 temp = readl(sport->port.membase + UCR4);
445 temp &= ~(UCR4_DREN);
446 writel(temp, sport->port.membase + UCR4);
447
448 temp = readl(sport->port.membase + UCR1);
449 temp &= ~(UCR1_RRDYEN);
450 writel(temp, sport->port.membase + UCR1);
451 }
452
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
455
456 if (USE_IRDA(sport)) {
457 temp = readl(sport->port.membase + UCR1);
458 temp |= UCR1_TRDYEN;
459 writel(temp, sport->port.membase + UCR1);
460
461 temp = readl(sport->port.membase + UCR4);
462 temp |= UCR4_TCEN;
463 writel(temp, sport->port.membase + UCR4);
464 }
465
466 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
467 imx_transmit_buffer(sport);
468 }
469
470 static irqreturn_t imx_rtsint(int irq, void *dev_id)
471 {
472 struct imx_port *sport = dev_id;
473 unsigned int val;
474 unsigned long flags;
475
476 spin_lock_irqsave(&sport->port.lock, flags);
477
478 writel(USR1_RTSD, sport->port.membase + USR1);
479 val = readl(sport->port.membase + USR1) & USR1_RTSS;
480 uart_handle_cts_change(&sport->port, !!val);
481 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
482
483 spin_unlock_irqrestore(&sport->port.lock, flags);
484 return IRQ_HANDLED;
485 }
486
487 static irqreturn_t imx_txint(int irq, void *dev_id)
488 {
489 struct imx_port *sport = dev_id;
490 struct circ_buf *xmit = &sport->port.state->xmit;
491 unsigned long flags;
492
493 spin_lock_irqsave(&sport->port.lock, flags);
494 if (sport->port.x_char) {
495 /* Send next char */
496 writel(sport->port.x_char, sport->port.membase + URTX0);
497 goto out;
498 }
499
500 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
501 imx_stop_tx(&sport->port);
502 goto out;
503 }
504
505 imx_transmit_buffer(sport);
506
507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
508 uart_write_wakeup(&sport->port);
509
510 out:
511 spin_unlock_irqrestore(&sport->port.lock, flags);
512 return IRQ_HANDLED;
513 }
514
515 static irqreturn_t imx_rxint(int irq, void *dev_id)
516 {
517 struct imx_port *sport = dev_id;
518 unsigned int rx, flg, ignored = 0;
519 struct tty_port *port = &sport->port.state->port;
520 unsigned long flags, temp;
521
522 spin_lock_irqsave(&sport->port.lock, flags);
523
524 while (readl(sport->port.membase + USR2) & USR2_RDR) {
525 flg = TTY_NORMAL;
526 sport->port.icount.rx++;
527
528 rx = readl(sport->port.membase + URXD0);
529
530 temp = readl(sport->port.membase + USR2);
531 if (temp & USR2_BRCD) {
532 writel(USR2_BRCD, sport->port.membase + USR2);
533 if (uart_handle_break(&sport->port))
534 continue;
535 }
536
537 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
538 continue;
539
540 if (unlikely(rx & URXD_ERR)) {
541 if (rx & URXD_BRK)
542 sport->port.icount.brk++;
543 else if (rx & URXD_PRERR)
544 sport->port.icount.parity++;
545 else if (rx & URXD_FRMERR)
546 sport->port.icount.frame++;
547 if (rx & URXD_OVRRUN)
548 sport->port.icount.overrun++;
549
550 if (rx & sport->port.ignore_status_mask) {
551 if (++ignored > 100)
552 goto out;
553 continue;
554 }
555
556 rx &= sport->port.read_status_mask;
557
558 if (rx & URXD_BRK)
559 flg = TTY_BREAK;
560 else if (rx & URXD_PRERR)
561 flg = TTY_PARITY;
562 else if (rx & URXD_FRMERR)
563 flg = TTY_FRAME;
564 if (rx & URXD_OVRRUN)
565 flg = TTY_OVERRUN;
566
567 #ifdef SUPPORT_SYSRQ
568 sport->port.sysrq = 0;
569 #endif
570 }
571
572 tty_insert_flip_char(port, rx, flg);
573 }
574
575 out:
576 spin_unlock_irqrestore(&sport->port.lock, flags);
577 tty_flip_buffer_push(port);
578 return IRQ_HANDLED;
579 }
580
581 static irqreturn_t imx_int(int irq, void *dev_id)
582 {
583 struct imx_port *sport = dev_id;
584 unsigned int sts;
585
586 sts = readl(sport->port.membase + USR1);
587
588 if (sts & USR1_RRDY)
589 imx_rxint(irq, dev_id);
590
591 if (sts & USR1_TRDY &&
592 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
593 imx_txint(irq, dev_id);
594
595 if (sts & USR1_RTSD)
596 imx_rtsint(irq, dev_id);
597
598 if (sts & USR1_AWAKE)
599 writel(USR1_AWAKE, sport->port.membase + USR1);
600
601 return IRQ_HANDLED;
602 }
603
604 /*
605 * Return TIOCSER_TEMT when transmitter is not busy.
606 */
607 static unsigned int imx_tx_empty(struct uart_port *port)
608 {
609 struct imx_port *sport = (struct imx_port *)port;
610
611 return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
612 }
613
614 /*
615 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
616 */
617 static unsigned int imx_get_mctrl(struct uart_port *port)
618 {
619 struct imx_port *sport = (struct imx_port *)port;
620 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
621
622 if (readl(sport->port.membase + USR1) & USR1_RTSS)
623 tmp |= TIOCM_CTS;
624
625 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
626 tmp |= TIOCM_RTS;
627
628 return tmp;
629 }
630
631 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
632 {
633 struct imx_port *sport = (struct imx_port *)port;
634 unsigned long temp;
635
636 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
637
638 if (mctrl & TIOCM_RTS)
639 temp |= UCR2_CTS;
640
641 writel(temp, sport->port.membase + UCR2);
642 }
643
644 /*
645 * Interrupts always disabled.
646 */
647 static void imx_break_ctl(struct uart_port *port, int break_state)
648 {
649 struct imx_port *sport = (struct imx_port *)port;
650 unsigned long flags, temp;
651
652 spin_lock_irqsave(&sport->port.lock, flags);
653
654 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
655
656 if (break_state != 0)
657 temp |= UCR1_SNDBRK;
658
659 writel(temp, sport->port.membase + UCR1);
660
661 spin_unlock_irqrestore(&sport->port.lock, flags);
662 }
663
664 #define TXTL 2 /* reset default */
665 #define RXTL 1 /* reset default */
666
667 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
668 {
669 unsigned int val;
670
671 /* set receiver / transmitter trigger level */
672 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
673 val |= TXTL << UFCR_TXTL_SHF | RXTL;
674 writel(val, sport->port.membase + UFCR);
675 return 0;
676 }
677
678 /* half the RX buffer size */
679 #define CTSTL 16
680
681 static int imx_startup(struct uart_port *port)
682 {
683 struct imx_port *sport = (struct imx_port *)port;
684 int retval;
685 unsigned long flags, temp;
686
687 imx_setup_ufcr(sport, 0);
688
689 /* disable the DREN bit (Data Ready interrupt enable) before
690 * requesting IRQs
691 */
692 temp = readl(sport->port.membase + UCR4);
693
694 if (USE_IRDA(sport))
695 temp |= UCR4_IRSC;
696
697 /* set the trigger level for CTS */
698 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
699 temp |= CTSTL << UCR4_CTSTL_SHF;
700
701 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
702
703 if (USE_IRDA(sport)) {
704 /* reset fifo's and state machines */
705 int i = 100;
706 temp = readl(sport->port.membase + UCR2);
707 temp &= ~UCR2_SRST;
708 writel(temp, sport->port.membase + UCR2);
709 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
710 (--i > 0)) {
711 udelay(1);
712 }
713 }
714
715 /*
716 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
717 * chips only have one interrupt.
718 */
719 if (sport->txirq > 0) {
720 retval = request_irq(sport->rxirq, imx_rxint, 0,
721 DRIVER_NAME, sport);
722 if (retval)
723 goto error_out1;
724
725 retval = request_irq(sport->txirq, imx_txint, 0,
726 DRIVER_NAME, sport);
727 if (retval)
728 goto error_out2;
729
730 /* do not use RTS IRQ on IrDA */
731 if (!USE_IRDA(sport)) {
732 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
733 DRIVER_NAME, sport);
734 if (retval)
735 goto error_out3;
736 }
737 } else {
738 retval = request_irq(sport->port.irq, imx_int, 0,
739 DRIVER_NAME, sport);
740 if (retval) {
741 free_irq(sport->port.irq, sport);
742 goto error_out1;
743 }
744 }
745
746 spin_lock_irqsave(&sport->port.lock, flags);
747 /*
748 * Finally, clear and enable interrupts
749 */
750 writel(USR1_RTSD, sport->port.membase + USR1);
751
752 temp = readl(sport->port.membase + UCR1);
753 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
754
755 if (USE_IRDA(sport)) {
756 temp |= UCR1_IREN;
757 temp &= ~(UCR1_RTSDEN);
758 }
759
760 writel(temp, sport->port.membase + UCR1);
761
762 temp = readl(sport->port.membase + UCR2);
763 temp |= (UCR2_RXEN | UCR2_TXEN);
764 if (!sport->have_rtscts)
765 temp |= UCR2_IRTS;
766 writel(temp, sport->port.membase + UCR2);
767
768 if (USE_IRDA(sport)) {
769 /* clear RX-FIFO */
770 int i = 64;
771 while ((--i > 0) &&
772 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
773 barrier();
774 }
775 }
776
777 if (is_imx21_uart(sport)) {
778 temp = readl(sport->port.membase + UCR3);
779 temp |= IMX21_UCR3_RXDMUXSEL;
780 writel(temp, sport->port.membase + UCR3);
781 }
782
783 if (USE_IRDA(sport)) {
784 temp = readl(sport->port.membase + UCR4);
785 if (sport->irda_inv_rx)
786 temp |= UCR4_INVR;
787 else
788 temp &= ~(UCR4_INVR);
789 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
790
791 temp = readl(sport->port.membase + UCR3);
792 if (sport->irda_inv_tx)
793 temp |= UCR3_INVT;
794 else
795 temp &= ~(UCR3_INVT);
796 writel(temp, sport->port.membase + UCR3);
797 }
798
799 /*
800 * Enable modem status interrupts
801 */
802 imx_enable_ms(&sport->port);
803 spin_unlock_irqrestore(&sport->port.lock, flags);
804
805 if (USE_IRDA(sport)) {
806 struct imxuart_platform_data *pdata;
807 pdata = sport->port.dev->platform_data;
808 sport->irda_inv_rx = pdata->irda_inv_rx;
809 sport->irda_inv_tx = pdata->irda_inv_tx;
810 sport->trcv_delay = pdata->transceiver_delay;
811 if (pdata->irda_enable)
812 pdata->irda_enable(1);
813 }
814
815 return 0;
816
817 error_out3:
818 if (sport->txirq)
819 free_irq(sport->txirq, sport);
820 error_out2:
821 if (sport->rxirq)
822 free_irq(sport->rxirq, sport);
823 error_out1:
824 return retval;
825 }
826
827 static void imx_shutdown(struct uart_port *port)
828 {
829 struct imx_port *sport = (struct imx_port *)port;
830 unsigned long temp;
831 unsigned long flags;
832
833 spin_lock_irqsave(&sport->port.lock, flags);
834 temp = readl(sport->port.membase + UCR2);
835 temp &= ~(UCR2_TXEN);
836 writel(temp, sport->port.membase + UCR2);
837 spin_unlock_irqrestore(&sport->port.lock, flags);
838
839 if (USE_IRDA(sport)) {
840 struct imxuart_platform_data *pdata;
841 pdata = sport->port.dev->platform_data;
842 if (pdata->irda_enable)
843 pdata->irda_enable(0);
844 }
845
846 /*
847 * Stop our timer.
848 */
849 del_timer_sync(&sport->timer);
850
851 /*
852 * Free the interrupts
853 */
854 if (sport->txirq > 0) {
855 if (!USE_IRDA(sport))
856 free_irq(sport->rtsirq, sport);
857 free_irq(sport->txirq, sport);
858 free_irq(sport->rxirq, sport);
859 } else
860 free_irq(sport->port.irq, sport);
861
862 /*
863 * Disable all interrupts, port and break condition.
864 */
865
866 spin_lock_irqsave(&sport->port.lock, flags);
867 temp = readl(sport->port.membase + UCR1);
868 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
869 if (USE_IRDA(sport))
870 temp &= ~(UCR1_IREN);
871
872 writel(temp, sport->port.membase + UCR1);
873 spin_unlock_irqrestore(&sport->port.lock, flags);
874 }
875
876 static void
877 imx_set_termios(struct uart_port *port, struct ktermios *termios,
878 struct ktermios *old)
879 {
880 struct imx_port *sport = (struct imx_port *)port;
881 unsigned long flags;
882 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
883 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
884 unsigned int div, ufcr;
885 unsigned long num, denom;
886 uint64_t tdiv64;
887
888 /*
889 * If we don't support modem control lines, don't allow
890 * these to be set.
891 */
892 if (0) {
893 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
894 termios->c_cflag |= CLOCAL;
895 }
896
897 /*
898 * We only support CS7 and CS8.
899 */
900 while ((termios->c_cflag & CSIZE) != CS7 &&
901 (termios->c_cflag & CSIZE) != CS8) {
902 termios->c_cflag &= ~CSIZE;
903 termios->c_cflag |= old_csize;
904 old_csize = CS8;
905 }
906
907 if ((termios->c_cflag & CSIZE) == CS8)
908 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
909 else
910 ucr2 = UCR2_SRST | UCR2_IRTS;
911
912 if (termios->c_cflag & CRTSCTS) {
913 if (sport->have_rtscts) {
914 ucr2 &= ~UCR2_IRTS;
915 ucr2 |= UCR2_CTSC;
916 } else {
917 termios->c_cflag &= ~CRTSCTS;
918 }
919 }
920
921 if (termios->c_cflag & CSTOPB)
922 ucr2 |= UCR2_STPB;
923 if (termios->c_cflag & PARENB) {
924 ucr2 |= UCR2_PREN;
925 if (termios->c_cflag & PARODD)
926 ucr2 |= UCR2_PROE;
927 }
928
929 del_timer_sync(&sport->timer);
930
931 /*
932 * Ask the core to calculate the divisor for us.
933 */
934 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
935 quot = uart_get_divisor(port, baud);
936
937 spin_lock_irqsave(&sport->port.lock, flags);
938
939 sport->port.read_status_mask = 0;
940 if (termios->c_iflag & INPCK)
941 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
942 if (termios->c_iflag & (BRKINT | PARMRK))
943 sport->port.read_status_mask |= URXD_BRK;
944
945 /*
946 * Characters to ignore
947 */
948 sport->port.ignore_status_mask = 0;
949 if (termios->c_iflag & IGNPAR)
950 sport->port.ignore_status_mask |= URXD_PRERR;
951 if (termios->c_iflag & IGNBRK) {
952 sport->port.ignore_status_mask |= URXD_BRK;
953 /*
954 * If we're ignoring parity and break indicators,
955 * ignore overruns too (for real raw support).
956 */
957 if (termios->c_iflag & IGNPAR)
958 sport->port.ignore_status_mask |= URXD_OVRRUN;
959 }
960
961 /*
962 * Update the per-port timeout.
963 */
964 uart_update_timeout(port, termios->c_cflag, baud);
965
966 /*
967 * disable interrupts and drain transmitter
968 */
969 old_ucr1 = readl(sport->port.membase + UCR1);
970 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
971 sport->port.membase + UCR1);
972
973 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
974 barrier();
975
976 /* then, disable everything */
977 old_txrxen = readl(sport->port.membase + UCR2);
978 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
979 sport->port.membase + UCR2);
980 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
981
982 if (USE_IRDA(sport)) {
983 /*
984 * use maximum available submodule frequency to
985 * avoid missing short pulses due to low sampling rate
986 */
987 div = 1;
988 } else {
989 div = sport->port.uartclk / (baud * 16);
990 if (div > 7)
991 div = 7;
992 if (!div)
993 div = 1;
994 }
995
996 rational_best_approximation(16 * div * baud, sport->port.uartclk,
997 1 << 16, 1 << 16, &num, &denom);
998
999 tdiv64 = sport->port.uartclk;
1000 tdiv64 *= num;
1001 do_div(tdiv64, denom * 16 * div);
1002 tty_termios_encode_baud_rate(termios,
1003 (speed_t)tdiv64, (speed_t)tdiv64);
1004
1005 num -= 1;
1006 denom -= 1;
1007
1008 ufcr = readl(sport->port.membase + UFCR);
1009 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1010 writel(ufcr, sport->port.membase + UFCR);
1011
1012 writel(num, sport->port.membase + UBIR);
1013 writel(denom, sport->port.membase + UBMR);
1014
1015 if (is_imx21_uart(sport))
1016 writel(sport->port.uartclk / div / 1000,
1017 sport->port.membase + IMX21_ONEMS);
1018
1019 writel(old_ucr1, sport->port.membase + UCR1);
1020
1021 /* set the parity, stop bits and data size */
1022 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1023
1024 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1025 imx_enable_ms(&sport->port);
1026
1027 spin_unlock_irqrestore(&sport->port.lock, flags);
1028 }
1029
1030 static const char *imx_type(struct uart_port *port)
1031 {
1032 struct imx_port *sport = (struct imx_port *)port;
1033
1034 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1035 }
1036
1037 /*
1038 * Release the memory region(s) being used by 'port'.
1039 */
1040 static void imx_release_port(struct uart_port *port)
1041 {
1042 struct platform_device *pdev = to_platform_device(port->dev);
1043 struct resource *mmres;
1044
1045 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046 release_mem_region(mmres->start, resource_size(mmres));
1047 }
1048
1049 /*
1050 * Request the memory region(s) being used by 'port'.
1051 */
1052 static int imx_request_port(struct uart_port *port)
1053 {
1054 struct platform_device *pdev = to_platform_device(port->dev);
1055 struct resource *mmres;
1056 void *ret;
1057
1058 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1059 if (!mmres)
1060 return -ENODEV;
1061
1062 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1063
1064 return ret ? 0 : -EBUSY;
1065 }
1066
1067 /*
1068 * Configure/autoconfigure the port.
1069 */
1070 static void imx_config_port(struct uart_port *port, int flags)
1071 {
1072 struct imx_port *sport = (struct imx_port *)port;
1073
1074 if (flags & UART_CONFIG_TYPE &&
1075 imx_request_port(&sport->port) == 0)
1076 sport->port.type = PORT_IMX;
1077 }
1078
1079 /*
1080 * Verify the new serial_struct (for TIOCSSERIAL).
1081 * The only change we allow are to the flags and type, and
1082 * even then only between PORT_IMX and PORT_UNKNOWN
1083 */
1084 static int
1085 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1086 {
1087 struct imx_port *sport = (struct imx_port *)port;
1088 int ret = 0;
1089
1090 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1091 ret = -EINVAL;
1092 if (sport->port.irq != ser->irq)
1093 ret = -EINVAL;
1094 if (ser->io_type != UPIO_MEM)
1095 ret = -EINVAL;
1096 if (sport->port.uartclk / 16 != ser->baud_base)
1097 ret = -EINVAL;
1098 if ((void *)sport->port.mapbase != ser->iomem_base)
1099 ret = -EINVAL;
1100 if (sport->port.iobase != ser->port)
1101 ret = -EINVAL;
1102 if (ser->hub6 != 0)
1103 ret = -EINVAL;
1104 return ret;
1105 }
1106
1107 #if defined(CONFIG_CONSOLE_POLL)
1108 static int imx_poll_get_char(struct uart_port *port)
1109 {
1110 struct imx_port_ucrs old_ucr;
1111 unsigned int status;
1112 unsigned char c;
1113
1114 /* save control registers */
1115 imx_port_ucrs_save(port, &old_ucr);
1116
1117 /* disable interrupts */
1118 writel(UCR1_UARTEN, port->membase + UCR1);
1119 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1120 port->membase + UCR2);
1121 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1122 port->membase + UCR3);
1123
1124 /* poll */
1125 do {
1126 status = readl(port->membase + USR2);
1127 } while (~status & USR2_RDR);
1128
1129 /* read */
1130 c = readl(port->membase + URXD0);
1131
1132 /* restore control registers */
1133 imx_port_ucrs_restore(port, &old_ucr);
1134
1135 return c;
1136 }
1137
1138 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1139 {
1140 struct imx_port_ucrs old_ucr;
1141 unsigned int status;
1142
1143 /* save control registers */
1144 imx_port_ucrs_save(port, &old_ucr);
1145
1146 /* disable interrupts */
1147 writel(UCR1_UARTEN, port->membase + UCR1);
1148 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1149 port->membase + UCR2);
1150 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1151 port->membase + UCR3);
1152
1153 /* drain */
1154 do {
1155 status = readl(port->membase + USR1);
1156 } while (~status & USR1_TRDY);
1157
1158 /* write */
1159 writel(c, port->membase + URTX0);
1160
1161 /* flush */
1162 do {
1163 status = readl(port->membase + USR2);
1164 } while (~status & USR2_TXDC);
1165
1166 /* restore control registers */
1167 imx_port_ucrs_restore(port, &old_ucr);
1168 }
1169 #endif
1170
1171 static struct uart_ops imx_pops = {
1172 .tx_empty = imx_tx_empty,
1173 .set_mctrl = imx_set_mctrl,
1174 .get_mctrl = imx_get_mctrl,
1175 .stop_tx = imx_stop_tx,
1176 .start_tx = imx_start_tx,
1177 .stop_rx = imx_stop_rx,
1178 .enable_ms = imx_enable_ms,
1179 .break_ctl = imx_break_ctl,
1180 .startup = imx_startup,
1181 .shutdown = imx_shutdown,
1182 .set_termios = imx_set_termios,
1183 .type = imx_type,
1184 .release_port = imx_release_port,
1185 .request_port = imx_request_port,
1186 .config_port = imx_config_port,
1187 .verify_port = imx_verify_port,
1188 #if defined(CONFIG_CONSOLE_POLL)
1189 .poll_get_char = imx_poll_get_char,
1190 .poll_put_char = imx_poll_put_char,
1191 #endif
1192 };
1193
1194 static struct imx_port *imx_ports[UART_NR];
1195
1196 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1197 static void imx_console_putchar(struct uart_port *port, int ch)
1198 {
1199 struct imx_port *sport = (struct imx_port *)port;
1200
1201 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1202 barrier();
1203
1204 writel(ch, sport->port.membase + URTX0);
1205 }
1206
1207 /*
1208 * Interrupts are disabled on entering
1209 */
1210 static void
1211 imx_console_write(struct console *co, const char *s, unsigned int count)
1212 {
1213 struct imx_port *sport = imx_ports[co->index];
1214 struct imx_port_ucrs old_ucr;
1215 unsigned int ucr1;
1216 unsigned long flags = 0;
1217 int locked = 1;
1218
1219 if (sport->port.sysrq)
1220 locked = 0;
1221 else if (oops_in_progress)
1222 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1223 else
1224 spin_lock_irqsave(&sport->port.lock, flags);
1225
1226 /*
1227 * First, save UCR1/2/3 and then disable interrupts
1228 */
1229 imx_port_ucrs_save(&sport->port, &old_ucr);
1230 ucr1 = old_ucr.ucr1;
1231
1232 if (is_imx1_uart(sport))
1233 ucr1 |= IMX1_UCR1_UARTCLKEN;
1234 ucr1 |= UCR1_UARTEN;
1235 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1236
1237 writel(ucr1, sport->port.membase + UCR1);
1238
1239 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1240
1241 uart_console_write(&sport->port, s, count, imx_console_putchar);
1242
1243 /*
1244 * Finally, wait for transmitter to become empty
1245 * and restore UCR1/2/3
1246 */
1247 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1248
1249 imx_port_ucrs_restore(&sport->port, &old_ucr);
1250
1251 if (locked)
1252 spin_unlock_irqrestore(&sport->port.lock, flags);
1253 }
1254
1255 /*
1256 * If the port was already initialised (eg, by a boot loader),
1257 * try to determine the current setup.
1258 */
1259 static void __init
1260 imx_console_get_options(struct imx_port *sport, int *baud,
1261 int *parity, int *bits)
1262 {
1263
1264 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1265 /* ok, the port was enabled */
1266 unsigned int ucr2, ubir, ubmr, uartclk;
1267 unsigned int baud_raw;
1268 unsigned int ucfr_rfdiv;
1269
1270 ucr2 = readl(sport->port.membase + UCR2);
1271
1272 *parity = 'n';
1273 if (ucr2 & UCR2_PREN) {
1274 if (ucr2 & UCR2_PROE)
1275 *parity = 'o';
1276 else
1277 *parity = 'e';
1278 }
1279
1280 if (ucr2 & UCR2_WS)
1281 *bits = 8;
1282 else
1283 *bits = 7;
1284
1285 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1286 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1287
1288 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1289 if (ucfr_rfdiv == 6)
1290 ucfr_rfdiv = 7;
1291 else
1292 ucfr_rfdiv = 6 - ucfr_rfdiv;
1293
1294 uartclk = clk_get_rate(sport->clk_per);
1295 uartclk /= ucfr_rfdiv;
1296
1297 { /*
1298 * The next code provides exact computation of
1299 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1300 * without need of float support or long long division,
1301 * which would be required to prevent 32bit arithmetic overflow
1302 */
1303 unsigned int mul = ubir + 1;
1304 unsigned int div = 16 * (ubmr + 1);
1305 unsigned int rem = uartclk % div;
1306
1307 baud_raw = (uartclk / div) * mul;
1308 baud_raw += (rem * mul + div / 2) / div;
1309 *baud = (baud_raw + 50) / 100 * 100;
1310 }
1311
1312 if (*baud != baud_raw)
1313 pr_info("Console IMX rounded baud rate from %d to %d\n",
1314 baud_raw, *baud);
1315 }
1316 }
1317
1318 static int __init
1319 imx_console_setup(struct console *co, char *options)
1320 {
1321 struct imx_port *sport;
1322 int baud = 9600;
1323 int bits = 8;
1324 int parity = 'n';
1325 int flow = 'n';
1326
1327 /*
1328 * Check whether an invalid uart number has been specified, and
1329 * if so, search for the first available port that does have
1330 * console support.
1331 */
1332 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1333 co->index = 0;
1334 sport = imx_ports[co->index];
1335 if (sport == NULL)
1336 return -ENODEV;
1337
1338 if (options)
1339 uart_parse_options(options, &baud, &parity, &bits, &flow);
1340 else
1341 imx_console_get_options(sport, &baud, &parity, &bits);
1342
1343 imx_setup_ufcr(sport, 0);
1344
1345 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1346 }
1347
1348 static struct uart_driver imx_reg;
1349 static struct console imx_console = {
1350 .name = DEV_NAME,
1351 .write = imx_console_write,
1352 .device = uart_console_device,
1353 .setup = imx_console_setup,
1354 .flags = CON_PRINTBUFFER,
1355 .index = -1,
1356 .data = &imx_reg,
1357 };
1358
1359 #define IMX_CONSOLE &imx_console
1360 #else
1361 #define IMX_CONSOLE NULL
1362 #endif
1363
1364 static struct uart_driver imx_reg = {
1365 .owner = THIS_MODULE,
1366 .driver_name = DRIVER_NAME,
1367 .dev_name = DEV_NAME,
1368 .major = SERIAL_IMX_MAJOR,
1369 .minor = MINOR_START,
1370 .nr = ARRAY_SIZE(imx_ports),
1371 .cons = IMX_CONSOLE,
1372 };
1373
1374 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1375 {
1376 struct imx_port *sport = platform_get_drvdata(dev);
1377 unsigned int val;
1378
1379 /* enable wakeup from i.MX UART */
1380 val = readl(sport->port.membase + UCR3);
1381 val |= UCR3_AWAKEN;
1382 writel(val, sport->port.membase + UCR3);
1383
1384 uart_suspend_port(&imx_reg, &sport->port);
1385
1386 return 0;
1387 }
1388
1389 static int serial_imx_resume(struct platform_device *dev)
1390 {
1391 struct imx_port *sport = platform_get_drvdata(dev);
1392 unsigned int val;
1393
1394 /* disable wakeup from i.MX UART */
1395 val = readl(sport->port.membase + UCR3);
1396 val &= ~UCR3_AWAKEN;
1397 writel(val, sport->port.membase + UCR3);
1398
1399 uart_resume_port(&imx_reg, &sport->port);
1400
1401 return 0;
1402 }
1403
1404 #ifdef CONFIG_OF
1405 /*
1406 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1407 * could successfully get all information from dt or a negative errno.
1408 */
1409 static int serial_imx_probe_dt(struct imx_port *sport,
1410 struct platform_device *pdev)
1411 {
1412 struct device_node *np = pdev->dev.of_node;
1413 const struct of_device_id *of_id =
1414 of_match_device(imx_uart_dt_ids, &pdev->dev);
1415 int ret;
1416
1417 if (!np)
1418 /* no device tree device */
1419 return 1;
1420
1421 ret = of_alias_get_id(np, "serial");
1422 if (ret < 0) {
1423 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1424 return ret;
1425 }
1426 sport->port.line = ret;
1427
1428 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1429 sport->have_rtscts = 1;
1430
1431 if (of_get_property(np, "fsl,irda-mode", NULL))
1432 sport->use_irda = 1;
1433
1434 sport->devdata = of_id->data;
1435
1436 return 0;
1437 }
1438 #else
1439 static inline int serial_imx_probe_dt(struct imx_port *sport,
1440 struct platform_device *pdev)
1441 {
1442 return 1;
1443 }
1444 #endif
1445
1446 static void serial_imx_probe_pdata(struct imx_port *sport,
1447 struct platform_device *pdev)
1448 {
1449 struct imxuart_platform_data *pdata = pdev->dev.platform_data;
1450
1451 sport->port.line = pdev->id;
1452 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1453
1454 if (!pdata)
1455 return;
1456
1457 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1458 sport->have_rtscts = 1;
1459
1460 if (pdata->flags & IMXUART_IRDA)
1461 sport->use_irda = 1;
1462 }
1463
1464 static int serial_imx_probe(struct platform_device *pdev)
1465 {
1466 struct imx_port *sport;
1467 struct imxuart_platform_data *pdata;
1468 void __iomem *base;
1469 int ret = 0;
1470 struct resource *res;
1471 struct pinctrl *pinctrl;
1472
1473 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1474 if (!sport)
1475 return -ENOMEM;
1476
1477 ret = serial_imx_probe_dt(sport, pdev);
1478 if (ret > 0)
1479 serial_imx_probe_pdata(sport, pdev);
1480 else if (ret < 0)
1481 return ret;
1482
1483 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1484 if (!res)
1485 return -ENODEV;
1486
1487 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1488 if (!base)
1489 return -ENOMEM;
1490
1491 sport->port.dev = &pdev->dev;
1492 sport->port.mapbase = res->start;
1493 sport->port.membase = base;
1494 sport->port.type = PORT_IMX,
1495 sport->port.iotype = UPIO_MEM;
1496 sport->port.irq = platform_get_irq(pdev, 0);
1497 sport->rxirq = platform_get_irq(pdev, 0);
1498 sport->txirq = platform_get_irq(pdev, 1);
1499 sport->rtsirq = platform_get_irq(pdev, 2);
1500 sport->port.fifosize = 32;
1501 sport->port.ops = &imx_pops;
1502 sport->port.flags = UPF_BOOT_AUTOCONF;
1503 init_timer(&sport->timer);
1504 sport->timer.function = imx_timeout;
1505 sport->timer.data = (unsigned long)sport;
1506
1507 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1508 if (IS_ERR(pinctrl)) {
1509 ret = PTR_ERR(pinctrl);
1510 dev_err(&pdev->dev, "failed to get default pinctrl: %d\n", ret);
1511 return ret;
1512 }
1513
1514 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1515 if (IS_ERR(sport->clk_ipg)) {
1516 ret = PTR_ERR(sport->clk_ipg);
1517 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1518 return ret;
1519 }
1520
1521 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1522 if (IS_ERR(sport->clk_per)) {
1523 ret = PTR_ERR(sport->clk_per);
1524 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1525 return ret;
1526 }
1527
1528 clk_prepare_enable(sport->clk_per);
1529 clk_prepare_enable(sport->clk_ipg);
1530
1531 sport->port.uartclk = clk_get_rate(sport->clk_per);
1532
1533 imx_ports[sport->port.line] = sport;
1534
1535 pdata = pdev->dev.platform_data;
1536 if (pdata && pdata->init) {
1537 ret = pdata->init(pdev);
1538 if (ret)
1539 goto clkput;
1540 }
1541
1542 ret = uart_add_one_port(&imx_reg, &sport->port);
1543 if (ret)
1544 goto deinit;
1545 platform_set_drvdata(pdev, sport);
1546
1547 return 0;
1548 deinit:
1549 if (pdata && pdata->exit)
1550 pdata->exit(pdev);
1551 clkput:
1552 clk_disable_unprepare(sport->clk_per);
1553 clk_disable_unprepare(sport->clk_ipg);
1554 return ret;
1555 }
1556
1557 static int serial_imx_remove(struct platform_device *pdev)
1558 {
1559 struct imxuart_platform_data *pdata;
1560 struct imx_port *sport = platform_get_drvdata(pdev);
1561
1562 pdata = pdev->dev.platform_data;
1563
1564 platform_set_drvdata(pdev, NULL);
1565
1566 uart_remove_one_port(&imx_reg, &sport->port);
1567
1568 clk_disable_unprepare(sport->clk_per);
1569 clk_disable_unprepare(sport->clk_ipg);
1570
1571 if (pdata && pdata->exit)
1572 pdata->exit(pdev);
1573
1574 return 0;
1575 }
1576
1577 static struct platform_driver serial_imx_driver = {
1578 .probe = serial_imx_probe,
1579 .remove = serial_imx_remove,
1580
1581 .suspend = serial_imx_suspend,
1582 .resume = serial_imx_resume,
1583 .id_table = imx_uart_devtype,
1584 .driver = {
1585 .name = "imx-uart",
1586 .owner = THIS_MODULE,
1587 .of_match_table = imx_uart_dt_ids,
1588 },
1589 };
1590
1591 static int __init imx_serial_init(void)
1592 {
1593 int ret;
1594
1595 pr_info("Serial: IMX driver\n");
1596
1597 ret = uart_register_driver(&imx_reg);
1598 if (ret)
1599 return ret;
1600
1601 ret = platform_driver_register(&serial_imx_driver);
1602 if (ret != 0)
1603 uart_unregister_driver(&imx_reg);
1604
1605 return ret;
1606 }
1607
1608 static void __exit imx_serial_exit(void)
1609 {
1610 platform_driver_unregister(&serial_imx_driver);
1611 uart_unregister_driver(&imx_reg);
1612 }
1613
1614 module_init(imx_serial_init);
1615 module_exit(imx_serial_exit);
1616
1617 MODULE_AUTHOR("Sascha Hauer");
1618 MODULE_DESCRIPTION("IMX generic serial port driver");
1619 MODULE_LICENSE("GPL");
1620 MODULE_ALIAS("platform:imx-uart");
kernel source for telekom puls (alcatel/mediatek)