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Linux 3.9-rc7
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / crisv10.c
1 /*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10 static char *serial_version = "$Revision: 1.25 $";
11
12 #include <linux/types.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/timer.h>
17 #include <linux/interrupt.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/major.h>
21 #include <linux/string.h>
22 #include <linux/fcntl.h>
23 #include <linux/mm.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/mutex.h>
28 #include <linux/bitops.h>
29 #include <linux/seq_file.h>
30 #include <linux/delay.h>
31 #include <linux/module.h>
32 #include <linux/uaccess.h>
33 #include <linux/io.h>
34
35 #include <asm/irq.h>
36 #include <asm/dma.h>
37
38 #include <arch/svinto.h>
39 #include <arch/system.h>
40
41 /* non-arch dependent serial structures are in linux/serial.h */
42 #include <linux/serial.h>
43 /* while we keep our own stuff (struct e100_serial) in a local .h file */
44 #include "crisv10.h"
45 #include <asm/fasttimer.h>
46 #include <arch/io_interface_mux.h>
47
48 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49 #ifndef CONFIG_ETRAX_FAST_TIMER
50 #error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51 #endif
52 #endif
53
54 #if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56 #error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57 #endif
58
59 #if defined(CONFIG_ETRAX_RS485_ON_PA) && defined(CONFIG_ETRAX_RS485_ON_PORT_G)
60 #error "Disable either CONFIG_ETRAX_RS485_ON_PA or CONFIG_ETRAX_RS485_ON_PORT_G"
61 #endif
62
63 /*
64 * All of the compatibilty code so we can compile serial.c against
65 * older kernels is hidden in serial_compat.h
66 */
67 #if defined(LOCAL_HEADERS)
68 #include "serial_compat.h"
69 #endif
70
71 struct tty_driver *serial_driver;
72
73 /* number of characters left in xmit buffer before we ask for more */
74 #define WAKEUP_CHARS 256
75
76 //#define SERIAL_DEBUG_INTR
77 //#define SERIAL_DEBUG_OPEN
78 //#define SERIAL_DEBUG_FLOW
79 //#define SERIAL_DEBUG_DATA
80 //#define SERIAL_DEBUG_THROTTLE
81 //#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
82 //#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
83
84 /* Enable this to use serial interrupts to handle when you
85 expect the first received event on the serial port to
86 be an error, break or similar. Used to be able to flash IRMA
87 from eLinux */
88 #define SERIAL_HANDLE_EARLY_ERRORS
89
90 /* Currently 16 descriptors x 128 bytes = 2048 bytes */
91 #define SERIAL_DESCR_BUF_SIZE 256
92
93 #define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
94 #define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
95
96 /* We don't want to load the system with massive fast timer interrupt
97 * on high baudrates so limit it to 250 us (4kHz) */
98 #define MIN_FLUSH_TIME_USEC 250
99
100 /* Add an x here to log a lot of timer stuff */
101 #define TIMERD(x)
102 /* Debug details of interrupt handling */
103 #define DINTR1(x) /* irq on/off, errors */
104 #define DINTR2(x) /* tx and rx */
105 /* Debug flip buffer stuff */
106 #define DFLIP(x)
107 /* Debug flow control and overview of data flow */
108 #define DFLOW(x)
109 #define DBAUD(x)
110 #define DLOG_INT_TRIG(x)
111
112 //#define DEBUG_LOG_INCLUDED
113 #ifndef DEBUG_LOG_INCLUDED
114 #define DEBUG_LOG(line, string, value)
115 #else
116 struct debug_log_info
117 {
118 unsigned long time;
119 unsigned long timer_data;
120 // int line;
121 const char *string;
122 int value;
123 };
124 #define DEBUG_LOG_SIZE 4096
125
126 struct debug_log_info debug_log[DEBUG_LOG_SIZE];
127 int debug_log_pos = 0;
128
129 #define DEBUG_LOG(_line, _string, _value) do { \
130 if ((_line) == SERIAL_DEBUG_LINE) {\
131 debug_log_func(_line, _string, _value); \
132 }\
133 }while(0)
134
135 void debug_log_func(int line, const char *string, int value)
136 {
137 if (debug_log_pos < DEBUG_LOG_SIZE) {
138 debug_log[debug_log_pos].time = jiffies;
139 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
140 // debug_log[debug_log_pos].line = line;
141 debug_log[debug_log_pos].string = string;
142 debug_log[debug_log_pos].value = value;
143 debug_log_pos++;
144 }
145 /*printk(string, value);*/
146 }
147 #endif
148
149 #ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
150 /* Default number of timer ticks before flushing rx fifo
151 * When using "little data, low latency applications: use 0
152 * When using "much data applications (PPP)" use ~5
153 */
154 #define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
155 #endif
156
157 unsigned long timer_data_to_ns(unsigned long timer_data);
158
159 static void change_speed(struct e100_serial *info);
160 static void rs_throttle(struct tty_struct * tty);
161 static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
162 static int rs_write(struct tty_struct *tty,
163 const unsigned char *buf, int count);
164 #ifdef CONFIG_ETRAX_RS485
165 static int e100_write_rs485(struct tty_struct *tty,
166 const unsigned char *buf, int count);
167 #endif
168 static int get_lsr_info(struct e100_serial *info, unsigned int *value);
169
170
171 #define DEF_BAUD 115200 /* 115.2 kbit/s */
172 #define STD_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
173 #define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
174 /* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
175 #define DEF_TX 0x80 /* or SERIAL_CTRL_B */
176
177 /* offsets from R_SERIALx_CTRL */
178
179 #define REG_DATA 0
180 #define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
181 #define REG_TR_DATA 0
182 #define REG_STATUS 1
183 #define REG_TR_CTRL 1
184 #define REG_REC_CTRL 2
185 #define REG_BAUD 3
186 #define REG_XOFF 4 /* this is a 32 bit register */
187
188 /* The bitfields are the same for all serial ports */
189 #define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
190 #define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
191 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
192 #define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
193 #define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
194
195 #define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
196
197 /* Values for info->errorcode */
198 #define ERRCODE_SET_BREAK (TTY_BREAK)
199 #define ERRCODE_INSERT 0x100
200 #define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
201
202 #define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
203
204 /*
205 * General note regarding the use of IO_* macros in this file:
206 *
207 * We will use the bits defined for DMA channel 6 when using various
208 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
209 * the same for all channels (which of course they are).
210 *
211 * We will also use the bits defined for serial port 0 when writing commands
212 * to the different ports, as these bits too are the same for all ports.
213 */
214
215
216 /* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
217 static const unsigned long e100_ser_int_mask = 0
218 #ifdef CONFIG_ETRAX_SERIAL_PORT0
219 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
220 #endif
221 #ifdef CONFIG_ETRAX_SERIAL_PORT1
222 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
223 #endif
224 #ifdef CONFIG_ETRAX_SERIAL_PORT2
225 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
226 #endif
227 #ifdef CONFIG_ETRAX_SERIAL_PORT3
228 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
229 #endif
230 ;
231 unsigned long r_alt_ser_baudrate_shadow = 0;
232
233 /* this is the data for the four serial ports in the etrax100 */
234 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
235 /* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
236
237 static struct e100_serial rs_table[] = {
238 { .baud = DEF_BAUD,
239 .ioport = (unsigned char *)R_SERIAL0_CTRL,
240 .irq = 1U << 12, /* uses DMA 6 and 7 */
241 .oclrintradr = R_DMA_CH6_CLR_INTR,
242 .ofirstadr = R_DMA_CH6_FIRST,
243 .ocmdadr = R_DMA_CH6_CMD,
244 .ostatusadr = R_DMA_CH6_STATUS,
245 .iclrintradr = R_DMA_CH7_CLR_INTR,
246 .ifirstadr = R_DMA_CH7_FIRST,
247 .icmdadr = R_DMA_CH7_CMD,
248 .idescradr = R_DMA_CH7_DESCR,
249 .flags = STD_FLAGS,
250 .rx_ctrl = DEF_RX,
251 .tx_ctrl = DEF_TX,
252 .iseteop = 2,
253 .dma_owner = dma_ser0,
254 .io_if = if_serial_0,
255 #ifdef CONFIG_ETRAX_SERIAL_PORT0
256 .enabled = 1,
257 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
258 .dma_out_enabled = 1,
259 .dma_out_nbr = SER0_TX_DMA_NBR,
260 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
261 .dma_out_irq_flags = 0,
262 .dma_out_irq_description = "serial 0 dma tr",
263 #else
264 .dma_out_enabled = 0,
265 .dma_out_nbr = UINT_MAX,
266 .dma_out_irq_nbr = 0,
267 .dma_out_irq_flags = 0,
268 .dma_out_irq_description = NULL,
269 #endif
270 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
271 .dma_in_enabled = 1,
272 .dma_in_nbr = SER0_RX_DMA_NBR,
273 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
274 .dma_in_irq_flags = 0,
275 .dma_in_irq_description = "serial 0 dma rec",
276 #else
277 .dma_in_enabled = 0,
278 .dma_in_nbr = UINT_MAX,
279 .dma_in_irq_nbr = 0,
280 .dma_in_irq_flags = 0,
281 .dma_in_irq_description = NULL,
282 #endif
283 #else
284 .enabled = 0,
285 .io_if_description = NULL,
286 .dma_out_enabled = 0,
287 .dma_in_enabled = 0
288 #endif
289
290 }, /* ttyS0 */
291 #ifndef CONFIG_SVINTO_SIM
292 { .baud = DEF_BAUD,
293 .ioport = (unsigned char *)R_SERIAL1_CTRL,
294 .irq = 1U << 16, /* uses DMA 8 and 9 */
295 .oclrintradr = R_DMA_CH8_CLR_INTR,
296 .ofirstadr = R_DMA_CH8_FIRST,
297 .ocmdadr = R_DMA_CH8_CMD,
298 .ostatusadr = R_DMA_CH8_STATUS,
299 .iclrintradr = R_DMA_CH9_CLR_INTR,
300 .ifirstadr = R_DMA_CH9_FIRST,
301 .icmdadr = R_DMA_CH9_CMD,
302 .idescradr = R_DMA_CH9_DESCR,
303 .flags = STD_FLAGS,
304 .rx_ctrl = DEF_RX,
305 .tx_ctrl = DEF_TX,
306 .iseteop = 3,
307 .dma_owner = dma_ser1,
308 .io_if = if_serial_1,
309 #ifdef CONFIG_ETRAX_SERIAL_PORT1
310 .enabled = 1,
311 .io_if_description = "ser1",
312 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
313 .dma_out_enabled = 1,
314 .dma_out_nbr = SER1_TX_DMA_NBR,
315 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
316 .dma_out_irq_flags = 0,
317 .dma_out_irq_description = "serial 1 dma tr",
318 #else
319 .dma_out_enabled = 0,
320 .dma_out_nbr = UINT_MAX,
321 .dma_out_irq_nbr = 0,
322 .dma_out_irq_flags = 0,
323 .dma_out_irq_description = NULL,
324 #endif
325 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
326 .dma_in_enabled = 1,
327 .dma_in_nbr = SER1_RX_DMA_NBR,
328 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
329 .dma_in_irq_flags = 0,
330 .dma_in_irq_description = "serial 1 dma rec",
331 #else
332 .dma_in_enabled = 0,
333 .dma_in_enabled = 0,
334 .dma_in_nbr = UINT_MAX,
335 .dma_in_irq_nbr = 0,
336 .dma_in_irq_flags = 0,
337 .dma_in_irq_description = NULL,
338 #endif
339 #else
340 .enabled = 0,
341 .io_if_description = NULL,
342 .dma_in_irq_nbr = 0,
343 .dma_out_enabled = 0,
344 .dma_in_enabled = 0
345 #endif
346 }, /* ttyS1 */
347
348 { .baud = DEF_BAUD,
349 .ioport = (unsigned char *)R_SERIAL2_CTRL,
350 .irq = 1U << 4, /* uses DMA 2 and 3 */
351 .oclrintradr = R_DMA_CH2_CLR_INTR,
352 .ofirstadr = R_DMA_CH2_FIRST,
353 .ocmdadr = R_DMA_CH2_CMD,
354 .ostatusadr = R_DMA_CH2_STATUS,
355 .iclrintradr = R_DMA_CH3_CLR_INTR,
356 .ifirstadr = R_DMA_CH3_FIRST,
357 .icmdadr = R_DMA_CH3_CMD,
358 .idescradr = R_DMA_CH3_DESCR,
359 .flags = STD_FLAGS,
360 .rx_ctrl = DEF_RX,
361 .tx_ctrl = DEF_TX,
362 .iseteop = 0,
363 .dma_owner = dma_ser2,
364 .io_if = if_serial_2,
365 #ifdef CONFIG_ETRAX_SERIAL_PORT2
366 .enabled = 1,
367 .io_if_description = "ser2",
368 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
369 .dma_out_enabled = 1,
370 .dma_out_nbr = SER2_TX_DMA_NBR,
371 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
372 .dma_out_irq_flags = 0,
373 .dma_out_irq_description = "serial 2 dma tr",
374 #else
375 .dma_out_enabled = 0,
376 .dma_out_nbr = UINT_MAX,
377 .dma_out_irq_nbr = 0,
378 .dma_out_irq_flags = 0,
379 .dma_out_irq_description = NULL,
380 #endif
381 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
382 .dma_in_enabled = 1,
383 .dma_in_nbr = SER2_RX_DMA_NBR,
384 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
385 .dma_in_irq_flags = 0,
386 .dma_in_irq_description = "serial 2 dma rec",
387 #else
388 .dma_in_enabled = 0,
389 .dma_in_nbr = UINT_MAX,
390 .dma_in_irq_nbr = 0,
391 .dma_in_irq_flags = 0,
392 .dma_in_irq_description = NULL,
393 #endif
394 #else
395 .enabled = 0,
396 .io_if_description = NULL,
397 .dma_out_enabled = 0,
398 .dma_in_enabled = 0
399 #endif
400 }, /* ttyS2 */
401
402 { .baud = DEF_BAUD,
403 .ioport = (unsigned char *)R_SERIAL3_CTRL,
404 .irq = 1U << 8, /* uses DMA 4 and 5 */
405 .oclrintradr = R_DMA_CH4_CLR_INTR,
406 .ofirstadr = R_DMA_CH4_FIRST,
407 .ocmdadr = R_DMA_CH4_CMD,
408 .ostatusadr = R_DMA_CH4_STATUS,
409 .iclrintradr = R_DMA_CH5_CLR_INTR,
410 .ifirstadr = R_DMA_CH5_FIRST,
411 .icmdadr = R_DMA_CH5_CMD,
412 .idescradr = R_DMA_CH5_DESCR,
413 .flags = STD_FLAGS,
414 .rx_ctrl = DEF_RX,
415 .tx_ctrl = DEF_TX,
416 .iseteop = 1,
417 .dma_owner = dma_ser3,
418 .io_if = if_serial_3,
419 #ifdef CONFIG_ETRAX_SERIAL_PORT3
420 .enabled = 1,
421 .io_if_description = "ser3",
422 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
423 .dma_out_enabled = 1,
424 .dma_out_nbr = SER3_TX_DMA_NBR,
425 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
426 .dma_out_irq_flags = 0,
427 .dma_out_irq_description = "serial 3 dma tr",
428 #else
429 .dma_out_enabled = 0,
430 .dma_out_nbr = UINT_MAX,
431 .dma_out_irq_nbr = 0,
432 .dma_out_irq_flags = 0,
433 .dma_out_irq_description = NULL,
434 #endif
435 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
436 .dma_in_enabled = 1,
437 .dma_in_nbr = SER3_RX_DMA_NBR,
438 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
439 .dma_in_irq_flags = 0,
440 .dma_in_irq_description = "serial 3 dma rec",
441 #else
442 .dma_in_enabled = 0,
443 .dma_in_nbr = UINT_MAX,
444 .dma_in_irq_nbr = 0,
445 .dma_in_irq_flags = 0,
446 .dma_in_irq_description = NULL
447 #endif
448 #else
449 .enabled = 0,
450 .io_if_description = NULL,
451 .dma_out_enabled = 0,
452 .dma_in_enabled = 0
453 #endif
454 } /* ttyS3 */
455 #endif
456 };
457
458
459 #define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
460
461 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
462 static struct fast_timer fast_timers[NR_PORTS];
463 #endif
464
465 #ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
466 #define PROCSTAT(x) x
467 struct ser_statistics_type {
468 int overrun_cnt;
469 int early_errors_cnt;
470 int ser_ints_ok_cnt;
471 int errors_cnt;
472 unsigned long int processing_flip;
473 unsigned long processing_flip_still_room;
474 unsigned long int timeout_flush_cnt;
475 int rx_dma_ints;
476 int tx_dma_ints;
477 int rx_tot;
478 int tx_tot;
479 };
480
481 static struct ser_statistics_type ser_stat[NR_PORTS];
482
483 #else
484
485 #define PROCSTAT(x)
486
487 #endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
488
489 /* RS-485 */
490 #if defined(CONFIG_ETRAX_RS485)
491 #ifdef CONFIG_ETRAX_FAST_TIMER
492 static struct fast_timer fast_timers_rs485[NR_PORTS];
493 #endif
494 #if defined(CONFIG_ETRAX_RS485_ON_PA)
495 static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
496 #endif
497 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
498 static int rs485_port_g_bit = CONFIG_ETRAX_RS485_ON_PORT_G_BIT;
499 #endif
500 #endif
501
502 /* Info and macros needed for each ports extra control/status signals. */
503 #define E100_STRUCT_PORT(line, pinname) \
504 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
505 (R_PORT_PA_DATA): ( \
506 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
507 (R_PORT_PB_DATA):&dummy_ser[line]))
508
509 #define E100_STRUCT_SHADOW(line, pinname) \
510 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
511 (&port_pa_data_shadow): ( \
512 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
513 (&port_pb_data_shadow):&dummy_ser[line]))
514 #define E100_STRUCT_MASK(line, pinname) \
515 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
516 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
517 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
518 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
519
520 #define DUMMY_DTR_MASK 1
521 #define DUMMY_RI_MASK 2
522 #define DUMMY_DSR_MASK 4
523 #define DUMMY_CD_MASK 8
524 static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
525
526 /* If not all status pins are used or disabled, use mixed mode */
527 #ifdef CONFIG_ETRAX_SERIAL_PORT0
528
529 #define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
530
531 #if SER0_PA_BITSUM != -4
532 # if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
533 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
534 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
535 # endif
536 # endif
537 # if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
538 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
539 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
540 # endif
541 # endif
542 # if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
543 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
544 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
545 # endif
546 # endif
547 # if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
548 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
549 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
550 # endif
551 # endif
552 #endif
553
554 #define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
555
556 #if SER0_PB_BITSUM != -4
557 # if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
558 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
559 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
560 # endif
561 # endif
562 # if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
563 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
564 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
565 # endif
566 # endif
567 # if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
568 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
569 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
570 # endif
571 # endif
572 # if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
573 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
574 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
575 # endif
576 # endif
577 #endif
578
579 #endif /* PORT0 */
580
581
582 #ifdef CONFIG_ETRAX_SERIAL_PORT1
583
584 #define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
585
586 #if SER1_PA_BITSUM != -4
587 # if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
588 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
589 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
590 # endif
591 # endif
592 # if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
593 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
594 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
595 # endif
596 # endif
597 # if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
598 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
599 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
600 # endif
601 # endif
602 # if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
603 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
604 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
605 # endif
606 # endif
607 #endif
608
609 #define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
610
611 #if SER1_PB_BITSUM != -4
612 # if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
613 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
614 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
615 # endif
616 # endif
617 # if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
618 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
619 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
620 # endif
621 # endif
622 # if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
623 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
624 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
625 # endif
626 # endif
627 # if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
628 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
629 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
630 # endif
631 # endif
632 #endif
633
634 #endif /* PORT1 */
635
636 #ifdef CONFIG_ETRAX_SERIAL_PORT2
637
638 #define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
639
640 #if SER2_PA_BITSUM != -4
641 # if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
642 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
643 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
644 # endif
645 # endif
646 # if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
647 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
648 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
649 # endif
650 # endif
651 # if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
652 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
653 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
654 # endif
655 # endif
656 # if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
657 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
658 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
659 # endif
660 # endif
661 #endif
662
663 #define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
664
665 #if SER2_PB_BITSUM != -4
666 # if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
667 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
668 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
669 # endif
670 # endif
671 # if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
672 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
673 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
674 # endif
675 # endif
676 # if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
677 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
678 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
679 # endif
680 # endif
681 # if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
682 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
683 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
684 # endif
685 # endif
686 #endif
687
688 #endif /* PORT2 */
689
690 #ifdef CONFIG_ETRAX_SERIAL_PORT3
691
692 #define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
693
694 #if SER3_PA_BITSUM != -4
695 # if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
696 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
697 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
698 # endif
699 # endif
700 # if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
701 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
702 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
703 # endif
704 # endif
705 # if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
706 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
707 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
708 # endif
709 # endif
710 # if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
711 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
712 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
713 # endif
714 # endif
715 #endif
716
717 #define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
718
719 #if SER3_PB_BITSUM != -4
720 # if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
721 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
722 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
723 # endif
724 # endif
725 # if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
726 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
727 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
728 # endif
729 # endif
730 # if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
731 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
732 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
733 # endif
734 # endif
735 # if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
736 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
737 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
738 # endif
739 # endif
740 #endif
741
742 #endif /* PORT3 */
743
744
745 #if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
746 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
747 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
748 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
749 #define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
750 #endif
751
752 #ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
753 /* The pins can be mixed on PA and PB */
754 #define CONTROL_PINS_PORT_NOT_USED(line) \
755 &dummy_ser[line], &dummy_ser[line], \
756 &dummy_ser[line], &dummy_ser[line], \
757 &dummy_ser[line], &dummy_ser[line], \
758 &dummy_ser[line], &dummy_ser[line], \
759 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
760
761
762 struct control_pins
763 {
764 volatile unsigned char *dtr_port;
765 unsigned char *dtr_shadow;
766 volatile unsigned char *ri_port;
767 unsigned char *ri_shadow;
768 volatile unsigned char *dsr_port;
769 unsigned char *dsr_shadow;
770 volatile unsigned char *cd_port;
771 unsigned char *cd_shadow;
772
773 unsigned char dtr_mask;
774 unsigned char ri_mask;
775 unsigned char dsr_mask;
776 unsigned char cd_mask;
777 };
778
779 static const struct control_pins e100_modem_pins[NR_PORTS] =
780 {
781 /* Ser 0 */
782 {
783 #ifdef CONFIG_ETRAX_SERIAL_PORT0
784 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
785 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
786 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
787 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
788 E100_STRUCT_MASK(0,DTR),
789 E100_STRUCT_MASK(0,RI),
790 E100_STRUCT_MASK(0,DSR),
791 E100_STRUCT_MASK(0,CD)
792 #else
793 CONTROL_PINS_PORT_NOT_USED(0)
794 #endif
795 },
796
797 /* Ser 1 */
798 {
799 #ifdef CONFIG_ETRAX_SERIAL_PORT1
800 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
801 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
802 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
803 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
804 E100_STRUCT_MASK(1,DTR),
805 E100_STRUCT_MASK(1,RI),
806 E100_STRUCT_MASK(1,DSR),
807 E100_STRUCT_MASK(1,CD)
808 #else
809 CONTROL_PINS_PORT_NOT_USED(1)
810 #endif
811 },
812
813 /* Ser 2 */
814 {
815 #ifdef CONFIG_ETRAX_SERIAL_PORT2
816 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
817 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
818 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
819 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
820 E100_STRUCT_MASK(2,DTR),
821 E100_STRUCT_MASK(2,RI),
822 E100_STRUCT_MASK(2,DSR),
823 E100_STRUCT_MASK(2,CD)
824 #else
825 CONTROL_PINS_PORT_NOT_USED(2)
826 #endif
827 },
828
829 /* Ser 3 */
830 {
831 #ifdef CONFIG_ETRAX_SERIAL_PORT3
832 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
833 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
834 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
835 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
836 E100_STRUCT_MASK(3,DTR),
837 E100_STRUCT_MASK(3,RI),
838 E100_STRUCT_MASK(3,DSR),
839 E100_STRUCT_MASK(3,CD)
840 #else
841 CONTROL_PINS_PORT_NOT_USED(3)
842 #endif
843 }
844 };
845 #else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
846
847 /* All pins are on either PA or PB for each serial port */
848 #define CONTROL_PINS_PORT_NOT_USED(line) \
849 &dummy_ser[line], &dummy_ser[line], \
850 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
851
852
853 struct control_pins
854 {
855 volatile unsigned char *port;
856 unsigned char *shadow;
857
858 unsigned char dtr_mask;
859 unsigned char ri_mask;
860 unsigned char dsr_mask;
861 unsigned char cd_mask;
862 };
863
864 #define dtr_port port
865 #define dtr_shadow shadow
866 #define ri_port port
867 #define ri_shadow shadow
868 #define dsr_port port
869 #define dsr_shadow shadow
870 #define cd_port port
871 #define cd_shadow shadow
872
873 static const struct control_pins e100_modem_pins[NR_PORTS] =
874 {
875 /* Ser 0 */
876 {
877 #ifdef CONFIG_ETRAX_SERIAL_PORT0
878 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
879 E100_STRUCT_MASK(0,DTR),
880 E100_STRUCT_MASK(0,RI),
881 E100_STRUCT_MASK(0,DSR),
882 E100_STRUCT_MASK(0,CD)
883 #else
884 CONTROL_PINS_PORT_NOT_USED(0)
885 #endif
886 },
887
888 /* Ser 1 */
889 {
890 #ifdef CONFIG_ETRAX_SERIAL_PORT1
891 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
892 E100_STRUCT_MASK(1,DTR),
893 E100_STRUCT_MASK(1,RI),
894 E100_STRUCT_MASK(1,DSR),
895 E100_STRUCT_MASK(1,CD)
896 #else
897 CONTROL_PINS_PORT_NOT_USED(1)
898 #endif
899 },
900
901 /* Ser 2 */
902 {
903 #ifdef CONFIG_ETRAX_SERIAL_PORT2
904 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
905 E100_STRUCT_MASK(2,DTR),
906 E100_STRUCT_MASK(2,RI),
907 E100_STRUCT_MASK(2,DSR),
908 E100_STRUCT_MASK(2,CD)
909 #else
910 CONTROL_PINS_PORT_NOT_USED(2)
911 #endif
912 },
913
914 /* Ser 3 */
915 {
916 #ifdef CONFIG_ETRAX_SERIAL_PORT3
917 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
918 E100_STRUCT_MASK(3,DTR),
919 E100_STRUCT_MASK(3,RI),
920 E100_STRUCT_MASK(3,DSR),
921 E100_STRUCT_MASK(3,CD)
922 #else
923 CONTROL_PINS_PORT_NOT_USED(3)
924 #endif
925 }
926 };
927 #endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
928
929 #define E100_RTS_MASK 0x20
930 #define E100_CTS_MASK 0x40
931
932 /* All serial port signals are active low:
933 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
934 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
935 *
936 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
937 */
938
939 /* Output */
940 #define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
941 /* Input */
942 #define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
943
944 /* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
945 /* Is an output */
946 #define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
947
948 /* Normally inputs */
949 #define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
950 #define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
951
952 /* Input */
953 #define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
954
955 /* Calculate the chartime depending on baudrate, numbor of bits etc. */
956 static void update_char_time(struct e100_serial * info)
957 {
958 tcflag_t cflags = info->port.tty->termios.c_cflag;
959 int bits;
960
961 /* calc. number of bits / data byte */
962 /* databits + startbit and 1 stopbit */
963 if ((cflags & CSIZE) == CS7)
964 bits = 9;
965 else
966 bits = 10;
967
968 if (cflags & CSTOPB) /* 2 stopbits ? */
969 bits++;
970
971 if (cflags & PARENB) /* parity bit ? */
972 bits++;
973
974 /* calc timeout */
975 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
976 info->flush_time_usec = 4*info->char_time_usec;
977 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
978 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
979
980 }
981
982 /*
983 * This function maps from the Bxxxx defines in asm/termbits.h into real
984 * baud rates.
985 */
986
987 static int
988 cflag_to_baud(unsigned int cflag)
989 {
990 static int baud_table[] = {
991 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
992 4800, 9600, 19200, 38400 };
993
994 static int ext_baud_table[] = {
995 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
996 0, 0, 0, 0, 0, 0, 0, 0 };
997
998 if (cflag & CBAUDEX)
999 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1000 else
1001 return baud_table[cflag & CBAUD];
1002 }
1003
1004 /* and this maps to an etrax100 hardware baud constant */
1005
1006 static unsigned char
1007 cflag_to_etrax_baud(unsigned int cflag)
1008 {
1009 char retval;
1010
1011 static char baud_table[] = {
1012 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
1013
1014 static char ext_baud_table[] = {
1015 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1016
1017 if (cflag & CBAUDEX)
1018 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1019 else
1020 retval = baud_table[cflag & CBAUD];
1021
1022 if (retval < 0) {
1023 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1024 retval = 5; /* choose default 9600 instead */
1025 }
1026
1027 return retval | (retval << 4); /* choose same for both TX and RX */
1028 }
1029
1030
1031 /* Various static support functions */
1032
1033 /* Functions to set or clear DTR/RTS on the requested line */
1034 /* It is complicated by the fact that RTS is a serial port register, while
1035 * DTR might not be implemented in the HW at all, and if it is, it can be on
1036 * any general port.
1037 */
1038
1039
1040 static inline void
1041 e100_dtr(struct e100_serial *info, int set)
1042 {
1043 #ifndef CONFIG_SVINTO_SIM
1044 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1045
1046 #ifdef SERIAL_DEBUG_IO
1047 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1048 printk("ser%i shadow before 0x%02X get: %i\n",
1049 info->line, *e100_modem_pins[info->line].dtr_shadow,
1050 E100_DTR_GET(info));
1051 #endif
1052 /* DTR is active low */
1053 {
1054 unsigned long flags;
1055
1056 local_irq_save(flags);
1057 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1058 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1059 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1060 local_irq_restore(flags);
1061 }
1062
1063 #ifdef SERIAL_DEBUG_IO
1064 printk("ser%i shadow after 0x%02X get: %i\n",
1065 info->line, *e100_modem_pins[info->line].dtr_shadow,
1066 E100_DTR_GET(info));
1067 #endif
1068 #endif
1069 }
1070
1071 /* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1072 * 0=0V , 1=3.3V
1073 */
1074 static inline void
1075 e100_rts(struct e100_serial *info, int set)
1076 {
1077 #ifndef CONFIG_SVINTO_SIM
1078 unsigned long flags;
1079 local_irq_save(flags);
1080 info->rx_ctrl &= ~E100_RTS_MASK;
1081 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1082 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1083 local_irq_restore(flags);
1084 #ifdef SERIAL_DEBUG_IO
1085 printk("ser%i rts %i\n", info->line, set);
1086 #endif
1087 #endif
1088 }
1089
1090
1091 /* If this behaves as a modem, RI and CD is an output */
1092 static inline void
1093 e100_ri_out(struct e100_serial *info, int set)
1094 {
1095 #ifndef CONFIG_SVINTO_SIM
1096 /* RI is active low */
1097 {
1098 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1099 unsigned long flags;
1100
1101 local_irq_save(flags);
1102 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1103 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1104 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1105 local_irq_restore(flags);
1106 }
1107 #endif
1108 }
1109 static inline void
1110 e100_cd_out(struct e100_serial *info, int set)
1111 {
1112 #ifndef CONFIG_SVINTO_SIM
1113 /* CD is active low */
1114 {
1115 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1116 unsigned long flags;
1117
1118 local_irq_save(flags);
1119 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1120 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1121 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1122 local_irq_restore(flags);
1123 }
1124 #endif
1125 }
1126
1127 static inline void
1128 e100_disable_rx(struct e100_serial *info)
1129 {
1130 #ifndef CONFIG_SVINTO_SIM
1131 /* disable the receiver */
1132 info->ioport[REG_REC_CTRL] =
1133 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1134 #endif
1135 }
1136
1137 static inline void
1138 e100_enable_rx(struct e100_serial *info)
1139 {
1140 #ifndef CONFIG_SVINTO_SIM
1141 /* enable the receiver */
1142 info->ioport[REG_REC_CTRL] =
1143 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1144 #endif
1145 }
1146
1147 /* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1148
1149 static inline void
1150 e100_disable_rxdma_irq(struct e100_serial *info)
1151 {
1152 #ifdef SERIAL_DEBUG_INTR
1153 printk("rxdma_irq(%d): 0\n",info->line);
1154 #endif
1155 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1156 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1157 }
1158
1159 static inline void
1160 e100_enable_rxdma_irq(struct e100_serial *info)
1161 {
1162 #ifdef SERIAL_DEBUG_INTR
1163 printk("rxdma_irq(%d): 1\n",info->line);
1164 #endif
1165 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1166 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1167 }
1168
1169 /* the tx DMA uses only dma_descr interrupt */
1170
1171 static void e100_disable_txdma_irq(struct e100_serial *info)
1172 {
1173 #ifdef SERIAL_DEBUG_INTR
1174 printk("txdma_irq(%d): 0\n",info->line);
1175 #endif
1176 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1177 *R_IRQ_MASK2_CLR = info->irq;
1178 }
1179
1180 static void e100_enable_txdma_irq(struct e100_serial *info)
1181 {
1182 #ifdef SERIAL_DEBUG_INTR
1183 printk("txdma_irq(%d): 1\n",info->line);
1184 #endif
1185 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1186 *R_IRQ_MASK2_SET = info->irq;
1187 }
1188
1189 static void e100_disable_txdma_channel(struct e100_serial *info)
1190 {
1191 unsigned long flags;
1192
1193 /* Disable output DMA channel for the serial port in question
1194 * ( set to something other than serialX)
1195 */
1196 local_irq_save(flags);
1197 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1198 if (info->line == 0) {
1199 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1200 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1201 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1202 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1203 }
1204 } else if (info->line == 1) {
1205 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1206 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1207 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1208 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1209 }
1210 } else if (info->line == 2) {
1211 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1212 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1213 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1214 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1215 }
1216 } else if (info->line == 3) {
1217 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1218 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1219 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1220 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1221 }
1222 }
1223 *R_GEN_CONFIG = genconfig_shadow;
1224 local_irq_restore(flags);
1225 }
1226
1227
1228 static void e100_enable_txdma_channel(struct e100_serial *info)
1229 {
1230 unsigned long flags;
1231
1232 local_irq_save(flags);
1233 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1234 /* Enable output DMA channel for the serial port in question */
1235 if (info->line == 0) {
1236 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1237 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1238 } else if (info->line == 1) {
1239 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1240 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1241 } else if (info->line == 2) {
1242 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1243 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1244 } else if (info->line == 3) {
1245 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1246 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1247 }
1248 *R_GEN_CONFIG = genconfig_shadow;
1249 local_irq_restore(flags);
1250 }
1251
1252 static void e100_disable_rxdma_channel(struct e100_serial *info)
1253 {
1254 unsigned long flags;
1255
1256 /* Disable input DMA channel for the serial port in question
1257 * ( set to something other than serialX)
1258 */
1259 local_irq_save(flags);
1260 if (info->line == 0) {
1261 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1262 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1263 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1264 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1265 }
1266 } else if (info->line == 1) {
1267 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1268 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1269 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1270 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1271 }
1272 } else if (info->line == 2) {
1273 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1274 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1275 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1276 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1277 }
1278 } else if (info->line == 3) {
1279 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1280 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1281 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1282 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1283 }
1284 }
1285 *R_GEN_CONFIG = genconfig_shadow;
1286 local_irq_restore(flags);
1287 }
1288
1289
1290 static void e100_enable_rxdma_channel(struct e100_serial *info)
1291 {
1292 unsigned long flags;
1293
1294 local_irq_save(flags);
1295 /* Enable input DMA channel for the serial port in question */
1296 if (info->line == 0) {
1297 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1298 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1299 } else if (info->line == 1) {
1300 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1301 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1302 } else if (info->line == 2) {
1303 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1304 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1305 } else if (info->line == 3) {
1306 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1307 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1308 }
1309 *R_GEN_CONFIG = genconfig_shadow;
1310 local_irq_restore(flags);
1311 }
1312
1313 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1314 /* in order to detect and fix errors on the first byte
1315 we have to use the serial interrupts as well. */
1316
1317 static inline void
1318 e100_disable_serial_data_irq(struct e100_serial *info)
1319 {
1320 #ifdef SERIAL_DEBUG_INTR
1321 printk("ser_irq(%d): 0\n",info->line);
1322 #endif
1323 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1324 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1325 }
1326
1327 static inline void
1328 e100_enable_serial_data_irq(struct e100_serial *info)
1329 {
1330 #ifdef SERIAL_DEBUG_INTR
1331 printk("ser_irq(%d): 1\n",info->line);
1332 printk("**** %d = %d\n",
1333 (8+2*info->line),
1334 (1U << (8+2*info->line)));
1335 #endif
1336 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1337 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1338 }
1339 #endif
1340
1341 static inline void
1342 e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1343 {
1344 #ifdef SERIAL_DEBUG_INTR
1345 printk("ser_tx_irq(%d): 0\n",info->line);
1346 #endif
1347 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1348 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1349 }
1350
1351 static inline void
1352 e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1353 {
1354 #ifdef SERIAL_DEBUG_INTR
1355 printk("ser_tx_irq(%d): 1\n",info->line);
1356 printk("**** %d = %d\n",
1357 (8+1+2*info->line),
1358 (1U << (8+1+2*info->line)));
1359 #endif
1360 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1361 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1362 }
1363
1364 static inline void e100_enable_rx_irq(struct e100_serial *info)
1365 {
1366 if (info->uses_dma_in)
1367 e100_enable_rxdma_irq(info);
1368 else
1369 e100_enable_serial_data_irq(info);
1370 }
1371 static inline void e100_disable_rx_irq(struct e100_serial *info)
1372 {
1373 if (info->uses_dma_in)
1374 e100_disable_rxdma_irq(info);
1375 else
1376 e100_disable_serial_data_irq(info);
1377 }
1378
1379 #if defined(CONFIG_ETRAX_RS485)
1380 /* Enable RS-485 mode on selected port. This is UGLY. */
1381 static int
1382 e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1383 {
1384 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1385
1386 #if defined(CONFIG_ETRAX_RS485_ON_PA)
1387 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1388 #endif
1389 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
1390 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1391 rs485_port_g_bit, 1);
1392 #endif
1393 #if defined(CONFIG_ETRAX_RS485_LTC1387)
1394 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1395 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 1);
1396 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
1397 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 1);
1398 #endif
1399
1400 info->rs485 = *r;
1401
1402 /* Maximum delay before RTS equal to 1000 */
1403 if (info->rs485.delay_rts_before_send >= 1000)
1404 info->rs485.delay_rts_before_send = 1000;
1405
1406 /* printk("rts: on send = %i, after = %i, enabled = %i",
1407 info->rs485.rts_on_send,
1408 info->rs485.rts_after_sent,
1409 info->rs485.enabled
1410 );
1411 */
1412 return 0;
1413 }
1414
1415 static int
1416 e100_write_rs485(struct tty_struct *tty,
1417 const unsigned char *buf, int count)
1418 {
1419 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1420 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1421
1422 /* rs485 is always implicitly enabled if we're using the ioctl()
1423 * but it doesn't have to be set in the serial_rs485
1424 * (to be backward compatible with old apps)
1425 * So we store, set and restore it.
1426 */
1427 info->rs485.flags |= SER_RS485_ENABLED;
1428 /* rs_write now deals with RS485 if enabled */
1429 count = rs_write(tty, buf, count);
1430 if (!old_value)
1431 info->rs485.flags &= ~(SER_RS485_ENABLED);
1432 return count;
1433 }
1434
1435 #ifdef CONFIG_ETRAX_FAST_TIMER
1436 /* Timer function to toggle RTS when using FAST_TIMER */
1437 static void rs485_toggle_rts_timer_function(unsigned long data)
1438 {
1439 struct e100_serial *info = (struct e100_serial *)data;
1440
1441 fast_timers_rs485[info->line].function = NULL;
1442 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1443 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1444 e100_enable_rx(info);
1445 e100_enable_rx_irq(info);
1446 #endif
1447 }
1448 #endif
1449 #endif /* CONFIG_ETRAX_RS485 */
1450
1451 /*
1452 * ------------------------------------------------------------
1453 * rs_stop() and rs_start()
1454 *
1455 * This routines are called before setting or resetting tty->stopped.
1456 * They enable or disable transmitter using the XOFF registers, as necessary.
1457 * ------------------------------------------------------------
1458 */
1459
1460 static void
1461 rs_stop(struct tty_struct *tty)
1462 {
1463 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1464 if (info) {
1465 unsigned long flags;
1466 unsigned long xoff;
1467
1468 local_irq_save(flags);
1469 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1470 CIRC_CNT(info->xmit.head,
1471 info->xmit.tail,SERIAL_XMIT_SIZE)));
1472
1473 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1474 STOP_CHAR(info->port.tty));
1475 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1476 if (tty->termios.c_iflag & IXON ) {
1477 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1478 }
1479
1480 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1481 local_irq_restore(flags);
1482 }
1483 }
1484
1485 static void
1486 rs_start(struct tty_struct *tty)
1487 {
1488 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1489 if (info) {
1490 unsigned long flags;
1491 unsigned long xoff;
1492
1493 local_irq_save(flags);
1494 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1495 CIRC_CNT(info->xmit.head,
1496 info->xmit.tail,SERIAL_XMIT_SIZE)));
1497 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1498 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1499 if (tty->termios.c_iflag & IXON ) {
1500 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1501 }
1502
1503 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1504 if (!info->uses_dma_out &&
1505 info->xmit.head != info->xmit.tail && info->xmit.buf)
1506 e100_enable_serial_tx_ready_irq(info);
1507
1508 local_irq_restore(flags);
1509 }
1510 }
1511
1512 /*
1513 * ----------------------------------------------------------------------
1514 *
1515 * Here starts the interrupt handling routines. All of the following
1516 * subroutines are declared as inline and are folded into
1517 * rs_interrupt(). They were separated out for readability's sake.
1518 *
1519 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1520 * runs with interrupts turned off. People who may want to modify
1521 * rs_interrupt() should try to keep the interrupt handler as fast as
1522 * possible. After you are done making modifications, it is not a bad
1523 * idea to do:
1524 *
1525 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1526 *
1527 * and look at the resulting assemble code in serial.s.
1528 *
1529 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1530 * -----------------------------------------------------------------------
1531 */
1532
1533 /*
1534 * This routine is used by the interrupt handler to schedule
1535 * processing in the software interrupt portion of the driver.
1536 */
1537 static void rs_sched_event(struct e100_serial *info, int event)
1538 {
1539 if (info->event & (1 << event))
1540 return;
1541 info->event |= 1 << event;
1542 schedule_work(&info->work);
1543 }
1544
1545 /* The output DMA channel is free - use it to send as many chars as possible
1546 * NOTES:
1547 * We don't pay attention to info->x_char, which means if the TTY wants to
1548 * use XON/XOFF it will set info->x_char but we won't send any X char!
1549 *
1550 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1551 * buffer containing the X char, and skip updating xmit. We'd also have to
1552 * check if the last sent char was the X char when we enter this function
1553 * the next time, to avoid updating xmit with the sent X value.
1554 */
1555
1556 static void
1557 transmit_chars_dma(struct e100_serial *info)
1558 {
1559 unsigned int c, sentl;
1560 struct etrax_dma_descr *descr;
1561
1562 #ifdef CONFIG_SVINTO_SIM
1563 /* This will output too little if tail is not 0 always since
1564 * we don't reloop to send the other part. Anyway this SHOULD be a
1565 * no-op - transmit_chars_dma would never really be called during sim
1566 * since rs_write does not write into the xmit buffer then.
1567 */
1568 if (info->xmit.tail)
1569 printk("Error in serial.c:transmit_chars-dma(), tail!=0\n");
1570 if (info->xmit.head != info->xmit.tail) {
1571 SIMCOUT(info->xmit.buf + info->xmit.tail,
1572 CIRC_CNT(info->xmit.head,
1573 info->xmit.tail,
1574 SERIAL_XMIT_SIZE));
1575 info->xmit.head = info->xmit.tail; /* move back head */
1576 info->tr_running = 0;
1577 }
1578 return;
1579 #endif
1580 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1581 *info->oclrintradr =
1582 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1583 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1584
1585 #ifdef SERIAL_DEBUG_INTR
1586 if (info->line == SERIAL_DEBUG_LINE)
1587 printk("tc\n");
1588 #endif
1589 if (!info->tr_running) {
1590 /* weirdo... we shouldn't get here! */
1591 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1592 return;
1593 }
1594
1595 descr = &info->tr_descr;
1596
1597 /* first get the amount of bytes sent during the last DMA transfer,
1598 and update xmit accordingly */
1599
1600 /* if the stop bit was not set, all data has been sent */
1601 if (!(descr->status & d_stop)) {
1602 sentl = descr->sw_len;
1603 } else
1604 /* otherwise we find the amount of data sent here */
1605 sentl = descr->hw_len;
1606
1607 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1608
1609 /* update stats */
1610 info->icount.tx += sentl;
1611
1612 /* update xmit buffer */
1613 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1614
1615 /* if there is only a few chars left in the buf, wake up the blocked
1616 write if any */
1617 if (CIRC_CNT(info->xmit.head,
1618 info->xmit.tail,
1619 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1620 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1621
1622 /* find out the largest amount of consecutive bytes we want to send now */
1623
1624 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1625
1626 /* Don't send all in one DMA transfer - divide it so we wake up
1627 * application before all is sent
1628 */
1629
1630 if (c >= 4*WAKEUP_CHARS)
1631 c = c/2;
1632
1633 if (c <= 0) {
1634 /* our job here is done, don't schedule any new DMA transfer */
1635 info->tr_running = 0;
1636
1637 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1638 if (info->rs485.flags & SER_RS485_ENABLED) {
1639 /* Set a short timer to toggle RTS */
1640 start_one_shot_timer(&fast_timers_rs485[info->line],
1641 rs485_toggle_rts_timer_function,
1642 (unsigned long)info,
1643 info->char_time_usec*2,
1644 "RS-485");
1645 }
1646 #endif /* RS485 */
1647 return;
1648 }
1649
1650 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1651 /* set up the descriptor correctly for output */
1652 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1653 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1654 descr->sw_len = c;
1655 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1656 descr->status = 0;
1657
1658 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1659 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1660
1661 /* DMA is now running (hopefully) */
1662 } /* transmit_chars_dma */
1663
1664 static void
1665 start_transmit(struct e100_serial *info)
1666 {
1667 #if 0
1668 if (info->line == SERIAL_DEBUG_LINE)
1669 printk("x\n");
1670 #endif
1671
1672 info->tr_descr.sw_len = 0;
1673 info->tr_descr.hw_len = 0;
1674 info->tr_descr.status = 0;
1675 info->tr_running = 1;
1676 if (info->uses_dma_out)
1677 transmit_chars_dma(info);
1678 else
1679 e100_enable_serial_tx_ready_irq(info);
1680 } /* start_transmit */
1681
1682 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1683 static int serial_fast_timer_started = 0;
1684 static int serial_fast_timer_expired = 0;
1685 static void flush_timeout_function(unsigned long data);
1686 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1687 unsigned long timer_flags; \
1688 local_irq_save(timer_flags); \
1689 if (fast_timers[info->line].function == NULL) { \
1690 serial_fast_timer_started++; \
1691 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1692 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1693 start_one_shot_timer(&fast_timers[info->line], \
1694 flush_timeout_function, \
1695 (unsigned long)info, \
1696 (usec), \
1697 string); \
1698 } \
1699 else { \
1700 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1701 } \
1702 local_irq_restore(timer_flags); \
1703 }
1704 #define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1705
1706 #else
1707 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1708 #define START_FLUSH_FAST_TIMER(info, string)
1709 #endif
1710
1711 static struct etrax_recv_buffer *
1712 alloc_recv_buffer(unsigned int size)
1713 {
1714 struct etrax_recv_buffer *buffer;
1715
1716 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1717 return NULL;
1718
1719 buffer->next = NULL;
1720 buffer->length = 0;
1721 buffer->error = TTY_NORMAL;
1722
1723 return buffer;
1724 }
1725
1726 static void
1727 append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1728 {
1729 unsigned long flags;
1730
1731 local_irq_save(flags);
1732
1733 if (!info->first_recv_buffer)
1734 info->first_recv_buffer = buffer;
1735 else
1736 info->last_recv_buffer->next = buffer;
1737
1738 info->last_recv_buffer = buffer;
1739
1740 info->recv_cnt += buffer->length;
1741 if (info->recv_cnt > info->max_recv_cnt)
1742 info->max_recv_cnt = info->recv_cnt;
1743
1744 local_irq_restore(flags);
1745 }
1746
1747 static int
1748 add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1749 {
1750 struct etrax_recv_buffer *buffer;
1751 if (info->uses_dma_in) {
1752 if (!(buffer = alloc_recv_buffer(4)))
1753 return 0;
1754
1755 buffer->length = 1;
1756 buffer->error = flag;
1757 buffer->buffer[0] = data;
1758
1759 append_recv_buffer(info, buffer);
1760
1761 info->icount.rx++;
1762 } else {
1763 tty_insert_flip_char(&info->port, data, flag);
1764 info->icount.rx++;
1765 }
1766
1767 return 1;
1768 }
1769
1770 static unsigned int handle_descr_data(struct e100_serial *info,
1771 struct etrax_dma_descr *descr,
1772 unsigned int recvl)
1773 {
1774 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1775
1776 if (info->recv_cnt + recvl > 65536) {
1777 printk(KERN_WARNING
1778 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1779 return 0;
1780 }
1781
1782 buffer->length = recvl;
1783
1784 if (info->errorcode == ERRCODE_SET_BREAK)
1785 buffer->error = TTY_BREAK;
1786 info->errorcode = 0;
1787
1788 append_recv_buffer(info, buffer);
1789
1790 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1791 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1792
1793 descr->buf = virt_to_phys(buffer->buffer);
1794
1795 return recvl;
1796 }
1797
1798 static unsigned int handle_all_descr_data(struct e100_serial *info)
1799 {
1800 struct etrax_dma_descr *descr;
1801 unsigned int recvl;
1802 unsigned int ret = 0;
1803
1804 while (1)
1805 {
1806 descr = &info->rec_descr[info->cur_rec_descr];
1807
1808 if (descr == phys_to_virt(*info->idescradr))
1809 break;
1810
1811 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1812 info->cur_rec_descr = 0;
1813
1814 /* find out how many bytes were read */
1815
1816 /* if the eop bit was not set, all data has been received */
1817 if (!(descr->status & d_eop)) {
1818 recvl = descr->sw_len;
1819 } else {
1820 /* otherwise we find the amount of data received here */
1821 recvl = descr->hw_len;
1822 }
1823
1824 /* Reset the status information */
1825 descr->status = 0;
1826
1827 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1828 if (info->port.tty->stopped) {
1829 unsigned char *buf = phys_to_virt(descr->buf);
1830 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1831 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1832 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1833 }
1834 );
1835
1836 /* update stats */
1837 info->icount.rx += recvl;
1838
1839 ret += handle_descr_data(info, descr, recvl);
1840 }
1841
1842 return ret;
1843 }
1844
1845 static void receive_chars_dma(struct e100_serial *info)
1846 {
1847 struct tty_struct *tty;
1848 unsigned char rstat;
1849
1850 #ifdef CONFIG_SVINTO_SIM
1851 /* No receive in the simulator. Will probably be when the rest of
1852 * the serial interface works, and this piece will just be removed.
1853 */
1854 return;
1855 #endif
1856
1857 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1858 *info->iclrintradr =
1859 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1860 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1861
1862 tty = info->port.tty;
1863 if (!tty) /* Something wrong... */
1864 return;
1865
1866 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1867 if (info->uses_dma_in)
1868 e100_enable_serial_data_irq(info);
1869 #endif
1870
1871 if (info->errorcode == ERRCODE_INSERT_BREAK)
1872 add_char_and_flag(info, '\0', TTY_BREAK);
1873
1874 handle_all_descr_data(info);
1875
1876 /* Read the status register to detect errors */
1877 rstat = info->ioport[REG_STATUS];
1878 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1879 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1880 }
1881
1882 if (rstat & SER_ERROR_MASK) {
1883 /* If we got an error, we must reset it by reading the
1884 * data_in field
1885 */
1886 unsigned char data = info->ioport[REG_DATA];
1887
1888 PROCSTAT(ser_stat[info->line].errors_cnt++);
1889 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1890 ((rstat & SER_ERROR_MASK) << 8) | data);
1891
1892 if (rstat & SER_PAR_ERR_MASK)
1893 add_char_and_flag(info, data, TTY_PARITY);
1894 else if (rstat & SER_OVERRUN_MASK)
1895 add_char_and_flag(info, data, TTY_OVERRUN);
1896 else if (rstat & SER_FRAMING_ERR_MASK)
1897 add_char_and_flag(info, data, TTY_FRAME);
1898 }
1899
1900 START_FLUSH_FAST_TIMER(info, "receive_chars");
1901
1902 /* Restart the receiving DMA */
1903 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1904 }
1905
1906 static int start_recv_dma(struct e100_serial *info)
1907 {
1908 struct etrax_dma_descr *descr = info->rec_descr;
1909 struct etrax_recv_buffer *buffer;
1910 int i;
1911
1912 /* Set up the receiving descriptors */
1913 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1914 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
1915 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1916
1917 descr[i].ctrl = d_int;
1918 descr[i].buf = virt_to_phys(buffer->buffer);
1919 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1920 descr[i].hw_len = 0;
1921 descr[i].status = 0;
1922 descr[i].next = virt_to_phys(&descr[i+1]);
1923 }
1924
1925 /* Link the last descriptor to the first */
1926 descr[i-1].next = virt_to_phys(&descr[0]);
1927
1928 /* Start with the first descriptor in the list */
1929 info->cur_rec_descr = 0;
1930
1931 /* Start the DMA */
1932 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1933 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1934
1935 /* Input DMA should be running now */
1936 return 1;
1937 }
1938
1939 static void
1940 start_receive(struct e100_serial *info)
1941 {
1942 #ifdef CONFIG_SVINTO_SIM
1943 /* No receive in the simulator. Will probably be when the rest of
1944 * the serial interface works, and this piece will just be removed.
1945 */
1946 return;
1947 #endif
1948 if (info->uses_dma_in) {
1949 /* reset the input dma channel to be sure it works */
1950
1951 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1952 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1953 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1954
1955 start_recv_dma(info);
1956 }
1957 }
1958
1959
1960 /* the bits in the MASK2 register are laid out like this:
1961 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1962 where I is the input channel and O is the output channel for the port.
1963 info->irq is the bit number for the DMAO_DESCR so to check the others we
1964 shift info->irq to the left.
1965 */
1966
1967 /* dma output channel interrupt handler
1968 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1969 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1970 */
1971
1972 static irqreturn_t
1973 tr_interrupt(int irq, void *dev_id)
1974 {
1975 struct e100_serial *info;
1976 unsigned long ireg;
1977 int i;
1978 int handled = 0;
1979
1980 #ifdef CONFIG_SVINTO_SIM
1981 /* No receive in the simulator. Will probably be when the rest of
1982 * the serial interface works, and this piece will just be removed.
1983 */
1984 {
1985 const char *s = "What? tr_interrupt in simulator??\n";
1986 SIMCOUT(s,strlen(s));
1987 }
1988 return IRQ_HANDLED;
1989 #endif
1990
1991 /* find out the line that caused this irq and get it from rs_table */
1992
1993 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1994
1995 for (i = 0; i < NR_PORTS; i++) {
1996 info = rs_table + i;
1997 if (!info->enabled || !info->uses_dma_out)
1998 continue;
1999 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
2000 if (ireg & info->irq) {
2001 handled = 1;
2002 /* we can send a new dma bunch. make it so. */
2003 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
2004 /* Read jiffies_usec first,
2005 * we want this time to be as late as possible
2006 */
2007 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
2008 info->last_tx_active_usec = GET_JIFFIES_USEC();
2009 info->last_tx_active = jiffies;
2010 transmit_chars_dma(info);
2011 }
2012
2013 /* FIXME: here we should really check for a change in the
2014 status lines and if so call status_handle(info) */
2015 }
2016 return IRQ_RETVAL(handled);
2017 } /* tr_interrupt */
2018
2019 /* dma input channel interrupt handler */
2020
2021 static irqreturn_t
2022 rec_interrupt(int irq, void *dev_id)
2023 {
2024 struct e100_serial *info;
2025 unsigned long ireg;
2026 int i;
2027 int handled = 0;
2028
2029 #ifdef CONFIG_SVINTO_SIM
2030 /* No receive in the simulator. Will probably be when the rest of
2031 * the serial interface works, and this piece will just be removed.
2032 */
2033 {
2034 const char *s = "What? rec_interrupt in simulator??\n";
2035 SIMCOUT(s,strlen(s));
2036 }
2037 return IRQ_HANDLED;
2038 #endif
2039
2040 /* find out the line that caused this irq and get it from rs_table */
2041
2042 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
2043
2044 for (i = 0; i < NR_PORTS; i++) {
2045 info = rs_table + i;
2046 if (!info->enabled || !info->uses_dma_in)
2047 continue;
2048 /* check for both dma_eop and dma_descr for the input dma channel */
2049 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
2050 handled = 1;
2051 /* we have received something */
2052 receive_chars_dma(info);
2053 }
2054
2055 /* FIXME: here we should really check for a change in the
2056 status lines and if so call status_handle(info) */
2057 }
2058 return IRQ_RETVAL(handled);
2059 } /* rec_interrupt */
2060
2061 static int force_eop_if_needed(struct e100_serial *info)
2062 {
2063 /* We check data_avail bit to determine if data has
2064 * arrived since last time
2065 */
2066 unsigned char rstat = info->ioport[REG_STATUS];
2067
2068 /* error or datavail? */
2069 if (rstat & SER_ERROR_MASK) {
2070 /* Some error has occurred. If there has been valid data, an
2071 * EOP interrupt will be made automatically. If no data, the
2072 * normal ser_interrupt should be enabled and handle it.
2073 * So do nothing!
2074 */
2075 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
2076 rstat | (info->line << 8));
2077 return 0;
2078 }
2079
2080 if (rstat & SER_DATA_AVAIL_MASK) {
2081 /* Ok data, no error, count it */
2082 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
2083 rstat | (info->line << 8)));
2084 /* Read data to clear status flags */
2085 (void)info->ioport[REG_DATA];
2086
2087 info->forced_eop = 0;
2088 START_FLUSH_FAST_TIMER(info, "magic");
2089 return 0;
2090 }
2091
2092 /* hit the timeout, force an EOP for the input
2093 * dma channel if we haven't already
2094 */
2095 if (!info->forced_eop) {
2096 info->forced_eop = 1;
2097 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2098 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2099 FORCE_EOP(info);
2100 }
2101
2102 return 1;
2103 }
2104
2105 static void flush_to_flip_buffer(struct e100_serial *info)
2106 {
2107 struct etrax_recv_buffer *buffer;
2108 unsigned long flags;
2109
2110 local_irq_save(flags);
2111
2112 while ((buffer = info->first_recv_buffer) != NULL) {
2113 unsigned int count = buffer->length;
2114
2115 tty_insert_flip_string(&info->port, buffer->buffer, count);
2116 info->recv_cnt -= count;
2117
2118 if (count == buffer->length) {
2119 info->first_recv_buffer = buffer->next;
2120 kfree(buffer);
2121 } else {
2122 buffer->length -= count;
2123 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2124 buffer->error = TTY_NORMAL;
2125 }
2126 }
2127
2128 if (!info->first_recv_buffer)
2129 info->last_recv_buffer = NULL;
2130
2131 local_irq_restore(flags);
2132
2133 /* This includes a check for low-latency */
2134 tty_flip_buffer_push(&info->port);
2135 }
2136
2137 static void check_flush_timeout(struct e100_serial *info)
2138 {
2139 /* Flip what we've got (if we can) */
2140 flush_to_flip_buffer(info);
2141
2142 /* We might need to flip later, but not to fast
2143 * since the system is busy processing input... */
2144 if (info->first_recv_buffer)
2145 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2146
2147 /* Force eop last, since data might have come while we're processing
2148 * and if we started the slow timer above, we won't start a fast
2149 * below.
2150 */
2151 force_eop_if_needed(info);
2152 }
2153
2154 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2155 static void flush_timeout_function(unsigned long data)
2156 {
2157 struct e100_serial *info = (struct e100_serial *)data;
2158
2159 fast_timers[info->line].function = NULL;
2160 serial_fast_timer_expired++;
2161 TIMERD(DEBUG_LOG(info->line, "flush_timout %i ", info->line));
2162 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2163 check_flush_timeout(info);
2164 }
2165
2166 #else
2167
2168 /* dma fifo/buffer timeout handler
2169 forces an end-of-packet for the dma input channel if no chars
2170 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2171 */
2172
2173 static struct timer_list flush_timer;
2174
2175 static void
2176 timed_flush_handler(unsigned long ptr)
2177 {
2178 struct e100_serial *info;
2179 int i;
2180
2181 #ifdef CONFIG_SVINTO_SIM
2182 return;
2183 #endif
2184
2185 for (i = 0; i < NR_PORTS; i++) {
2186 info = rs_table + i;
2187 if (info->uses_dma_in)
2188 check_flush_timeout(info);
2189 }
2190
2191 /* restart flush timer */
2192 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2193 }
2194 #endif
2195
2196 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2197
2198 /* If there is an error (ie break) when the DMA is running and
2199 * there are no bytes in the fifo the DMA is stopped and we get no
2200 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2201 * transfer, and if it is without error we can turn the serial
2202 * interrupts off.
2203 */
2204
2205 /*
2206 BREAK handling on ETRAX 100:
2207 ETRAX will generate interrupt although there is no stop bit between the
2208 characters.
2209
2210 Depending on how long the break sequence is, the end of the breaksequence
2211 will look differently:
2212 | indicates start/end of a character.
2213
2214 B= Break character (0x00) with framing error.
2215 E= Error byte with parity error received after B characters.
2216 F= "Faked" valid byte received immediately after B characters.
2217 V= Valid byte
2218
2219 1.
2220 B BL ___________________________ V
2221 .._|__________|__________| |valid data |
2222
2223 Multiple frame errors with data == 0x00 (B),
2224 the timing matches up "perfectly" so no extra ending char is detected.
2225 The RXD pin is 1 in the last interrupt, in that case
2226 we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2227 know if another byte will come and this really is case 2. below
2228 (e.g F=0xFF or 0xFE)
2229 If RXD pin is 0 we can expect another character (see 2. below).
2230
2231
2232 2.
2233
2234 B B E or F__________________..__ V
2235 .._|__________|__________|______ | |valid data
2236 "valid" or
2237 parity error
2238
2239 Multiple frame errors with data == 0x00 (B),
2240 but the part of the break trigs is interpreted as a start bit (and possibly
2241 some 0 bits followed by a number of 1 bits and a stop bit).
2242 Depending on parity settings etc. this last character can be either
2243 a fake "valid" char (F) or have a parity error (E).
2244
2245 If the character is valid it will be put in the buffer,
2246 we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2247 will set the flags so the tty will handle it,
2248 if it's an error byte it will not be put in the buffer
2249 and we set info->errorcode = ERRCODE_INSERT_BREAK.
2250
2251 To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2252 of the last faulty char (B) and compares it with the current time:
2253 If the time elapsed time is less then 2*char_time_usec we will assume
2254 it's a faked F char and not a Valid char and set
2255 info->errorcode = ERRCODE_SET_BREAK.
2256
2257 Flaws in the above solution:
2258 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2259 We use the timer to distinguish a F character from a V character,
2260 if a V character is to close after the break we might make the wrong decision.
2261
2262 TODO: The break will be delayed until an F or V character is received.
2263
2264 */
2265
2266 static
2267 struct e100_serial * handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2268 {
2269 unsigned long data_read;
2270
2271 /* Read data and status at the same time */
2272 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2273 more_data:
2274 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2275 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2276 }
2277 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2278
2279 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2280 IO_MASK(R_SERIAL0_READ, par_err) |
2281 IO_MASK(R_SERIAL0_READ, overrun) )) {
2282 /* An error */
2283 info->last_rx_active_usec = GET_JIFFIES_USEC();
2284 info->last_rx_active = jiffies;
2285 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2286 DLOG_INT_TRIG(
2287 if (!log_int_trig1_pos) {
2288 log_int_trig1_pos = log_int_pos;
2289 log_int(rdpc(), 0, 0);
2290 }
2291 );
2292
2293
2294 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2295 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2296 /* Most likely a break, but we get interrupts over and
2297 * over again.
2298 */
2299
2300 if (!info->break_detected_cnt) {
2301 DEBUG_LOG(info->line, "#BRK start\n", 0);
2302 }
2303 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2304 /* The RX pin is high now, so the break
2305 * must be over, but....
2306 * we can't really know if we will get another
2307 * last byte ending the break or not.
2308 * And we don't know if the byte (if any) will
2309 * have an error or look valid.
2310 */
2311 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2312 info->errorcode = ERRCODE_INSERT_BREAK;
2313 }
2314 info->break_detected_cnt++;
2315 } else {
2316 /* The error does not look like a break, but could be
2317 * the end of one
2318 */
2319 if (info->break_detected_cnt) {
2320 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2321 info->errorcode = ERRCODE_INSERT_BREAK;
2322 } else {
2323 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2324 data_in, data_read);
2325 char flag = TTY_NORMAL;
2326 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2327 tty_insert_flip_char(&info->port, 0, flag);
2328 info->icount.rx++;
2329 }
2330
2331 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2332 info->icount.parity++;
2333 flag = TTY_PARITY;
2334 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2335 info->icount.overrun++;
2336 flag = TTY_OVERRUN;
2337 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2338 info->icount.frame++;
2339 flag = TTY_FRAME;
2340 }
2341 tty_insert_flip_char(&info->port, data, flag);
2342 info->errorcode = 0;
2343 }
2344 info->break_detected_cnt = 0;
2345 }
2346 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2347 /* No error */
2348 DLOG_INT_TRIG(
2349 if (!log_int_trig1_pos) {
2350 if (log_int_pos >= log_int_size) {
2351 log_int_pos = 0;
2352 }
2353 log_int_trig0_pos = log_int_pos;
2354 log_int(rdpc(), 0, 0);
2355 }
2356 );
2357 tty_insert_flip_char(&info->port,
2358 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2359 TTY_NORMAL);
2360 } else {
2361 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2362 }
2363
2364
2365 info->icount.rx++;
2366 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2367 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2368 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2369 goto more_data;
2370 }
2371
2372 tty_flip_buffer_push(&info->port);
2373 return info;
2374 }
2375
2376 static struct e100_serial* handle_ser_rx_interrupt(struct e100_serial *info)
2377 {
2378 unsigned char rstat;
2379
2380 #ifdef SERIAL_DEBUG_INTR
2381 printk("Interrupt from serport %d\n", i);
2382 #endif
2383 /* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2384 if (!info->uses_dma_in) {
2385 return handle_ser_rx_interrupt_no_dma(info);
2386 }
2387 /* DMA is used */
2388 rstat = info->ioport[REG_STATUS];
2389 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2390 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2391 }
2392
2393 if (rstat & SER_ERROR_MASK) {
2394 unsigned char data;
2395
2396 info->last_rx_active_usec = GET_JIFFIES_USEC();
2397 info->last_rx_active = jiffies;
2398 /* If we got an error, we must reset it by reading the
2399 * data_in field
2400 */
2401 data = info->ioport[REG_DATA];
2402 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2403 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2404 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2405 /* Most likely a break, but we get interrupts over and
2406 * over again.
2407 */
2408
2409 if (!info->break_detected_cnt) {
2410 DEBUG_LOG(info->line, "#BRK start\n", 0);
2411 }
2412 if (rstat & SER_RXD_MASK) {
2413 /* The RX pin is high now, so the break
2414 * must be over, but....
2415 * we can't really know if we will get another
2416 * last byte ending the break or not.
2417 * And we don't know if the byte (if any) will
2418 * have an error or look valid.
2419 */
2420 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2421 info->errorcode = ERRCODE_INSERT_BREAK;
2422 }
2423 info->break_detected_cnt++;
2424 } else {
2425 /* The error does not look like a break, but could be
2426 * the end of one
2427 */
2428 if (info->break_detected_cnt) {
2429 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2430 info->errorcode = ERRCODE_INSERT_BREAK;
2431 } else {
2432 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2433 info->icount.brk++;
2434 add_char_and_flag(info, '\0', TTY_BREAK);
2435 }
2436
2437 if (rstat & SER_PAR_ERR_MASK) {
2438 info->icount.parity++;
2439 add_char_and_flag(info, data, TTY_PARITY);
2440 } else if (rstat & SER_OVERRUN_MASK) {
2441 info->icount.overrun++;
2442 add_char_and_flag(info, data, TTY_OVERRUN);
2443 } else if (rstat & SER_FRAMING_ERR_MASK) {
2444 info->icount.frame++;
2445 add_char_and_flag(info, data, TTY_FRAME);
2446 }
2447
2448 info->errorcode = 0;
2449 }
2450 info->break_detected_cnt = 0;
2451 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2452 ((rstat & SER_ERROR_MASK) << 8) | data);
2453 }
2454 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2455 } else { /* It was a valid byte, now let the DMA do the rest */
2456 unsigned long curr_time_u = GET_JIFFIES_USEC();
2457 unsigned long curr_time = jiffies;
2458
2459 if (info->break_detected_cnt) {
2460 /* Detect if this character is a new valid char or the
2461 * last char in a break sequence: If LSBits are 0 and
2462 * MSBits are high AND the time is close to the
2463 * previous interrupt we should discard it.
2464 */
2465 long elapsed_usec =
2466 (curr_time - info->last_rx_active) * (1000000/HZ) +
2467 curr_time_u - info->last_rx_active_usec;
2468 if (elapsed_usec < 2*info->char_time_usec) {
2469 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2470 /* Report as BREAK (error) and let
2471 * receive_chars_dma() handle it
2472 */
2473 info->errorcode = ERRCODE_SET_BREAK;
2474 } else {
2475 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2476 }
2477 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2478 }
2479
2480 #ifdef SERIAL_DEBUG_INTR
2481 printk("** OK, disabling ser_interrupts\n");
2482 #endif
2483 e100_disable_serial_data_irq(info);
2484 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2485 info->break_detected_cnt = 0;
2486
2487 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2488 }
2489 /* Restarting the DMA never hurts */
2490 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2491 START_FLUSH_FAST_TIMER(info, "ser_int");
2492 return info;
2493 } /* handle_ser_rx_interrupt */
2494
2495 static void handle_ser_tx_interrupt(struct e100_serial *info)
2496 {
2497 unsigned long flags;
2498
2499 if (info->x_char) {
2500 unsigned char rstat;
2501 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2502 local_irq_save(flags);
2503 rstat = info->ioport[REG_STATUS];
2504 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2505
2506 info->ioport[REG_TR_DATA] = info->x_char;
2507 info->icount.tx++;
2508 info->x_char = 0;
2509 /* We must enable since it is disabled in ser_interrupt */
2510 e100_enable_serial_tx_ready_irq(info);
2511 local_irq_restore(flags);
2512 return;
2513 }
2514 if (info->uses_dma_out) {
2515 unsigned char rstat;
2516 int i;
2517 /* We only use normal tx interrupt when sending x_char */
2518 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2519 local_irq_save(flags);
2520 rstat = info->ioport[REG_STATUS];
2521 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2522 e100_disable_serial_tx_ready_irq(info);
2523 if (info->port.tty->stopped)
2524 rs_stop(info->port.tty);
2525 /* Enable the DMA channel and tell it to continue */
2526 e100_enable_txdma_channel(info);
2527 /* Wait 12 cycles before doing the DMA command */
2528 for(i = 6; i > 0; i--)
2529 nop();
2530
2531 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2532 local_irq_restore(flags);
2533 return;
2534 }
2535 /* Normal char-by-char interrupt */
2536 if (info->xmit.head == info->xmit.tail
2537 || info->port.tty->stopped
2538 || info->port.tty->hw_stopped) {
2539 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2540 info->port.tty->stopped));
2541 e100_disable_serial_tx_ready_irq(info);
2542 info->tr_running = 0;
2543 return;
2544 }
2545 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2546 /* Send a byte, rs485 timing is critical so turn of ints */
2547 local_irq_save(flags);
2548 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2549 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2550 info->icount.tx++;
2551 if (info->xmit.head == info->xmit.tail) {
2552 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2553 if (info->rs485.flags & SER_RS485_ENABLED) {
2554 /* Set a short timer to toggle RTS */
2555 start_one_shot_timer(&fast_timers_rs485[info->line],
2556 rs485_toggle_rts_timer_function,
2557 (unsigned long)info,
2558 info->char_time_usec*2,
2559 "RS-485");
2560 }
2561 #endif /* RS485 */
2562 info->last_tx_active_usec = GET_JIFFIES_USEC();
2563 info->last_tx_active = jiffies;
2564 e100_disable_serial_tx_ready_irq(info);
2565 info->tr_running = 0;
2566 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2567 } else {
2568 /* We must enable since it is disabled in ser_interrupt */
2569 e100_enable_serial_tx_ready_irq(info);
2570 }
2571 local_irq_restore(flags);
2572
2573 if (CIRC_CNT(info->xmit.head,
2574 info->xmit.tail,
2575 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2576 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2577
2578 } /* handle_ser_tx_interrupt */
2579
2580 /* result of time measurements:
2581 * RX duration 54-60 us when doing something, otherwise 6-9 us
2582 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2583 */
2584 static irqreturn_t
2585 ser_interrupt(int irq, void *dev_id)
2586 {
2587 static volatile int tx_started = 0;
2588 struct e100_serial *info;
2589 int i;
2590 unsigned long flags;
2591 unsigned long irq_mask1_rd;
2592 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2593 int handled = 0;
2594 static volatile unsigned long reentered_ready_mask = 0;
2595
2596 local_irq_save(flags);
2597 irq_mask1_rd = *R_IRQ_MASK1_RD;
2598 /* First handle all rx interrupts with ints disabled */
2599 info = rs_table;
2600 irq_mask1_rd &= e100_ser_int_mask;
2601 for (i = 0; i < NR_PORTS; i++) {
2602 /* Which line caused the data irq? */
2603 if (irq_mask1_rd & data_mask) {
2604 handled = 1;
2605 handle_ser_rx_interrupt(info);
2606 }
2607 info += 1;
2608 data_mask <<= 2;
2609 }
2610 /* Handle tx interrupts with interrupts enabled so we
2611 * can take care of new data interrupts while transmitting
2612 * We protect the tx part with the tx_started flag.
2613 * We disable the tr_ready interrupts we are about to handle and
2614 * unblock the serial interrupt so new serial interrupts may come.
2615 *
2616 * If we get a new interrupt:
2617 * - it migth be due to synchronous serial ports.
2618 * - serial irq will be blocked by general irq handler.
2619 * - async data will be handled above (sync will be ignored).
2620 * - tx_started flag will prevent us from trying to send again and
2621 * we will exit fast - no need to unblock serial irq.
2622 * - Next (sync) serial interrupt handler will be runned with
2623 * disabled interrupt due to restore_flags() at end of function,
2624 * so sync handler will not be preempted or reentered.
2625 */
2626 if (!tx_started) {
2627 unsigned long ready_mask;
2628 unsigned long
2629 tx_started = 1;
2630 /* Only the tr_ready interrupts left */
2631 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2632 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2633 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2634 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2635 while (irq_mask1_rd) {
2636 /* Disable those we are about to handle */
2637 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2638 /* Unblock the serial interrupt */
2639 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2640
2641 local_irq_enable();
2642 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2643 info = rs_table;
2644 for (i = 0; i < NR_PORTS; i++) {
2645 /* Which line caused the ready irq? */
2646 if (irq_mask1_rd & ready_mask) {
2647 handled = 1;
2648 handle_ser_tx_interrupt(info);
2649 }
2650 info += 1;
2651 ready_mask <<= 2;
2652 }
2653 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2654 local_irq_disable();
2655 /* Handle reentered TX interrupt */
2656 irq_mask1_rd = reentered_ready_mask;
2657 }
2658 local_irq_disable();
2659 tx_started = 0;
2660 } else {
2661 unsigned long ready_mask;
2662 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2663 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2664 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2665 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2666 if (ready_mask) {
2667 reentered_ready_mask |= ready_mask;
2668 /* Disable those we are about to handle */
2669 *R_IRQ_MASK1_CLR = ready_mask;
2670 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2671 }
2672 }
2673
2674 local_irq_restore(flags);
2675 return IRQ_RETVAL(handled);
2676 } /* ser_interrupt */
2677 #endif
2678
2679 /*
2680 * -------------------------------------------------------------------
2681 * Here ends the serial interrupt routines.
2682 * -------------------------------------------------------------------
2683 */
2684
2685 /*
2686 * This routine is used to handle the "bottom half" processing for the
2687 * serial driver, known also the "software interrupt" processing.
2688 * This processing is done at the kernel interrupt level, after the
2689 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2690 * is where time-consuming activities which can not be done in the
2691 * interrupt driver proper are done; the interrupt driver schedules
2692 * them using rs_sched_event(), and they get done here.
2693 */
2694 static void
2695 do_softint(struct work_struct *work)
2696 {
2697 struct e100_serial *info;
2698 struct tty_struct *tty;
2699
2700 info = container_of(work, struct e100_serial, work);
2701
2702 tty = info->port.tty;
2703 if (!tty)
2704 return;
2705
2706 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2707 tty_wakeup(tty);
2708 }
2709
2710 static int
2711 startup(struct e100_serial * info)
2712 {
2713 unsigned long flags;
2714 unsigned long xmit_page;
2715 int i;
2716
2717 xmit_page = get_zeroed_page(GFP_KERNEL);
2718 if (!xmit_page)
2719 return -ENOMEM;
2720
2721 local_irq_save(flags);
2722
2723 /* if it was already initialized, skip this */
2724
2725 if (info->flags & ASYNC_INITIALIZED) {
2726 local_irq_restore(flags);
2727 free_page(xmit_page);
2728 return 0;
2729 }
2730
2731 if (info->xmit.buf)
2732 free_page(xmit_page);
2733 else
2734 info->xmit.buf = (unsigned char *) xmit_page;
2735
2736 #ifdef SERIAL_DEBUG_OPEN
2737 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2738 #endif
2739
2740 #ifdef CONFIG_SVINTO_SIM
2741 /* Bits and pieces collected from below. Better to have them
2742 in one ifdef:ed clause than to mix in a lot of ifdefs,
2743 right? */
2744 if (info->port.tty)
2745 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2746
2747 info->xmit.head = info->xmit.tail = 0;
2748 info->first_recv_buffer = info->last_recv_buffer = NULL;
2749 info->recv_cnt = info->max_recv_cnt = 0;
2750
2751 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2752 info->rec_descr[i].buf = NULL;
2753
2754 /* No real action in the simulator, but may set info important
2755 to ioctl. */
2756 change_speed(info);
2757 #else
2758
2759 /*
2760 * Clear the FIFO buffers and disable them
2761 * (they will be reenabled in change_speed())
2762 */
2763
2764 /*
2765 * Reset the DMA channels and make sure their interrupts are cleared
2766 */
2767
2768 if (info->dma_in_enabled) {
2769 info->uses_dma_in = 1;
2770 e100_enable_rxdma_channel(info);
2771
2772 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2773
2774 /* Wait until reset cycle is complete */
2775 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2776 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2777
2778 /* Make sure the irqs are cleared */
2779 *info->iclrintradr =
2780 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2781 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2782 } else {
2783 e100_disable_rxdma_channel(info);
2784 }
2785
2786 if (info->dma_out_enabled) {
2787 info->uses_dma_out = 1;
2788 e100_enable_txdma_channel(info);
2789 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2790
2791 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2792 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2793
2794 /* Make sure the irqs are cleared */
2795 *info->oclrintradr =
2796 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2797 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2798 } else {
2799 e100_disable_txdma_channel(info);
2800 }
2801
2802 if (info->port.tty)
2803 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2804
2805 info->xmit.head = info->xmit.tail = 0;
2806 info->first_recv_buffer = info->last_recv_buffer = NULL;
2807 info->recv_cnt = info->max_recv_cnt = 0;
2808
2809 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2810 info->rec_descr[i].buf = 0;
2811
2812 /*
2813 * and set the speed and other flags of the serial port
2814 * this will start the rx/tx as well
2815 */
2816 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2817 e100_enable_serial_data_irq(info);
2818 #endif
2819 change_speed(info);
2820
2821 /* dummy read to reset any serial errors */
2822
2823 (void)info->ioport[REG_DATA];
2824
2825 /* enable the interrupts */
2826 if (info->uses_dma_out)
2827 e100_enable_txdma_irq(info);
2828
2829 e100_enable_rx_irq(info);
2830
2831 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2832
2833 /* setup the dma input descriptor and start dma */
2834
2835 start_receive(info);
2836
2837 /* for safety, make sure the descriptors last result is 0 bytes written */
2838
2839 info->tr_descr.sw_len = 0;
2840 info->tr_descr.hw_len = 0;
2841 info->tr_descr.status = 0;
2842
2843 /* enable RTS/DTR last */
2844
2845 e100_rts(info, 1);
2846 e100_dtr(info, 1);
2847
2848 #endif /* CONFIG_SVINTO_SIM */
2849
2850 info->flags |= ASYNC_INITIALIZED;
2851
2852 local_irq_restore(flags);
2853 return 0;
2854 }
2855
2856 /*
2857 * This routine will shutdown a serial port; interrupts are disabled, and
2858 * DTR is dropped if the hangup on close termio flag is on.
2859 */
2860 static void
2861 shutdown(struct e100_serial * info)
2862 {
2863 unsigned long flags;
2864 struct etrax_dma_descr *descr = info->rec_descr;
2865 struct etrax_recv_buffer *buffer;
2866 int i;
2867
2868 #ifndef CONFIG_SVINTO_SIM
2869 /* shut down the transmitter and receiver */
2870 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2871 e100_disable_rx(info);
2872 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2873
2874 /* disable interrupts, reset dma channels */
2875 if (info->uses_dma_in) {
2876 e100_disable_rxdma_irq(info);
2877 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2878 info->uses_dma_in = 0;
2879 } else {
2880 e100_disable_serial_data_irq(info);
2881 }
2882
2883 if (info->uses_dma_out) {
2884 e100_disable_txdma_irq(info);
2885 info->tr_running = 0;
2886 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2887 info->uses_dma_out = 0;
2888 } else {
2889 e100_disable_serial_tx_ready_irq(info);
2890 info->tr_running = 0;
2891 }
2892
2893 #endif /* CONFIG_SVINTO_SIM */
2894
2895 if (!(info->flags & ASYNC_INITIALIZED))
2896 return;
2897
2898 #ifdef SERIAL_DEBUG_OPEN
2899 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2900 info->irq);
2901 #endif
2902
2903 local_irq_save(flags);
2904
2905 if (info->xmit.buf) {
2906 free_page((unsigned long)info->xmit.buf);
2907 info->xmit.buf = NULL;
2908 }
2909
2910 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2911 if (descr[i].buf) {
2912 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2913 kfree(buffer);
2914 descr[i].buf = 0;
2915 }
2916
2917 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
2918 /* hang up DTR and RTS if HUPCL is enabled */
2919 e100_dtr(info, 0);
2920 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2921 }
2922
2923 if (info->port.tty)
2924 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2925
2926 info->flags &= ~ASYNC_INITIALIZED;
2927 local_irq_restore(flags);
2928 }
2929
2930
2931 /* change baud rate and other assorted parameters */
2932
2933 static void
2934 change_speed(struct e100_serial *info)
2935 {
2936 unsigned int cflag;
2937 unsigned long xoff;
2938 unsigned long flags;
2939 /* first some safety checks */
2940
2941 if (!info->port.tty)
2942 return;
2943 if (!info->ioport)
2944 return;
2945
2946 cflag = info->port.tty->termios.c_cflag;
2947
2948 /* possibly, the tx/rx should be disabled first to do this safely */
2949
2950 /* change baud-rate and write it to the hardware */
2951 if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2952 /* Special baudrate */
2953 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2954 unsigned long alt_source =
2955 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2956 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2957 /* R_ALT_SER_BAUDRATE selects the source */
2958 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2959 (unsigned long)info->baud_base, info->custom_divisor));
2960 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2961 /* 0, 2-65535 (0=65536) */
2962 u16 divisor = info->custom_divisor;
2963 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2964 /* baudrate is 3.125MHz/custom_divisor */
2965 alt_source =
2966 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2967 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2968 alt_source = 0x11;
2969 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2970 *R_SERIAL_PRESCALE = divisor;
2971 info->baud = SERIAL_PRESCALE_BASE/divisor;
2972 }
2973 #ifdef CONFIG_ETRAX_EXTERN_PB6CLK_ENABLED
2974 else if ((info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8 &&
2975 info->custom_divisor == 1) ||
2976 (info->baud_base==CONFIG_ETRAX_EXTERN_PB6CLK_FREQ &&
2977 info->custom_divisor == 8)) {
2978 /* ext_clk selected */
2979 alt_source =
2980 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) |
2981 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern);
2982 DBAUD(printk("using external baudrate: %lu\n", CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8));
2983 info->baud = CONFIG_ETRAX_EXTERN_PB6CLK_FREQ/8;
2984 }
2985 #endif
2986 else
2987 {
2988 /* Bad baudbase, we don't support using timer0
2989 * for baudrate.
2990 */
2991 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
2992 (unsigned long)info->baud_base, info->custom_divisor);
2993 }
2994 r_alt_ser_baudrate_shadow &= ~mask;
2995 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2996 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2997 } else {
2998 /* Normal baudrate */
2999 /* Make sure we use normal baudrate */
3000 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
3001 unsigned long alt_source =
3002 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
3003 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
3004 r_alt_ser_baudrate_shadow &= ~mask;
3005 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
3006 #ifndef CONFIG_SVINTO_SIM
3007 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
3008 #endif /* CONFIG_SVINTO_SIM */
3009
3010 info->baud = cflag_to_baud(cflag);
3011 #ifndef CONFIG_SVINTO_SIM
3012 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
3013 #endif /* CONFIG_SVINTO_SIM */
3014 }
3015
3016 #ifndef CONFIG_SVINTO_SIM
3017 /* start with default settings and then fill in changes */
3018 local_irq_save(flags);
3019 /* 8 bit, no/even parity */
3020 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
3021 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
3022 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
3023
3024 /* 8 bit, no/even parity, 1 stop bit, no cts */
3025 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
3026 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
3027 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
3028 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
3029 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
3030
3031 if ((cflag & CSIZE) == CS7) {
3032 /* set 7 bit mode */
3033 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
3034 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
3035 }
3036
3037 if (cflag & CSTOPB) {
3038 /* set 2 stop bit mode */
3039 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
3040 }
3041
3042 if (cflag & PARENB) {
3043 /* enable parity */
3044 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
3045 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
3046 }
3047
3048 if (cflag & CMSPAR) {
3049 /* enable stick parity, PARODD mean Mark which matches ETRAX */
3050 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
3051 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
3052 }
3053 if (cflag & PARODD) {
3054 /* set odd parity (or Mark if CMSPAR) */
3055 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
3056 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
3057 }
3058
3059 if (cflag & CRTSCTS) {
3060 /* enable automatic CTS handling */
3061 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
3062 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
3063 }
3064
3065 /* make sure the tx and rx are enabled */
3066
3067 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
3068 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
3069
3070 /* actually write the control regs to the hardware */
3071
3072 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3073 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
3074 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
3075 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
3076 if (info->port.tty->termios.c_iflag & IXON ) {
3077 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
3078 STOP_CHAR(info->port.tty)));
3079 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
3080 }
3081
3082 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
3083 local_irq_restore(flags);
3084 #endif /* !CONFIG_SVINTO_SIM */
3085
3086 update_char_time(info);
3087
3088 } /* change_speed */
3089
3090 /* start transmitting chars NOW */
3091
3092 static void
3093 rs_flush_chars(struct tty_struct *tty)
3094 {
3095 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3096 unsigned long flags;
3097
3098 if (info->tr_running ||
3099 info->xmit.head == info->xmit.tail ||
3100 tty->stopped ||
3101 tty->hw_stopped ||
3102 !info->xmit.buf)
3103 return;
3104
3105 #ifdef SERIAL_DEBUG_FLOW
3106 printk("rs_flush_chars\n");
3107 #endif
3108
3109 /* this protection might not exactly be necessary here */
3110
3111 local_irq_save(flags);
3112 start_transmit(info);
3113 local_irq_restore(flags);
3114 }
3115
3116 static int rs_raw_write(struct tty_struct *tty,
3117 const unsigned char *buf, int count)
3118 {
3119 int c, ret = 0;
3120 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3121 unsigned long flags;
3122
3123 /* first some sanity checks */
3124
3125 if (!info->xmit.buf)
3126 return 0;
3127
3128 #ifdef SERIAL_DEBUG_DATA
3129 if (info->line == SERIAL_DEBUG_LINE)
3130 printk("rs_raw_write (%d), status %d\n",
3131 count, info->ioport[REG_STATUS]);
3132 #endif
3133
3134 #ifdef CONFIG_SVINTO_SIM
3135 /* Really simple. The output is here and now. */
3136 SIMCOUT(buf, count);
3137 return count;
3138 #endif
3139 local_save_flags(flags);
3140 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
3141 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
3142
3143
3144 /* The local_irq_disable/restore_flags pairs below are needed
3145 * because the DMA interrupt handler moves the info->xmit values.
3146 * the memcpy needs to be in the critical region unfortunately,
3147 * because we need to read xmit values, memcpy, write xmit values
3148 * in one atomic operation... this could perhaps be avoided by
3149 * more clever design.
3150 */
3151 local_irq_disable();
3152 while (count) {
3153 c = CIRC_SPACE_TO_END(info->xmit.head,
3154 info->xmit.tail,
3155 SERIAL_XMIT_SIZE);
3156
3157 if (count < c)
3158 c = count;
3159 if (c <= 0)
3160 break;
3161
3162 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3163 info->xmit.head = (info->xmit.head + c) &
3164 (SERIAL_XMIT_SIZE-1);
3165 buf += c;
3166 count -= c;
3167 ret += c;
3168 }
3169 local_irq_restore(flags);
3170
3171 /* enable transmitter if not running, unless the tty is stopped
3172 * this does not need IRQ protection since if tr_running == 0
3173 * the IRQ's are not running anyway for this port.
3174 */
3175 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3176
3177 if (info->xmit.head != info->xmit.tail &&
3178 !tty->stopped &&
3179 !tty->hw_stopped &&
3180 !info->tr_running) {
3181 start_transmit(info);
3182 }
3183
3184 return ret;
3185 } /* raw_raw_write() */
3186
3187 static int
3188 rs_write(struct tty_struct *tty,
3189 const unsigned char *buf, int count)
3190 {
3191 #if defined(CONFIG_ETRAX_RS485)
3192 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3193
3194 if (info->rs485.flags & SER_RS485_ENABLED)
3195 {
3196 /* If we are in RS-485 mode, we need to toggle RTS and disable
3197 * the receiver before initiating a DMA transfer
3198 */
3199 #ifdef CONFIG_ETRAX_FAST_TIMER
3200 /* Abort any started timer */
3201 fast_timers_rs485[info->line].function = NULL;
3202 del_fast_timer(&fast_timers_rs485[info->line]);
3203 #endif
3204 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3205 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3206 e100_disable_rx(info);
3207 e100_enable_rx_irq(info);
3208 #endif
3209 if (info->rs485.delay_rts_before_send > 0)
3210 msleep(info->rs485.delay_rts_before_send);
3211 }
3212 #endif /* CONFIG_ETRAX_RS485 */
3213
3214 count = rs_raw_write(tty, buf, count);
3215
3216 #if defined(CONFIG_ETRAX_RS485)
3217 if (info->rs485.flags & SER_RS485_ENABLED)
3218 {
3219 unsigned int val;
3220 /* If we are in RS-485 mode the following has to be done:
3221 * wait until DMA is ready
3222 * wait on transmit shift register
3223 * toggle RTS
3224 * enable the receiver
3225 */
3226
3227 /* Sleep until all sent */
3228 tty_wait_until_sent(tty, 0);
3229 #ifdef CONFIG_ETRAX_FAST_TIMER
3230 /* Now sleep a little more so that shift register is empty */
3231 schedule_usleep(info->char_time_usec * 2);
3232 #endif
3233 /* wait on transmit shift register */
3234 do{
3235 get_lsr_info(info, &val);
3236 }while (!(val & TIOCSER_TEMT));
3237
3238 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3239
3240 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3241 e100_enable_rx(info);
3242 e100_enable_rxdma_irq(info);
3243 #endif
3244 }
3245 #endif /* CONFIG_ETRAX_RS485 */
3246
3247 return count;
3248 } /* rs_write */
3249
3250
3251 /* how much space is available in the xmit buffer? */
3252
3253 static int
3254 rs_write_room(struct tty_struct *tty)
3255 {
3256 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3257
3258 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3259 }
3260
3261 /* How many chars are in the xmit buffer?
3262 * This does not include any chars in the transmitter FIFO.
3263 * Use wait_until_sent for waiting for FIFO drain.
3264 */
3265
3266 static int
3267 rs_chars_in_buffer(struct tty_struct *tty)
3268 {
3269 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3270
3271 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3272 }
3273
3274 /* discard everything in the xmit buffer */
3275
3276 static void
3277 rs_flush_buffer(struct tty_struct *tty)
3278 {
3279 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3280 unsigned long flags;
3281
3282 local_irq_save(flags);
3283 info->xmit.head = info->xmit.tail = 0;
3284 local_irq_restore(flags);
3285
3286 tty_wakeup(tty);
3287 }
3288
3289 /*
3290 * This function is used to send a high-priority XON/XOFF character to
3291 * the device
3292 *
3293 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3294 * but we do it in handle_ser_tx_interrupt().
3295 * We disable DMA channel and enable tx ready interrupt and write the
3296 * character when possible.
3297 */
3298 static void rs_send_xchar(struct tty_struct *tty, char ch)
3299 {
3300 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3301 unsigned long flags;
3302 local_irq_save(flags);
3303 if (info->uses_dma_out) {
3304 /* Put the DMA on hold and disable the channel */
3305 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3306 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3307 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3308 e100_disable_txdma_channel(info);
3309 }
3310
3311 /* Must make sure transmitter is not stopped before we can transmit */
3312 if (tty->stopped)
3313 rs_start(tty);
3314
3315 /* Enable manual transmit interrupt and send from there */
3316 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3317 info->x_char = ch;
3318 e100_enable_serial_tx_ready_irq(info);
3319 local_irq_restore(flags);
3320 }
3321
3322 /*
3323 * ------------------------------------------------------------
3324 * rs_throttle()
3325 *
3326 * This routine is called by the upper-layer tty layer to signal that
3327 * incoming characters should be throttled.
3328 * ------------------------------------------------------------
3329 */
3330 static void
3331 rs_throttle(struct tty_struct * tty)
3332 {
3333 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3334 #ifdef SERIAL_DEBUG_THROTTLE
3335 char buf[64];
3336
3337 printk("throttle %s: %lu....\n", tty_name(tty, buf),
3338 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3339 #endif
3340 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3341
3342 /* Do RTS before XOFF since XOFF might take some time */
3343 if (tty->termios.c_cflag & CRTSCTS) {
3344 /* Turn off RTS line */
3345 e100_rts(info, 0);
3346 }
3347 if (I_IXOFF(tty))
3348 rs_send_xchar(tty, STOP_CHAR(tty));
3349
3350 }
3351
3352 static void
3353 rs_unthrottle(struct tty_struct * tty)
3354 {
3355 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3356 #ifdef SERIAL_DEBUG_THROTTLE
3357 char buf[64];
3358
3359 printk("unthrottle %s: %lu....\n", tty_name(tty, buf),
3360 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3361 #endif
3362 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3363 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3364 /* Do RTS before XOFF since XOFF might take some time */
3365 if (tty->termios.c_cflag & CRTSCTS) {
3366 /* Assert RTS line */
3367 e100_rts(info, 1);
3368 }
3369
3370 if (I_IXOFF(tty)) {
3371 if (info->x_char)
3372 info->x_char = 0;
3373 else
3374 rs_send_xchar(tty, START_CHAR(tty));
3375 }
3376
3377 }
3378
3379 /*
3380 * ------------------------------------------------------------
3381 * rs_ioctl() and friends
3382 * ------------------------------------------------------------
3383 */
3384
3385 static int
3386 get_serial_info(struct e100_serial * info,
3387 struct serial_struct * retinfo)
3388 {
3389 struct serial_struct tmp;
3390
3391 /* this is all probably wrong, there are a lot of fields
3392 * here that we don't have in e100_serial and maybe we
3393 * should set them to something else than 0.
3394 */
3395
3396 if (!retinfo)
3397 return -EFAULT;
3398 memset(&tmp, 0, sizeof(tmp));
3399 tmp.type = info->type;
3400 tmp.line = info->line;
3401 tmp.port = (int)info->ioport;
3402 tmp.irq = info->irq;
3403 tmp.flags = info->flags;
3404 tmp.baud_base = info->baud_base;
3405 tmp.close_delay = info->close_delay;
3406 tmp.closing_wait = info->closing_wait;
3407 tmp.custom_divisor = info->custom_divisor;
3408 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3409 return -EFAULT;
3410 return 0;
3411 }
3412
3413 static int
3414 set_serial_info(struct e100_serial *info,
3415 struct serial_struct *new_info)
3416 {
3417 struct serial_struct new_serial;
3418 struct e100_serial old_info;
3419 int retval = 0;
3420
3421 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3422 return -EFAULT;
3423
3424 old_info = *info;
3425
3426 if (!capable(CAP_SYS_ADMIN)) {
3427 if ((new_serial.type != info->type) ||
3428 (new_serial.close_delay != info->close_delay) ||
3429 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3430 (info->flags & ~ASYNC_USR_MASK)))
3431 return -EPERM;
3432 info->flags = ((info->flags & ~ASYNC_USR_MASK) |
3433 (new_serial.flags & ASYNC_USR_MASK));
3434 goto check_and_exit;
3435 }
3436
3437 if (info->count > 1)
3438 return -EBUSY;
3439
3440 /*
3441 * OK, past this point, all the error checking has been done.
3442 * At this point, we start making changes.....
3443 */
3444
3445 info->baud_base = new_serial.baud_base;
3446 info->flags = ((info->flags & ~ASYNC_FLAGS) |
3447 (new_serial.flags & ASYNC_FLAGS));
3448 info->custom_divisor = new_serial.custom_divisor;
3449 info->type = new_serial.type;
3450 info->close_delay = new_serial.close_delay;
3451 info->closing_wait = new_serial.closing_wait;
3452 info->port.low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3453
3454 check_and_exit:
3455 if (info->flags & ASYNC_INITIALIZED) {
3456 change_speed(info);
3457 } else
3458 retval = startup(info);
3459 return retval;
3460 }
3461
3462 /*
3463 * get_lsr_info - get line status register info
3464 *
3465 * Purpose: Let user call ioctl() to get info when the UART physically
3466 * is emptied. On bus types like RS485, the transmitter must
3467 * release the bus after transmitting. This must be done when
3468 * the transmit shift register is empty, not be done when the
3469 * transmit holding register is empty. This functionality
3470 * allows an RS485 driver to be written in user space.
3471 */
3472 static int
3473 get_lsr_info(struct e100_serial * info, unsigned int *value)
3474 {
3475 unsigned int result = TIOCSER_TEMT;
3476 #ifndef CONFIG_SVINTO_SIM
3477 unsigned long curr_time = jiffies;
3478 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3479 unsigned long elapsed_usec =
3480 (curr_time - info->last_tx_active) * 1000000/HZ +
3481 curr_time_usec - info->last_tx_active_usec;
3482
3483 if (info->xmit.head != info->xmit.tail ||
3484 elapsed_usec < 2*info->char_time_usec) {
3485 result = 0;
3486 }
3487 #endif
3488
3489 if (copy_to_user(value, &result, sizeof(int)))
3490 return -EFAULT;
3491 return 0;
3492 }
3493
3494 #ifdef SERIAL_DEBUG_IO
3495 struct state_str
3496 {
3497 int state;
3498 const char *str;
3499 };
3500
3501 const struct state_str control_state_str[] = {
3502 {TIOCM_DTR, "DTR" },
3503 {TIOCM_RTS, "RTS"},
3504 {TIOCM_ST, "ST?" },
3505 {TIOCM_SR, "SR?" },
3506 {TIOCM_CTS, "CTS" },
3507 {TIOCM_CD, "CD" },
3508 {TIOCM_RI, "RI" },
3509 {TIOCM_DSR, "DSR" },
3510 {0, NULL }
3511 };
3512
3513 char *get_control_state_str(int MLines, char *s)
3514 {
3515 int i = 0;
3516
3517 s[0]='\0';
3518 while (control_state_str[i].str != NULL) {
3519 if (MLines & control_state_str[i].state) {
3520 if (s[0] != '\0') {
3521 strcat(s, ", ");
3522 }
3523 strcat(s, control_state_str[i].str);
3524 }
3525 i++;
3526 }
3527 return s;
3528 }
3529 #endif
3530
3531 static int
3532 rs_break(struct tty_struct *tty, int break_state)
3533 {
3534 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3535 unsigned long flags;
3536
3537 if (!info->ioport)
3538 return -EIO;
3539
3540 local_irq_save(flags);
3541 if (break_state == -1) {
3542 /* Go to manual mode and set the txd pin to 0 */
3543 /* Clear bit 7 (txd) and 6 (tr_enable) */
3544 info->tx_ctrl &= 0x3F;
3545 } else {
3546 /* Set bit 7 (txd) and 6 (tr_enable) */
3547 info->tx_ctrl |= (0x80 | 0x40);
3548 }
3549 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3550 local_irq_restore(flags);
3551 return 0;
3552 }
3553
3554 static int
3555 rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
3556 {
3557 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3558 unsigned long flags;
3559
3560 local_irq_save(flags);
3561
3562 if (clear & TIOCM_RTS)
3563 e100_rts(info, 0);
3564 if (clear & TIOCM_DTR)
3565 e100_dtr(info, 0);
3566 /* Handle FEMALE behaviour */
3567 if (clear & TIOCM_RI)
3568 e100_ri_out(info, 0);
3569 if (clear & TIOCM_CD)
3570 e100_cd_out(info, 0);
3571
3572 if (set & TIOCM_RTS)
3573 e100_rts(info, 1);
3574 if (set & TIOCM_DTR)
3575 e100_dtr(info, 1);
3576 /* Handle FEMALE behaviour */
3577 if (set & TIOCM_RI)
3578 e100_ri_out(info, 1);
3579 if (set & TIOCM_CD)
3580 e100_cd_out(info, 1);
3581
3582 local_irq_restore(flags);
3583 return 0;
3584 }
3585
3586 static int
3587 rs_tiocmget(struct tty_struct *tty)
3588 {
3589 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3590 unsigned int result;
3591 unsigned long flags;
3592
3593 local_irq_save(flags);
3594
3595 result =
3596 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3597 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3598 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3599 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3600 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3601 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3602
3603 local_irq_restore(flags);
3604
3605 #ifdef SERIAL_DEBUG_IO
3606 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3607 info->line, result, result);
3608 {
3609 char s[100];
3610
3611 get_control_state_str(result, s);
3612 printk(KERN_DEBUG "state: %s\n", s);
3613 }
3614 #endif
3615 return result;
3616
3617 }
3618
3619
3620 static int
3621 rs_ioctl(struct tty_struct *tty,
3622 unsigned int cmd, unsigned long arg)
3623 {
3624 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3625
3626 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3627 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3628 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3629 if (tty->flags & (1 << TTY_IO_ERROR))
3630 return -EIO;
3631 }
3632
3633 switch (cmd) {
3634 case TIOCGSERIAL:
3635 return get_serial_info(info,
3636 (struct serial_struct *) arg);
3637 case TIOCSSERIAL:
3638 return set_serial_info(info,
3639 (struct serial_struct *) arg);
3640 case TIOCSERGETLSR: /* Get line status register */
3641 return get_lsr_info(info, (unsigned int *) arg);
3642
3643 case TIOCSERGSTRUCT:
3644 if (copy_to_user((struct e100_serial *) arg,
3645 info, sizeof(struct e100_serial)))
3646 return -EFAULT;
3647 return 0;
3648
3649 #if defined(CONFIG_ETRAX_RS485)
3650 case TIOCSERSETRS485:
3651 {
3652 /* In this ioctl we still use the old structure
3653 * rs485_control for backward compatibility
3654 * (if we use serial_rs485, then old user-level code
3655 * wouldn't work anymore...).
3656 * The use of this ioctl is deprecated: use TIOCSRS485
3657 * instead.*/
3658 struct rs485_control rs485ctrl;
3659 struct serial_rs485 rs485data;
3660 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3661 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3662 sizeof(rs485ctrl)))
3663 return -EFAULT;
3664
3665 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3666 rs485data.flags = 0;
3667
3668 if (rs485ctrl.enabled)
3669 rs485data.flags |= SER_RS485_ENABLED;
3670 else
3671 rs485data.flags &= ~(SER_RS485_ENABLED);
3672
3673 if (rs485ctrl.rts_on_send)
3674 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3675 else
3676 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3677
3678 if (rs485ctrl.rts_after_sent)
3679 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3680 else
3681 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3682
3683 return e100_enable_rs485(tty, &rs485data);
3684 }
3685
3686 case TIOCSRS485:
3687 {
3688 /* This is the new version of TIOCSRS485, with new
3689 * data structure serial_rs485 */
3690 struct serial_rs485 rs485data;
3691 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3692 sizeof(rs485data)))
3693 return -EFAULT;
3694
3695 return e100_enable_rs485(tty, &rs485data);
3696 }
3697
3698 case TIOCGRS485:
3699 {
3700 struct serial_rs485 *rs485data =
3701 &(((struct e100_serial *)tty->driver_data)->rs485);
3702 /* This is the ioctl to get RS485 data from user-space */
3703 if (copy_to_user((struct serial_rs485 *) arg,
3704 rs485data,
3705 sizeof(struct serial_rs485)))
3706 return -EFAULT;
3707 break;
3708 }
3709
3710 case TIOCSERWRRS485:
3711 {
3712 struct rs485_write rs485wr;
3713 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3714 sizeof(rs485wr)))
3715 return -EFAULT;
3716
3717 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3718 }
3719 #endif
3720
3721 default:
3722 return -ENOIOCTLCMD;
3723 }
3724 return 0;
3725 }
3726
3727 static void
3728 rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3729 {
3730 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3731
3732 change_speed(info);
3733
3734 /* Handle turning off CRTSCTS */
3735 if ((old_termios->c_cflag & CRTSCTS) &&
3736 !(tty->termios.c_cflag & CRTSCTS)) {
3737 tty->hw_stopped = 0;
3738 rs_start(tty);
3739 }
3740
3741 }
3742
3743 /*
3744 * ------------------------------------------------------------
3745 * rs_close()
3746 *
3747 * This routine is called when the serial port gets closed. First, we
3748 * wait for the last remaining data to be sent. Then, we unlink its
3749 * S structure from the interrupt chain if necessary, and we free
3750 * that IRQ if nothing is left in the chain.
3751 * ------------------------------------------------------------
3752 */
3753 static void
3754 rs_close(struct tty_struct *tty, struct file * filp)
3755 {
3756 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3757 unsigned long flags;
3758
3759 if (!info)
3760 return;
3761
3762 /* interrupts are disabled for this entire function */
3763
3764 local_irq_save(flags);
3765
3766 if (tty_hung_up_p(filp)) {
3767 local_irq_restore(flags);
3768 return;
3769 }
3770
3771 #ifdef SERIAL_DEBUG_OPEN
3772 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3773 info->line, info->count);
3774 #endif
3775 if ((tty->count == 1) && (info->count != 1)) {
3776 /*
3777 * Uh, oh. tty->count is 1, which means that the tty
3778 * structure will be freed. Info->count should always
3779 * be one in these conditions. If it's greater than
3780 * one, we've got real problems, since it means the
3781 * serial port won't be shutdown.
3782 */
3783 printk(KERN_ERR
3784 "rs_close: bad serial port count; tty->count is 1, "
3785 "info->count is %d\n", info->count);
3786 info->count = 1;
3787 }
3788 if (--info->count < 0) {
3789 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
3790 info->line, info->count);
3791 info->count = 0;
3792 }
3793 if (info->count) {
3794 local_irq_restore(flags);
3795 return;
3796 }
3797 info->flags |= ASYNC_CLOSING;
3798 /*
3799 * Save the termios structure, since this port may have
3800 * separate termios for callout and dialin.
3801 */
3802 if (info->flags & ASYNC_NORMAL_ACTIVE)
3803 info->normal_termios = tty->termios;
3804 /*
3805 * Now we wait for the transmit buffer to clear; and we notify
3806 * the line discipline to only process XON/XOFF characters.
3807 */
3808 tty->closing = 1;
3809 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
3810 tty_wait_until_sent(tty, info->closing_wait);
3811 /*
3812 * At this point we stop accepting input. To do this, we
3813 * disable the serial receiver and the DMA receive interrupt.
3814 */
3815 #ifdef SERIAL_HANDLE_EARLY_ERRORS
3816 e100_disable_serial_data_irq(info);
3817 #endif
3818
3819 #ifndef CONFIG_SVINTO_SIM
3820 e100_disable_rx(info);
3821 e100_disable_rx_irq(info);
3822
3823 if (info->flags & ASYNC_INITIALIZED) {
3824 /*
3825 * Before we drop DTR, make sure the UART transmitter
3826 * has completely drained; this is especially
3827 * important as we have a transmit FIFO!
3828 */
3829 rs_wait_until_sent(tty, HZ);
3830 }
3831 #endif
3832
3833 shutdown(info);
3834 rs_flush_buffer(tty);
3835 tty_ldisc_flush(tty);
3836 tty->closing = 0;
3837 info->event = 0;
3838 info->port.tty = NULL;
3839 if (info->blocked_open) {
3840 if (info->close_delay)
3841 schedule_timeout_interruptible(info->close_delay);
3842 wake_up_interruptible(&info->open_wait);
3843 }
3844 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3845 wake_up_interruptible(&info->close_wait);
3846 local_irq_restore(flags);
3847
3848 /* port closed */
3849
3850 #if defined(CONFIG_ETRAX_RS485)
3851 if (info->rs485.flags & SER_RS485_ENABLED) {
3852 info->rs485.flags &= ~(SER_RS485_ENABLED);
3853 #if defined(CONFIG_ETRAX_RS485_ON_PA)
3854 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3855 #endif
3856 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
3857 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3858 rs485_port_g_bit, 0);
3859 #endif
3860 #if defined(CONFIG_ETRAX_RS485_LTC1387)
3861 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3862 CONFIG_ETRAX_RS485_LTC1387_DXEN_PORT_G_BIT, 0);
3863 REG_SHADOW_SET(R_PORT_G_DATA, port_g_data_shadow,
3864 CONFIG_ETRAX_RS485_LTC1387_RXEN_PORT_G_BIT, 0);
3865 #endif
3866 }
3867 #endif
3868
3869 /*
3870 * Release any allocated DMA irq's.
3871 */
3872 if (info->dma_in_enabled) {
3873 free_irq(info->dma_in_irq_nbr, info);
3874 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3875 info->uses_dma_in = 0;
3876 #ifdef SERIAL_DEBUG_OPEN
3877 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3878 info->dma_in_irq_description);
3879 #endif
3880 }
3881 if (info->dma_out_enabled) {
3882 free_irq(info->dma_out_irq_nbr, info);
3883 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3884 info->uses_dma_out = 0;
3885 #ifdef SERIAL_DEBUG_OPEN
3886 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3887 info->dma_out_irq_description);
3888 #endif
3889 }
3890 }
3891
3892 /*
3893 * rs_wait_until_sent() --- wait until the transmitter is empty
3894 */
3895 static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3896 {
3897 unsigned long orig_jiffies;
3898 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3899 unsigned long curr_time = jiffies;
3900 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3901 long elapsed_usec =
3902 (curr_time - info->last_tx_active) * (1000000/HZ) +
3903 curr_time_usec - info->last_tx_active_usec;
3904
3905 /*
3906 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3907 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3908 */
3909 orig_jiffies = jiffies;
3910 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3911 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3912 (elapsed_usec < 2*info->char_time_usec)) {
3913 schedule_timeout_interruptible(1);
3914 if (signal_pending(current))
3915 break;
3916 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3917 break;
3918 curr_time = jiffies;
3919 curr_time_usec = GET_JIFFIES_USEC();
3920 elapsed_usec =
3921 (curr_time - info->last_tx_active) * (1000000/HZ) +
3922 curr_time_usec - info->last_tx_active_usec;
3923 }
3924 set_current_state(TASK_RUNNING);
3925 }
3926
3927 /*
3928 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3929 */
3930 void
3931 rs_hangup(struct tty_struct *tty)
3932 {
3933 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3934
3935 rs_flush_buffer(tty);
3936 shutdown(info);
3937 info->event = 0;
3938 info->count = 0;
3939 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3940 info->port.tty = NULL;
3941 wake_up_interruptible(&info->open_wait);
3942 }
3943
3944 /*
3945 * ------------------------------------------------------------
3946 * rs_open() and friends
3947 * ------------------------------------------------------------
3948 */
3949 static int
3950 block_til_ready(struct tty_struct *tty, struct file * filp,
3951 struct e100_serial *info)
3952 {
3953 DECLARE_WAITQUEUE(wait, current);
3954 unsigned long flags;
3955 int retval;
3956 int do_clocal = 0, extra_count = 0;
3957
3958 /*
3959 * If the device is in the middle of being closed, then block
3960 * until it's done, and then try again.
3961 */
3962 if (tty_hung_up_p(filp) ||
3963 (info->flags & ASYNC_CLOSING)) {
3964 wait_event_interruptible_tty(tty, info->close_wait,
3965 !(info->flags & ASYNC_CLOSING));
3966 #ifdef SERIAL_DO_RESTART
3967 if (info->flags & ASYNC_HUP_NOTIFY)
3968 return -EAGAIN;
3969 else
3970 return -ERESTARTSYS;
3971 #else
3972 return -EAGAIN;
3973 #endif
3974 }
3975
3976 /*
3977 * If non-blocking mode is set, or the port is not enabled,
3978 * then make the check up front and then exit.
3979 */
3980 if ((filp->f_flags & O_NONBLOCK) ||
3981 (tty->flags & (1 << TTY_IO_ERROR))) {
3982 info->flags |= ASYNC_NORMAL_ACTIVE;
3983 return 0;
3984 }
3985
3986 if (tty->termios.c_cflag & CLOCAL) {
3987 do_clocal = 1;
3988 }
3989
3990 /*
3991 * Block waiting for the carrier detect and the line to become
3992 * free (i.e., not in use by the callout). While we are in
3993 * this loop, info->count is dropped by one, so that
3994 * rs_close() knows when to free things. We restore it upon
3995 * exit, either normal or abnormal.
3996 */
3997 retval = 0;
3998 add_wait_queue(&info->open_wait, &wait);
3999 #ifdef SERIAL_DEBUG_OPEN
4000 printk("block_til_ready before block: ttyS%d, count = %d\n",
4001 info->line, info->count);
4002 #endif
4003 local_irq_save(flags);
4004 if (!tty_hung_up_p(filp)) {
4005 extra_count++;
4006 info->count--;
4007 }
4008 local_irq_restore(flags);
4009 info->blocked_open++;
4010 while (1) {
4011 local_irq_save(flags);
4012 /* assert RTS and DTR */
4013 e100_rts(info, 1);
4014 e100_dtr(info, 1);
4015 local_irq_restore(flags);
4016 set_current_state(TASK_INTERRUPTIBLE);
4017 if (tty_hung_up_p(filp) ||
4018 !(info->flags & ASYNC_INITIALIZED)) {
4019 #ifdef SERIAL_DO_RESTART
4020 if (info->flags & ASYNC_HUP_NOTIFY)
4021 retval = -EAGAIN;
4022 else
4023 retval = -ERESTARTSYS;
4024 #else
4025 retval = -EAGAIN;
4026 #endif
4027 break;
4028 }
4029 if (!(info->flags & ASYNC_CLOSING) && do_clocal)
4030 /* && (do_clocal || DCD_IS_ASSERTED) */
4031 break;
4032 if (signal_pending(current)) {
4033 retval = -ERESTARTSYS;
4034 break;
4035 }
4036 #ifdef SERIAL_DEBUG_OPEN
4037 printk("block_til_ready blocking: ttyS%d, count = %d\n",
4038 info->line, info->count);
4039 #endif
4040 tty_unlock(tty);
4041 schedule();
4042 tty_lock(tty);
4043 }
4044 set_current_state(TASK_RUNNING);
4045 remove_wait_queue(&info->open_wait, &wait);
4046 if (extra_count)
4047 info->count++;
4048 info->blocked_open--;
4049 #ifdef SERIAL_DEBUG_OPEN
4050 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
4051 info->line, info->count);
4052 #endif
4053 if (retval)
4054 return retval;
4055 info->flags |= ASYNC_NORMAL_ACTIVE;
4056 return 0;
4057 }
4058
4059 static void
4060 deinit_port(struct e100_serial *info)
4061 {
4062 if (info->dma_out_enabled) {
4063 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
4064 free_irq(info->dma_out_irq_nbr, info);
4065 }
4066 if (info->dma_in_enabled) {
4067 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
4068 free_irq(info->dma_in_irq_nbr, info);
4069 }
4070 }
4071
4072 /*
4073 * This routine is called whenever a serial port is opened.
4074 * It performs the serial-specific initialization for the tty structure.
4075 */
4076 static int
4077 rs_open(struct tty_struct *tty, struct file * filp)
4078 {
4079 struct e100_serial *info;
4080 int retval;
4081 int allocated_resources = 0;
4082
4083 info = rs_table + tty->index;
4084 if (!info->enabled)
4085 return -ENODEV;
4086
4087 #ifdef SERIAL_DEBUG_OPEN
4088 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
4089 info->count);
4090 #endif
4091
4092 info->count++;
4093 tty->driver_data = info;
4094 info->port.tty = tty;
4095
4096 info->port.low_latency = !!(info->flags & ASYNC_LOW_LATENCY);
4097
4098 /*
4099 * If the port is in the middle of closing, bail out now
4100 */
4101 if (tty_hung_up_p(filp) ||
4102 (info->flags & ASYNC_CLOSING)) {
4103 wait_event_interruptible_tty(tty, info->close_wait,
4104 !(info->flags & ASYNC_CLOSING));
4105 #ifdef SERIAL_DO_RESTART
4106 return ((info->flags & ASYNC_HUP_NOTIFY) ?
4107 -EAGAIN : -ERESTARTSYS);
4108 #else
4109 return -EAGAIN;
4110 #endif
4111 }
4112
4113 /*
4114 * If DMA is enabled try to allocate the irq's.
4115 */
4116 if (info->count == 1) {
4117 allocated_resources = 1;
4118 if (info->dma_in_enabled) {
4119 if (request_irq(info->dma_in_irq_nbr,
4120 rec_interrupt,
4121 info->dma_in_irq_flags,
4122 info->dma_in_irq_description,
4123 info)) {
4124 printk(KERN_WARNING "DMA irq '%s' busy; "
4125 "falling back to non-DMA mode\n",
4126 info->dma_in_irq_description);
4127 /* Make sure we never try to use DMA in */
4128 /* for the port again. */
4129 info->dma_in_enabled = 0;
4130 } else if (cris_request_dma(info->dma_in_nbr,
4131 info->dma_in_irq_description,
4132 DMA_VERBOSE_ON_ERROR,
4133 info->dma_owner)) {
4134 free_irq(info->dma_in_irq_nbr, info);
4135 printk(KERN_WARNING "DMA '%s' busy; "
4136 "falling back to non-DMA mode\n",
4137 info->dma_in_irq_description);
4138 /* Make sure we never try to use DMA in */
4139 /* for the port again. */
4140 info->dma_in_enabled = 0;
4141 }
4142 #ifdef SERIAL_DEBUG_OPEN
4143 else
4144 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4145 info->dma_in_irq_description);
4146 #endif
4147 }
4148 if (info->dma_out_enabled) {
4149 if (request_irq(info->dma_out_irq_nbr,
4150 tr_interrupt,
4151 info->dma_out_irq_flags,
4152 info->dma_out_irq_description,
4153 info)) {
4154 printk(KERN_WARNING "DMA irq '%s' busy; "
4155 "falling back to non-DMA mode\n",
4156 info->dma_out_irq_description);
4157 /* Make sure we never try to use DMA out */
4158 /* for the port again. */
4159 info->dma_out_enabled = 0;
4160 } else if (cris_request_dma(info->dma_out_nbr,
4161 info->dma_out_irq_description,
4162 DMA_VERBOSE_ON_ERROR,
4163 info->dma_owner)) {
4164 free_irq(info->dma_out_irq_nbr, info);
4165 printk(KERN_WARNING "DMA '%s' busy; "
4166 "falling back to non-DMA mode\n",
4167 info->dma_out_irq_description);
4168 /* Make sure we never try to use DMA out */
4169 /* for the port again. */
4170 info->dma_out_enabled = 0;
4171 }
4172 #ifdef SERIAL_DEBUG_OPEN
4173 else
4174 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
4175 info->dma_out_irq_description);
4176 #endif
4177 }
4178 }
4179
4180 /*
4181 * Start up the serial port
4182 */
4183
4184 retval = startup(info);
4185 if (retval) {
4186 if (allocated_resources)
4187 deinit_port(info);
4188
4189 /* FIXME Decrease count info->count here too? */
4190 return retval;
4191 }
4192
4193
4194 retval = block_til_ready(tty, filp, info);
4195 if (retval) {
4196 #ifdef SERIAL_DEBUG_OPEN
4197 printk("rs_open returning after block_til_ready with %d\n",
4198 retval);
4199 #endif
4200 if (allocated_resources)
4201 deinit_port(info);
4202
4203 return retval;
4204 }
4205
4206 if ((info->count == 1) && (info->flags & ASYNC_SPLIT_TERMIOS)) {
4207 tty->termios = info->normal_termios;
4208 change_speed(info);
4209 }
4210
4211 #ifdef SERIAL_DEBUG_OPEN
4212 printk("rs_open ttyS%d successful...\n", info->line);
4213 #endif
4214 DLOG_INT_TRIG( log_int_pos = 0);
4215
4216 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4217 info->icount.rx = 0;
4218 } );
4219
4220 return 0;
4221 }
4222
4223 #ifdef CONFIG_PROC_FS
4224 /*
4225 * /proc fs routines....
4226 */
4227
4228 static void seq_line_info(struct seq_file *m, struct e100_serial *info)
4229 {
4230 unsigned long tmp;
4231
4232 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4233 info->line, (unsigned long)info->ioport, info->irq);
4234
4235 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
4236 seq_printf(m, "\n");
4237 return;
4238 }
4239
4240 seq_printf(m, " baud:%d", info->baud);
4241 seq_printf(m, " tx:%lu rx:%lu",
4242 (unsigned long)info->icount.tx,
4243 (unsigned long)info->icount.rx);
4244 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4245 if (tmp)
4246 seq_printf(m, " tx_pend:%lu/%lu",
4247 (unsigned long)tmp,
4248 (unsigned long)SERIAL_XMIT_SIZE);
4249
4250 seq_printf(m, " rx_pend:%lu/%lu",
4251 (unsigned long)info->recv_cnt,
4252 (unsigned long)info->max_recv_cnt);
4253
4254 #if 1
4255 if (info->port.tty) {
4256 if (info->port.tty->stopped)
4257 seq_printf(m, " stopped:%i",
4258 (int)info->port.tty->stopped);
4259 if (info->port.tty->hw_stopped)
4260 seq_printf(m, " hw_stopped:%i",
4261 (int)info->port.tty->hw_stopped);
4262 }
4263
4264 {
4265 unsigned char rstat = info->ioport[REG_STATUS];
4266 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4267 seq_printf(m, " xoff_detect:1");
4268 }
4269
4270 #endif
4271
4272 if (info->icount.frame)
4273 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4274
4275 if (info->icount.parity)
4276 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4277
4278 if (info->icount.brk)
4279 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4280
4281 if (info->icount.overrun)
4282 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4283
4284 /*
4285 * Last thing is the RS-232 status lines
4286 */
4287 if (!E100_RTS_GET(info))
4288 seq_puts(m, "|RTS");
4289 if (!E100_CTS_GET(info))
4290 seq_puts(m, "|CTS");
4291 if (!E100_DTR_GET(info))
4292 seq_puts(m, "|DTR");
4293 if (!E100_DSR_GET(info))
4294 seq_puts(m, "|DSR");
4295 if (!E100_CD_GET(info))
4296 seq_puts(m, "|CD");
4297 if (!E100_RI_GET(info))
4298 seq_puts(m, "|RI");
4299 seq_puts(m, "\n");
4300 }
4301
4302
4303 static int crisv10_proc_show(struct seq_file *m, void *v)
4304 {
4305 int i;
4306
4307 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4308
4309 for (i = 0; i < NR_PORTS; i++) {
4310 if (!rs_table[i].enabled)
4311 continue;
4312 seq_line_info(m, &rs_table[i]);
4313 }
4314 #ifdef DEBUG_LOG_INCLUDED
4315 for (i = 0; i < debug_log_pos; i++) {
4316 seq_printf(m, "%-4i %lu.%lu ",
4317 i, debug_log[i].time,
4318 timer_data_to_ns(debug_log[i].timer_data));
4319 seq_printf(m, debug_log[i].string, debug_log[i].value);
4320 }
4321 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4322 debug_log_pos = 0;
4323 #endif
4324 return 0;
4325 }
4326
4327 static int crisv10_proc_open(struct inode *inode, struct file *file)
4328 {
4329 return single_open(file, crisv10_proc_show, NULL);
4330 }
4331
4332 static const struct file_operations crisv10_proc_fops = {
4333 .owner = THIS_MODULE,
4334 .open = crisv10_proc_open,
4335 .read = seq_read,
4336 .llseek = seq_lseek,
4337 .release = single_release,
4338 };
4339 #endif
4340
4341
4342 /* Finally, routines used to initialize the serial driver. */
4343
4344 static void show_serial_version(void)
4345 {
4346 printk(KERN_INFO
4347 "ETRAX 100LX serial-driver %s, "
4348 "(c) 2000-2004 Axis Communications AB\r\n",
4349 &serial_version[11]); /* "$Revision: x.yy" */
4350 }
4351
4352 /* rs_init inits the driver at boot (using the module_init chain) */
4353
4354 static const struct tty_operations rs_ops = {
4355 .open = rs_open,
4356 .close = rs_close,
4357 .write = rs_write,
4358 .flush_chars = rs_flush_chars,
4359 .write_room = rs_write_room,
4360 .chars_in_buffer = rs_chars_in_buffer,
4361 .flush_buffer = rs_flush_buffer,
4362 .ioctl = rs_ioctl,
4363 .throttle = rs_throttle,
4364 .unthrottle = rs_unthrottle,
4365 .set_termios = rs_set_termios,
4366 .stop = rs_stop,
4367 .start = rs_start,
4368 .hangup = rs_hangup,
4369 .break_ctl = rs_break,
4370 .send_xchar = rs_send_xchar,
4371 .wait_until_sent = rs_wait_until_sent,
4372 .tiocmget = rs_tiocmget,
4373 .tiocmset = rs_tiocmset,
4374 #ifdef CONFIG_PROC_FS
4375 .proc_fops = &crisv10_proc_fops,
4376 #endif
4377 };
4378
4379 static int __init rs_init(void)
4380 {
4381 int i;
4382 struct e100_serial *info;
4383 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4384
4385 if (!driver)
4386 return -ENOMEM;
4387
4388 show_serial_version();
4389
4390 /* Setup the timed flush handler system */
4391
4392 #if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4393 setup_timer(&flush_timer, timed_flush_handler, 0);
4394 mod_timer(&flush_timer, jiffies + 5);
4395 #endif
4396
4397 #if defined(CONFIG_ETRAX_RS485)
4398 #if defined(CONFIG_ETRAX_RS485_ON_PA)
4399 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
4400 rs485_pa_bit)) {
4401 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
4402 "RS485 pin\n");
4403 put_tty_driver(driver);
4404 return -EBUSY;
4405 }
4406 #endif
4407 #if defined(CONFIG_ETRAX_RS485_ON_PORT_G)
4408 if (cris_io_interface_allocate_pins(if_serial_0, 'g', rs485_pa_bit,
4409 rs485_port_g_bit)) {
4410 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
4411 "RS485 pin\n");
4412 put_tty_driver(driver);
4413 return -EBUSY;
4414 }
4415 #endif
4416 #endif
4417
4418 /* Initialize the tty_driver structure */
4419
4420 driver->driver_name = "serial";
4421 driver->name = "ttyS";
4422 driver->major = TTY_MAJOR;
4423 driver->minor_start = 64;
4424 driver->type = TTY_DRIVER_TYPE_SERIAL;
4425 driver->subtype = SERIAL_TYPE_NORMAL;
4426 driver->init_termios = tty_std_termios;
4427 driver->init_termios.c_cflag =
4428 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4429 driver->init_termios.c_ispeed = 115200;
4430 driver->init_termios.c_ospeed = 115200;
4431 driver->flags = TTY_DRIVER_REAL_RAW;
4432
4433 tty_set_operations(driver, &rs_ops);
4434 serial_driver = driver;
4435
4436 /* do some initializing for the separate ports */
4437 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4438 if (info->enabled) {
4439 if (cris_request_io_interface(info->io_if,
4440 info->io_if_description)) {
4441 printk(KERN_ERR "ETRAX100LX async serial: "
4442 "Could not allocate IO pins for "
4443 "%s, port %d\n",
4444 info->io_if_description, i);
4445 info->enabled = 0;
4446 }
4447 }
4448 tty_port_init(&info->port);
4449 info->uses_dma_in = 0;
4450 info->uses_dma_out = 0;
4451 info->line = i;
4452 info->port.tty = NULL;
4453 info->type = PORT_ETRAX;
4454 info->tr_running = 0;
4455 info->forced_eop = 0;
4456 info->baud_base = DEF_BAUD_BASE;
4457 info->custom_divisor = 0;
4458 info->flags = 0;
4459 info->close_delay = 5*HZ/10;
4460 info->closing_wait = 30*HZ;
4461 info->x_char = 0;
4462 info->event = 0;
4463 info->count = 0;
4464 info->blocked_open = 0;
4465 info->normal_termios = driver->init_termios;
4466 init_waitqueue_head(&info->open_wait);
4467 init_waitqueue_head(&info->close_wait);
4468 info->xmit.buf = NULL;
4469 info->xmit.tail = info->xmit.head = 0;
4470 info->first_recv_buffer = info->last_recv_buffer = NULL;
4471 info->recv_cnt = info->max_recv_cnt = 0;
4472 info->last_tx_active_usec = 0;
4473 info->last_tx_active = 0;
4474
4475 #if defined(CONFIG_ETRAX_RS485)
4476 /* Set sane defaults */
4477 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4478 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4479 info->rs485.delay_rts_before_send = 0;
4480 info->rs485.flags &= ~(SER_RS485_ENABLED);
4481 #endif
4482 INIT_WORK(&info->work, do_softint);
4483
4484 if (info->enabled) {
4485 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4486 serial_driver->name, info->line, info->ioport);
4487 }
4488 tty_port_link_device(&info->port, driver, i);
4489 }
4490
4491 if (tty_register_driver(driver))
4492 panic("Couldn't register serial driver\n");
4493
4494 #ifdef CONFIG_ETRAX_FAST_TIMER
4495 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4496 memset(fast_timers, 0, sizeof(fast_timers));
4497 #endif
4498 #ifdef CONFIG_ETRAX_RS485
4499 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4500 #endif
4501 fast_timer_init();
4502 #endif
4503
4504 #ifndef CONFIG_SVINTO_SIM
4505 #ifndef CONFIG_ETRAX_KGDB
4506 /* Not needed in simulator. May only complicate stuff. */
4507 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4508
4509 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4510 IRQF_SHARED, "serial ", driver))
4511 panic("%s: Failed to request irq8", __func__);
4512
4513 #endif
4514 #endif /* CONFIG_SVINTO_SIM */
4515
4516 return 0;
4517 }
4518
4519 /* this makes sure that rs_init is called during kernel boot */
4520
4521 module_init(rs_init);
kernel source for telekom puls (alcatel/mediatek)