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Merge tag 'v3.10.73' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include "8250.h"
29
30 #undef SERIAL_DEBUG_PCI
31
32 /*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38 struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
43 int (*probe)(struct pci_dev *dev);
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_8250_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_8250_port *, int);
63
64 static void moan_device(const char *str, struct pci_dev *dev)
65 {
66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to <linux-serial@vger.kernel.org>.\n",
72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74 }
75
76 static int
77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
78 int bar, int offset, int regshift)
79 {
80 struct pci_dev *dev = priv->dev;
81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 base = pci_resource_start(dev, bar);
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
101 } else {
102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
107 }
108 return 0;
109 }
110
111 /*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114 static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board,
116 struct uart_8250_port *port, int idx)
117 {
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135 }
136
137 /*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141 static int
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_8250_port *port, int idx)
144 {
145 unsigned int bar, offset = board->first_offset;
146
147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
155 return setup_port(priv, port, bar, offset, board->reg_shift);
156 }
157
158 /*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
165 static int pci_hp_diva_init(struct pci_dev *dev)
166 {
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
184 rc = 1;
185 break;
186 }
187
188 return rc;
189 }
190
191 /*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195 static int
196 pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
198 struct uart_8250_port *port, int idx)
199 {
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
203 switch (priv->dev->subsystem_device) {
204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
220 return setup_port(priv, port, bar, offset, board->reg_shift);
221 }
222
223 /*
224 * Added for EKF Intel i960 serial boards
225 */
226 static int pci_inteli960ni_init(struct pci_dev *dev)
227 {
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240 }
241
242 /*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
248 static int pci_plx9050_init(struct pci_dev *dev)
249 {
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
261 irq_config = 0x43;
262
263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
274 /*
275 * enable/disable interrupts
276 */
277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289 }
290
291 static void pci_plx9050_exit(struct pci_dev *dev)
292 {
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311 }
312
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
315
316 static void pci_ni8420_exit(struct pci_dev *dev)
317 {
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337 }
338
339
340 /* MITE registers */
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
345
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
348 static void pci_ni8430_exit(struct pci_dev *dev)
349 {
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368 }
369
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371 static int
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_8250_port *port, int idx)
374 {
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
388 return setup_port(priv, port, bar, offset, board->reg_shift);
389 }
390
391 /*
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
396 */
397
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
400
401 static int sbs_init(struct pci_dev *dev)
402 {
403 u8 __iomem *p;
404
405 p = pci_ioremap_bar(dev, 0);
406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410 writeb(0x10, p + OCT_REG_CR_OFF);
411 udelay(50);
412 writeb(0x0, p + OCT_REG_CR_OFF);
413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419 }
420
421 /*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
425 static void sbs_exit(struct pci_dev *dev)
426 {
427 u8 __iomem *p;
428
429 p = pci_ioremap_bar(dev, 0);
430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
432 writeb(0, p + OCT_REG_CR_OFF);
433 iounmap(p);
434 }
435
436 /*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
439 * (except cards equipped with 4 UARTs) and initial clocking settings
440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
448 *
449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466 static int pci_siig10x_init(struct pci_dev *dev)
467 {
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491 }
492
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496 static int pci_siig20x_init(struct pci_dev *dev)
497 {
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511 }
512
513 static int pci_siig_init(struct pci_dev *dev)
514 {
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524 }
525
526 static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board,
528 struct uart_8250_port *port, int idx)
529 {
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538 }
539
540 /*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
545 static const unsigned short timedia_single_port[] = {
546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 };
548
549 static const unsigned short timedia_dual_port[] = {
550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555 };
556
557 static const unsigned short timedia_quad_port[] = {
558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562 };
563
564 static const unsigned short timedia_eight_port[] = {
565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 };
568
569 static const struct timedia_struct {
570 int num;
571 const unsigned short *ids;
572 } timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
576 { 8, timedia_eight_port }
577 };
578
579 /*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585 static int pci_timedia_probe(struct pci_dev *dev)
586 {
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599 }
600
601 static int pci_timedia_init(struct pci_dev *dev)
602 {
603 const unsigned short *ids;
604 int i, j;
605
606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613 }
614
615 /*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619 static int
620 pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
622 struct uart_8250_port *port, int idx)
623 {
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
639 /* FALLTHROUGH */
640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649
650 /*
651 * Some Titan cards are also a little weird
652 */
653 static int
654 titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board,
656 struct uart_8250_port *port, int idx)
657 {
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
672 return setup_port(priv, port, bar, offset, board->reg_shift);
673 }
674
675 static int pci_xircom_init(struct pci_dev *dev)
676 {
677 msleep(100);
678 return 0;
679 }
680
681 static int pci_ni8420_init(struct pci_dev *dev)
682 {
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704 }
705
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713 static int pci_ni8430_init(struct pci_dev *dev)
714 {
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748 }
749
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754 static int
755 pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
757 struct uart_8250_port *port, int idx)
758 {
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
773 /* enable the transceiver */
774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780 }
781
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
784 struct uart_8250_port *port, int idx)
785 {
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798 }
799
800 /* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837 }
838
839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 return 0;
847
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
866 if (num_serial == 0)
867 return -ENODEV;
868
869 return num_serial;
870 }
871
872 /*
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899
900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992 }
993
994 static void pci_ite887x_exit(struct pci_dev *dev)
995 {
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_8250_port *port, int idx)
1038 {
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 /* Quatech devices have their own extra interface features */
1044
1045 struct quatech_feature {
1046 u16 devid;
1047 bool amcc;
1048 };
1049
1050 #define QPCR_TEST_FOR1 0x3F
1051 #define QPCR_TEST_GET1 0x00
1052 #define QPCR_TEST_FOR2 0x40
1053 #define QPCR_TEST_GET2 0x40
1054 #define QPCR_TEST_FOR3 0x80
1055 #define QPCR_TEST_GET3 0x40
1056 #define QPCR_TEST_FOR4 0xC0
1057 #define QPCR_TEST_GET4 0x80
1058
1059 #define QOPR_CLOCK_X1 0x0000
1060 #define QOPR_CLOCK_X2 0x0001
1061 #define QOPR_CLOCK_X4 0x0002
1062 #define QOPR_CLOCK_X8 0x0003
1063 #define QOPR_CLOCK_RATE_MASK 0x0003
1064
1065
1066 static struct quatech_feature quatech_cards[] = {
1067 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1069 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1073 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1074 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1076 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1078 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1086 { 0, }
1087 };
1088
1089 static int pci_quatech_amcc(u16 devid)
1090 {
1091 struct quatech_feature *qf = &quatech_cards[0];
1092 while (qf->devid) {
1093 if (qf->devid == devid)
1094 return qf->amcc;
1095 qf++;
1096 }
1097 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1098 return 0;
1099 };
1100
1101 static int pci_quatech_rqopr(struct uart_8250_port *port)
1102 {
1103 unsigned long base = port->port.iobase;
1104 u8 LCR, val;
1105
1106 LCR = inb(base + UART_LCR);
1107 outb(0xBF, base + UART_LCR);
1108 val = inb(base + UART_SCR);
1109 outb(LCR, base + UART_LCR);
1110 return val;
1111 }
1112
1113 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1114 {
1115 unsigned long base = port->port.iobase;
1116 u8 LCR, val;
1117
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(qopr, base + UART_SCR);
1122 outb(LCR, base + UART_LCR);
1123 }
1124
1125 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1126 {
1127 unsigned long base = port->port.iobase;
1128 u8 LCR, val, qmcr;
1129
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 val = inb(base + UART_SCR);
1133 outb(val | 0x10, base + UART_SCR);
1134 qmcr = inb(base + UART_MCR);
1135 outb(val, base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137
1138 return qmcr;
1139 }
1140
1141 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1142 {
1143 unsigned long base = port->port.iobase;
1144 u8 LCR, val;
1145
1146 LCR = inb(base + UART_LCR);
1147 outb(0xBF, base + UART_LCR);
1148 val = inb(base + UART_SCR);
1149 outb(val | 0x10, base + UART_SCR);
1150 outb(qmcr, base + UART_MCR);
1151 outb(val, base + UART_SCR);
1152 outb(LCR, base + UART_LCR);
1153 }
1154
1155 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1156 {
1157 unsigned long base = port->port.iobase;
1158 u8 LCR, val;
1159
1160 LCR = inb(base + UART_LCR);
1161 outb(0xBF, base + UART_LCR);
1162 val = inb(base + UART_SCR);
1163 if (val & 0x20) {
1164 outb(0x80, UART_LCR);
1165 if (!(inb(UART_SCR) & 0x20)) {
1166 outb(LCR, base + UART_LCR);
1167 return 1;
1168 }
1169 }
1170 return 0;
1171 }
1172
1173 static int pci_quatech_test(struct uart_8250_port *port)
1174 {
1175 u8 reg;
1176 u8 qopr = pci_quatech_rqopr(port);
1177 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1178 reg = pci_quatech_rqopr(port) & 0xC0;
1179 if (reg != QPCR_TEST_GET1)
1180 return -EINVAL;
1181 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1182 reg = pci_quatech_rqopr(port) & 0xC0;
1183 if (reg != QPCR_TEST_GET2)
1184 return -EINVAL;
1185 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1186 reg = pci_quatech_rqopr(port) & 0xC0;
1187 if (reg != QPCR_TEST_GET3)
1188 return -EINVAL;
1189 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1190 reg = pci_quatech_rqopr(port) & 0xC0;
1191 if (reg != QPCR_TEST_GET4)
1192 return -EINVAL;
1193
1194 pci_quatech_wqopr(port, qopr);
1195 return 0;
1196 }
1197
1198 static int pci_quatech_clock(struct uart_8250_port *port)
1199 {
1200 u8 qopr, reg, set;
1201 unsigned long clock;
1202
1203 if (pci_quatech_test(port) < 0)
1204 return 1843200;
1205
1206 qopr = pci_quatech_rqopr(port);
1207
1208 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1209 reg = pci_quatech_rqopr(port);
1210 if (reg & QOPR_CLOCK_X8) {
1211 clock = 1843200;
1212 goto out;
1213 }
1214 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1215 reg = pci_quatech_rqopr(port);
1216 if (!(reg & QOPR_CLOCK_X8)) {
1217 clock = 1843200;
1218 goto out;
1219 }
1220 reg &= QOPR_CLOCK_X8;
1221 if (reg == QOPR_CLOCK_X2) {
1222 clock = 3685400;
1223 set = QOPR_CLOCK_X2;
1224 } else if (reg == QOPR_CLOCK_X4) {
1225 clock = 7372800;
1226 set = QOPR_CLOCK_X4;
1227 } else if (reg == QOPR_CLOCK_X8) {
1228 clock = 14745600;
1229 set = QOPR_CLOCK_X8;
1230 } else {
1231 clock = 1843200;
1232 set = QOPR_CLOCK_X1;
1233 }
1234 qopr &= ~QOPR_CLOCK_RATE_MASK;
1235 qopr |= set;
1236
1237 out:
1238 pci_quatech_wqopr(port, qopr);
1239 return clock;
1240 }
1241
1242 static int pci_quatech_rs422(struct uart_8250_port *port)
1243 {
1244 u8 qmcr;
1245 int rs422 = 0;
1246
1247 if (!pci_quatech_has_qmcr(port))
1248 return 0;
1249 qmcr = pci_quatech_rqmcr(port);
1250 pci_quatech_wqmcr(port, 0xFF);
1251 if (pci_quatech_rqmcr(port))
1252 rs422 = 1;
1253 pci_quatech_wqmcr(port, qmcr);
1254 return rs422;
1255 }
1256
1257 static int pci_quatech_init(struct pci_dev *dev)
1258 {
1259 if (pci_quatech_amcc(dev->device)) {
1260 unsigned long base = pci_resource_start(dev, 0);
1261 if (base) {
1262 u32 tmp;
1263 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1264 tmp = inl(base + 0x3c);
1265 outl(tmp | 0x01000000, base + 0x3c);
1266 outl(tmp &= ~0x01000000, base + 0x3c);
1267 }
1268 }
1269 return 0;
1270 }
1271
1272 static int pci_quatech_setup(struct serial_private *priv,
1273 const struct pciserial_board *board,
1274 struct uart_8250_port *port, int idx)
1275 {
1276 /* Needed by pci_quatech calls below */
1277 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1278 /* Set up the clocking */
1279 port->port.uartclk = pci_quatech_clock(port);
1280 /* For now just warn about RS422 */
1281 if (pci_quatech_rs422(port))
1282 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1283 return pci_default_setup(priv, board, port, idx);
1284 }
1285
1286 static void pci_quatech_exit(struct pci_dev *dev)
1287 {
1288 }
1289
1290 static int pci_default_setup(struct serial_private *priv,
1291 const struct pciserial_board *board,
1292 struct uart_8250_port *port, int idx)
1293 {
1294 unsigned int bar, offset = board->first_offset, maxnr;
1295
1296 bar = FL_GET_BASE(board->flags);
1297 if (board->flags & FL_BASE_BARS)
1298 bar += idx;
1299 else
1300 offset += idx * board->uart_offset;
1301
1302 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1303 (board->reg_shift + 3);
1304
1305 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1306 return 1;
1307
1308 return setup_port(priv, port, bar, offset, board->reg_shift);
1309 }
1310
1311 static int
1312 ce4100_serial_setup(struct serial_private *priv,
1313 const struct pciserial_board *board,
1314 struct uart_8250_port *port, int idx)
1315 {
1316 int ret;
1317
1318 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1319 port->port.iotype = UPIO_MEM32;
1320 port->port.type = PORT_XSCALE;
1321 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1322 port->port.regshift = 2;
1323
1324 return ret;
1325 }
1326
1327 static int
1328 pci_omegapci_setup(struct serial_private *priv,
1329 const struct pciserial_board *board,
1330 struct uart_8250_port *port, int idx)
1331 {
1332 return setup_port(priv, port, 2, idx * 8, 0);
1333 }
1334
1335 static int
1336 pci_brcm_trumanage_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1339 {
1340 int ret = pci_default_setup(priv, board, port, idx);
1341
1342 port->port.type = PORT_BRCM_TRUMANAGE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 return ret;
1345 }
1346
1347 static int skip_tx_en_setup(struct serial_private *priv,
1348 const struct pciserial_board *board,
1349 struct uart_8250_port *port, int idx)
1350 {
1351 port->port.flags |= UPF_NO_TXEN_TEST;
1352 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1353 "[%04x:%04x] subsystem [%04x:%04x]\n",
1354 priv->dev->vendor,
1355 priv->dev->device,
1356 priv->dev->subsystem_vendor,
1357 priv->dev->subsystem_device);
1358
1359 return pci_default_setup(priv, board, port, idx);
1360 }
1361
1362 static void kt_handle_break(struct uart_port *p)
1363 {
1364 struct uart_8250_port *up =
1365 container_of(p, struct uart_8250_port, port);
1366 /*
1367 * On receipt of a BI, serial device in Intel ME (Intel
1368 * management engine) needs to have its fifos cleared for sane
1369 * SOL (Serial Over Lan) output.
1370 */
1371 serial8250_clear_and_reinit_fifos(up);
1372 }
1373
1374 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1375 {
1376 struct uart_8250_port *up =
1377 container_of(p, struct uart_8250_port, port);
1378 unsigned int val;
1379
1380 /*
1381 * When the Intel ME (management engine) gets reset its serial
1382 * port registers could return 0 momentarily. Functions like
1383 * serial8250_console_write, read and save the IER, perform
1384 * some operation and then restore it. In order to avoid
1385 * setting IER register inadvertently to 0, if the value read
1386 * is 0, double check with ier value in uart_8250_port and use
1387 * that instead. up->ier should be the same value as what is
1388 * currently configured.
1389 */
1390 val = inb(p->iobase + offset);
1391 if (offset == UART_IER) {
1392 if (val == 0)
1393 val = up->ier;
1394 }
1395 return val;
1396 }
1397
1398 static int kt_serial_setup(struct serial_private *priv,
1399 const struct pciserial_board *board,
1400 struct uart_8250_port *port, int idx)
1401 {
1402 port->port.flags |= UPF_BUG_THRE;
1403 port->port.serial_in = kt_serial_in;
1404 port->port.handle_break = kt_handle_break;
1405 return skip_tx_en_setup(priv, board, port, idx);
1406 }
1407
1408 static int pci_eg20t_init(struct pci_dev *dev)
1409 {
1410 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1411 return -ENODEV;
1412 #else
1413 return 0;
1414 #endif
1415 }
1416
1417 static int
1418 pci_xr17c154_setup(struct serial_private *priv,
1419 const struct pciserial_board *board,
1420 struct uart_8250_port *port, int idx)
1421 {
1422 port->port.flags |= UPF_EXAR_EFR;
1423 return pci_default_setup(priv, board, port, idx);
1424 }
1425
1426 static int
1427 pci_xr17v35x_setup(struct serial_private *priv,
1428 const struct pciserial_board *board,
1429 struct uart_8250_port *port, int idx)
1430 {
1431 u8 __iomem *p;
1432
1433 p = pci_ioremap_bar(priv->dev, 0);
1434 if (p == NULL)
1435 return -ENOMEM;
1436
1437 port->port.flags |= UPF_EXAR_EFR;
1438
1439 /*
1440 * Setup Multipurpose Input/Output pins.
1441 */
1442 if (idx == 0) {
1443 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1444 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1445 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1446 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1447 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1448 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1449 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1450 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1451 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1452 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1453 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1454 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1455 }
1456 writeb(0x00, p + UART_EXAR_8XMODE);
1457 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1458 writeb(128, p + UART_EXAR_TXTRG);
1459 writeb(128, p + UART_EXAR_RXTRG);
1460 iounmap(p);
1461
1462 return pci_default_setup(priv, board, port, idx);
1463 }
1464
1465 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1466 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1467 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1468 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1469
1470 static int
1471 pci_fastcom335_setup(struct serial_private *priv,
1472 const struct pciserial_board *board,
1473 struct uart_8250_port *port, int idx)
1474 {
1475 u8 __iomem *p;
1476
1477 p = pci_ioremap_bar(priv->dev, 0);
1478 if (p == NULL)
1479 return -ENOMEM;
1480
1481 port->port.flags |= UPF_EXAR_EFR;
1482
1483 /*
1484 * Setup Multipurpose Input/Output pins.
1485 */
1486 if (idx == 0) {
1487 switch (priv->dev->device) {
1488 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1489 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1490 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1491 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1492 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1493 break;
1494 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1495 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1496 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1497 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1498 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1499 break;
1500 }
1501 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1502 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1503 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1504 }
1505 writeb(0x00, p + UART_EXAR_8XMODE);
1506 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1507 writeb(32, p + UART_EXAR_TXTRG);
1508 writeb(32, p + UART_EXAR_RXTRG);
1509 iounmap(p);
1510
1511 return pci_default_setup(priv, board, port, idx);
1512 }
1513
1514 static int
1515 pci_wch_ch353_setup(struct serial_private *priv,
1516 const struct pciserial_board *board,
1517 struct uart_8250_port *port, int idx)
1518 {
1519 port->port.flags |= UPF_FIXED_TYPE;
1520 port->port.type = PORT_16550A;
1521 return pci_default_setup(priv, board, port, idx);
1522 }
1523
1524 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1525 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1526 #define PCI_DEVICE_ID_OCTPRO 0x0001
1527 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1528 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1529 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1530 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1531 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1532 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1533 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1534 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1535 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1536 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1537 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1538 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1539 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1540 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1541 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1542 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1543 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1544 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1545 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1546 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1547 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1548 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1549 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1550 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1551 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1552 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1553 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1554 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1555 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1556 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1557 #define PCI_VENDOR_ID_WCH 0x4348
1558 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1559 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1560 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1561 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1562 #define PCI_VENDOR_ID_AGESTAR 0x5372
1563 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1564 #define PCI_VENDOR_ID_ASIX 0x9710
1565 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1566 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1567 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1568 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1569
1570 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1571 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1572
1573
1574 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1575 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1576 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1577
1578 /*
1579 * Master list of serial port init/setup/exit quirks.
1580 * This does not describe the general nature of the port.
1581 * (ie, baud base, number and location of ports, etc)
1582 *
1583 * This list is ordered alphabetically by vendor then device.
1584 * Specific entries must come before more generic entries.
1585 */
1586 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1587 /*
1588 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1589 */
1590 {
1591 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1592 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1593 .subvendor = PCI_ANY_ID,
1594 .subdevice = PCI_ANY_ID,
1595 .setup = addidata_apci7800_setup,
1596 },
1597 /*
1598 * AFAVLAB cards - these may be called via parport_serial
1599 * It is not clear whether this applies to all products.
1600 */
1601 {
1602 .vendor = PCI_VENDOR_ID_AFAVLAB,
1603 .device = PCI_ANY_ID,
1604 .subvendor = PCI_ANY_ID,
1605 .subdevice = PCI_ANY_ID,
1606 .setup = afavlab_setup,
1607 },
1608 /*
1609 * HP Diva
1610 */
1611 {
1612 .vendor = PCI_VENDOR_ID_HP,
1613 .device = PCI_DEVICE_ID_HP_DIVA,
1614 .subvendor = PCI_ANY_ID,
1615 .subdevice = PCI_ANY_ID,
1616 .init = pci_hp_diva_init,
1617 .setup = pci_hp_diva_setup,
1618 },
1619 /*
1620 * Intel
1621 */
1622 {
1623 .vendor = PCI_VENDOR_ID_INTEL,
1624 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1625 .subvendor = 0xe4bf,
1626 .subdevice = PCI_ANY_ID,
1627 .init = pci_inteli960ni_init,
1628 .setup = pci_default_setup,
1629 },
1630 {
1631 .vendor = PCI_VENDOR_ID_INTEL,
1632 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1633 .subvendor = PCI_ANY_ID,
1634 .subdevice = PCI_ANY_ID,
1635 .setup = skip_tx_en_setup,
1636 },
1637 {
1638 .vendor = PCI_VENDOR_ID_INTEL,
1639 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1640 .subvendor = PCI_ANY_ID,
1641 .subdevice = PCI_ANY_ID,
1642 .setup = skip_tx_en_setup,
1643 },
1644 {
1645 .vendor = PCI_VENDOR_ID_INTEL,
1646 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1647 .subvendor = PCI_ANY_ID,
1648 .subdevice = PCI_ANY_ID,
1649 .setup = skip_tx_en_setup,
1650 },
1651 {
1652 .vendor = PCI_VENDOR_ID_INTEL,
1653 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1654 .subvendor = PCI_ANY_ID,
1655 .subdevice = PCI_ANY_ID,
1656 .setup = ce4100_serial_setup,
1657 },
1658 {
1659 .vendor = PCI_VENDOR_ID_INTEL,
1660 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1661 .subvendor = PCI_ANY_ID,
1662 .subdevice = PCI_ANY_ID,
1663 .setup = kt_serial_setup,
1664 },
1665 /*
1666 * ITE
1667 */
1668 {
1669 .vendor = PCI_VENDOR_ID_ITE,
1670 .device = PCI_DEVICE_ID_ITE_8872,
1671 .subvendor = PCI_ANY_ID,
1672 .subdevice = PCI_ANY_ID,
1673 .init = pci_ite887x_init,
1674 .setup = pci_default_setup,
1675 .exit = pci_ite887x_exit,
1676 },
1677 /*
1678 * National Instruments
1679 */
1680 {
1681 .vendor = PCI_VENDOR_ID_NI,
1682 .device = PCI_DEVICE_ID_NI_PCI23216,
1683 .subvendor = PCI_ANY_ID,
1684 .subdevice = PCI_ANY_ID,
1685 .init = pci_ni8420_init,
1686 .setup = pci_default_setup,
1687 .exit = pci_ni8420_exit,
1688 },
1689 {
1690 .vendor = PCI_VENDOR_ID_NI,
1691 .device = PCI_DEVICE_ID_NI_PCI2328,
1692 .subvendor = PCI_ANY_ID,
1693 .subdevice = PCI_ANY_ID,
1694 .init = pci_ni8420_init,
1695 .setup = pci_default_setup,
1696 .exit = pci_ni8420_exit,
1697 },
1698 {
1699 .vendor = PCI_VENDOR_ID_NI,
1700 .device = PCI_DEVICE_ID_NI_PCI2324,
1701 .subvendor = PCI_ANY_ID,
1702 .subdevice = PCI_ANY_ID,
1703 .init = pci_ni8420_init,
1704 .setup = pci_default_setup,
1705 .exit = pci_ni8420_exit,
1706 },
1707 {
1708 .vendor = PCI_VENDOR_ID_NI,
1709 .device = PCI_DEVICE_ID_NI_PCI2322,
1710 .subvendor = PCI_ANY_ID,
1711 .subdevice = PCI_ANY_ID,
1712 .init = pci_ni8420_init,
1713 .setup = pci_default_setup,
1714 .exit = pci_ni8420_exit,
1715 },
1716 {
1717 .vendor = PCI_VENDOR_ID_NI,
1718 .device = PCI_DEVICE_ID_NI_PCI2324I,
1719 .subvendor = PCI_ANY_ID,
1720 .subdevice = PCI_ANY_ID,
1721 .init = pci_ni8420_init,
1722 .setup = pci_default_setup,
1723 .exit = pci_ni8420_exit,
1724 },
1725 {
1726 .vendor = PCI_VENDOR_ID_NI,
1727 .device = PCI_DEVICE_ID_NI_PCI2322I,
1728 .subvendor = PCI_ANY_ID,
1729 .subdevice = PCI_ANY_ID,
1730 .init = pci_ni8420_init,
1731 .setup = pci_default_setup,
1732 .exit = pci_ni8420_exit,
1733 },
1734 {
1735 .vendor = PCI_VENDOR_ID_NI,
1736 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1737 .subvendor = PCI_ANY_ID,
1738 .subdevice = PCI_ANY_ID,
1739 .init = pci_ni8420_init,
1740 .setup = pci_default_setup,
1741 .exit = pci_ni8420_exit,
1742 },
1743 {
1744 .vendor = PCI_VENDOR_ID_NI,
1745 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1746 .subvendor = PCI_ANY_ID,
1747 .subdevice = PCI_ANY_ID,
1748 .init = pci_ni8420_init,
1749 .setup = pci_default_setup,
1750 .exit = pci_ni8420_exit,
1751 },
1752 {
1753 .vendor = PCI_VENDOR_ID_NI,
1754 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1755 .subvendor = PCI_ANY_ID,
1756 .subdevice = PCI_ANY_ID,
1757 .init = pci_ni8420_init,
1758 .setup = pci_default_setup,
1759 .exit = pci_ni8420_exit,
1760 },
1761 {
1762 .vendor = PCI_VENDOR_ID_NI,
1763 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1764 .subvendor = PCI_ANY_ID,
1765 .subdevice = PCI_ANY_ID,
1766 .init = pci_ni8420_init,
1767 .setup = pci_default_setup,
1768 .exit = pci_ni8420_exit,
1769 },
1770 {
1771 .vendor = PCI_VENDOR_ID_NI,
1772 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1773 .subvendor = PCI_ANY_ID,
1774 .subdevice = PCI_ANY_ID,
1775 .init = pci_ni8420_init,
1776 .setup = pci_default_setup,
1777 .exit = pci_ni8420_exit,
1778 },
1779 {
1780 .vendor = PCI_VENDOR_ID_NI,
1781 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1782 .subvendor = PCI_ANY_ID,
1783 .subdevice = PCI_ANY_ID,
1784 .init = pci_ni8420_init,
1785 .setup = pci_default_setup,
1786 .exit = pci_ni8420_exit,
1787 },
1788 {
1789 .vendor = PCI_VENDOR_ID_NI,
1790 .device = PCI_ANY_ID,
1791 .subvendor = PCI_ANY_ID,
1792 .subdevice = PCI_ANY_ID,
1793 .init = pci_ni8430_init,
1794 .setup = pci_ni8430_setup,
1795 .exit = pci_ni8430_exit,
1796 },
1797 /* Quatech */
1798 {
1799 .vendor = PCI_VENDOR_ID_QUATECH,
1800 .device = PCI_ANY_ID,
1801 .subvendor = PCI_ANY_ID,
1802 .subdevice = PCI_ANY_ID,
1803 .init = pci_quatech_init,
1804 .setup = pci_quatech_setup,
1805 .exit = pci_quatech_exit,
1806 },
1807 /*
1808 * Panacom
1809 */
1810 {
1811 .vendor = PCI_VENDOR_ID_PANACOM,
1812 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1813 .subvendor = PCI_ANY_ID,
1814 .subdevice = PCI_ANY_ID,
1815 .init = pci_plx9050_init,
1816 .setup = pci_default_setup,
1817 .exit = pci_plx9050_exit,
1818 },
1819 {
1820 .vendor = PCI_VENDOR_ID_PANACOM,
1821 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1822 .subvendor = PCI_ANY_ID,
1823 .subdevice = PCI_ANY_ID,
1824 .init = pci_plx9050_init,
1825 .setup = pci_default_setup,
1826 .exit = pci_plx9050_exit,
1827 },
1828 /*
1829 * PLX
1830 */
1831 {
1832 .vendor = PCI_VENDOR_ID_PLX,
1833 .device = PCI_DEVICE_ID_PLX_9030,
1834 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1835 .subdevice = PCI_ANY_ID,
1836 .setup = pci_default_setup,
1837 },
1838 {
1839 .vendor = PCI_VENDOR_ID_PLX,
1840 .device = PCI_DEVICE_ID_PLX_9050,
1841 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1842 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1843 .init = pci_plx9050_init,
1844 .setup = pci_default_setup,
1845 .exit = pci_plx9050_exit,
1846 },
1847 {
1848 .vendor = PCI_VENDOR_ID_PLX,
1849 .device = PCI_DEVICE_ID_PLX_9050,
1850 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1851 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1852 .init = pci_plx9050_init,
1853 .setup = pci_default_setup,
1854 .exit = pci_plx9050_exit,
1855 },
1856 {
1857 .vendor = PCI_VENDOR_ID_PLX,
1858 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1859 .subvendor = PCI_VENDOR_ID_PLX,
1860 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1861 .init = pci_plx9050_init,
1862 .setup = pci_default_setup,
1863 .exit = pci_plx9050_exit,
1864 },
1865 /*
1866 * SBS Technologies, Inc., PMC-OCTALPRO 232
1867 */
1868 {
1869 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1870 .device = PCI_DEVICE_ID_OCTPRO,
1871 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1872 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1873 .init = sbs_init,
1874 .setup = sbs_setup,
1875 .exit = sbs_exit,
1876 },
1877 /*
1878 * SBS Technologies, Inc., PMC-OCTALPRO 422
1879 */
1880 {
1881 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1882 .device = PCI_DEVICE_ID_OCTPRO,
1883 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1884 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1885 .init = sbs_init,
1886 .setup = sbs_setup,
1887 .exit = sbs_exit,
1888 },
1889 /*
1890 * SBS Technologies, Inc., P-Octal 232
1891 */
1892 {
1893 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1894 .device = PCI_DEVICE_ID_OCTPRO,
1895 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1896 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1897 .init = sbs_init,
1898 .setup = sbs_setup,
1899 .exit = sbs_exit,
1900 },
1901 /*
1902 * SBS Technologies, Inc., P-Octal 422
1903 */
1904 {
1905 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1906 .device = PCI_DEVICE_ID_OCTPRO,
1907 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1908 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1909 .init = sbs_init,
1910 .setup = sbs_setup,
1911 .exit = sbs_exit,
1912 },
1913 /*
1914 * SIIG cards - these may be called via parport_serial
1915 */
1916 {
1917 .vendor = PCI_VENDOR_ID_SIIG,
1918 .device = PCI_ANY_ID,
1919 .subvendor = PCI_ANY_ID,
1920 .subdevice = PCI_ANY_ID,
1921 .init = pci_siig_init,
1922 .setup = pci_siig_setup,
1923 },
1924 /*
1925 * Titan cards
1926 */
1927 {
1928 .vendor = PCI_VENDOR_ID_TITAN,
1929 .device = PCI_DEVICE_ID_TITAN_400L,
1930 .subvendor = PCI_ANY_ID,
1931 .subdevice = PCI_ANY_ID,
1932 .setup = titan_400l_800l_setup,
1933 },
1934 {
1935 .vendor = PCI_VENDOR_ID_TITAN,
1936 .device = PCI_DEVICE_ID_TITAN_800L,
1937 .subvendor = PCI_ANY_ID,
1938 .subdevice = PCI_ANY_ID,
1939 .setup = titan_400l_800l_setup,
1940 },
1941 /*
1942 * Timedia cards
1943 */
1944 {
1945 .vendor = PCI_VENDOR_ID_TIMEDIA,
1946 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1947 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1948 .subdevice = PCI_ANY_ID,
1949 .probe = pci_timedia_probe,
1950 .init = pci_timedia_init,
1951 .setup = pci_timedia_setup,
1952 },
1953 {
1954 .vendor = PCI_VENDOR_ID_TIMEDIA,
1955 .device = PCI_ANY_ID,
1956 .subvendor = PCI_ANY_ID,
1957 .subdevice = PCI_ANY_ID,
1958 .setup = pci_timedia_setup,
1959 },
1960 /*
1961 * SUNIX (Timedia) cards
1962 * Do not "probe" for these cards as there is at least one combination
1963 * card that should be handled by parport_pc that doesn't match the
1964 * rule in pci_timedia_probe.
1965 * It is part number is MIO5079A but its subdevice ID is 0x0102.
1966 * There are some boards with part number SER5037AL that report
1967 * subdevice ID 0x0002.
1968 */
1969 {
1970 .vendor = PCI_VENDOR_ID_SUNIX,
1971 .device = PCI_DEVICE_ID_SUNIX_1999,
1972 .subvendor = PCI_VENDOR_ID_SUNIX,
1973 .subdevice = PCI_ANY_ID,
1974 .init = pci_timedia_init,
1975 .setup = pci_timedia_setup,
1976 },
1977 /*
1978 * Exar cards
1979 */
1980 {
1981 .vendor = PCI_VENDOR_ID_EXAR,
1982 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1983 .subvendor = PCI_ANY_ID,
1984 .subdevice = PCI_ANY_ID,
1985 .setup = pci_xr17c154_setup,
1986 },
1987 {
1988 .vendor = PCI_VENDOR_ID_EXAR,
1989 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1990 .subvendor = PCI_ANY_ID,
1991 .subdevice = PCI_ANY_ID,
1992 .setup = pci_xr17c154_setup,
1993 },
1994 {
1995 .vendor = PCI_VENDOR_ID_EXAR,
1996 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1997 .subvendor = PCI_ANY_ID,
1998 .subdevice = PCI_ANY_ID,
1999 .setup = pci_xr17c154_setup,
2000 },
2001 {
2002 .vendor = PCI_VENDOR_ID_EXAR,
2003 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2004 .subvendor = PCI_ANY_ID,
2005 .subdevice = PCI_ANY_ID,
2006 .setup = pci_xr17v35x_setup,
2007 },
2008 {
2009 .vendor = PCI_VENDOR_ID_EXAR,
2010 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2011 .subvendor = PCI_ANY_ID,
2012 .subdevice = PCI_ANY_ID,
2013 .setup = pci_xr17v35x_setup,
2014 },
2015 {
2016 .vendor = PCI_VENDOR_ID_EXAR,
2017 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2018 .subvendor = PCI_ANY_ID,
2019 .subdevice = PCI_ANY_ID,
2020 .setup = pci_xr17v35x_setup,
2021 },
2022 /*
2023 * Xircom cards
2024 */
2025 {
2026 .vendor = PCI_VENDOR_ID_XIRCOM,
2027 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2028 .subvendor = PCI_ANY_ID,
2029 .subdevice = PCI_ANY_ID,
2030 .init = pci_xircom_init,
2031 .setup = pci_default_setup,
2032 },
2033 /*
2034 * Netmos cards - these may be called via parport_serial
2035 */
2036 {
2037 .vendor = PCI_VENDOR_ID_NETMOS,
2038 .device = PCI_ANY_ID,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .init = pci_netmos_init,
2042 .setup = pci_netmos_9900_setup,
2043 },
2044 /*
2045 * For Oxford Semiconductor Tornado based devices
2046 */
2047 {
2048 .vendor = PCI_VENDOR_ID_OXSEMI,
2049 .device = PCI_ANY_ID,
2050 .subvendor = PCI_ANY_ID,
2051 .subdevice = PCI_ANY_ID,
2052 .init = pci_oxsemi_tornado_init,
2053 .setup = pci_default_setup,
2054 },
2055 {
2056 .vendor = PCI_VENDOR_ID_MAINPINE,
2057 .device = PCI_ANY_ID,
2058 .subvendor = PCI_ANY_ID,
2059 .subdevice = PCI_ANY_ID,
2060 .init = pci_oxsemi_tornado_init,
2061 .setup = pci_default_setup,
2062 },
2063 {
2064 .vendor = PCI_VENDOR_ID_DIGI,
2065 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2066 .subvendor = PCI_SUBVENDOR_ID_IBM,
2067 .subdevice = PCI_ANY_ID,
2068 .init = pci_oxsemi_tornado_init,
2069 .setup = pci_default_setup,
2070 },
2071 {
2072 .vendor = PCI_VENDOR_ID_INTEL,
2073 .device = 0x8811,
2074 .subvendor = PCI_ANY_ID,
2075 .subdevice = PCI_ANY_ID,
2076 .init = pci_eg20t_init,
2077 .setup = pci_default_setup,
2078 },
2079 {
2080 .vendor = PCI_VENDOR_ID_INTEL,
2081 .device = 0x8812,
2082 .subvendor = PCI_ANY_ID,
2083 .subdevice = PCI_ANY_ID,
2084 .init = pci_eg20t_init,
2085 .setup = pci_default_setup,
2086 },
2087 {
2088 .vendor = PCI_VENDOR_ID_INTEL,
2089 .device = 0x8813,
2090 .subvendor = PCI_ANY_ID,
2091 .subdevice = PCI_ANY_ID,
2092 .init = pci_eg20t_init,
2093 .setup = pci_default_setup,
2094 },
2095 {
2096 .vendor = PCI_VENDOR_ID_INTEL,
2097 .device = 0x8814,
2098 .subvendor = PCI_ANY_ID,
2099 .subdevice = PCI_ANY_ID,
2100 .init = pci_eg20t_init,
2101 .setup = pci_default_setup,
2102 },
2103 {
2104 .vendor = 0x10DB,
2105 .device = 0x8027,
2106 .subvendor = PCI_ANY_ID,
2107 .subdevice = PCI_ANY_ID,
2108 .init = pci_eg20t_init,
2109 .setup = pci_default_setup,
2110 },
2111 {
2112 .vendor = 0x10DB,
2113 .device = 0x8028,
2114 .subvendor = PCI_ANY_ID,
2115 .subdevice = PCI_ANY_ID,
2116 .init = pci_eg20t_init,
2117 .setup = pci_default_setup,
2118 },
2119 {
2120 .vendor = 0x10DB,
2121 .device = 0x8029,
2122 .subvendor = PCI_ANY_ID,
2123 .subdevice = PCI_ANY_ID,
2124 .init = pci_eg20t_init,
2125 .setup = pci_default_setup,
2126 },
2127 {
2128 .vendor = 0x10DB,
2129 .device = 0x800C,
2130 .subvendor = PCI_ANY_ID,
2131 .subdevice = PCI_ANY_ID,
2132 .init = pci_eg20t_init,
2133 .setup = pci_default_setup,
2134 },
2135 {
2136 .vendor = 0x10DB,
2137 .device = 0x800D,
2138 .subvendor = PCI_ANY_ID,
2139 .subdevice = PCI_ANY_ID,
2140 .init = pci_eg20t_init,
2141 .setup = pci_default_setup,
2142 },
2143 /*
2144 * Cronyx Omega PCI (PLX-chip based)
2145 */
2146 {
2147 .vendor = PCI_VENDOR_ID_PLX,
2148 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2149 .subvendor = PCI_ANY_ID,
2150 .subdevice = PCI_ANY_ID,
2151 .setup = pci_omegapci_setup,
2152 },
2153 /* WCH CH353 2S1P card (16550 clone) */
2154 {
2155 .vendor = PCI_VENDOR_ID_WCH,
2156 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2157 .subvendor = PCI_ANY_ID,
2158 .subdevice = PCI_ANY_ID,
2159 .setup = pci_wch_ch353_setup,
2160 },
2161 /* WCH CH353 4S card (16550 clone) */
2162 {
2163 .vendor = PCI_VENDOR_ID_WCH,
2164 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2165 .subvendor = PCI_ANY_ID,
2166 .subdevice = PCI_ANY_ID,
2167 .setup = pci_wch_ch353_setup,
2168 },
2169 /* WCH CH353 2S1PF card (16550 clone) */
2170 {
2171 .vendor = PCI_VENDOR_ID_WCH,
2172 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2173 .subvendor = PCI_ANY_ID,
2174 .subdevice = PCI_ANY_ID,
2175 .setup = pci_wch_ch353_setup,
2176 },
2177 /* WCH CH352 2S card (16550 clone) */
2178 {
2179 .vendor = PCI_VENDOR_ID_WCH,
2180 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2181 .subvendor = PCI_ANY_ID,
2182 .subdevice = PCI_ANY_ID,
2183 .setup = pci_wch_ch353_setup,
2184 },
2185 /*
2186 * ASIX devices with FIFO bug
2187 */
2188 {
2189 .vendor = PCI_VENDOR_ID_ASIX,
2190 .device = PCI_ANY_ID,
2191 .subvendor = PCI_ANY_ID,
2192 .subdevice = PCI_ANY_ID,
2193 .setup = pci_asix_setup,
2194 },
2195 /*
2196 * Commtech, Inc. Fastcom adapters
2197 *
2198 */
2199 {
2200 .vendor = PCI_VENDOR_ID_COMMTECH,
2201 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2202 .subvendor = PCI_ANY_ID,
2203 .subdevice = PCI_ANY_ID,
2204 .setup = pci_fastcom335_setup,
2205 },
2206 {
2207 .vendor = PCI_VENDOR_ID_COMMTECH,
2208 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2209 .subvendor = PCI_ANY_ID,
2210 .subdevice = PCI_ANY_ID,
2211 .setup = pci_fastcom335_setup,
2212 },
2213 {
2214 .vendor = PCI_VENDOR_ID_COMMTECH,
2215 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2216 .subvendor = PCI_ANY_ID,
2217 .subdevice = PCI_ANY_ID,
2218 .setup = pci_fastcom335_setup,
2219 },
2220 {
2221 .vendor = PCI_VENDOR_ID_COMMTECH,
2222 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2223 .subvendor = PCI_ANY_ID,
2224 .subdevice = PCI_ANY_ID,
2225 .setup = pci_fastcom335_setup,
2226 },
2227 {
2228 .vendor = PCI_VENDOR_ID_COMMTECH,
2229 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2230 .subvendor = PCI_ANY_ID,
2231 .subdevice = PCI_ANY_ID,
2232 .setup = pci_xr17v35x_setup,
2233 },
2234 {
2235 .vendor = PCI_VENDOR_ID_COMMTECH,
2236 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2237 .subvendor = PCI_ANY_ID,
2238 .subdevice = PCI_ANY_ID,
2239 .setup = pci_xr17v35x_setup,
2240 },
2241 {
2242 .vendor = PCI_VENDOR_ID_COMMTECH,
2243 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2244 .subvendor = PCI_ANY_ID,
2245 .subdevice = PCI_ANY_ID,
2246 .setup = pci_xr17v35x_setup,
2247 },
2248 /*
2249 * Broadcom TruManage (NetXtreme)
2250 */
2251 {
2252 .vendor = PCI_VENDOR_ID_BROADCOM,
2253 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2254 .subvendor = PCI_ANY_ID,
2255 .subdevice = PCI_ANY_ID,
2256 .setup = pci_brcm_trumanage_setup,
2257 },
2258
2259 /*
2260 * Default "match everything" terminator entry
2261 */
2262 {
2263 .vendor = PCI_ANY_ID,
2264 .device = PCI_ANY_ID,
2265 .subvendor = PCI_ANY_ID,
2266 .subdevice = PCI_ANY_ID,
2267 .setup = pci_default_setup,
2268 }
2269 };
2270
2271 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2272 {
2273 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2274 }
2275
2276 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2277 {
2278 struct pci_serial_quirk *quirk;
2279
2280 for (quirk = pci_serial_quirks; ; quirk++)
2281 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2282 quirk_id_matches(quirk->device, dev->device) &&
2283 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2284 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2285 break;
2286 return quirk;
2287 }
2288
2289 static inline int get_pci_irq(struct pci_dev *dev,
2290 const struct pciserial_board *board)
2291 {
2292 if (board->flags & FL_NOIRQ)
2293 return 0;
2294 else
2295 return dev->irq;
2296 }
2297
2298 /*
2299 * This is the configuration table for all of the PCI serial boards
2300 * which we support. It is directly indexed by the pci_board_num_t enum
2301 * value, which is encoded in the pci_device_id PCI probe table's
2302 * driver_data member.
2303 *
2304 * The makeup of these names are:
2305 * pbn_bn{_bt}_n_baud{_offsetinhex}
2306 *
2307 * bn = PCI BAR number
2308 * bt = Index using PCI BARs
2309 * n = number of serial ports
2310 * baud = baud rate
2311 * offsetinhex = offset for each sequential port (in hex)
2312 *
2313 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2314 *
2315 * Please note: in theory if n = 1, _bt infix should make no difference.
2316 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2317 */
2318 enum pci_board_num_t {
2319 pbn_default = 0,
2320
2321 pbn_b0_1_115200,
2322 pbn_b0_2_115200,
2323 pbn_b0_4_115200,
2324 pbn_b0_5_115200,
2325 pbn_b0_8_115200,
2326
2327 pbn_b0_1_921600,
2328 pbn_b0_2_921600,
2329 pbn_b0_4_921600,
2330
2331 pbn_b0_2_1130000,
2332
2333 pbn_b0_4_1152000,
2334
2335 pbn_b0_2_1152000_200,
2336 pbn_b0_4_1152000_200,
2337 pbn_b0_8_1152000_200,
2338
2339 pbn_b0_2_1843200,
2340 pbn_b0_4_1843200,
2341
2342 pbn_b0_2_1843200_200,
2343 pbn_b0_4_1843200_200,
2344 pbn_b0_8_1843200_200,
2345
2346 pbn_b0_1_4000000,
2347
2348 pbn_b0_bt_1_115200,
2349 pbn_b0_bt_2_115200,
2350 pbn_b0_bt_4_115200,
2351 pbn_b0_bt_8_115200,
2352
2353 pbn_b0_bt_1_460800,
2354 pbn_b0_bt_2_460800,
2355 pbn_b0_bt_4_460800,
2356
2357 pbn_b0_bt_1_921600,
2358 pbn_b0_bt_2_921600,
2359 pbn_b0_bt_4_921600,
2360 pbn_b0_bt_8_921600,
2361
2362 pbn_b1_1_115200,
2363 pbn_b1_2_115200,
2364 pbn_b1_4_115200,
2365 pbn_b1_8_115200,
2366 pbn_b1_16_115200,
2367
2368 pbn_b1_1_921600,
2369 pbn_b1_2_921600,
2370 pbn_b1_4_921600,
2371 pbn_b1_8_921600,
2372
2373 pbn_b1_2_1250000,
2374
2375 pbn_b1_bt_1_115200,
2376 pbn_b1_bt_2_115200,
2377 pbn_b1_bt_4_115200,
2378
2379 pbn_b1_bt_2_921600,
2380
2381 pbn_b1_1_1382400,
2382 pbn_b1_2_1382400,
2383 pbn_b1_4_1382400,
2384 pbn_b1_8_1382400,
2385
2386 pbn_b2_1_115200,
2387 pbn_b2_2_115200,
2388 pbn_b2_4_115200,
2389 pbn_b2_8_115200,
2390
2391 pbn_b2_1_460800,
2392 pbn_b2_4_460800,
2393 pbn_b2_8_460800,
2394 pbn_b2_16_460800,
2395
2396 pbn_b2_1_921600,
2397 pbn_b2_4_921600,
2398 pbn_b2_8_921600,
2399
2400 pbn_b2_8_1152000,
2401
2402 pbn_b2_bt_1_115200,
2403 pbn_b2_bt_2_115200,
2404 pbn_b2_bt_4_115200,
2405
2406 pbn_b2_bt_2_921600,
2407 pbn_b2_bt_4_921600,
2408
2409 pbn_b3_2_115200,
2410 pbn_b3_4_115200,
2411 pbn_b3_8_115200,
2412
2413 pbn_b4_bt_2_921600,
2414 pbn_b4_bt_4_921600,
2415 pbn_b4_bt_8_921600,
2416
2417 /*
2418 * Board-specific versions.
2419 */
2420 pbn_panacom,
2421 pbn_panacom2,
2422 pbn_panacom4,
2423 pbn_plx_romulus,
2424 pbn_oxsemi,
2425 pbn_oxsemi_1_4000000,
2426 pbn_oxsemi_2_4000000,
2427 pbn_oxsemi_4_4000000,
2428 pbn_oxsemi_8_4000000,
2429 pbn_intel_i960,
2430 pbn_sgi_ioc3,
2431 pbn_computone_4,
2432 pbn_computone_6,
2433 pbn_computone_8,
2434 pbn_sbsxrsio,
2435 pbn_exar_XR17C152,
2436 pbn_exar_XR17C154,
2437 pbn_exar_XR17C158,
2438 pbn_exar_XR17V352,
2439 pbn_exar_XR17V354,
2440 pbn_exar_XR17V358,
2441 pbn_exar_ibm_saturn,
2442 pbn_pasemi_1682M,
2443 pbn_ni8430_2,
2444 pbn_ni8430_4,
2445 pbn_ni8430_8,
2446 pbn_ni8430_16,
2447 pbn_ADDIDATA_PCIe_1_3906250,
2448 pbn_ADDIDATA_PCIe_2_3906250,
2449 pbn_ADDIDATA_PCIe_4_3906250,
2450 pbn_ADDIDATA_PCIe_8_3906250,
2451 pbn_ce4100_1_115200,
2452 pbn_omegapci,
2453 pbn_NETMOS9900_2s_115200,
2454 pbn_brcm_trumanage,
2455 };
2456
2457 /*
2458 * uart_offset - the space between channels
2459 * reg_shift - describes how the UART registers are mapped
2460 * to PCI memory by the card.
2461 * For example IER register on SBS, Inc. PMC-OctPro is located at
2462 * offset 0x10 from the UART base, while UART_IER is defined as 1
2463 * in include/linux/serial_reg.h,
2464 * see first lines of serial_in() and serial_out() in 8250.c
2465 */
2466
2467 static struct pciserial_board pci_boards[] = {
2468 [pbn_default] = {
2469 .flags = FL_BASE0,
2470 .num_ports = 1,
2471 .base_baud = 115200,
2472 .uart_offset = 8,
2473 },
2474 [pbn_b0_1_115200] = {
2475 .flags = FL_BASE0,
2476 .num_ports = 1,
2477 .base_baud = 115200,
2478 .uart_offset = 8,
2479 },
2480 [pbn_b0_2_115200] = {
2481 .flags = FL_BASE0,
2482 .num_ports = 2,
2483 .base_baud = 115200,
2484 .uart_offset = 8,
2485 },
2486 [pbn_b0_4_115200] = {
2487 .flags = FL_BASE0,
2488 .num_ports = 4,
2489 .base_baud = 115200,
2490 .uart_offset = 8,
2491 },
2492 [pbn_b0_5_115200] = {
2493 .flags = FL_BASE0,
2494 .num_ports = 5,
2495 .base_baud = 115200,
2496 .uart_offset = 8,
2497 },
2498 [pbn_b0_8_115200] = {
2499 .flags = FL_BASE0,
2500 .num_ports = 8,
2501 .base_baud = 115200,
2502 .uart_offset = 8,
2503 },
2504 [pbn_b0_1_921600] = {
2505 .flags = FL_BASE0,
2506 .num_ports = 1,
2507 .base_baud = 921600,
2508 .uart_offset = 8,
2509 },
2510 [pbn_b0_2_921600] = {
2511 .flags = FL_BASE0,
2512 .num_ports = 2,
2513 .base_baud = 921600,
2514 .uart_offset = 8,
2515 },
2516 [pbn_b0_4_921600] = {
2517 .flags = FL_BASE0,
2518 .num_ports = 4,
2519 .base_baud = 921600,
2520 .uart_offset = 8,
2521 },
2522
2523 [pbn_b0_2_1130000] = {
2524 .flags = FL_BASE0,
2525 .num_ports = 2,
2526 .base_baud = 1130000,
2527 .uart_offset = 8,
2528 },
2529
2530 [pbn_b0_4_1152000] = {
2531 .flags = FL_BASE0,
2532 .num_ports = 4,
2533 .base_baud = 1152000,
2534 .uart_offset = 8,
2535 },
2536
2537 [pbn_b0_2_1152000_200] = {
2538 .flags = FL_BASE0,
2539 .num_ports = 2,
2540 .base_baud = 1152000,
2541 .uart_offset = 0x200,
2542 },
2543
2544 [pbn_b0_4_1152000_200] = {
2545 .flags = FL_BASE0,
2546 .num_ports = 4,
2547 .base_baud = 1152000,
2548 .uart_offset = 0x200,
2549 },
2550
2551 [pbn_b0_8_1152000_200] = {
2552 .flags = FL_BASE0,
2553 .num_ports = 8,
2554 .base_baud = 1152000,
2555 .uart_offset = 0x200,
2556 },
2557
2558 [pbn_b0_2_1843200] = {
2559 .flags = FL_BASE0,
2560 .num_ports = 2,
2561 .base_baud = 1843200,
2562 .uart_offset = 8,
2563 },
2564 [pbn_b0_4_1843200] = {
2565 .flags = FL_BASE0,
2566 .num_ports = 4,
2567 .base_baud = 1843200,
2568 .uart_offset = 8,
2569 },
2570
2571 [pbn_b0_2_1843200_200] = {
2572 .flags = FL_BASE0,
2573 .num_ports = 2,
2574 .base_baud = 1843200,
2575 .uart_offset = 0x200,
2576 },
2577 [pbn_b0_4_1843200_200] = {
2578 .flags = FL_BASE0,
2579 .num_ports = 4,
2580 .base_baud = 1843200,
2581 .uart_offset = 0x200,
2582 },
2583 [pbn_b0_8_1843200_200] = {
2584 .flags = FL_BASE0,
2585 .num_ports = 8,
2586 .base_baud = 1843200,
2587 .uart_offset = 0x200,
2588 },
2589 [pbn_b0_1_4000000] = {
2590 .flags = FL_BASE0,
2591 .num_ports = 1,
2592 .base_baud = 4000000,
2593 .uart_offset = 8,
2594 },
2595
2596 [pbn_b0_bt_1_115200] = {
2597 .flags = FL_BASE0|FL_BASE_BARS,
2598 .num_ports = 1,
2599 .base_baud = 115200,
2600 .uart_offset = 8,
2601 },
2602 [pbn_b0_bt_2_115200] = {
2603 .flags = FL_BASE0|FL_BASE_BARS,
2604 .num_ports = 2,
2605 .base_baud = 115200,
2606 .uart_offset = 8,
2607 },
2608 [pbn_b0_bt_4_115200] = {
2609 .flags = FL_BASE0|FL_BASE_BARS,
2610 .num_ports = 4,
2611 .base_baud = 115200,
2612 .uart_offset = 8,
2613 },
2614 [pbn_b0_bt_8_115200] = {
2615 .flags = FL_BASE0|FL_BASE_BARS,
2616 .num_ports = 8,
2617 .base_baud = 115200,
2618 .uart_offset = 8,
2619 },
2620
2621 [pbn_b0_bt_1_460800] = {
2622 .flags = FL_BASE0|FL_BASE_BARS,
2623 .num_ports = 1,
2624 .base_baud = 460800,
2625 .uart_offset = 8,
2626 },
2627 [pbn_b0_bt_2_460800] = {
2628 .flags = FL_BASE0|FL_BASE_BARS,
2629 .num_ports = 2,
2630 .base_baud = 460800,
2631 .uart_offset = 8,
2632 },
2633 [pbn_b0_bt_4_460800] = {
2634 .flags = FL_BASE0|FL_BASE_BARS,
2635 .num_ports = 4,
2636 .base_baud = 460800,
2637 .uart_offset = 8,
2638 },
2639
2640 [pbn_b0_bt_1_921600] = {
2641 .flags = FL_BASE0|FL_BASE_BARS,
2642 .num_ports = 1,
2643 .base_baud = 921600,
2644 .uart_offset = 8,
2645 },
2646 [pbn_b0_bt_2_921600] = {
2647 .flags = FL_BASE0|FL_BASE_BARS,
2648 .num_ports = 2,
2649 .base_baud = 921600,
2650 .uart_offset = 8,
2651 },
2652 [pbn_b0_bt_4_921600] = {
2653 .flags = FL_BASE0|FL_BASE_BARS,
2654 .num_ports = 4,
2655 .base_baud = 921600,
2656 .uart_offset = 8,
2657 },
2658 [pbn_b0_bt_8_921600] = {
2659 .flags = FL_BASE0|FL_BASE_BARS,
2660 .num_ports = 8,
2661 .base_baud = 921600,
2662 .uart_offset = 8,
2663 },
2664
2665 [pbn_b1_1_115200] = {
2666 .flags = FL_BASE1,
2667 .num_ports = 1,
2668 .base_baud = 115200,
2669 .uart_offset = 8,
2670 },
2671 [pbn_b1_2_115200] = {
2672 .flags = FL_BASE1,
2673 .num_ports = 2,
2674 .base_baud = 115200,
2675 .uart_offset = 8,
2676 },
2677 [pbn_b1_4_115200] = {
2678 .flags = FL_BASE1,
2679 .num_ports = 4,
2680 .base_baud = 115200,
2681 .uart_offset = 8,
2682 },
2683 [pbn_b1_8_115200] = {
2684 .flags = FL_BASE1,
2685 .num_ports = 8,
2686 .base_baud = 115200,
2687 .uart_offset = 8,
2688 },
2689 [pbn_b1_16_115200] = {
2690 .flags = FL_BASE1,
2691 .num_ports = 16,
2692 .base_baud = 115200,
2693 .uart_offset = 8,
2694 },
2695
2696 [pbn_b1_1_921600] = {
2697 .flags = FL_BASE1,
2698 .num_ports = 1,
2699 .base_baud = 921600,
2700 .uart_offset = 8,
2701 },
2702 [pbn_b1_2_921600] = {
2703 .flags = FL_BASE1,
2704 .num_ports = 2,
2705 .base_baud = 921600,
2706 .uart_offset = 8,
2707 },
2708 [pbn_b1_4_921600] = {
2709 .flags = FL_BASE1,
2710 .num_ports = 4,
2711 .base_baud = 921600,
2712 .uart_offset = 8,
2713 },
2714 [pbn_b1_8_921600] = {
2715 .flags = FL_BASE1,
2716 .num_ports = 8,
2717 .base_baud = 921600,
2718 .uart_offset = 8,
2719 },
2720 [pbn_b1_2_1250000] = {
2721 .flags = FL_BASE1,
2722 .num_ports = 2,
2723 .base_baud = 1250000,
2724 .uart_offset = 8,
2725 },
2726
2727 [pbn_b1_bt_1_115200] = {
2728 .flags = FL_BASE1|FL_BASE_BARS,
2729 .num_ports = 1,
2730 .base_baud = 115200,
2731 .uart_offset = 8,
2732 },
2733 [pbn_b1_bt_2_115200] = {
2734 .flags = FL_BASE1|FL_BASE_BARS,
2735 .num_ports = 2,
2736 .base_baud = 115200,
2737 .uart_offset = 8,
2738 },
2739 [pbn_b1_bt_4_115200] = {
2740 .flags = FL_BASE1|FL_BASE_BARS,
2741 .num_ports = 4,
2742 .base_baud = 115200,
2743 .uart_offset = 8,
2744 },
2745
2746 [pbn_b1_bt_2_921600] = {
2747 .flags = FL_BASE1|FL_BASE_BARS,
2748 .num_ports = 2,
2749 .base_baud = 921600,
2750 .uart_offset = 8,
2751 },
2752
2753 [pbn_b1_1_1382400] = {
2754 .flags = FL_BASE1,
2755 .num_ports = 1,
2756 .base_baud = 1382400,
2757 .uart_offset = 8,
2758 },
2759 [pbn_b1_2_1382400] = {
2760 .flags = FL_BASE1,
2761 .num_ports = 2,
2762 .base_baud = 1382400,
2763 .uart_offset = 8,
2764 },
2765 [pbn_b1_4_1382400] = {
2766 .flags = FL_BASE1,
2767 .num_ports = 4,
2768 .base_baud = 1382400,
2769 .uart_offset = 8,
2770 },
2771 [pbn_b1_8_1382400] = {
2772 .flags = FL_BASE1,
2773 .num_ports = 8,
2774 .base_baud = 1382400,
2775 .uart_offset = 8,
2776 },
2777
2778 [pbn_b2_1_115200] = {
2779 .flags = FL_BASE2,
2780 .num_ports = 1,
2781 .base_baud = 115200,
2782 .uart_offset = 8,
2783 },
2784 [pbn_b2_2_115200] = {
2785 .flags = FL_BASE2,
2786 .num_ports = 2,
2787 .base_baud = 115200,
2788 .uart_offset = 8,
2789 },
2790 [pbn_b2_4_115200] = {
2791 .flags = FL_BASE2,
2792 .num_ports = 4,
2793 .base_baud = 115200,
2794 .uart_offset = 8,
2795 },
2796 [pbn_b2_8_115200] = {
2797 .flags = FL_BASE2,
2798 .num_ports = 8,
2799 .base_baud = 115200,
2800 .uart_offset = 8,
2801 },
2802
2803 [pbn_b2_1_460800] = {
2804 .flags = FL_BASE2,
2805 .num_ports = 1,
2806 .base_baud = 460800,
2807 .uart_offset = 8,
2808 },
2809 [pbn_b2_4_460800] = {
2810 .flags = FL_BASE2,
2811 .num_ports = 4,
2812 .base_baud = 460800,
2813 .uart_offset = 8,
2814 },
2815 [pbn_b2_8_460800] = {
2816 .flags = FL_BASE2,
2817 .num_ports = 8,
2818 .base_baud = 460800,
2819 .uart_offset = 8,
2820 },
2821 [pbn_b2_16_460800] = {
2822 .flags = FL_BASE2,
2823 .num_ports = 16,
2824 .base_baud = 460800,
2825 .uart_offset = 8,
2826 },
2827
2828 [pbn_b2_1_921600] = {
2829 .flags = FL_BASE2,
2830 .num_ports = 1,
2831 .base_baud = 921600,
2832 .uart_offset = 8,
2833 },
2834 [pbn_b2_4_921600] = {
2835 .flags = FL_BASE2,
2836 .num_ports = 4,
2837 .base_baud = 921600,
2838 .uart_offset = 8,
2839 },
2840 [pbn_b2_8_921600] = {
2841 .flags = FL_BASE2,
2842 .num_ports = 8,
2843 .base_baud = 921600,
2844 .uart_offset = 8,
2845 },
2846
2847 [pbn_b2_8_1152000] = {
2848 .flags = FL_BASE2,
2849 .num_ports = 8,
2850 .base_baud = 1152000,
2851 .uart_offset = 8,
2852 },
2853
2854 [pbn_b2_bt_1_115200] = {
2855 .flags = FL_BASE2|FL_BASE_BARS,
2856 .num_ports = 1,
2857 .base_baud = 115200,
2858 .uart_offset = 8,
2859 },
2860 [pbn_b2_bt_2_115200] = {
2861 .flags = FL_BASE2|FL_BASE_BARS,
2862 .num_ports = 2,
2863 .base_baud = 115200,
2864 .uart_offset = 8,
2865 },
2866 [pbn_b2_bt_4_115200] = {
2867 .flags = FL_BASE2|FL_BASE_BARS,
2868 .num_ports = 4,
2869 .base_baud = 115200,
2870 .uart_offset = 8,
2871 },
2872
2873 [pbn_b2_bt_2_921600] = {
2874 .flags = FL_BASE2|FL_BASE_BARS,
2875 .num_ports = 2,
2876 .base_baud = 921600,
2877 .uart_offset = 8,
2878 },
2879 [pbn_b2_bt_4_921600] = {
2880 .flags = FL_BASE2|FL_BASE_BARS,
2881 .num_ports = 4,
2882 .base_baud = 921600,
2883 .uart_offset = 8,
2884 },
2885
2886 [pbn_b3_2_115200] = {
2887 .flags = FL_BASE3,
2888 .num_ports = 2,
2889 .base_baud = 115200,
2890 .uart_offset = 8,
2891 },
2892 [pbn_b3_4_115200] = {
2893 .flags = FL_BASE3,
2894 .num_ports = 4,
2895 .base_baud = 115200,
2896 .uart_offset = 8,
2897 },
2898 [pbn_b3_8_115200] = {
2899 .flags = FL_BASE3,
2900 .num_ports = 8,
2901 .base_baud = 115200,
2902 .uart_offset = 8,
2903 },
2904
2905 [pbn_b4_bt_2_921600] = {
2906 .flags = FL_BASE4,
2907 .num_ports = 2,
2908 .base_baud = 921600,
2909 .uart_offset = 8,
2910 },
2911 [pbn_b4_bt_4_921600] = {
2912 .flags = FL_BASE4,
2913 .num_ports = 4,
2914 .base_baud = 921600,
2915 .uart_offset = 8,
2916 },
2917 [pbn_b4_bt_8_921600] = {
2918 .flags = FL_BASE4,
2919 .num_ports = 8,
2920 .base_baud = 921600,
2921 .uart_offset = 8,
2922 },
2923
2924 /*
2925 * Entries following this are board-specific.
2926 */
2927
2928 /*
2929 * Panacom - IOMEM
2930 */
2931 [pbn_panacom] = {
2932 .flags = FL_BASE2,
2933 .num_ports = 2,
2934 .base_baud = 921600,
2935 .uart_offset = 0x400,
2936 .reg_shift = 7,
2937 },
2938 [pbn_panacom2] = {
2939 .flags = FL_BASE2|FL_BASE_BARS,
2940 .num_ports = 2,
2941 .base_baud = 921600,
2942 .uart_offset = 0x400,
2943 .reg_shift = 7,
2944 },
2945 [pbn_panacom4] = {
2946 .flags = FL_BASE2|FL_BASE_BARS,
2947 .num_ports = 4,
2948 .base_baud = 921600,
2949 .uart_offset = 0x400,
2950 .reg_shift = 7,
2951 },
2952
2953 /* I think this entry is broken - the first_offset looks wrong --rmk */
2954 [pbn_plx_romulus] = {
2955 .flags = FL_BASE2,
2956 .num_ports = 4,
2957 .base_baud = 921600,
2958 .uart_offset = 8 << 2,
2959 .reg_shift = 2,
2960 .first_offset = 0x03,
2961 },
2962
2963 /*
2964 * This board uses the size of PCI Base region 0 to
2965 * signal now many ports are available
2966 */
2967 [pbn_oxsemi] = {
2968 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2969 .num_ports = 32,
2970 .base_baud = 115200,
2971 .uart_offset = 8,
2972 },
2973 [pbn_oxsemi_1_4000000] = {
2974 .flags = FL_BASE0,
2975 .num_ports = 1,
2976 .base_baud = 4000000,
2977 .uart_offset = 0x200,
2978 .first_offset = 0x1000,
2979 },
2980 [pbn_oxsemi_2_4000000] = {
2981 .flags = FL_BASE0,
2982 .num_ports = 2,
2983 .base_baud = 4000000,
2984 .uart_offset = 0x200,
2985 .first_offset = 0x1000,
2986 },
2987 [pbn_oxsemi_4_4000000] = {
2988 .flags = FL_BASE0,
2989 .num_ports = 4,
2990 .base_baud = 4000000,
2991 .uart_offset = 0x200,
2992 .first_offset = 0x1000,
2993 },
2994 [pbn_oxsemi_8_4000000] = {
2995 .flags = FL_BASE0,
2996 .num_ports = 8,
2997 .base_baud = 4000000,
2998 .uart_offset = 0x200,
2999 .first_offset = 0x1000,
3000 },
3001
3002
3003 /*
3004 * EKF addition for i960 Boards form EKF with serial port.
3005 * Max 256 ports.
3006 */
3007 [pbn_intel_i960] = {
3008 .flags = FL_BASE0,
3009 .num_ports = 32,
3010 .base_baud = 921600,
3011 .uart_offset = 8 << 2,
3012 .reg_shift = 2,
3013 .first_offset = 0x10000,
3014 },
3015 [pbn_sgi_ioc3] = {
3016 .flags = FL_BASE0|FL_NOIRQ,
3017 .num_ports = 1,
3018 .base_baud = 458333,
3019 .uart_offset = 8,
3020 .reg_shift = 0,
3021 .first_offset = 0x20178,
3022 },
3023
3024 /*
3025 * Computone - uses IOMEM.
3026 */
3027 [pbn_computone_4] = {
3028 .flags = FL_BASE0,
3029 .num_ports = 4,
3030 .base_baud = 921600,
3031 .uart_offset = 0x40,
3032 .reg_shift = 2,
3033 .first_offset = 0x200,
3034 },
3035 [pbn_computone_6] = {
3036 .flags = FL_BASE0,
3037 .num_ports = 6,
3038 .base_baud = 921600,
3039 .uart_offset = 0x40,
3040 .reg_shift = 2,
3041 .first_offset = 0x200,
3042 },
3043 [pbn_computone_8] = {
3044 .flags = FL_BASE0,
3045 .num_ports = 8,
3046 .base_baud = 921600,
3047 .uart_offset = 0x40,
3048 .reg_shift = 2,
3049 .first_offset = 0x200,
3050 },
3051 [pbn_sbsxrsio] = {
3052 .flags = FL_BASE0,
3053 .num_ports = 8,
3054 .base_baud = 460800,
3055 .uart_offset = 256,
3056 .reg_shift = 4,
3057 },
3058 /*
3059 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3060 * Only basic 16550A support.
3061 * XR17C15[24] are not tested, but they should work.
3062 */
3063 [pbn_exar_XR17C152] = {
3064 .flags = FL_BASE0,
3065 .num_ports = 2,
3066 .base_baud = 921600,
3067 .uart_offset = 0x200,
3068 },
3069 [pbn_exar_XR17C154] = {
3070 .flags = FL_BASE0,
3071 .num_ports = 4,
3072 .base_baud = 921600,
3073 .uart_offset = 0x200,
3074 },
3075 [pbn_exar_XR17C158] = {
3076 .flags = FL_BASE0,
3077 .num_ports = 8,
3078 .base_baud = 921600,
3079 .uart_offset = 0x200,
3080 },
3081 [pbn_exar_XR17V352] = {
3082 .flags = FL_BASE0,
3083 .num_ports = 2,
3084 .base_baud = 7812500,
3085 .uart_offset = 0x400,
3086 .reg_shift = 0,
3087 .first_offset = 0,
3088 },
3089 [pbn_exar_XR17V354] = {
3090 .flags = FL_BASE0,
3091 .num_ports = 4,
3092 .base_baud = 7812500,
3093 .uart_offset = 0x400,
3094 .reg_shift = 0,
3095 .first_offset = 0,
3096 },
3097 [pbn_exar_XR17V358] = {
3098 .flags = FL_BASE0,
3099 .num_ports = 8,
3100 .base_baud = 7812500,
3101 .uart_offset = 0x400,
3102 .reg_shift = 0,
3103 .first_offset = 0,
3104 },
3105 [pbn_exar_ibm_saturn] = {
3106 .flags = FL_BASE0,
3107 .num_ports = 1,
3108 .base_baud = 921600,
3109 .uart_offset = 0x200,
3110 },
3111
3112 /*
3113 * PA Semi PWRficient PA6T-1682M on-chip UART
3114 */
3115 [pbn_pasemi_1682M] = {
3116 .flags = FL_BASE0,
3117 .num_ports = 1,
3118 .base_baud = 8333333,
3119 },
3120 /*
3121 * National Instruments 843x
3122 */
3123 [pbn_ni8430_16] = {
3124 .flags = FL_BASE0,
3125 .num_ports = 16,
3126 .base_baud = 3686400,
3127 .uart_offset = 0x10,
3128 .first_offset = 0x800,
3129 },
3130 [pbn_ni8430_8] = {
3131 .flags = FL_BASE0,
3132 .num_ports = 8,
3133 .base_baud = 3686400,
3134 .uart_offset = 0x10,
3135 .first_offset = 0x800,
3136 },
3137 [pbn_ni8430_4] = {
3138 .flags = FL_BASE0,
3139 .num_ports = 4,
3140 .base_baud = 3686400,
3141 .uart_offset = 0x10,
3142 .first_offset = 0x800,
3143 },
3144 [pbn_ni8430_2] = {
3145 .flags = FL_BASE0,
3146 .num_ports = 2,
3147 .base_baud = 3686400,
3148 .uart_offset = 0x10,
3149 .first_offset = 0x800,
3150 },
3151 /*
3152 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3153 */
3154 [pbn_ADDIDATA_PCIe_1_3906250] = {
3155 .flags = FL_BASE0,
3156 .num_ports = 1,
3157 .base_baud = 3906250,
3158 .uart_offset = 0x200,
3159 .first_offset = 0x1000,
3160 },
3161 [pbn_ADDIDATA_PCIe_2_3906250] = {
3162 .flags = FL_BASE0,
3163 .num_ports = 2,
3164 .base_baud = 3906250,
3165 .uart_offset = 0x200,
3166 .first_offset = 0x1000,
3167 },
3168 [pbn_ADDIDATA_PCIe_4_3906250] = {
3169 .flags = FL_BASE0,
3170 .num_ports = 4,
3171 .base_baud = 3906250,
3172 .uart_offset = 0x200,
3173 .first_offset = 0x1000,
3174 },
3175 [pbn_ADDIDATA_PCIe_8_3906250] = {
3176 .flags = FL_BASE0,
3177 .num_ports = 8,
3178 .base_baud = 3906250,
3179 .uart_offset = 0x200,
3180 .first_offset = 0x1000,
3181 },
3182 [pbn_ce4100_1_115200] = {
3183 .flags = FL_BASE_BARS,
3184 .num_ports = 2,
3185 .base_baud = 921600,
3186 .reg_shift = 2,
3187 },
3188 [pbn_omegapci] = {
3189 .flags = FL_BASE0,
3190 .num_ports = 8,
3191 .base_baud = 115200,
3192 .uart_offset = 0x200,
3193 },
3194 [pbn_NETMOS9900_2s_115200] = {
3195 .flags = FL_BASE0,
3196 .num_ports = 2,
3197 .base_baud = 115200,
3198 },
3199 [pbn_brcm_trumanage] = {
3200 .flags = FL_BASE0,
3201 .num_ports = 1,
3202 .reg_shift = 2,
3203 .base_baud = 115200,
3204 },
3205 };
3206
3207 static const struct pci_device_id blacklist[] = {
3208 /* softmodems */
3209 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3210 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3211 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3212
3213 /* multi-io cards handled by parport_serial */
3214 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3215 };
3216
3217 /*
3218 * Given a complete unknown PCI device, try to use some heuristics to
3219 * guess what the configuration might be, based on the pitiful PCI
3220 * serial specs. Returns 0 on success, 1 on failure.
3221 */
3222 static int
3223 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3224 {
3225 const struct pci_device_id *bldev;
3226 int num_iomem, num_port, first_port = -1, i;
3227
3228 /*
3229 * If it is not a communications device or the programming
3230 * interface is greater than 6, give up.
3231 *
3232 * (Should we try to make guesses for multiport serial devices
3233 * later?)
3234 */
3235 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3236 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3237 (dev->class & 0xff) > 6)
3238 return -ENODEV;
3239
3240 /*
3241 * Do not access blacklisted devices that are known not to
3242 * feature serial ports or are handled by other modules.
3243 */
3244 for (bldev = blacklist;
3245 bldev < blacklist + ARRAY_SIZE(blacklist);
3246 bldev++) {
3247 if (dev->vendor == bldev->vendor &&
3248 dev->device == bldev->device)
3249 return -ENODEV;
3250 }
3251
3252 num_iomem = num_port = 0;
3253 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3254 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3255 num_port++;
3256 if (first_port == -1)
3257 first_port = i;
3258 }
3259 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3260 num_iomem++;
3261 }
3262
3263 /*
3264 * If there is 1 or 0 iomem regions, and exactly one port,
3265 * use it. We guess the number of ports based on the IO
3266 * region size.
3267 */
3268 if (num_iomem <= 1 && num_port == 1) {
3269 board->flags = first_port;
3270 board->num_ports = pci_resource_len(dev, first_port) / 8;
3271 return 0;
3272 }
3273
3274 /*
3275 * Now guess if we've got a board which indexes by BARs.
3276 * Each IO BAR should be 8 bytes, and they should follow
3277 * consecutively.
3278 */
3279 first_port = -1;
3280 num_port = 0;
3281 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3282 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3283 pci_resource_len(dev, i) == 8 &&
3284 (first_port == -1 || (first_port + num_port) == i)) {
3285 num_port++;
3286 if (first_port == -1)
3287 first_port = i;
3288 }
3289 }
3290
3291 if (num_port > 1) {
3292 board->flags = first_port | FL_BASE_BARS;
3293 board->num_ports = num_port;
3294 return 0;
3295 }
3296
3297 return -ENODEV;
3298 }
3299
3300 static inline int
3301 serial_pci_matches(const struct pciserial_board *board,
3302 const struct pciserial_board *guessed)
3303 {
3304 return
3305 board->num_ports == guessed->num_ports &&
3306 board->base_baud == guessed->base_baud &&
3307 board->uart_offset == guessed->uart_offset &&
3308 board->reg_shift == guessed->reg_shift &&
3309 board->first_offset == guessed->first_offset;
3310 }
3311
3312 struct serial_private *
3313 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3314 {
3315 struct uart_8250_port uart;
3316 struct serial_private *priv;
3317 struct pci_serial_quirk *quirk;
3318 int rc, nr_ports, i;
3319
3320 nr_ports = board->num_ports;
3321
3322 /*
3323 * Find an init and setup quirks.
3324 */
3325 quirk = find_quirk(dev);
3326
3327 /*
3328 * Run the new-style initialization function.
3329 * The initialization function returns:
3330 * <0 - error
3331 * 0 - use board->num_ports
3332 * >0 - number of ports
3333 */
3334 if (quirk->init) {
3335 rc = quirk->init(dev);
3336 if (rc < 0) {
3337 priv = ERR_PTR(rc);
3338 goto err_out;
3339 }
3340 if (rc)
3341 nr_ports = rc;
3342 }
3343
3344 priv = kzalloc(sizeof(struct serial_private) +
3345 sizeof(unsigned int) * nr_ports,
3346 GFP_KERNEL);
3347 if (!priv) {
3348 priv = ERR_PTR(-ENOMEM);
3349 goto err_deinit;
3350 }
3351
3352 priv->dev = dev;
3353 priv->quirk = quirk;
3354
3355 memset(&uart, 0, sizeof(uart));
3356 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3357 uart.port.uartclk = board->base_baud * 16;
3358 uart.port.irq = get_pci_irq(dev, board);
3359 uart.port.dev = &dev->dev;
3360
3361 for (i = 0; i < nr_ports; i++) {
3362 if (quirk->setup(priv, board, &uart, i))
3363 break;
3364
3365 #ifdef SERIAL_DEBUG_PCI
3366 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
3367 uart.port.iobase, uart.port.irq, uart.port.iotype);
3368 #endif
3369
3370 priv->line[i] = serial8250_register_8250_port(&uart);
3371 if (priv->line[i] < 0) {
3372 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3373 break;
3374 }
3375 }
3376 priv->nr = i;
3377 return priv;
3378
3379 err_deinit:
3380 if (quirk->exit)
3381 quirk->exit(dev);
3382 err_out:
3383 return priv;
3384 }
3385 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3386
3387 void pciserial_remove_ports(struct serial_private *priv)
3388 {
3389 struct pci_serial_quirk *quirk;
3390 int i;
3391
3392 for (i = 0; i < priv->nr; i++)
3393 serial8250_unregister_port(priv->line[i]);
3394
3395 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3396 if (priv->remapped_bar[i])
3397 iounmap(priv->remapped_bar[i]);
3398 priv->remapped_bar[i] = NULL;
3399 }
3400
3401 /*
3402 * Find the exit quirks.
3403 */
3404 quirk = find_quirk(priv->dev);
3405 if (quirk->exit)
3406 quirk->exit(priv->dev);
3407
3408 kfree(priv);
3409 }
3410 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3411
3412 void pciserial_suspend_ports(struct serial_private *priv)
3413 {
3414 int i;
3415
3416 for (i = 0; i < priv->nr; i++)
3417 if (priv->line[i] >= 0)
3418 serial8250_suspend_port(priv->line[i]);
3419
3420 /*
3421 * Ensure that every init quirk is properly torn down
3422 */
3423 if (priv->quirk->exit)
3424 priv->quirk->exit(priv->dev);
3425 }
3426 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3427
3428 void pciserial_resume_ports(struct serial_private *priv)
3429 {
3430 int i;
3431
3432 /*
3433 * Ensure that the board is correctly configured.
3434 */
3435 if (priv->quirk->init)
3436 priv->quirk->init(priv->dev);
3437
3438 for (i = 0; i < priv->nr; i++)
3439 if (priv->line[i] >= 0)
3440 serial8250_resume_port(priv->line[i]);
3441 }
3442 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3443
3444 /*
3445 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3446 * to the arrangement of serial ports on a PCI card.
3447 */
3448 static int
3449 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3450 {
3451 struct pci_serial_quirk *quirk;
3452 struct serial_private *priv;
3453 const struct pciserial_board *board;
3454 struct pciserial_board tmp;
3455 int rc;
3456
3457 quirk = find_quirk(dev);
3458 if (quirk->probe) {
3459 rc = quirk->probe(dev);
3460 if (rc)
3461 return rc;
3462 }
3463
3464 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3465 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3466 ent->driver_data);
3467 return -EINVAL;
3468 }
3469
3470 board = &pci_boards[ent->driver_data];
3471
3472 rc = pci_enable_device(dev);
3473 pci_save_state(dev);
3474 if (rc)
3475 return rc;
3476
3477 if (ent->driver_data == pbn_default) {
3478 /*
3479 * Use a copy of the pci_board entry for this;
3480 * avoid changing entries in the table.
3481 */
3482 memcpy(&tmp, board, sizeof(struct pciserial_board));
3483 board = &tmp;
3484
3485 /*
3486 * We matched one of our class entries. Try to
3487 * determine the parameters of this board.
3488 */
3489 rc = serial_pci_guess_board(dev, &tmp);
3490 if (rc)
3491 goto disable;
3492 } else {
3493 /*
3494 * We matched an explicit entry. If we are able to
3495 * detect this boards settings with our heuristic,
3496 * then we no longer need this entry.
3497 */
3498 memcpy(&tmp, &pci_boards[pbn_default],
3499 sizeof(struct pciserial_board));
3500 rc = serial_pci_guess_board(dev, &tmp);
3501 if (rc == 0 && serial_pci_matches(board, &tmp))
3502 moan_device("Redundant entry in serial pci_table.",
3503 dev);
3504 }
3505
3506 priv = pciserial_init_ports(dev, board);
3507 if (!IS_ERR(priv)) {
3508 pci_set_drvdata(dev, priv);
3509 return 0;
3510 }
3511
3512 rc = PTR_ERR(priv);
3513
3514 disable:
3515 pci_disable_device(dev);
3516 return rc;
3517 }
3518
3519 static void pciserial_remove_one(struct pci_dev *dev)
3520 {
3521 struct serial_private *priv = pci_get_drvdata(dev);
3522
3523 pci_set_drvdata(dev, NULL);
3524
3525 pciserial_remove_ports(priv);
3526
3527 pci_disable_device(dev);
3528 }
3529
3530 #ifdef CONFIG_PM
3531 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3532 {
3533 struct serial_private *priv = pci_get_drvdata(dev);
3534
3535 if (priv)
3536 pciserial_suspend_ports(priv);
3537
3538 pci_save_state(dev);
3539 pci_set_power_state(dev, pci_choose_state(dev, state));
3540 return 0;
3541 }
3542
3543 static int pciserial_resume_one(struct pci_dev *dev)
3544 {
3545 int err;
3546 struct serial_private *priv = pci_get_drvdata(dev);
3547
3548 pci_set_power_state(dev, PCI_D0);
3549 pci_restore_state(dev);
3550
3551 if (priv) {
3552 /*
3553 * The device may have been disabled. Re-enable it.
3554 */
3555 err = pci_enable_device(dev);
3556 /* FIXME: We cannot simply error out here */
3557 if (err)
3558 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3559 pciserial_resume_ports(priv);
3560 }
3561 return 0;
3562 }
3563 #endif
3564
3565 static struct pci_device_id serial_pci_tbl[] = {
3566 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3567 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3568 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3569 pbn_b2_8_921600 },
3570 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3571 PCI_SUBVENDOR_ID_CONNECT_TECH,
3572 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3573 pbn_b1_8_1382400 },
3574 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3575 PCI_SUBVENDOR_ID_CONNECT_TECH,
3576 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3577 pbn_b1_4_1382400 },
3578 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3579 PCI_SUBVENDOR_ID_CONNECT_TECH,
3580 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3581 pbn_b1_2_1382400 },
3582 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3583 PCI_SUBVENDOR_ID_CONNECT_TECH,
3584 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3585 pbn_b1_8_1382400 },
3586 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3587 PCI_SUBVENDOR_ID_CONNECT_TECH,
3588 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3589 pbn_b1_4_1382400 },
3590 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3591 PCI_SUBVENDOR_ID_CONNECT_TECH,
3592 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3593 pbn_b1_2_1382400 },
3594 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3595 PCI_SUBVENDOR_ID_CONNECT_TECH,
3596 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3597 pbn_b1_8_921600 },
3598 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3599 PCI_SUBVENDOR_ID_CONNECT_TECH,
3600 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3601 pbn_b1_8_921600 },
3602 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3603 PCI_SUBVENDOR_ID_CONNECT_TECH,
3604 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3605 pbn_b1_4_921600 },
3606 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3607 PCI_SUBVENDOR_ID_CONNECT_TECH,
3608 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3609 pbn_b1_4_921600 },
3610 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3611 PCI_SUBVENDOR_ID_CONNECT_TECH,
3612 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3613 pbn_b1_2_921600 },
3614 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3615 PCI_SUBVENDOR_ID_CONNECT_TECH,
3616 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3617 pbn_b1_8_921600 },
3618 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3619 PCI_SUBVENDOR_ID_CONNECT_TECH,
3620 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3621 pbn_b1_8_921600 },
3622 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3623 PCI_SUBVENDOR_ID_CONNECT_TECH,
3624 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3625 pbn_b1_4_921600 },
3626 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3627 PCI_SUBVENDOR_ID_CONNECT_TECH,
3628 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3629 pbn_b1_2_1250000 },
3630 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3631 PCI_SUBVENDOR_ID_CONNECT_TECH,
3632 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3633 pbn_b0_2_1843200 },
3634 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3635 PCI_SUBVENDOR_ID_CONNECT_TECH,
3636 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3637 pbn_b0_4_1843200 },
3638 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3639 PCI_VENDOR_ID_AFAVLAB,
3640 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3641 pbn_b0_4_1152000 },
3642 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3643 PCI_SUBVENDOR_ID_CONNECT_TECH,
3644 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3645 pbn_b0_2_1843200_200 },
3646 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3647 PCI_SUBVENDOR_ID_CONNECT_TECH,
3648 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3649 pbn_b0_4_1843200_200 },
3650 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3651 PCI_SUBVENDOR_ID_CONNECT_TECH,
3652 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3653 pbn_b0_8_1843200_200 },
3654 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3655 PCI_SUBVENDOR_ID_CONNECT_TECH,
3656 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3657 pbn_b0_2_1843200_200 },
3658 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3659 PCI_SUBVENDOR_ID_CONNECT_TECH,
3660 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3661 pbn_b0_4_1843200_200 },
3662 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3663 PCI_SUBVENDOR_ID_CONNECT_TECH,
3664 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3665 pbn_b0_8_1843200_200 },
3666 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3667 PCI_SUBVENDOR_ID_CONNECT_TECH,
3668 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3669 pbn_b0_2_1843200_200 },
3670 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3671 PCI_SUBVENDOR_ID_CONNECT_TECH,
3672 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3673 pbn_b0_4_1843200_200 },
3674 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3675 PCI_SUBVENDOR_ID_CONNECT_TECH,
3676 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3677 pbn_b0_8_1843200_200 },
3678 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3679 PCI_SUBVENDOR_ID_CONNECT_TECH,
3680 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3681 pbn_b0_2_1843200_200 },
3682 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3683 PCI_SUBVENDOR_ID_CONNECT_TECH,
3684 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3685 pbn_b0_4_1843200_200 },
3686 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3687 PCI_SUBVENDOR_ID_CONNECT_TECH,
3688 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3689 pbn_b0_8_1843200_200 },
3690 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3691 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3692 0, 0, pbn_exar_ibm_saturn },
3693
3694 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3696 pbn_b2_bt_1_115200 },
3697 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3699 pbn_b2_bt_2_115200 },
3700 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3702 pbn_b2_bt_4_115200 },
3703 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3705 pbn_b2_bt_2_115200 },
3706 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3708 pbn_b2_bt_4_115200 },
3709 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3711 pbn_b2_8_115200 },
3712 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3714 pbn_b2_8_460800 },
3715 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3717 pbn_b2_8_115200 },
3718
3719 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3721 pbn_b2_bt_2_115200 },
3722 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3724 pbn_b2_bt_2_921600 },
3725 /*
3726 * VScom SPCOM800, from sl@s.pl
3727 */
3728 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3730 pbn_b2_8_921600 },
3731 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3733 pbn_b2_4_921600 },
3734 /* Unknown card - subdevice 0x1584 */
3735 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3736 PCI_VENDOR_ID_PLX,
3737 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3738 pbn_b2_4_115200 },
3739 /* Unknown card - subdevice 0x1588 */
3740 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3741 PCI_VENDOR_ID_PLX,
3742 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3743 pbn_b2_8_115200 },
3744 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3745 PCI_SUBVENDOR_ID_KEYSPAN,
3746 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3747 pbn_panacom },
3748 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3750 pbn_panacom4 },
3751 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3753 pbn_panacom2 },
3754 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3755 PCI_VENDOR_ID_ESDGMBH,
3756 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3757 pbn_b2_4_115200 },
3758 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3759 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3760 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3761 pbn_b2_4_460800 },
3762 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3763 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3764 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3765 pbn_b2_8_460800 },
3766 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3767 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3768 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3769 pbn_b2_16_460800 },
3770 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3771 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3772 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3773 pbn_b2_16_460800 },
3774 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3775 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3776 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3777 pbn_b2_4_460800 },
3778 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3779 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3780 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3781 pbn_b2_8_460800 },
3782 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3783 PCI_SUBVENDOR_ID_EXSYS,
3784 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3785 pbn_b2_4_115200 },
3786 /*
3787 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3788 * (Exoray@isys.ca)
3789 */
3790 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3791 0x10b5, 0x106a, 0, 0,
3792 pbn_plx_romulus },
3793 /*
3794 * Quatech cards. These actually have configurable clocks but for
3795 * now we just use the default.
3796 *
3797 * 100 series are RS232, 200 series RS422,
3798 */
3799 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3801 pbn_b1_4_115200 },
3802 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3804 pbn_b1_2_115200 },
3805 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3807 pbn_b2_2_115200 },
3808 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3810 pbn_b1_2_115200 },
3811 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3813 pbn_b2_2_115200 },
3814 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3816 pbn_b1_4_115200 },
3817 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3819 pbn_b1_8_115200 },
3820 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3822 pbn_b1_8_115200 },
3823 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3825 pbn_b1_4_115200 },
3826 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3828 pbn_b1_2_115200 },
3829 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3831 pbn_b1_4_115200 },
3832 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3834 pbn_b1_2_115200 },
3835 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3837 pbn_b2_4_115200 },
3838 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840 pbn_b2_2_115200 },
3841 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3843 pbn_b2_1_115200 },
3844 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3846 pbn_b2_4_115200 },
3847 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3849 pbn_b2_2_115200 },
3850 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3851 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3852 pbn_b2_1_115200 },
3853 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3854 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3855 pbn_b0_8_115200 },
3856
3857 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3858 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3859 0, 0,
3860 pbn_b0_4_921600 },
3861 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3862 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3863 0, 0,
3864 pbn_b0_4_1152000 },
3865 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3867 pbn_b0_bt_2_921600 },
3868
3869 /*
3870 * The below card is a little controversial since it is the
3871 * subject of a PCI vendor/device ID clash. (See
3872 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3873 * For now just used the hex ID 0x950a.
3874 */
3875 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3876 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3877 0, 0, pbn_b0_2_115200 },
3878 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3879 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3880 0, 0, pbn_b0_2_115200 },
3881 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3883 pbn_b0_2_1130000 },
3884 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3885 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3886 pbn_b0_1_921600 },
3887 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3889 pbn_b0_4_115200 },
3890 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3892 pbn_b0_bt_2_921600 },
3893 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3894 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3895 pbn_b2_8_1152000 },
3896
3897 /*
3898 * Oxford Semiconductor Inc. Tornado PCI express device range.
3899 */
3900 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3902 pbn_b0_1_4000000 },
3903 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3905 pbn_b0_1_4000000 },
3906 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3908 pbn_oxsemi_1_4000000 },
3909 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3911 pbn_oxsemi_1_4000000 },
3912 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3914 pbn_b0_1_4000000 },
3915 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3917 pbn_b0_1_4000000 },
3918 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3920 pbn_oxsemi_1_4000000 },
3921 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3923 pbn_oxsemi_1_4000000 },
3924 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3926 pbn_b0_1_4000000 },
3927 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929 pbn_b0_1_4000000 },
3930 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932 pbn_b0_1_4000000 },
3933 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 pbn_b0_1_4000000 },
3936 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3938 pbn_oxsemi_2_4000000 },
3939 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941 pbn_oxsemi_2_4000000 },
3942 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 pbn_oxsemi_4_4000000 },
3945 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947 pbn_oxsemi_4_4000000 },
3948 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 pbn_oxsemi_8_4000000 },
3951 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_oxsemi_8_4000000 },
3954 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 pbn_oxsemi_1_4000000 },
3957 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3959 pbn_oxsemi_1_4000000 },
3960 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 pbn_oxsemi_1_4000000 },
3963 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 pbn_oxsemi_1_4000000 },
3966 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968 pbn_oxsemi_1_4000000 },
3969 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 pbn_oxsemi_1_4000000 },
3972 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 pbn_oxsemi_1_4000000 },
3975 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 pbn_oxsemi_1_4000000 },
3978 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 pbn_oxsemi_1_4000000 },
3981 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 pbn_oxsemi_1_4000000 },
3984 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 pbn_oxsemi_1_4000000 },
3987 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 pbn_oxsemi_1_4000000 },
3990 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 pbn_oxsemi_1_4000000 },
3993 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3995 pbn_oxsemi_1_4000000 },
3996 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3998 pbn_oxsemi_1_4000000 },
3999 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4001 pbn_oxsemi_1_4000000 },
4002 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4004 pbn_oxsemi_1_4000000 },
4005 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4007 pbn_oxsemi_1_4000000 },
4008 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4010 pbn_oxsemi_1_4000000 },
4011 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4012 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4013 pbn_oxsemi_1_4000000 },
4014 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4015 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4016 pbn_oxsemi_1_4000000 },
4017 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4018 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4019 pbn_oxsemi_1_4000000 },
4020 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4021 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4022 pbn_oxsemi_1_4000000 },
4023 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4024 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4025 pbn_oxsemi_1_4000000 },
4026 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4027 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4028 pbn_oxsemi_1_4000000 },
4029 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031 pbn_oxsemi_1_4000000 },
4032 /*
4033 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4034 */
4035 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4036 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4037 pbn_oxsemi_1_4000000 },
4038 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4039 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4040 pbn_oxsemi_2_4000000 },
4041 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4042 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4043 pbn_oxsemi_4_4000000 },
4044 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4045 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4046 pbn_oxsemi_8_4000000 },
4047
4048 /*
4049 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4050 */
4051 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4052 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4053 pbn_oxsemi_2_4000000 },
4054
4055 /*
4056 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4057 * from skokodyn@yahoo.com
4058 */
4059 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4060 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4061 pbn_sbsxrsio },
4062 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4063 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4064 pbn_sbsxrsio },
4065 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4066 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4067 pbn_sbsxrsio },
4068 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4069 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4070 pbn_sbsxrsio },
4071
4072 /*
4073 * Digitan DS560-558, from jimd@esoft.com
4074 */
4075 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077 pbn_b1_1_115200 },
4078
4079 /*
4080 * Titan Electronic cards
4081 * The 400L and 800L have a custom setup quirk.
4082 */
4083 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 pbn_b0_1_921600 },
4086 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 pbn_b0_2_921600 },
4089 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 pbn_b0_4_921600 },
4092 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_b0_4_921600 },
4095 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097 pbn_b1_1_921600 },
4098 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100 pbn_b1_bt_2_921600 },
4101 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 pbn_b0_bt_4_921600 },
4104 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106 pbn_b0_bt_8_921600 },
4107 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 pbn_b4_bt_2_921600 },
4110 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112 pbn_b4_bt_4_921600 },
4113 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4115 pbn_b4_bt_8_921600 },
4116 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118 pbn_b0_4_921600 },
4119 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4121 pbn_b0_4_921600 },
4122 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4124 pbn_b0_4_921600 },
4125 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4127 pbn_oxsemi_1_4000000 },
4128 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130 pbn_oxsemi_2_4000000 },
4131 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4133 pbn_oxsemi_4_4000000 },
4134 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4136 pbn_oxsemi_8_4000000 },
4137 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139 pbn_oxsemi_2_4000000 },
4140 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142 pbn_oxsemi_2_4000000 },
4143 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4145 pbn_b0_bt_2_921600 },
4146 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4148 pbn_b0_4_921600 },
4149 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151 pbn_b0_4_921600 },
4152 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 pbn_b0_4_921600 },
4155 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4157 pbn_b0_4_921600 },
4158
4159 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_b2_1_460800 },
4162 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_b2_1_460800 },
4165 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 pbn_b2_1_460800 },
4168 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_b2_bt_2_921600 },
4171 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 pbn_b2_bt_2_921600 },
4174 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 pbn_b2_bt_2_921600 },
4177 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179 pbn_b2_bt_4_921600 },
4180 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 pbn_b2_bt_4_921600 },
4183 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4185 pbn_b2_bt_4_921600 },
4186 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4188 pbn_b0_1_921600 },
4189 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4191 pbn_b0_1_921600 },
4192 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4194 pbn_b0_1_921600 },
4195 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4197 pbn_b0_bt_2_921600 },
4198 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4200 pbn_b0_bt_2_921600 },
4201 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4203 pbn_b0_bt_2_921600 },
4204 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4206 pbn_b0_bt_4_921600 },
4207 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4209 pbn_b0_bt_4_921600 },
4210 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4212 pbn_b0_bt_4_921600 },
4213 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4215 pbn_b0_bt_8_921600 },
4216 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218 pbn_b0_bt_8_921600 },
4219 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221 pbn_b0_bt_8_921600 },
4222
4223 /*
4224 * Computone devices submitted by Doug McNash dmcnash@computone.com
4225 */
4226 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4227 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4228 0, 0, pbn_computone_4 },
4229 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4230 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4231 0, 0, pbn_computone_8 },
4232 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4233 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4234 0, 0, pbn_computone_6 },
4235
4236 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238 pbn_oxsemi },
4239 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4240 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4241 pbn_b0_bt_1_921600 },
4242
4243 /*
4244 * SUNIX (TIMEDIA)
4245 */
4246 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4247 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4248 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4249 pbn_b0_bt_1_921600 },
4250
4251 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4252 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4253 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4254 pbn_b0_bt_1_921600 },
4255
4256 /*
4257 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4258 */
4259 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_b0_bt_8_115200 },
4262 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_b0_bt_8_115200 },
4265
4266 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268 pbn_b0_bt_2_115200 },
4269 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4271 pbn_b0_bt_2_115200 },
4272 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4274 pbn_b0_bt_2_115200 },
4275 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4277 pbn_b0_bt_2_115200 },
4278 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280 pbn_b0_bt_2_115200 },
4281 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283 pbn_b0_bt_4_460800 },
4284 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286 pbn_b0_bt_4_460800 },
4287 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 pbn_b0_bt_2_460800 },
4290 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292 pbn_b0_bt_2_460800 },
4293 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295 pbn_b0_bt_2_460800 },
4296 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_b0_bt_1_115200 },
4299 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_b0_bt_1_460800 },
4302
4303 /*
4304 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4305 * Cards are identified by their subsystem vendor IDs, which
4306 * (in hex) match the model number.
4307 *
4308 * Note that JC140x are RS422/485 cards which require ox950
4309 * ACR = 0x10, and as such are not currently fully supported.
4310 */
4311 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4312 0x1204, 0x0004, 0, 0,
4313 pbn_b0_4_921600 },
4314 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4315 0x1208, 0x0004, 0, 0,
4316 pbn_b0_4_921600 },
4317 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4318 0x1402, 0x0002, 0, 0,
4319 pbn_b0_2_921600 }, */
4320 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4321 0x1404, 0x0004, 0, 0,
4322 pbn_b0_4_921600 }, */
4323 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4324 0x1208, 0x0004, 0, 0,
4325 pbn_b0_4_921600 },
4326
4327 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4328 0x1204, 0x0004, 0, 0,
4329 pbn_b0_4_921600 },
4330 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4331 0x1208, 0x0004, 0, 0,
4332 pbn_b0_4_921600 },
4333 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4334 0x1208, 0x0004, 0, 0,
4335 pbn_b0_4_921600 },
4336 /*
4337 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4338 */
4339 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341 pbn_b1_1_1382400 },
4342
4343 /*
4344 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4345 */
4346 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b1_1_1382400 },
4349
4350 /*
4351 * RAStel 2 port modem, gerg@moreton.com.au
4352 */
4353 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 pbn_b2_bt_2_115200 },
4356
4357 /*
4358 * EKF addition for i960 Boards form EKF with serial port
4359 */
4360 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4361 0xE4BF, PCI_ANY_ID, 0, 0,
4362 pbn_intel_i960 },
4363
4364 /*
4365 * Xircom Cardbus/Ethernet combos
4366 */
4367 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 pbn_b0_1_115200 },
4370 /*
4371 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4372 */
4373 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 pbn_b0_1_115200 },
4376
4377 /*
4378 * Untested PCI modems, sent in from various folks...
4379 */
4380
4381 /*
4382 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4383 */
4384 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4385 0x1048, 0x1500, 0, 0,
4386 pbn_b1_1_115200 },
4387
4388 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4389 0xFF00, 0, 0, 0,
4390 pbn_sgi_ioc3 },
4391
4392 /*
4393 * HP Diva card
4394 */
4395 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4396 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4397 pbn_b1_1_115200 },
4398 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_b0_5_115200 },
4401 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_b2_1_115200 },
4404
4405 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b3_2_115200 },
4408 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b3_4_115200 },
4411 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_b3_8_115200 },
4414
4415 /*
4416 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4417 */
4418 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4419 PCI_ANY_ID, PCI_ANY_ID,
4420 0,
4421 0, pbn_exar_XR17C152 },
4422 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4423 PCI_ANY_ID, PCI_ANY_ID,
4424 0,
4425 0, pbn_exar_XR17C154 },
4426 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4427 PCI_ANY_ID, PCI_ANY_ID,
4428 0,
4429 0, pbn_exar_XR17C158 },
4430 /*
4431 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4432 */
4433 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4434 PCI_ANY_ID, PCI_ANY_ID,
4435 0,
4436 0, pbn_exar_XR17V352 },
4437 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4438 PCI_ANY_ID, PCI_ANY_ID,
4439 0,
4440 0, pbn_exar_XR17V354 },
4441 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4442 PCI_ANY_ID, PCI_ANY_ID,
4443 0,
4444 0, pbn_exar_XR17V358 },
4445
4446 /*
4447 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4448 */
4449 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b0_1_115200 },
4452 /*
4453 * ITE
4454 */
4455 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4456 PCI_ANY_ID, PCI_ANY_ID,
4457 0, 0,
4458 pbn_b1_bt_1_115200 },
4459
4460 /*
4461 * IntaShield IS-200
4462 */
4463 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4464 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4465 pbn_b2_2_115200 },
4466 /*
4467 * IntaShield IS-400
4468 */
4469 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4471 pbn_b2_4_115200 },
4472 /*
4473 * Perle PCI-RAS cards
4474 */
4475 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4476 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4477 0, 0, pbn_b2_4_921600 },
4478 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4479 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4480 0, 0, pbn_b2_8_921600 },
4481
4482 /*
4483 * Mainpine series cards: Fairly standard layout but fools
4484 * parts of the autodetect in some cases and uses otherwise
4485 * unmatched communications subclasses in the PCI Express case
4486 */
4487
4488 { /* RockForceDUO */
4489 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4490 PCI_VENDOR_ID_MAINPINE, 0x0200,
4491 0, 0, pbn_b0_2_115200 },
4492 { /* RockForceQUATRO */
4493 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4494 PCI_VENDOR_ID_MAINPINE, 0x0300,
4495 0, 0, pbn_b0_4_115200 },
4496 { /* RockForceDUO+ */
4497 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4498 PCI_VENDOR_ID_MAINPINE, 0x0400,
4499 0, 0, pbn_b0_2_115200 },
4500 { /* RockForceQUATRO+ */
4501 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4502 PCI_VENDOR_ID_MAINPINE, 0x0500,
4503 0, 0, pbn_b0_4_115200 },
4504 { /* RockForce+ */
4505 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4506 PCI_VENDOR_ID_MAINPINE, 0x0600,
4507 0, 0, pbn_b0_2_115200 },
4508 { /* RockForce+ */
4509 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4510 PCI_VENDOR_ID_MAINPINE, 0x0700,
4511 0, 0, pbn_b0_4_115200 },
4512 { /* RockForceOCTO+ */
4513 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4514 PCI_VENDOR_ID_MAINPINE, 0x0800,
4515 0, 0, pbn_b0_8_115200 },
4516 { /* RockForceDUO+ */
4517 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4518 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4519 0, 0, pbn_b0_2_115200 },
4520 { /* RockForceQUARTRO+ */
4521 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4522 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4523 0, 0, pbn_b0_4_115200 },
4524 { /* RockForceOCTO+ */
4525 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4526 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4527 0, 0, pbn_b0_8_115200 },
4528 { /* RockForceD1 */
4529 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4530 PCI_VENDOR_ID_MAINPINE, 0x2000,
4531 0, 0, pbn_b0_1_115200 },
4532 { /* RockForceF1 */
4533 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4534 PCI_VENDOR_ID_MAINPINE, 0x2100,
4535 0, 0, pbn_b0_1_115200 },
4536 { /* RockForceD2 */
4537 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4538 PCI_VENDOR_ID_MAINPINE, 0x2200,
4539 0, 0, pbn_b0_2_115200 },
4540 { /* RockForceF2 */
4541 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4542 PCI_VENDOR_ID_MAINPINE, 0x2300,
4543 0, 0, pbn_b0_2_115200 },
4544 { /* RockForceD4 */
4545 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4546 PCI_VENDOR_ID_MAINPINE, 0x2400,
4547 0, 0, pbn_b0_4_115200 },
4548 { /* RockForceF4 */
4549 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4550 PCI_VENDOR_ID_MAINPINE, 0x2500,
4551 0, 0, pbn_b0_4_115200 },
4552 { /* RockForceD8 */
4553 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4554 PCI_VENDOR_ID_MAINPINE, 0x2600,
4555 0, 0, pbn_b0_8_115200 },
4556 { /* RockForceF8 */
4557 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4558 PCI_VENDOR_ID_MAINPINE, 0x2700,
4559 0, 0, pbn_b0_8_115200 },
4560 { /* IQ Express D1 */
4561 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4562 PCI_VENDOR_ID_MAINPINE, 0x3000,
4563 0, 0, pbn_b0_1_115200 },
4564 { /* IQ Express F1 */
4565 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4566 PCI_VENDOR_ID_MAINPINE, 0x3100,
4567 0, 0, pbn_b0_1_115200 },
4568 { /* IQ Express D2 */
4569 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4570 PCI_VENDOR_ID_MAINPINE, 0x3200,
4571 0, 0, pbn_b0_2_115200 },
4572 { /* IQ Express F2 */
4573 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4574 PCI_VENDOR_ID_MAINPINE, 0x3300,
4575 0, 0, pbn_b0_2_115200 },
4576 { /* IQ Express D4 */
4577 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4578 PCI_VENDOR_ID_MAINPINE, 0x3400,
4579 0, 0, pbn_b0_4_115200 },
4580 { /* IQ Express F4 */
4581 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4582 PCI_VENDOR_ID_MAINPINE, 0x3500,
4583 0, 0, pbn_b0_4_115200 },
4584 { /* IQ Express D8 */
4585 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4586 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4587 0, 0, pbn_b0_8_115200 },
4588 { /* IQ Express F8 */
4589 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4590 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4591 0, 0, pbn_b0_8_115200 },
4592
4593
4594 /*
4595 * PA Semi PA6T-1682M on-chip UART
4596 */
4597 { PCI_VENDOR_ID_PASEMI, 0xa004,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_pasemi_1682M },
4600
4601 /*
4602 * National Instruments
4603 */
4604 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_b1_16_115200 },
4607 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_b1_8_115200 },
4610 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_b1_bt_4_115200 },
4613 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_b1_bt_2_115200 },
4616 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_b1_bt_4_115200 },
4619 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_b1_bt_2_115200 },
4622 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_b1_16_115200 },
4625 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_b1_8_115200 },
4628 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_b1_bt_4_115200 },
4631 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b1_bt_2_115200 },
4634 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b1_bt_4_115200 },
4637 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b1_bt_2_115200 },
4640 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_ni8430_2 },
4643 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_ni8430_2 },
4646 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_ni8430_4 },
4649 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_ni8430_4 },
4652 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_ni8430_8 },
4655 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_ni8430_8 },
4658 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_ni8430_16 },
4661 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_ni8430_16 },
4664 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_ni8430_2 },
4667 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_ni8430_2 },
4670 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_ni8430_4 },
4673 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_ni8430_4 },
4676
4677 /*
4678 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4679 */
4680 { PCI_VENDOR_ID_ADDIDATA,
4681 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4682 PCI_ANY_ID,
4683 PCI_ANY_ID,
4684 0,
4685 0,
4686 pbn_b0_4_115200 },
4687
4688 { PCI_VENDOR_ID_ADDIDATA,
4689 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4690 PCI_ANY_ID,
4691 PCI_ANY_ID,
4692 0,
4693 0,
4694 pbn_b0_2_115200 },
4695
4696 { PCI_VENDOR_ID_ADDIDATA,
4697 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4698 PCI_ANY_ID,
4699 PCI_ANY_ID,
4700 0,
4701 0,
4702 pbn_b0_1_115200 },
4703
4704 { PCI_VENDOR_ID_ADDIDATA_OLD,
4705 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4706 PCI_ANY_ID,
4707 PCI_ANY_ID,
4708 0,
4709 0,
4710 pbn_b1_8_115200 },
4711
4712 { PCI_VENDOR_ID_ADDIDATA,
4713 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4714 PCI_ANY_ID,
4715 PCI_ANY_ID,
4716 0,
4717 0,
4718 pbn_b0_4_115200 },
4719
4720 { PCI_VENDOR_ID_ADDIDATA,
4721 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4722 PCI_ANY_ID,
4723 PCI_ANY_ID,
4724 0,
4725 0,
4726 pbn_b0_2_115200 },
4727
4728 { PCI_VENDOR_ID_ADDIDATA,
4729 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4730 PCI_ANY_ID,
4731 PCI_ANY_ID,
4732 0,
4733 0,
4734 pbn_b0_1_115200 },
4735
4736 { PCI_VENDOR_ID_ADDIDATA,
4737 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4738 PCI_ANY_ID,
4739 PCI_ANY_ID,
4740 0,
4741 0,
4742 pbn_b0_4_115200 },
4743
4744 { PCI_VENDOR_ID_ADDIDATA,
4745 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4746 PCI_ANY_ID,
4747 PCI_ANY_ID,
4748 0,
4749 0,
4750 pbn_b0_2_115200 },
4751
4752 { PCI_VENDOR_ID_ADDIDATA,
4753 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4754 PCI_ANY_ID,
4755 PCI_ANY_ID,
4756 0,
4757 0,
4758 pbn_b0_1_115200 },
4759
4760 { PCI_VENDOR_ID_ADDIDATA,
4761 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4762 PCI_ANY_ID,
4763 PCI_ANY_ID,
4764 0,
4765 0,
4766 pbn_b0_8_115200 },
4767
4768 { PCI_VENDOR_ID_ADDIDATA,
4769 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4770 PCI_ANY_ID,
4771 PCI_ANY_ID,
4772 0,
4773 0,
4774 pbn_ADDIDATA_PCIe_4_3906250 },
4775
4776 { PCI_VENDOR_ID_ADDIDATA,
4777 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4778 PCI_ANY_ID,
4779 PCI_ANY_ID,
4780 0,
4781 0,
4782 pbn_ADDIDATA_PCIe_2_3906250 },
4783
4784 { PCI_VENDOR_ID_ADDIDATA,
4785 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4786 PCI_ANY_ID,
4787 PCI_ANY_ID,
4788 0,
4789 0,
4790 pbn_ADDIDATA_PCIe_1_3906250 },
4791
4792 { PCI_VENDOR_ID_ADDIDATA,
4793 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4794 PCI_ANY_ID,
4795 PCI_ANY_ID,
4796 0,
4797 0,
4798 pbn_ADDIDATA_PCIe_8_3906250 },
4799
4800 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4801 PCI_VENDOR_ID_IBM, 0x0299,
4802 0, 0, pbn_b0_bt_2_115200 },
4803
4804 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4805 0xA000, 0x1000,
4806 0, 0, pbn_b0_1_115200 },
4807
4808 /* the 9901 is a rebranded 9912 */
4809 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4810 0xA000, 0x1000,
4811 0, 0, pbn_b0_1_115200 },
4812
4813 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4814 0xA000, 0x1000,
4815 0, 0, pbn_b0_1_115200 },
4816
4817 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4818 0xA000, 0x1000,
4819 0, 0, pbn_b0_1_115200 },
4820
4821 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4822 0xA000, 0x1000,
4823 0, 0, pbn_b0_1_115200 },
4824
4825 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4826 0xA000, 0x3002,
4827 0, 0, pbn_NETMOS9900_2s_115200 },
4828
4829 /*
4830 * Best Connectivity and Rosewill PCI Multi I/O cards
4831 */
4832
4833 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4834 0xA000, 0x1000,
4835 0, 0, pbn_b0_1_115200 },
4836
4837 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4838 0xA000, 0x3002,
4839 0, 0, pbn_b0_bt_2_115200 },
4840
4841 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4842 0xA000, 0x3004,
4843 0, 0, pbn_b0_bt_4_115200 },
4844 /* Intel CE4100 */
4845 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_ce4100_1_115200 },
4848
4849 /*
4850 * Cronyx Omega PCI
4851 */
4852 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_omegapci },
4855
4856 /*
4857 * Broadcom TruManage
4858 */
4859 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4860 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4861 pbn_brcm_trumanage },
4862
4863 /*
4864 * AgeStar as-prs2-009
4865 */
4866 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4867 PCI_ANY_ID, PCI_ANY_ID,
4868 0, 0, pbn_b0_bt_2_115200 },
4869
4870 /*
4871 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4872 * so not listed here.
4873 */
4874 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4875 PCI_ANY_ID, PCI_ANY_ID,
4876 0, 0, pbn_b0_bt_4_115200 },
4877
4878 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4879 PCI_ANY_ID, PCI_ANY_ID,
4880 0, 0, pbn_b0_bt_2_115200 },
4881
4882 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
4883 PCI_ANY_ID, PCI_ANY_ID,
4884 0, 0, pbn_b0_bt_2_115200 },
4885
4886 /*
4887 * Commtech, Inc. Fastcom adapters
4888 */
4889 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4890 PCI_ANY_ID, PCI_ANY_ID,
4891 0,
4892 0, pbn_b0_2_1152000_200 },
4893 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4894 PCI_ANY_ID, PCI_ANY_ID,
4895 0,
4896 0, pbn_b0_4_1152000_200 },
4897 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4898 PCI_ANY_ID, PCI_ANY_ID,
4899 0,
4900 0, pbn_b0_4_1152000_200 },
4901 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4902 PCI_ANY_ID, PCI_ANY_ID,
4903 0,
4904 0, pbn_b0_8_1152000_200 },
4905 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4906 PCI_ANY_ID, PCI_ANY_ID,
4907 0,
4908 0, pbn_exar_XR17V352 },
4909 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4910 PCI_ANY_ID, PCI_ANY_ID,
4911 0,
4912 0, pbn_exar_XR17V354 },
4913 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4914 PCI_ANY_ID, PCI_ANY_ID,
4915 0,
4916 0, pbn_exar_XR17V358 },
4917
4918 /*
4919 * These entries match devices with class COMMUNICATION_SERIAL,
4920 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4921 */
4922 { PCI_ANY_ID, PCI_ANY_ID,
4923 PCI_ANY_ID, PCI_ANY_ID,
4924 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4925 0xffff00, pbn_default },
4926 { PCI_ANY_ID, PCI_ANY_ID,
4927 PCI_ANY_ID, PCI_ANY_ID,
4928 PCI_CLASS_COMMUNICATION_MODEM << 8,
4929 0xffff00, pbn_default },
4930 { PCI_ANY_ID, PCI_ANY_ID,
4931 PCI_ANY_ID, PCI_ANY_ID,
4932 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4933 0xffff00, pbn_default },
4934 { 0, }
4935 };
4936
4937 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4938 pci_channel_state_t state)
4939 {
4940 struct serial_private *priv = pci_get_drvdata(dev);
4941
4942 if (state == pci_channel_io_perm_failure)
4943 return PCI_ERS_RESULT_DISCONNECT;
4944
4945 if (priv)
4946 pciserial_suspend_ports(priv);
4947
4948 pci_disable_device(dev);
4949
4950 return PCI_ERS_RESULT_NEED_RESET;
4951 }
4952
4953 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4954 {
4955 int rc;
4956
4957 rc = pci_enable_device(dev);
4958
4959 if (rc)
4960 return PCI_ERS_RESULT_DISCONNECT;
4961
4962 pci_restore_state(dev);
4963 pci_save_state(dev);
4964
4965 return PCI_ERS_RESULT_RECOVERED;
4966 }
4967
4968 static void serial8250_io_resume(struct pci_dev *dev)
4969 {
4970 struct serial_private *priv = pci_get_drvdata(dev);
4971
4972 if (priv)
4973 pciserial_resume_ports(priv);
4974 }
4975
4976 static const struct pci_error_handlers serial8250_err_handler = {
4977 .error_detected = serial8250_io_error_detected,
4978 .slot_reset = serial8250_io_slot_reset,
4979 .resume = serial8250_io_resume,
4980 };
4981
4982 static struct pci_driver serial_pci_driver = {
4983 .name = "serial",
4984 .probe = pciserial_init_one,
4985 .remove = pciserial_remove_one,
4986 #ifdef CONFIG_PM
4987 .suspend = pciserial_suspend_one,
4988 .resume = pciserial_resume_one,
4989 #endif
4990 .id_table = serial_pci_tbl,
4991 .err_handler = &serial8250_err_handler,
4992 };
4993
4994 module_pci_driver(serial_pci_driver);
4995
4996 MODULE_LICENSE("GPL");
4997 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4998 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
kernel source for telekom puls (alcatel/mediatek)