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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include "8250.h"
29
30 #undef SERIAL_DEBUG_PCI
31
32 /*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38 struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
43 int (*probe)(struct pci_dev *dev);
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_8250_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_8250_port *, int);
63
64 static void moan_device(const char *str, struct pci_dev *dev)
65 {
66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74 }
75
76 static int
77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
78 int bar, int offset, int regshift)
79 {
80 struct pci_dev *dev = priv->dev;
81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 base = pci_resource_start(dev, bar);
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
101 } else {
102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
107 }
108 return 0;
109 }
110
111 /*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114 static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board,
116 struct uart_8250_port *port, int idx)
117 {
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135 }
136
137 /*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141 static int
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_8250_port *port, int idx)
144 {
145 unsigned int bar, offset = board->first_offset;
146
147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
155 return setup_port(priv, port, bar, offset, board->reg_shift);
156 }
157
158 /*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
165 static int pci_hp_diva_init(struct pci_dev *dev)
166 {
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
184 rc = 1;
185 break;
186 }
187
188 return rc;
189 }
190
191 /*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195 static int
196 pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
198 struct uart_8250_port *port, int idx)
199 {
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
203 switch (priv->dev->subsystem_device) {
204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
220 return setup_port(priv, port, bar, offset, board->reg_shift);
221 }
222
223 /*
224 * Added for EKF Intel i960 serial boards
225 */
226 static int pci_inteli960ni_init(struct pci_dev *dev)
227 {
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240 }
241
242 /*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
248 static int pci_plx9050_init(struct pci_dev *dev)
249 {
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
261 irq_config = 0x43;
262
263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
274 /*
275 * enable/disable interrupts
276 */
277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289 }
290
291 static void pci_plx9050_exit(struct pci_dev *dev)
292 {
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311 }
312
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
315
316 static void pci_ni8420_exit(struct pci_dev *dev)
317 {
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337 }
338
339
340 /* MITE registers */
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
345
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
348 static void pci_ni8430_exit(struct pci_dev *dev)
349 {
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368 }
369
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371 static int
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_8250_port *port, int idx)
374 {
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
388 return setup_port(priv, port, bar, offset, board->reg_shift);
389 }
390
391 /*
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
396 */
397
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
400
401 static int sbs_init(struct pci_dev *dev)
402 {
403 u8 __iomem *p;
404
405 p = pci_ioremap_bar(dev, 0);
406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410 writeb(0x10, p + OCT_REG_CR_OFF);
411 udelay(50);
412 writeb(0x0, p + OCT_REG_CR_OFF);
413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419 }
420
421 /*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
425 static void sbs_exit(struct pci_dev *dev)
426 {
427 u8 __iomem *p;
428
429 p = pci_ioremap_bar(dev, 0);
430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
432 writeb(0, p + OCT_REG_CR_OFF);
433 iounmap(p);
434 }
435
436 /*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
439 * (except cards equipped with 4 UARTs) and initial clocking settings
440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
448 *
449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466 static int pci_siig10x_init(struct pci_dev *dev)
467 {
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491 }
492
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496 static int pci_siig20x_init(struct pci_dev *dev)
497 {
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511 }
512
513 static int pci_siig_init(struct pci_dev *dev)
514 {
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524 }
525
526 static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board,
528 struct uart_8250_port *port, int idx)
529 {
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538 }
539
540 /*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
545 static const unsigned short timedia_single_port[] = {
546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 };
548
549 static const unsigned short timedia_dual_port[] = {
550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555 };
556
557 static const unsigned short timedia_quad_port[] = {
558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562 };
563
564 static const unsigned short timedia_eight_port[] = {
565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 };
568
569 static const struct timedia_struct {
570 int num;
571 const unsigned short *ids;
572 } timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
576 { 8, timedia_eight_port }
577 };
578
579 /*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585 static int pci_timedia_probe(struct pci_dev *dev)
586 {
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599 }
600
601 static int pci_timedia_init(struct pci_dev *dev)
602 {
603 const unsigned short *ids;
604 int i, j;
605
606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613 }
614
615 /*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619 static int
620 pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
622 struct uart_8250_port *port, int idx)
623 {
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
639 /* FALLTHROUGH */
640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649
650 /*
651 * Some Titan cards are also a little weird
652 */
653 static int
654 titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board,
656 struct uart_8250_port *port, int idx)
657 {
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
672 return setup_port(priv, port, bar, offset, board->reg_shift);
673 }
674
675 static int pci_xircom_init(struct pci_dev *dev)
676 {
677 msleep(100);
678 return 0;
679 }
680
681 static int pci_ni8420_init(struct pci_dev *dev)
682 {
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704 }
705
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713 static int pci_ni8430_init(struct pci_dev *dev)
714 {
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748 }
749
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754 static int
755 pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
757 struct uart_8250_port *port, int idx)
758 {
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
773 /* enable the transceiver */
774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780 }
781
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
784 struct uart_8250_port *port, int idx)
785 {
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798 }
799
800 /* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837 }
838
839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 return 0;
847
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
866 if (num_serial == 0)
867 return -ENODEV;
868
869 return num_serial;
870 }
871
872 /*
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899
900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992 }
993
994 static void pci_ite887x_exit(struct pci_dev *dev)
995 {
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_8250_port *port, int idx)
1038 {
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 /* Quatech devices have their own extra interface features */
1044
1045 struct quatech_feature {
1046 u16 devid;
1047 bool amcc;
1048 };
1049
1050 #define QPCR_TEST_FOR1 0x3F
1051 #define QPCR_TEST_GET1 0x00
1052 #define QPCR_TEST_FOR2 0x40
1053 #define QPCR_TEST_GET2 0x40
1054 #define QPCR_TEST_FOR3 0x80
1055 #define QPCR_TEST_GET3 0x40
1056 #define QPCR_TEST_FOR4 0xC0
1057 #define QPCR_TEST_GET4 0x80
1058
1059 #define QOPR_CLOCK_X1 0x0000
1060 #define QOPR_CLOCK_X2 0x0001
1061 #define QOPR_CLOCK_X4 0x0002
1062 #define QOPR_CLOCK_X8 0x0003
1063 #define QOPR_CLOCK_RATE_MASK 0x0003
1064
1065
1066 static struct quatech_feature quatech_cards[] = {
1067 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1069 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1073 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1074 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1076 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1078 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1086 { 0, }
1087 };
1088
1089 static int pci_quatech_amcc(u16 devid)
1090 {
1091 struct quatech_feature *qf = &quatech_cards[0];
1092 while (qf->devid) {
1093 if (qf->devid == devid)
1094 return qf->amcc;
1095 qf++;
1096 }
1097 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1098 return 0;
1099 };
1100
1101 static int pci_quatech_rqopr(struct uart_8250_port *port)
1102 {
1103 unsigned long base = port->port.iobase;
1104 u8 LCR, val;
1105
1106 LCR = inb(base + UART_LCR);
1107 outb(0xBF, base + UART_LCR);
1108 val = inb(base + UART_SCR);
1109 outb(LCR, base + UART_LCR);
1110 return val;
1111 }
1112
1113 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1114 {
1115 unsigned long base = port->port.iobase;
1116 u8 LCR, val;
1117
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(qopr, base + UART_SCR);
1122 outb(LCR, base + UART_LCR);
1123 }
1124
1125 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1126 {
1127 unsigned long base = port->port.iobase;
1128 u8 LCR, val, qmcr;
1129
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 val = inb(base + UART_SCR);
1133 outb(val | 0x10, base + UART_SCR);
1134 qmcr = inb(base + UART_MCR);
1135 outb(val, base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137
1138 return qmcr;
1139 }
1140
1141 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1142 {
1143 unsigned long base = port->port.iobase;
1144 u8 LCR, val;
1145
1146 LCR = inb(base + UART_LCR);
1147 outb(0xBF, base + UART_LCR);
1148 val = inb(base + UART_SCR);
1149 outb(val | 0x10, base + UART_SCR);
1150 outb(qmcr, base + UART_MCR);
1151 outb(val, base + UART_SCR);
1152 outb(LCR, base + UART_LCR);
1153 }
1154
1155 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1156 {
1157 unsigned long base = port->port.iobase;
1158 u8 LCR, val;
1159
1160 LCR = inb(base + UART_LCR);
1161 outb(0xBF, base + UART_LCR);
1162 val = inb(base + UART_SCR);
1163 if (val & 0x20) {
1164 outb(0x80, UART_LCR);
1165 if (!(inb(UART_SCR) & 0x20)) {
1166 outb(LCR, base + UART_LCR);
1167 return 1;
1168 }
1169 }
1170 return 0;
1171 }
1172
1173 static int pci_quatech_test(struct uart_8250_port *port)
1174 {
1175 u8 reg;
1176 u8 qopr = pci_quatech_rqopr(port);
1177 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1178 reg = pci_quatech_rqopr(port) & 0xC0;
1179 if (reg != QPCR_TEST_GET1)
1180 return -EINVAL;
1181 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1182 reg = pci_quatech_rqopr(port) & 0xC0;
1183 if (reg != QPCR_TEST_GET2)
1184 return -EINVAL;
1185 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1186 reg = pci_quatech_rqopr(port) & 0xC0;
1187 if (reg != QPCR_TEST_GET3)
1188 return -EINVAL;
1189 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1190 reg = pci_quatech_rqopr(port) & 0xC0;
1191 if (reg != QPCR_TEST_GET4)
1192 return -EINVAL;
1193
1194 pci_quatech_wqopr(port, qopr);
1195 return 0;
1196 }
1197
1198 static int pci_quatech_clock(struct uart_8250_port *port)
1199 {
1200 u8 qopr, reg, set;
1201 unsigned long clock;
1202
1203 if (pci_quatech_test(port) < 0)
1204 return 1843200;
1205
1206 qopr = pci_quatech_rqopr(port);
1207
1208 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1209 reg = pci_quatech_rqopr(port);
1210 if (reg & QOPR_CLOCK_X8) {
1211 clock = 1843200;
1212 goto out;
1213 }
1214 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1215 reg = pci_quatech_rqopr(port);
1216 if (!(reg & QOPR_CLOCK_X8)) {
1217 clock = 1843200;
1218 goto out;
1219 }
1220 reg &= QOPR_CLOCK_X8;
1221 if (reg == QOPR_CLOCK_X2) {
1222 clock = 3685400;
1223 set = QOPR_CLOCK_X2;
1224 } else if (reg == QOPR_CLOCK_X4) {
1225 clock = 7372800;
1226 set = QOPR_CLOCK_X4;
1227 } else if (reg == QOPR_CLOCK_X8) {
1228 clock = 14745600;
1229 set = QOPR_CLOCK_X8;
1230 } else {
1231 clock = 1843200;
1232 set = QOPR_CLOCK_X1;
1233 }
1234 qopr &= ~QOPR_CLOCK_RATE_MASK;
1235 qopr |= set;
1236
1237 out:
1238 pci_quatech_wqopr(port, qopr);
1239 return clock;
1240 }
1241
1242 static int pci_quatech_rs422(struct uart_8250_port *port)
1243 {
1244 u8 qmcr;
1245 int rs422 = 0;
1246
1247 if (!pci_quatech_has_qmcr(port))
1248 return 0;
1249 qmcr = pci_quatech_rqmcr(port);
1250 pci_quatech_wqmcr(port, 0xFF);
1251 if (pci_quatech_rqmcr(port))
1252 rs422 = 1;
1253 pci_quatech_wqmcr(port, qmcr);
1254 return rs422;
1255 }
1256
1257 static int pci_quatech_init(struct pci_dev *dev)
1258 {
1259 if (pci_quatech_amcc(dev->device)) {
1260 unsigned long base = pci_resource_start(dev, 0);
1261 if (base) {
1262 u32 tmp;
1263 outl(inl(base + 0x38), base + 0x38);
1264 tmp = inl(base + 0x3c);
1265 outl(tmp | 0x01000000, base + 0x3c);
1266 outl(tmp, base + 0x3c);
1267 }
1268 }
1269 return 0;
1270 }
1271
1272 static int pci_quatech_setup(struct serial_private *priv,
1273 const struct pciserial_board *board,
1274 struct uart_8250_port *port, int idx)
1275 {
1276 /* Needed by pci_quatech calls below */
1277 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1278 /* Set up the clocking */
1279 port->port.uartclk = pci_quatech_clock(port);
1280 /* For now just warn about RS422 */
1281 if (pci_quatech_rs422(port))
1282 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1283 return pci_default_setup(priv, board, port, idx);
1284 }
1285
1286 static void pci_quatech_exit(struct pci_dev *dev)
1287 {
1288 }
1289
1290 static int pci_default_setup(struct serial_private *priv,
1291 const struct pciserial_board *board,
1292 struct uart_8250_port *port, int idx)
1293 {
1294 unsigned int bar, offset = board->first_offset, maxnr;
1295
1296 bar = FL_GET_BASE(board->flags);
1297 if (board->flags & FL_BASE_BARS)
1298 bar += idx;
1299 else
1300 offset += idx * board->uart_offset;
1301
1302 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1303 (board->reg_shift + 3);
1304
1305 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1306 return 1;
1307
1308 return setup_port(priv, port, bar, offset, board->reg_shift);
1309 }
1310
1311 static int
1312 ce4100_serial_setup(struct serial_private *priv,
1313 const struct pciserial_board *board,
1314 struct uart_8250_port *port, int idx)
1315 {
1316 int ret;
1317
1318 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1319 port->port.iotype = UPIO_MEM32;
1320 port->port.type = PORT_XSCALE;
1321 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1322 port->port.regshift = 2;
1323
1324 return ret;
1325 }
1326
1327 static int
1328 pci_omegapci_setup(struct serial_private *priv,
1329 const struct pciserial_board *board,
1330 struct uart_8250_port *port, int idx)
1331 {
1332 return setup_port(priv, port, 2, idx * 8, 0);
1333 }
1334
1335 static int
1336 pci_brcm_trumanage_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1339 {
1340 int ret = pci_default_setup(priv, board, port, idx);
1341
1342 port->port.type = PORT_BRCM_TRUMANAGE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 return ret;
1345 }
1346
1347 static int skip_tx_en_setup(struct serial_private *priv,
1348 const struct pciserial_board *board,
1349 struct uart_8250_port *port, int idx)
1350 {
1351 port->port.flags |= UPF_NO_TXEN_TEST;
1352 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1353 "[%04x:%04x] subsystem [%04x:%04x]\n",
1354 priv->dev->vendor,
1355 priv->dev->device,
1356 priv->dev->subsystem_vendor,
1357 priv->dev->subsystem_device);
1358
1359 return pci_default_setup(priv, board, port, idx);
1360 }
1361
1362 static void kt_handle_break(struct uart_port *p)
1363 {
1364 struct uart_8250_port *up =
1365 container_of(p, struct uart_8250_port, port);
1366 /*
1367 * On receipt of a BI, serial device in Intel ME (Intel
1368 * management engine) needs to have its fifos cleared for sane
1369 * SOL (Serial Over Lan) output.
1370 */
1371 serial8250_clear_and_reinit_fifos(up);
1372 }
1373
1374 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1375 {
1376 struct uart_8250_port *up =
1377 container_of(p, struct uart_8250_port, port);
1378 unsigned int val;
1379
1380 /*
1381 * When the Intel ME (management engine) gets reset its serial
1382 * port registers could return 0 momentarily. Functions like
1383 * serial8250_console_write, read and save the IER, perform
1384 * some operation and then restore it. In order to avoid
1385 * setting IER register inadvertently to 0, if the value read
1386 * is 0, double check with ier value in uart_8250_port and use
1387 * that instead. up->ier should be the same value as what is
1388 * currently configured.
1389 */
1390 val = inb(p->iobase + offset);
1391 if (offset == UART_IER) {
1392 if (val == 0)
1393 val = up->ier;
1394 }
1395 return val;
1396 }
1397
1398 static int kt_serial_setup(struct serial_private *priv,
1399 const struct pciserial_board *board,
1400 struct uart_8250_port *port, int idx)
1401 {
1402 port->port.flags |= UPF_BUG_THRE;
1403 port->port.serial_in = kt_serial_in;
1404 port->port.handle_break = kt_handle_break;
1405 return skip_tx_en_setup(priv, board, port, idx);
1406 }
1407
1408 static int pci_eg20t_init(struct pci_dev *dev)
1409 {
1410 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1411 return -ENODEV;
1412 #else
1413 return 0;
1414 #endif
1415 }
1416
1417 static int
1418 pci_xr17c154_setup(struct serial_private *priv,
1419 const struct pciserial_board *board,
1420 struct uart_8250_port *port, int idx)
1421 {
1422 port->port.flags |= UPF_EXAR_EFR;
1423 return pci_default_setup(priv, board, port, idx);
1424 }
1425
1426 static int
1427 pci_xr17v35x_setup(struct serial_private *priv,
1428 const struct pciserial_board *board,
1429 struct uart_8250_port *port, int idx)
1430 {
1431 u8 __iomem *p;
1432
1433 p = pci_ioremap_bar(priv->dev, 0);
1434 if (p == NULL)
1435 return -ENOMEM;
1436
1437 port->port.flags |= UPF_EXAR_EFR;
1438
1439 /*
1440 * Setup Multipurpose Input/Output pins.
1441 */
1442 if (idx == 0) {
1443 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1444 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1445 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1446 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1447 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1448 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1449 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1450 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1451 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1452 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1453 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1454 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1455 }
1456 writeb(0x00, p + UART_EXAR_8XMODE);
1457 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1458 writeb(128, p + UART_EXAR_TXTRG);
1459 writeb(128, p + UART_EXAR_RXTRG);
1460 iounmap(p);
1461
1462 return pci_default_setup(priv, board, port, idx);
1463 }
1464
1465 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1466 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1467 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1468 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1469
1470 static int
1471 pci_fastcom335_setup(struct serial_private *priv,
1472 const struct pciserial_board *board,
1473 struct uart_8250_port *port, int idx)
1474 {
1475 u8 __iomem *p;
1476
1477 p = pci_ioremap_bar(priv->dev, 0);
1478 if (p == NULL)
1479 return -ENOMEM;
1480
1481 port->port.flags |= UPF_EXAR_EFR;
1482
1483 /*
1484 * Setup Multipurpose Input/Output pins.
1485 */
1486 if (idx == 0) {
1487 switch (priv->dev->device) {
1488 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1489 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1490 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1491 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1492 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1493 break;
1494 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1495 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1496 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1497 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1498 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1499 break;
1500 }
1501 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1502 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1503 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1504 }
1505 writeb(0x00, p + UART_EXAR_8XMODE);
1506 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1507 writeb(32, p + UART_EXAR_TXTRG);
1508 writeb(32, p + UART_EXAR_RXTRG);
1509 iounmap(p);
1510
1511 return pci_default_setup(priv, board, port, idx);
1512 }
1513
1514 static int
1515 pci_wch_ch353_setup(struct serial_private *priv,
1516 const struct pciserial_board *board,
1517 struct uart_8250_port *port, int idx)
1518 {
1519 port->port.flags |= UPF_FIXED_TYPE;
1520 port->port.type = PORT_16550A;
1521 return pci_default_setup(priv, board, port, idx);
1522 }
1523
1524 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1525 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1526 #define PCI_DEVICE_ID_OCTPRO 0x0001
1527 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1528 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1529 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1530 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1531 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1532 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1533 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1534 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1535 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1536 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1537 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1538 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1539 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1540 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1541 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1542 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1543 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1544 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1545 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1546 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1547 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1548 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1549 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1550 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1551 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1552 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1553 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1554 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1555 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1556 #define PCI_VENDOR_ID_WCH 0x4348
1557 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1558 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1559 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1560 #define PCI_VENDOR_ID_AGESTAR 0x5372
1561 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1562 #define PCI_VENDOR_ID_ASIX 0x9710
1563 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1564 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1565 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1566 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1567
1568 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1569 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1570
1571
1572 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1573 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1574
1575 /*
1576 * Master list of serial port init/setup/exit quirks.
1577 * This does not describe the general nature of the port.
1578 * (ie, baud base, number and location of ports, etc)
1579 *
1580 * This list is ordered alphabetically by vendor then device.
1581 * Specific entries must come before more generic entries.
1582 */
1583 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1584 /*
1585 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1586 */
1587 {
1588 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1589 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1590 .subvendor = PCI_ANY_ID,
1591 .subdevice = PCI_ANY_ID,
1592 .setup = addidata_apci7800_setup,
1593 },
1594 /*
1595 * AFAVLAB cards - these may be called via parport_serial
1596 * It is not clear whether this applies to all products.
1597 */
1598 {
1599 .vendor = PCI_VENDOR_ID_AFAVLAB,
1600 .device = PCI_ANY_ID,
1601 .subvendor = PCI_ANY_ID,
1602 .subdevice = PCI_ANY_ID,
1603 .setup = afavlab_setup,
1604 },
1605 /*
1606 * HP Diva
1607 */
1608 {
1609 .vendor = PCI_VENDOR_ID_HP,
1610 .device = PCI_DEVICE_ID_HP_DIVA,
1611 .subvendor = PCI_ANY_ID,
1612 .subdevice = PCI_ANY_ID,
1613 .init = pci_hp_diva_init,
1614 .setup = pci_hp_diva_setup,
1615 },
1616 /*
1617 * Intel
1618 */
1619 {
1620 .vendor = PCI_VENDOR_ID_INTEL,
1621 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1622 .subvendor = 0xe4bf,
1623 .subdevice = PCI_ANY_ID,
1624 .init = pci_inteli960ni_init,
1625 .setup = pci_default_setup,
1626 },
1627 {
1628 .vendor = PCI_VENDOR_ID_INTEL,
1629 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1630 .subvendor = PCI_ANY_ID,
1631 .subdevice = PCI_ANY_ID,
1632 .setup = skip_tx_en_setup,
1633 },
1634 {
1635 .vendor = PCI_VENDOR_ID_INTEL,
1636 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1637 .subvendor = PCI_ANY_ID,
1638 .subdevice = PCI_ANY_ID,
1639 .setup = skip_tx_en_setup,
1640 },
1641 {
1642 .vendor = PCI_VENDOR_ID_INTEL,
1643 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1644 .subvendor = PCI_ANY_ID,
1645 .subdevice = PCI_ANY_ID,
1646 .setup = skip_tx_en_setup,
1647 },
1648 {
1649 .vendor = PCI_VENDOR_ID_INTEL,
1650 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1651 .subvendor = PCI_ANY_ID,
1652 .subdevice = PCI_ANY_ID,
1653 .setup = ce4100_serial_setup,
1654 },
1655 {
1656 .vendor = PCI_VENDOR_ID_INTEL,
1657 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1658 .subvendor = PCI_ANY_ID,
1659 .subdevice = PCI_ANY_ID,
1660 .setup = kt_serial_setup,
1661 },
1662 /*
1663 * ITE
1664 */
1665 {
1666 .vendor = PCI_VENDOR_ID_ITE,
1667 .device = PCI_DEVICE_ID_ITE_8872,
1668 .subvendor = PCI_ANY_ID,
1669 .subdevice = PCI_ANY_ID,
1670 .init = pci_ite887x_init,
1671 .setup = pci_default_setup,
1672 .exit = pci_ite887x_exit,
1673 },
1674 /*
1675 * National Instruments
1676 */
1677 {
1678 .vendor = PCI_VENDOR_ID_NI,
1679 .device = PCI_DEVICE_ID_NI_PCI23216,
1680 .subvendor = PCI_ANY_ID,
1681 .subdevice = PCI_ANY_ID,
1682 .init = pci_ni8420_init,
1683 .setup = pci_default_setup,
1684 .exit = pci_ni8420_exit,
1685 },
1686 {
1687 .vendor = PCI_VENDOR_ID_NI,
1688 .device = PCI_DEVICE_ID_NI_PCI2328,
1689 .subvendor = PCI_ANY_ID,
1690 .subdevice = PCI_ANY_ID,
1691 .init = pci_ni8420_init,
1692 .setup = pci_default_setup,
1693 .exit = pci_ni8420_exit,
1694 },
1695 {
1696 .vendor = PCI_VENDOR_ID_NI,
1697 .device = PCI_DEVICE_ID_NI_PCI2324,
1698 .subvendor = PCI_ANY_ID,
1699 .subdevice = PCI_ANY_ID,
1700 .init = pci_ni8420_init,
1701 .setup = pci_default_setup,
1702 .exit = pci_ni8420_exit,
1703 },
1704 {
1705 .vendor = PCI_VENDOR_ID_NI,
1706 .device = PCI_DEVICE_ID_NI_PCI2322,
1707 .subvendor = PCI_ANY_ID,
1708 .subdevice = PCI_ANY_ID,
1709 .init = pci_ni8420_init,
1710 .setup = pci_default_setup,
1711 .exit = pci_ni8420_exit,
1712 },
1713 {
1714 .vendor = PCI_VENDOR_ID_NI,
1715 .device = PCI_DEVICE_ID_NI_PCI2324I,
1716 .subvendor = PCI_ANY_ID,
1717 .subdevice = PCI_ANY_ID,
1718 .init = pci_ni8420_init,
1719 .setup = pci_default_setup,
1720 .exit = pci_ni8420_exit,
1721 },
1722 {
1723 .vendor = PCI_VENDOR_ID_NI,
1724 .device = PCI_DEVICE_ID_NI_PCI2322I,
1725 .subvendor = PCI_ANY_ID,
1726 .subdevice = PCI_ANY_ID,
1727 .init = pci_ni8420_init,
1728 .setup = pci_default_setup,
1729 .exit = pci_ni8420_exit,
1730 },
1731 {
1732 .vendor = PCI_VENDOR_ID_NI,
1733 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1734 .subvendor = PCI_ANY_ID,
1735 .subdevice = PCI_ANY_ID,
1736 .init = pci_ni8420_init,
1737 .setup = pci_default_setup,
1738 .exit = pci_ni8420_exit,
1739 },
1740 {
1741 .vendor = PCI_VENDOR_ID_NI,
1742 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1743 .subvendor = PCI_ANY_ID,
1744 .subdevice = PCI_ANY_ID,
1745 .init = pci_ni8420_init,
1746 .setup = pci_default_setup,
1747 .exit = pci_ni8420_exit,
1748 },
1749 {
1750 .vendor = PCI_VENDOR_ID_NI,
1751 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1752 .subvendor = PCI_ANY_ID,
1753 .subdevice = PCI_ANY_ID,
1754 .init = pci_ni8420_init,
1755 .setup = pci_default_setup,
1756 .exit = pci_ni8420_exit,
1757 },
1758 {
1759 .vendor = PCI_VENDOR_ID_NI,
1760 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1761 .subvendor = PCI_ANY_ID,
1762 .subdevice = PCI_ANY_ID,
1763 .init = pci_ni8420_init,
1764 .setup = pci_default_setup,
1765 .exit = pci_ni8420_exit,
1766 },
1767 {
1768 .vendor = PCI_VENDOR_ID_NI,
1769 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1770 .subvendor = PCI_ANY_ID,
1771 .subdevice = PCI_ANY_ID,
1772 .init = pci_ni8420_init,
1773 .setup = pci_default_setup,
1774 .exit = pci_ni8420_exit,
1775 },
1776 {
1777 .vendor = PCI_VENDOR_ID_NI,
1778 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1779 .subvendor = PCI_ANY_ID,
1780 .subdevice = PCI_ANY_ID,
1781 .init = pci_ni8420_init,
1782 .setup = pci_default_setup,
1783 .exit = pci_ni8420_exit,
1784 },
1785 {
1786 .vendor = PCI_VENDOR_ID_NI,
1787 .device = PCI_ANY_ID,
1788 .subvendor = PCI_ANY_ID,
1789 .subdevice = PCI_ANY_ID,
1790 .init = pci_ni8430_init,
1791 .setup = pci_ni8430_setup,
1792 .exit = pci_ni8430_exit,
1793 },
1794 /* Quatech */
1795 {
1796 .vendor = PCI_VENDOR_ID_QUATECH,
1797 .device = PCI_ANY_ID,
1798 .subvendor = PCI_ANY_ID,
1799 .subdevice = PCI_ANY_ID,
1800 .init = pci_quatech_init,
1801 .setup = pci_quatech_setup,
1802 .exit = pci_quatech_exit,
1803 },
1804 /*
1805 * Panacom
1806 */
1807 {
1808 .vendor = PCI_VENDOR_ID_PANACOM,
1809 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1810 .subvendor = PCI_ANY_ID,
1811 .subdevice = PCI_ANY_ID,
1812 .init = pci_plx9050_init,
1813 .setup = pci_default_setup,
1814 .exit = pci_plx9050_exit,
1815 },
1816 {
1817 .vendor = PCI_VENDOR_ID_PANACOM,
1818 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1819 .subvendor = PCI_ANY_ID,
1820 .subdevice = PCI_ANY_ID,
1821 .init = pci_plx9050_init,
1822 .setup = pci_default_setup,
1823 .exit = pci_plx9050_exit,
1824 },
1825 /*
1826 * PLX
1827 */
1828 {
1829 .vendor = PCI_VENDOR_ID_PLX,
1830 .device = PCI_DEVICE_ID_PLX_9030,
1831 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1832 .subdevice = PCI_ANY_ID,
1833 .setup = pci_default_setup,
1834 },
1835 {
1836 .vendor = PCI_VENDOR_ID_PLX,
1837 .device = PCI_DEVICE_ID_PLX_9050,
1838 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1839 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1840 .init = pci_plx9050_init,
1841 .setup = pci_default_setup,
1842 .exit = pci_plx9050_exit,
1843 },
1844 {
1845 .vendor = PCI_VENDOR_ID_PLX,
1846 .device = PCI_DEVICE_ID_PLX_9050,
1847 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1848 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1849 .init = pci_plx9050_init,
1850 .setup = pci_default_setup,
1851 .exit = pci_plx9050_exit,
1852 },
1853 {
1854 .vendor = PCI_VENDOR_ID_PLX,
1855 .device = PCI_DEVICE_ID_PLX_9050,
1856 .subvendor = PCI_VENDOR_ID_PLX,
1857 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1858 .init = pci_plx9050_init,
1859 .setup = pci_default_setup,
1860 .exit = pci_plx9050_exit,
1861 },
1862 {
1863 .vendor = PCI_VENDOR_ID_PLX,
1864 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1865 .subvendor = PCI_VENDOR_ID_PLX,
1866 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1867 .init = pci_plx9050_init,
1868 .setup = pci_default_setup,
1869 .exit = pci_plx9050_exit,
1870 },
1871 /*
1872 * SBS Technologies, Inc., PMC-OCTALPRO 232
1873 */
1874 {
1875 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1876 .device = PCI_DEVICE_ID_OCTPRO,
1877 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1878 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1879 .init = sbs_init,
1880 .setup = sbs_setup,
1881 .exit = sbs_exit,
1882 },
1883 /*
1884 * SBS Technologies, Inc., PMC-OCTALPRO 422
1885 */
1886 {
1887 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1888 .device = PCI_DEVICE_ID_OCTPRO,
1889 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1890 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1891 .init = sbs_init,
1892 .setup = sbs_setup,
1893 .exit = sbs_exit,
1894 },
1895 /*
1896 * SBS Technologies, Inc., P-Octal 232
1897 */
1898 {
1899 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1900 .device = PCI_DEVICE_ID_OCTPRO,
1901 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1902 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1903 .init = sbs_init,
1904 .setup = sbs_setup,
1905 .exit = sbs_exit,
1906 },
1907 /*
1908 * SBS Technologies, Inc., P-Octal 422
1909 */
1910 {
1911 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1912 .device = PCI_DEVICE_ID_OCTPRO,
1913 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1914 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1915 .init = sbs_init,
1916 .setup = sbs_setup,
1917 .exit = sbs_exit,
1918 },
1919 /*
1920 * SIIG cards - these may be called via parport_serial
1921 */
1922 {
1923 .vendor = PCI_VENDOR_ID_SIIG,
1924 .device = PCI_ANY_ID,
1925 .subvendor = PCI_ANY_ID,
1926 .subdevice = PCI_ANY_ID,
1927 .init = pci_siig_init,
1928 .setup = pci_siig_setup,
1929 },
1930 /*
1931 * Titan cards
1932 */
1933 {
1934 .vendor = PCI_VENDOR_ID_TITAN,
1935 .device = PCI_DEVICE_ID_TITAN_400L,
1936 .subvendor = PCI_ANY_ID,
1937 .subdevice = PCI_ANY_ID,
1938 .setup = titan_400l_800l_setup,
1939 },
1940 {
1941 .vendor = PCI_VENDOR_ID_TITAN,
1942 .device = PCI_DEVICE_ID_TITAN_800L,
1943 .subvendor = PCI_ANY_ID,
1944 .subdevice = PCI_ANY_ID,
1945 .setup = titan_400l_800l_setup,
1946 },
1947 /*
1948 * Timedia cards
1949 */
1950 {
1951 .vendor = PCI_VENDOR_ID_TIMEDIA,
1952 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1953 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1954 .subdevice = PCI_ANY_ID,
1955 .probe = pci_timedia_probe,
1956 .init = pci_timedia_init,
1957 .setup = pci_timedia_setup,
1958 },
1959 {
1960 .vendor = PCI_VENDOR_ID_TIMEDIA,
1961 .device = PCI_ANY_ID,
1962 .subvendor = PCI_ANY_ID,
1963 .subdevice = PCI_ANY_ID,
1964 .setup = pci_timedia_setup,
1965 },
1966 /*
1967 * SUNIX (Timedia) cards
1968 * Do not "probe" for these cards as there is at least one combination
1969 * card that should be handled by parport_pc that doesn't match the
1970 * rule in pci_timedia_probe.
1971 * It is part number is MIO5079A but its subdevice ID is 0x0102.
1972 * There are some boards with part number SER5037AL that report
1973 * subdevice ID 0x0002.
1974 */
1975 {
1976 .vendor = PCI_VENDOR_ID_SUNIX,
1977 .device = PCI_DEVICE_ID_SUNIX_1999,
1978 .subvendor = PCI_VENDOR_ID_SUNIX,
1979 .subdevice = PCI_ANY_ID,
1980 .init = pci_timedia_init,
1981 .setup = pci_timedia_setup,
1982 },
1983 /*
1984 * Exar cards
1985 */
1986 {
1987 .vendor = PCI_VENDOR_ID_EXAR,
1988 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1989 .subvendor = PCI_ANY_ID,
1990 .subdevice = PCI_ANY_ID,
1991 .setup = pci_xr17c154_setup,
1992 },
1993 {
1994 .vendor = PCI_VENDOR_ID_EXAR,
1995 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1996 .subvendor = PCI_ANY_ID,
1997 .subdevice = PCI_ANY_ID,
1998 .setup = pci_xr17c154_setup,
1999 },
2000 {
2001 .vendor = PCI_VENDOR_ID_EXAR,
2002 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .setup = pci_xr17c154_setup,
2006 },
2007 {
2008 .vendor = PCI_VENDOR_ID_EXAR,
2009 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .setup = pci_xr17v35x_setup,
2013 },
2014 {
2015 .vendor = PCI_VENDOR_ID_EXAR,
2016 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .setup = pci_xr17v35x_setup,
2020 },
2021 {
2022 .vendor = PCI_VENDOR_ID_EXAR,
2023 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2024 .subvendor = PCI_ANY_ID,
2025 .subdevice = PCI_ANY_ID,
2026 .setup = pci_xr17v35x_setup,
2027 },
2028 /*
2029 * Xircom cards
2030 */
2031 {
2032 .vendor = PCI_VENDOR_ID_XIRCOM,
2033 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2034 .subvendor = PCI_ANY_ID,
2035 .subdevice = PCI_ANY_ID,
2036 .init = pci_xircom_init,
2037 .setup = pci_default_setup,
2038 },
2039 /*
2040 * Netmos cards - these may be called via parport_serial
2041 */
2042 {
2043 .vendor = PCI_VENDOR_ID_NETMOS,
2044 .device = PCI_ANY_ID,
2045 .subvendor = PCI_ANY_ID,
2046 .subdevice = PCI_ANY_ID,
2047 .init = pci_netmos_init,
2048 .setup = pci_netmos_9900_setup,
2049 },
2050 /*
2051 * For Oxford Semiconductor Tornado based devices
2052 */
2053 {
2054 .vendor = PCI_VENDOR_ID_OXSEMI,
2055 .device = PCI_ANY_ID,
2056 .subvendor = PCI_ANY_ID,
2057 .subdevice = PCI_ANY_ID,
2058 .init = pci_oxsemi_tornado_init,
2059 .setup = pci_default_setup,
2060 },
2061 {
2062 .vendor = PCI_VENDOR_ID_MAINPINE,
2063 .device = PCI_ANY_ID,
2064 .subvendor = PCI_ANY_ID,
2065 .subdevice = PCI_ANY_ID,
2066 .init = pci_oxsemi_tornado_init,
2067 .setup = pci_default_setup,
2068 },
2069 {
2070 .vendor = PCI_VENDOR_ID_DIGI,
2071 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2072 .subvendor = PCI_SUBVENDOR_ID_IBM,
2073 .subdevice = PCI_ANY_ID,
2074 .init = pci_oxsemi_tornado_init,
2075 .setup = pci_default_setup,
2076 },
2077 {
2078 .vendor = PCI_VENDOR_ID_INTEL,
2079 .device = 0x8811,
2080 .subvendor = PCI_ANY_ID,
2081 .subdevice = PCI_ANY_ID,
2082 .init = pci_eg20t_init,
2083 .setup = pci_default_setup,
2084 },
2085 {
2086 .vendor = PCI_VENDOR_ID_INTEL,
2087 .device = 0x8812,
2088 .subvendor = PCI_ANY_ID,
2089 .subdevice = PCI_ANY_ID,
2090 .init = pci_eg20t_init,
2091 .setup = pci_default_setup,
2092 },
2093 {
2094 .vendor = PCI_VENDOR_ID_INTEL,
2095 .device = 0x8813,
2096 .subvendor = PCI_ANY_ID,
2097 .subdevice = PCI_ANY_ID,
2098 .init = pci_eg20t_init,
2099 .setup = pci_default_setup,
2100 },
2101 {
2102 .vendor = PCI_VENDOR_ID_INTEL,
2103 .device = 0x8814,
2104 .subvendor = PCI_ANY_ID,
2105 .subdevice = PCI_ANY_ID,
2106 .init = pci_eg20t_init,
2107 .setup = pci_default_setup,
2108 },
2109 {
2110 .vendor = 0x10DB,
2111 .device = 0x8027,
2112 .subvendor = PCI_ANY_ID,
2113 .subdevice = PCI_ANY_ID,
2114 .init = pci_eg20t_init,
2115 .setup = pci_default_setup,
2116 },
2117 {
2118 .vendor = 0x10DB,
2119 .device = 0x8028,
2120 .subvendor = PCI_ANY_ID,
2121 .subdevice = PCI_ANY_ID,
2122 .init = pci_eg20t_init,
2123 .setup = pci_default_setup,
2124 },
2125 {
2126 .vendor = 0x10DB,
2127 .device = 0x8029,
2128 .subvendor = PCI_ANY_ID,
2129 .subdevice = PCI_ANY_ID,
2130 .init = pci_eg20t_init,
2131 .setup = pci_default_setup,
2132 },
2133 {
2134 .vendor = 0x10DB,
2135 .device = 0x800C,
2136 .subvendor = PCI_ANY_ID,
2137 .subdevice = PCI_ANY_ID,
2138 .init = pci_eg20t_init,
2139 .setup = pci_default_setup,
2140 },
2141 {
2142 .vendor = 0x10DB,
2143 .device = 0x800D,
2144 .subvendor = PCI_ANY_ID,
2145 .subdevice = PCI_ANY_ID,
2146 .init = pci_eg20t_init,
2147 .setup = pci_default_setup,
2148 },
2149 /*
2150 * Cronyx Omega PCI (PLX-chip based)
2151 */
2152 {
2153 .vendor = PCI_VENDOR_ID_PLX,
2154 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2155 .subvendor = PCI_ANY_ID,
2156 .subdevice = PCI_ANY_ID,
2157 .setup = pci_omegapci_setup,
2158 },
2159 /* WCH CH353 2S1P card (16550 clone) */
2160 {
2161 .vendor = PCI_VENDOR_ID_WCH,
2162 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2163 .subvendor = PCI_ANY_ID,
2164 .subdevice = PCI_ANY_ID,
2165 .setup = pci_wch_ch353_setup,
2166 },
2167 /* WCH CH353 4S card (16550 clone) */
2168 {
2169 .vendor = PCI_VENDOR_ID_WCH,
2170 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .setup = pci_wch_ch353_setup,
2174 },
2175 /* WCH CH353 2S1PF card (16550 clone) */
2176 {
2177 .vendor = PCI_VENDOR_ID_WCH,
2178 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2179 .subvendor = PCI_ANY_ID,
2180 .subdevice = PCI_ANY_ID,
2181 .setup = pci_wch_ch353_setup,
2182 },
2183 /*
2184 * ASIX devices with FIFO bug
2185 */
2186 {
2187 .vendor = PCI_VENDOR_ID_ASIX,
2188 .device = PCI_ANY_ID,
2189 .subvendor = PCI_ANY_ID,
2190 .subdevice = PCI_ANY_ID,
2191 .setup = pci_asix_setup,
2192 },
2193 /*
2194 * Commtech, Inc. Fastcom adapters
2195 *
2196 */
2197 {
2198 .vendor = PCI_VENDOR_ID_COMMTECH,
2199 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2200 .subvendor = PCI_ANY_ID,
2201 .subdevice = PCI_ANY_ID,
2202 .setup = pci_fastcom335_setup,
2203 },
2204 {
2205 .vendor = PCI_VENDOR_ID_COMMTECH,
2206 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2207 .subvendor = PCI_ANY_ID,
2208 .subdevice = PCI_ANY_ID,
2209 .setup = pci_fastcom335_setup,
2210 },
2211 {
2212 .vendor = PCI_VENDOR_ID_COMMTECH,
2213 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2214 .subvendor = PCI_ANY_ID,
2215 .subdevice = PCI_ANY_ID,
2216 .setup = pci_fastcom335_setup,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_COMMTECH,
2220 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .setup = pci_fastcom335_setup,
2224 },
2225 {
2226 .vendor = PCI_VENDOR_ID_COMMTECH,
2227 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
2230 .setup = pci_xr17v35x_setup,
2231 },
2232 {
2233 .vendor = PCI_VENDOR_ID_COMMTECH,
2234 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2235 .subvendor = PCI_ANY_ID,
2236 .subdevice = PCI_ANY_ID,
2237 .setup = pci_xr17v35x_setup,
2238 },
2239 {
2240 .vendor = PCI_VENDOR_ID_COMMTECH,
2241 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2242 .subvendor = PCI_ANY_ID,
2243 .subdevice = PCI_ANY_ID,
2244 .setup = pci_xr17v35x_setup,
2245 },
2246 /*
2247 * Broadcom TruManage (NetXtreme)
2248 */
2249 {
2250 .vendor = PCI_VENDOR_ID_BROADCOM,
2251 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2252 .subvendor = PCI_ANY_ID,
2253 .subdevice = PCI_ANY_ID,
2254 .setup = pci_brcm_trumanage_setup,
2255 },
2256
2257 /*
2258 * Default "match everything" terminator entry
2259 */
2260 {
2261 .vendor = PCI_ANY_ID,
2262 .device = PCI_ANY_ID,
2263 .subvendor = PCI_ANY_ID,
2264 .subdevice = PCI_ANY_ID,
2265 .setup = pci_default_setup,
2266 }
2267 };
2268
2269 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2270 {
2271 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2272 }
2273
2274 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2275 {
2276 struct pci_serial_quirk *quirk;
2277
2278 for (quirk = pci_serial_quirks; ; quirk++)
2279 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2280 quirk_id_matches(quirk->device, dev->device) &&
2281 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2282 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2283 break;
2284 return quirk;
2285 }
2286
2287 static inline int get_pci_irq(struct pci_dev *dev,
2288 const struct pciserial_board *board)
2289 {
2290 if (board->flags & FL_NOIRQ)
2291 return 0;
2292 else
2293 return dev->irq;
2294 }
2295
2296 /*
2297 * This is the configuration table for all of the PCI serial boards
2298 * which we support. It is directly indexed by the pci_board_num_t enum
2299 * value, which is encoded in the pci_device_id PCI probe table's
2300 * driver_data member.
2301 *
2302 * The makeup of these names are:
2303 * pbn_bn{_bt}_n_baud{_offsetinhex}
2304 *
2305 * bn = PCI BAR number
2306 * bt = Index using PCI BARs
2307 * n = number of serial ports
2308 * baud = baud rate
2309 * offsetinhex = offset for each sequential port (in hex)
2310 *
2311 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2312 *
2313 * Please note: in theory if n = 1, _bt infix should make no difference.
2314 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2315 */
2316 enum pci_board_num_t {
2317 pbn_default = 0,
2318
2319 pbn_b0_1_115200,
2320 pbn_b0_2_115200,
2321 pbn_b0_4_115200,
2322 pbn_b0_5_115200,
2323 pbn_b0_8_115200,
2324
2325 pbn_b0_1_921600,
2326 pbn_b0_2_921600,
2327 pbn_b0_4_921600,
2328
2329 pbn_b0_2_1130000,
2330
2331 pbn_b0_4_1152000,
2332
2333 pbn_b0_2_1152000_200,
2334 pbn_b0_4_1152000_200,
2335 pbn_b0_8_1152000_200,
2336
2337 pbn_b0_2_1843200,
2338 pbn_b0_4_1843200,
2339
2340 pbn_b0_2_1843200_200,
2341 pbn_b0_4_1843200_200,
2342 pbn_b0_8_1843200_200,
2343
2344 pbn_b0_1_4000000,
2345
2346 pbn_b0_bt_1_115200,
2347 pbn_b0_bt_2_115200,
2348 pbn_b0_bt_4_115200,
2349 pbn_b0_bt_8_115200,
2350
2351 pbn_b0_bt_1_460800,
2352 pbn_b0_bt_2_460800,
2353 pbn_b0_bt_4_460800,
2354
2355 pbn_b0_bt_1_921600,
2356 pbn_b0_bt_2_921600,
2357 pbn_b0_bt_4_921600,
2358 pbn_b0_bt_8_921600,
2359
2360 pbn_b1_1_115200,
2361 pbn_b1_2_115200,
2362 pbn_b1_4_115200,
2363 pbn_b1_8_115200,
2364 pbn_b1_16_115200,
2365
2366 pbn_b1_1_921600,
2367 pbn_b1_2_921600,
2368 pbn_b1_4_921600,
2369 pbn_b1_8_921600,
2370
2371 pbn_b1_2_1250000,
2372
2373 pbn_b1_bt_1_115200,
2374 pbn_b1_bt_2_115200,
2375 pbn_b1_bt_4_115200,
2376
2377 pbn_b1_bt_2_921600,
2378
2379 pbn_b1_1_1382400,
2380 pbn_b1_2_1382400,
2381 pbn_b1_4_1382400,
2382 pbn_b1_8_1382400,
2383
2384 pbn_b2_1_115200,
2385 pbn_b2_2_115200,
2386 pbn_b2_4_115200,
2387 pbn_b2_8_115200,
2388
2389 pbn_b2_1_460800,
2390 pbn_b2_4_460800,
2391 pbn_b2_8_460800,
2392 pbn_b2_16_460800,
2393
2394 pbn_b2_1_921600,
2395 pbn_b2_4_921600,
2396 pbn_b2_8_921600,
2397
2398 pbn_b2_8_1152000,
2399
2400 pbn_b2_bt_1_115200,
2401 pbn_b2_bt_2_115200,
2402 pbn_b2_bt_4_115200,
2403
2404 pbn_b2_bt_2_921600,
2405 pbn_b2_bt_4_921600,
2406
2407 pbn_b3_2_115200,
2408 pbn_b3_4_115200,
2409 pbn_b3_8_115200,
2410
2411 pbn_b4_bt_2_921600,
2412 pbn_b4_bt_4_921600,
2413 pbn_b4_bt_8_921600,
2414
2415 /*
2416 * Board-specific versions.
2417 */
2418 pbn_panacom,
2419 pbn_panacom2,
2420 pbn_panacom4,
2421 pbn_plx_romulus,
2422 pbn_oxsemi,
2423 pbn_oxsemi_1_4000000,
2424 pbn_oxsemi_2_4000000,
2425 pbn_oxsemi_4_4000000,
2426 pbn_oxsemi_8_4000000,
2427 pbn_intel_i960,
2428 pbn_sgi_ioc3,
2429 pbn_computone_4,
2430 pbn_computone_6,
2431 pbn_computone_8,
2432 pbn_sbsxrsio,
2433 pbn_exar_XR17C152,
2434 pbn_exar_XR17C154,
2435 pbn_exar_XR17C158,
2436 pbn_exar_XR17V352,
2437 pbn_exar_XR17V354,
2438 pbn_exar_XR17V358,
2439 pbn_exar_ibm_saturn,
2440 pbn_pasemi_1682M,
2441 pbn_ni8430_2,
2442 pbn_ni8430_4,
2443 pbn_ni8430_8,
2444 pbn_ni8430_16,
2445 pbn_ADDIDATA_PCIe_1_3906250,
2446 pbn_ADDIDATA_PCIe_2_3906250,
2447 pbn_ADDIDATA_PCIe_4_3906250,
2448 pbn_ADDIDATA_PCIe_8_3906250,
2449 pbn_ce4100_1_115200,
2450 pbn_omegapci,
2451 pbn_NETMOS9900_2s_115200,
2452 pbn_brcm_trumanage,
2453 };
2454
2455 /*
2456 * uart_offset - the space between channels
2457 * reg_shift - describes how the UART registers are mapped
2458 * to PCI memory by the card.
2459 * For example IER register on SBS, Inc. PMC-OctPro is located at
2460 * offset 0x10 from the UART base, while UART_IER is defined as 1
2461 * in include/linux/serial_reg.h,
2462 * see first lines of serial_in() and serial_out() in 8250.c
2463 */
2464
2465 static struct pciserial_board pci_boards[] = {
2466 [pbn_default] = {
2467 .flags = FL_BASE0,
2468 .num_ports = 1,
2469 .base_baud = 115200,
2470 .uart_offset = 8,
2471 },
2472 [pbn_b0_1_115200] = {
2473 .flags = FL_BASE0,
2474 .num_ports = 1,
2475 .base_baud = 115200,
2476 .uart_offset = 8,
2477 },
2478 [pbn_b0_2_115200] = {
2479 .flags = FL_BASE0,
2480 .num_ports = 2,
2481 .base_baud = 115200,
2482 .uart_offset = 8,
2483 },
2484 [pbn_b0_4_115200] = {
2485 .flags = FL_BASE0,
2486 .num_ports = 4,
2487 .base_baud = 115200,
2488 .uart_offset = 8,
2489 },
2490 [pbn_b0_5_115200] = {
2491 .flags = FL_BASE0,
2492 .num_ports = 5,
2493 .base_baud = 115200,
2494 .uart_offset = 8,
2495 },
2496 [pbn_b0_8_115200] = {
2497 .flags = FL_BASE0,
2498 .num_ports = 8,
2499 .base_baud = 115200,
2500 .uart_offset = 8,
2501 },
2502 [pbn_b0_1_921600] = {
2503 .flags = FL_BASE0,
2504 .num_ports = 1,
2505 .base_baud = 921600,
2506 .uart_offset = 8,
2507 },
2508 [pbn_b0_2_921600] = {
2509 .flags = FL_BASE0,
2510 .num_ports = 2,
2511 .base_baud = 921600,
2512 .uart_offset = 8,
2513 },
2514 [pbn_b0_4_921600] = {
2515 .flags = FL_BASE0,
2516 .num_ports = 4,
2517 .base_baud = 921600,
2518 .uart_offset = 8,
2519 },
2520
2521 [pbn_b0_2_1130000] = {
2522 .flags = FL_BASE0,
2523 .num_ports = 2,
2524 .base_baud = 1130000,
2525 .uart_offset = 8,
2526 },
2527
2528 [pbn_b0_4_1152000] = {
2529 .flags = FL_BASE0,
2530 .num_ports = 4,
2531 .base_baud = 1152000,
2532 .uart_offset = 8,
2533 },
2534
2535 [pbn_b0_2_1152000_200] = {
2536 .flags = FL_BASE0,
2537 .num_ports = 2,
2538 .base_baud = 1152000,
2539 .uart_offset = 0x200,
2540 },
2541
2542 [pbn_b0_4_1152000_200] = {
2543 .flags = FL_BASE0,
2544 .num_ports = 4,
2545 .base_baud = 1152000,
2546 .uart_offset = 0x200,
2547 },
2548
2549 [pbn_b0_8_1152000_200] = {
2550 .flags = FL_BASE0,
2551 .num_ports = 8,
2552 .base_baud = 1152000,
2553 .uart_offset = 0x200,
2554 },
2555
2556 [pbn_b0_2_1843200] = {
2557 .flags = FL_BASE0,
2558 .num_ports = 2,
2559 .base_baud = 1843200,
2560 .uart_offset = 8,
2561 },
2562 [pbn_b0_4_1843200] = {
2563 .flags = FL_BASE0,
2564 .num_ports = 4,
2565 .base_baud = 1843200,
2566 .uart_offset = 8,
2567 },
2568
2569 [pbn_b0_2_1843200_200] = {
2570 .flags = FL_BASE0,
2571 .num_ports = 2,
2572 .base_baud = 1843200,
2573 .uart_offset = 0x200,
2574 },
2575 [pbn_b0_4_1843200_200] = {
2576 .flags = FL_BASE0,
2577 .num_ports = 4,
2578 .base_baud = 1843200,
2579 .uart_offset = 0x200,
2580 },
2581 [pbn_b0_8_1843200_200] = {
2582 .flags = FL_BASE0,
2583 .num_ports = 8,
2584 .base_baud = 1843200,
2585 .uart_offset = 0x200,
2586 },
2587 [pbn_b0_1_4000000] = {
2588 .flags = FL_BASE0,
2589 .num_ports = 1,
2590 .base_baud = 4000000,
2591 .uart_offset = 8,
2592 },
2593
2594 [pbn_b0_bt_1_115200] = {
2595 .flags = FL_BASE0|FL_BASE_BARS,
2596 .num_ports = 1,
2597 .base_baud = 115200,
2598 .uart_offset = 8,
2599 },
2600 [pbn_b0_bt_2_115200] = {
2601 .flags = FL_BASE0|FL_BASE_BARS,
2602 .num_ports = 2,
2603 .base_baud = 115200,
2604 .uart_offset = 8,
2605 },
2606 [pbn_b0_bt_4_115200] = {
2607 .flags = FL_BASE0|FL_BASE_BARS,
2608 .num_ports = 4,
2609 .base_baud = 115200,
2610 .uart_offset = 8,
2611 },
2612 [pbn_b0_bt_8_115200] = {
2613 .flags = FL_BASE0|FL_BASE_BARS,
2614 .num_ports = 8,
2615 .base_baud = 115200,
2616 .uart_offset = 8,
2617 },
2618
2619 [pbn_b0_bt_1_460800] = {
2620 .flags = FL_BASE0|FL_BASE_BARS,
2621 .num_ports = 1,
2622 .base_baud = 460800,
2623 .uart_offset = 8,
2624 },
2625 [pbn_b0_bt_2_460800] = {
2626 .flags = FL_BASE0|FL_BASE_BARS,
2627 .num_ports = 2,
2628 .base_baud = 460800,
2629 .uart_offset = 8,
2630 },
2631 [pbn_b0_bt_4_460800] = {
2632 .flags = FL_BASE0|FL_BASE_BARS,
2633 .num_ports = 4,
2634 .base_baud = 460800,
2635 .uart_offset = 8,
2636 },
2637
2638 [pbn_b0_bt_1_921600] = {
2639 .flags = FL_BASE0|FL_BASE_BARS,
2640 .num_ports = 1,
2641 .base_baud = 921600,
2642 .uart_offset = 8,
2643 },
2644 [pbn_b0_bt_2_921600] = {
2645 .flags = FL_BASE0|FL_BASE_BARS,
2646 .num_ports = 2,
2647 .base_baud = 921600,
2648 .uart_offset = 8,
2649 },
2650 [pbn_b0_bt_4_921600] = {
2651 .flags = FL_BASE0|FL_BASE_BARS,
2652 .num_ports = 4,
2653 .base_baud = 921600,
2654 .uart_offset = 8,
2655 },
2656 [pbn_b0_bt_8_921600] = {
2657 .flags = FL_BASE0|FL_BASE_BARS,
2658 .num_ports = 8,
2659 .base_baud = 921600,
2660 .uart_offset = 8,
2661 },
2662
2663 [pbn_b1_1_115200] = {
2664 .flags = FL_BASE1,
2665 .num_ports = 1,
2666 .base_baud = 115200,
2667 .uart_offset = 8,
2668 },
2669 [pbn_b1_2_115200] = {
2670 .flags = FL_BASE1,
2671 .num_ports = 2,
2672 .base_baud = 115200,
2673 .uart_offset = 8,
2674 },
2675 [pbn_b1_4_115200] = {
2676 .flags = FL_BASE1,
2677 .num_ports = 4,
2678 .base_baud = 115200,
2679 .uart_offset = 8,
2680 },
2681 [pbn_b1_8_115200] = {
2682 .flags = FL_BASE1,
2683 .num_ports = 8,
2684 .base_baud = 115200,
2685 .uart_offset = 8,
2686 },
2687 [pbn_b1_16_115200] = {
2688 .flags = FL_BASE1,
2689 .num_ports = 16,
2690 .base_baud = 115200,
2691 .uart_offset = 8,
2692 },
2693
2694 [pbn_b1_1_921600] = {
2695 .flags = FL_BASE1,
2696 .num_ports = 1,
2697 .base_baud = 921600,
2698 .uart_offset = 8,
2699 },
2700 [pbn_b1_2_921600] = {
2701 .flags = FL_BASE1,
2702 .num_ports = 2,
2703 .base_baud = 921600,
2704 .uart_offset = 8,
2705 },
2706 [pbn_b1_4_921600] = {
2707 .flags = FL_BASE1,
2708 .num_ports = 4,
2709 .base_baud = 921600,
2710 .uart_offset = 8,
2711 },
2712 [pbn_b1_8_921600] = {
2713 .flags = FL_BASE1,
2714 .num_ports = 8,
2715 .base_baud = 921600,
2716 .uart_offset = 8,
2717 },
2718 [pbn_b1_2_1250000] = {
2719 .flags = FL_BASE1,
2720 .num_ports = 2,
2721 .base_baud = 1250000,
2722 .uart_offset = 8,
2723 },
2724
2725 [pbn_b1_bt_1_115200] = {
2726 .flags = FL_BASE1|FL_BASE_BARS,
2727 .num_ports = 1,
2728 .base_baud = 115200,
2729 .uart_offset = 8,
2730 },
2731 [pbn_b1_bt_2_115200] = {
2732 .flags = FL_BASE1|FL_BASE_BARS,
2733 .num_ports = 2,
2734 .base_baud = 115200,
2735 .uart_offset = 8,
2736 },
2737 [pbn_b1_bt_4_115200] = {
2738 .flags = FL_BASE1|FL_BASE_BARS,
2739 .num_ports = 4,
2740 .base_baud = 115200,
2741 .uart_offset = 8,
2742 },
2743
2744 [pbn_b1_bt_2_921600] = {
2745 .flags = FL_BASE1|FL_BASE_BARS,
2746 .num_ports = 2,
2747 .base_baud = 921600,
2748 .uart_offset = 8,
2749 },
2750
2751 [pbn_b1_1_1382400] = {
2752 .flags = FL_BASE1,
2753 .num_ports = 1,
2754 .base_baud = 1382400,
2755 .uart_offset = 8,
2756 },
2757 [pbn_b1_2_1382400] = {
2758 .flags = FL_BASE1,
2759 .num_ports = 2,
2760 .base_baud = 1382400,
2761 .uart_offset = 8,
2762 },
2763 [pbn_b1_4_1382400] = {
2764 .flags = FL_BASE1,
2765 .num_ports = 4,
2766 .base_baud = 1382400,
2767 .uart_offset = 8,
2768 },
2769 [pbn_b1_8_1382400] = {
2770 .flags = FL_BASE1,
2771 .num_ports = 8,
2772 .base_baud = 1382400,
2773 .uart_offset = 8,
2774 },
2775
2776 [pbn_b2_1_115200] = {
2777 .flags = FL_BASE2,
2778 .num_ports = 1,
2779 .base_baud = 115200,
2780 .uart_offset = 8,
2781 },
2782 [pbn_b2_2_115200] = {
2783 .flags = FL_BASE2,
2784 .num_ports = 2,
2785 .base_baud = 115200,
2786 .uart_offset = 8,
2787 },
2788 [pbn_b2_4_115200] = {
2789 .flags = FL_BASE2,
2790 .num_ports = 4,
2791 .base_baud = 115200,
2792 .uart_offset = 8,
2793 },
2794 [pbn_b2_8_115200] = {
2795 .flags = FL_BASE2,
2796 .num_ports = 8,
2797 .base_baud = 115200,
2798 .uart_offset = 8,
2799 },
2800
2801 [pbn_b2_1_460800] = {
2802 .flags = FL_BASE2,
2803 .num_ports = 1,
2804 .base_baud = 460800,
2805 .uart_offset = 8,
2806 },
2807 [pbn_b2_4_460800] = {
2808 .flags = FL_BASE2,
2809 .num_ports = 4,
2810 .base_baud = 460800,
2811 .uart_offset = 8,
2812 },
2813 [pbn_b2_8_460800] = {
2814 .flags = FL_BASE2,
2815 .num_ports = 8,
2816 .base_baud = 460800,
2817 .uart_offset = 8,
2818 },
2819 [pbn_b2_16_460800] = {
2820 .flags = FL_BASE2,
2821 .num_ports = 16,
2822 .base_baud = 460800,
2823 .uart_offset = 8,
2824 },
2825
2826 [pbn_b2_1_921600] = {
2827 .flags = FL_BASE2,
2828 .num_ports = 1,
2829 .base_baud = 921600,
2830 .uart_offset = 8,
2831 },
2832 [pbn_b2_4_921600] = {
2833 .flags = FL_BASE2,
2834 .num_ports = 4,
2835 .base_baud = 921600,
2836 .uart_offset = 8,
2837 },
2838 [pbn_b2_8_921600] = {
2839 .flags = FL_BASE2,
2840 .num_ports = 8,
2841 .base_baud = 921600,
2842 .uart_offset = 8,
2843 },
2844
2845 [pbn_b2_8_1152000] = {
2846 .flags = FL_BASE2,
2847 .num_ports = 8,
2848 .base_baud = 1152000,
2849 .uart_offset = 8,
2850 },
2851
2852 [pbn_b2_bt_1_115200] = {
2853 .flags = FL_BASE2|FL_BASE_BARS,
2854 .num_ports = 1,
2855 .base_baud = 115200,
2856 .uart_offset = 8,
2857 },
2858 [pbn_b2_bt_2_115200] = {
2859 .flags = FL_BASE2|FL_BASE_BARS,
2860 .num_ports = 2,
2861 .base_baud = 115200,
2862 .uart_offset = 8,
2863 },
2864 [pbn_b2_bt_4_115200] = {
2865 .flags = FL_BASE2|FL_BASE_BARS,
2866 .num_ports = 4,
2867 .base_baud = 115200,
2868 .uart_offset = 8,
2869 },
2870
2871 [pbn_b2_bt_2_921600] = {
2872 .flags = FL_BASE2|FL_BASE_BARS,
2873 .num_ports = 2,
2874 .base_baud = 921600,
2875 .uart_offset = 8,
2876 },
2877 [pbn_b2_bt_4_921600] = {
2878 .flags = FL_BASE2|FL_BASE_BARS,
2879 .num_ports = 4,
2880 .base_baud = 921600,
2881 .uart_offset = 8,
2882 },
2883
2884 [pbn_b3_2_115200] = {
2885 .flags = FL_BASE3,
2886 .num_ports = 2,
2887 .base_baud = 115200,
2888 .uart_offset = 8,
2889 },
2890 [pbn_b3_4_115200] = {
2891 .flags = FL_BASE3,
2892 .num_ports = 4,
2893 .base_baud = 115200,
2894 .uart_offset = 8,
2895 },
2896 [pbn_b3_8_115200] = {
2897 .flags = FL_BASE3,
2898 .num_ports = 8,
2899 .base_baud = 115200,
2900 .uart_offset = 8,
2901 },
2902
2903 [pbn_b4_bt_2_921600] = {
2904 .flags = FL_BASE4,
2905 .num_ports = 2,
2906 .base_baud = 921600,
2907 .uart_offset = 8,
2908 },
2909 [pbn_b4_bt_4_921600] = {
2910 .flags = FL_BASE4,
2911 .num_ports = 4,
2912 .base_baud = 921600,
2913 .uart_offset = 8,
2914 },
2915 [pbn_b4_bt_8_921600] = {
2916 .flags = FL_BASE4,
2917 .num_ports = 8,
2918 .base_baud = 921600,
2919 .uart_offset = 8,
2920 },
2921
2922 /*
2923 * Entries following this are board-specific.
2924 */
2925
2926 /*
2927 * Panacom - IOMEM
2928 */
2929 [pbn_panacom] = {
2930 .flags = FL_BASE2,
2931 .num_ports = 2,
2932 .base_baud = 921600,
2933 .uart_offset = 0x400,
2934 .reg_shift = 7,
2935 },
2936 [pbn_panacom2] = {
2937 .flags = FL_BASE2|FL_BASE_BARS,
2938 .num_ports = 2,
2939 .base_baud = 921600,
2940 .uart_offset = 0x400,
2941 .reg_shift = 7,
2942 },
2943 [pbn_panacom4] = {
2944 .flags = FL_BASE2|FL_BASE_BARS,
2945 .num_ports = 4,
2946 .base_baud = 921600,
2947 .uart_offset = 0x400,
2948 .reg_shift = 7,
2949 },
2950
2951 /* I think this entry is broken - the first_offset looks wrong --rmk */
2952 [pbn_plx_romulus] = {
2953 .flags = FL_BASE2,
2954 .num_ports = 4,
2955 .base_baud = 921600,
2956 .uart_offset = 8 << 2,
2957 .reg_shift = 2,
2958 .first_offset = 0x03,
2959 },
2960
2961 /*
2962 * This board uses the size of PCI Base region 0 to
2963 * signal now many ports are available
2964 */
2965 [pbn_oxsemi] = {
2966 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2967 .num_ports = 32,
2968 .base_baud = 115200,
2969 .uart_offset = 8,
2970 },
2971 [pbn_oxsemi_1_4000000] = {
2972 .flags = FL_BASE0,
2973 .num_ports = 1,
2974 .base_baud = 4000000,
2975 .uart_offset = 0x200,
2976 .first_offset = 0x1000,
2977 },
2978 [pbn_oxsemi_2_4000000] = {
2979 .flags = FL_BASE0,
2980 .num_ports = 2,
2981 .base_baud = 4000000,
2982 .uart_offset = 0x200,
2983 .first_offset = 0x1000,
2984 },
2985 [pbn_oxsemi_4_4000000] = {
2986 .flags = FL_BASE0,
2987 .num_ports = 4,
2988 .base_baud = 4000000,
2989 .uart_offset = 0x200,
2990 .first_offset = 0x1000,
2991 },
2992 [pbn_oxsemi_8_4000000] = {
2993 .flags = FL_BASE0,
2994 .num_ports = 8,
2995 .base_baud = 4000000,
2996 .uart_offset = 0x200,
2997 .first_offset = 0x1000,
2998 },
2999
3000
3001 /*
3002 * EKF addition for i960 Boards form EKF with serial port.
3003 * Max 256 ports.
3004 */
3005 [pbn_intel_i960] = {
3006 .flags = FL_BASE0,
3007 .num_ports = 32,
3008 .base_baud = 921600,
3009 .uart_offset = 8 << 2,
3010 .reg_shift = 2,
3011 .first_offset = 0x10000,
3012 },
3013 [pbn_sgi_ioc3] = {
3014 .flags = FL_BASE0|FL_NOIRQ,
3015 .num_ports = 1,
3016 .base_baud = 458333,
3017 .uart_offset = 8,
3018 .reg_shift = 0,
3019 .first_offset = 0x20178,
3020 },
3021
3022 /*
3023 * Computone - uses IOMEM.
3024 */
3025 [pbn_computone_4] = {
3026 .flags = FL_BASE0,
3027 .num_ports = 4,
3028 .base_baud = 921600,
3029 .uart_offset = 0x40,
3030 .reg_shift = 2,
3031 .first_offset = 0x200,
3032 },
3033 [pbn_computone_6] = {
3034 .flags = FL_BASE0,
3035 .num_ports = 6,
3036 .base_baud = 921600,
3037 .uart_offset = 0x40,
3038 .reg_shift = 2,
3039 .first_offset = 0x200,
3040 },
3041 [pbn_computone_8] = {
3042 .flags = FL_BASE0,
3043 .num_ports = 8,
3044 .base_baud = 921600,
3045 .uart_offset = 0x40,
3046 .reg_shift = 2,
3047 .first_offset = 0x200,
3048 },
3049 [pbn_sbsxrsio] = {
3050 .flags = FL_BASE0,
3051 .num_ports = 8,
3052 .base_baud = 460800,
3053 .uart_offset = 256,
3054 .reg_shift = 4,
3055 },
3056 /*
3057 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3058 * Only basic 16550A support.
3059 * XR17C15[24] are not tested, but they should work.
3060 */
3061 [pbn_exar_XR17C152] = {
3062 .flags = FL_BASE0,
3063 .num_ports = 2,
3064 .base_baud = 921600,
3065 .uart_offset = 0x200,
3066 },
3067 [pbn_exar_XR17C154] = {
3068 .flags = FL_BASE0,
3069 .num_ports = 4,
3070 .base_baud = 921600,
3071 .uart_offset = 0x200,
3072 },
3073 [pbn_exar_XR17C158] = {
3074 .flags = FL_BASE0,
3075 .num_ports = 8,
3076 .base_baud = 921600,
3077 .uart_offset = 0x200,
3078 },
3079 [pbn_exar_XR17V352] = {
3080 .flags = FL_BASE0,
3081 .num_ports = 2,
3082 .base_baud = 7812500,
3083 .uart_offset = 0x400,
3084 .reg_shift = 0,
3085 .first_offset = 0,
3086 },
3087 [pbn_exar_XR17V354] = {
3088 .flags = FL_BASE0,
3089 .num_ports = 4,
3090 .base_baud = 7812500,
3091 .uart_offset = 0x400,
3092 .reg_shift = 0,
3093 .first_offset = 0,
3094 },
3095 [pbn_exar_XR17V358] = {
3096 .flags = FL_BASE0,
3097 .num_ports = 8,
3098 .base_baud = 7812500,
3099 .uart_offset = 0x400,
3100 .reg_shift = 0,
3101 .first_offset = 0,
3102 },
3103 [pbn_exar_ibm_saturn] = {
3104 .flags = FL_BASE0,
3105 .num_ports = 1,
3106 .base_baud = 921600,
3107 .uart_offset = 0x200,
3108 },
3109
3110 /*
3111 * PA Semi PWRficient PA6T-1682M on-chip UART
3112 */
3113 [pbn_pasemi_1682M] = {
3114 .flags = FL_BASE0,
3115 .num_ports = 1,
3116 .base_baud = 8333333,
3117 },
3118 /*
3119 * National Instruments 843x
3120 */
3121 [pbn_ni8430_16] = {
3122 .flags = FL_BASE0,
3123 .num_ports = 16,
3124 .base_baud = 3686400,
3125 .uart_offset = 0x10,
3126 .first_offset = 0x800,
3127 },
3128 [pbn_ni8430_8] = {
3129 .flags = FL_BASE0,
3130 .num_ports = 8,
3131 .base_baud = 3686400,
3132 .uart_offset = 0x10,
3133 .first_offset = 0x800,
3134 },
3135 [pbn_ni8430_4] = {
3136 .flags = FL_BASE0,
3137 .num_ports = 4,
3138 .base_baud = 3686400,
3139 .uart_offset = 0x10,
3140 .first_offset = 0x800,
3141 },
3142 [pbn_ni8430_2] = {
3143 .flags = FL_BASE0,
3144 .num_ports = 2,
3145 .base_baud = 3686400,
3146 .uart_offset = 0x10,
3147 .first_offset = 0x800,
3148 },
3149 /*
3150 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3151 */
3152 [pbn_ADDIDATA_PCIe_1_3906250] = {
3153 .flags = FL_BASE0,
3154 .num_ports = 1,
3155 .base_baud = 3906250,
3156 .uart_offset = 0x200,
3157 .first_offset = 0x1000,
3158 },
3159 [pbn_ADDIDATA_PCIe_2_3906250] = {
3160 .flags = FL_BASE0,
3161 .num_ports = 2,
3162 .base_baud = 3906250,
3163 .uart_offset = 0x200,
3164 .first_offset = 0x1000,
3165 },
3166 [pbn_ADDIDATA_PCIe_4_3906250] = {
3167 .flags = FL_BASE0,
3168 .num_ports = 4,
3169 .base_baud = 3906250,
3170 .uart_offset = 0x200,
3171 .first_offset = 0x1000,
3172 },
3173 [pbn_ADDIDATA_PCIe_8_3906250] = {
3174 .flags = FL_BASE0,
3175 .num_ports = 8,
3176 .base_baud = 3906250,
3177 .uart_offset = 0x200,
3178 .first_offset = 0x1000,
3179 },
3180 [pbn_ce4100_1_115200] = {
3181 .flags = FL_BASE_BARS,
3182 .num_ports = 2,
3183 .base_baud = 921600,
3184 .reg_shift = 2,
3185 },
3186 [pbn_omegapci] = {
3187 .flags = FL_BASE0,
3188 .num_ports = 8,
3189 .base_baud = 115200,
3190 .uart_offset = 0x200,
3191 },
3192 [pbn_NETMOS9900_2s_115200] = {
3193 .flags = FL_BASE0,
3194 .num_ports = 2,
3195 .base_baud = 115200,
3196 },
3197 [pbn_brcm_trumanage] = {
3198 .flags = FL_BASE0,
3199 .num_ports = 1,
3200 .reg_shift = 2,
3201 .base_baud = 115200,
3202 },
3203 };
3204
3205 static const struct pci_device_id blacklist[] = {
3206 /* softmodems */
3207 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3208 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3209 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3210
3211 /* multi-io cards handled by parport_serial */
3212 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3213 };
3214
3215 /*
3216 * Given a complete unknown PCI device, try to use some heuristics to
3217 * guess what the configuration might be, based on the pitiful PCI
3218 * serial specs. Returns 0 on success, 1 on failure.
3219 */
3220 static int
3221 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3222 {
3223 const struct pci_device_id *bldev;
3224 int num_iomem, num_port, first_port = -1, i;
3225
3226 /*
3227 * If it is not a communications device or the programming
3228 * interface is greater than 6, give up.
3229 *
3230 * (Should we try to make guesses for multiport serial devices
3231 * later?)
3232 */
3233 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3234 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3235 (dev->class & 0xff) > 6)
3236 return -ENODEV;
3237
3238 /*
3239 * Do not access blacklisted devices that are known not to
3240 * feature serial ports or are handled by other modules.
3241 */
3242 for (bldev = blacklist;
3243 bldev < blacklist + ARRAY_SIZE(blacklist);
3244 bldev++) {
3245 if (dev->vendor == bldev->vendor &&
3246 dev->device == bldev->device)
3247 return -ENODEV;
3248 }
3249
3250 num_iomem = num_port = 0;
3251 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3252 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3253 num_port++;
3254 if (first_port == -1)
3255 first_port = i;
3256 }
3257 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3258 num_iomem++;
3259 }
3260
3261 /*
3262 * If there is 1 or 0 iomem regions, and exactly one port,
3263 * use it. We guess the number of ports based on the IO
3264 * region size.
3265 */
3266 if (num_iomem <= 1 && num_port == 1) {
3267 board->flags = first_port;
3268 board->num_ports = pci_resource_len(dev, first_port) / 8;
3269 return 0;
3270 }
3271
3272 /*
3273 * Now guess if we've got a board which indexes by BARs.
3274 * Each IO BAR should be 8 bytes, and they should follow
3275 * consecutively.
3276 */
3277 first_port = -1;
3278 num_port = 0;
3279 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3280 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3281 pci_resource_len(dev, i) == 8 &&
3282 (first_port == -1 || (first_port + num_port) == i)) {
3283 num_port++;
3284 if (first_port == -1)
3285 first_port = i;
3286 }
3287 }
3288
3289 if (num_port > 1) {
3290 board->flags = first_port | FL_BASE_BARS;
3291 board->num_ports = num_port;
3292 return 0;
3293 }
3294
3295 return -ENODEV;
3296 }
3297
3298 static inline int
3299 serial_pci_matches(const struct pciserial_board *board,
3300 const struct pciserial_board *guessed)
3301 {
3302 return
3303 board->num_ports == guessed->num_ports &&
3304 board->base_baud == guessed->base_baud &&
3305 board->uart_offset == guessed->uart_offset &&
3306 board->reg_shift == guessed->reg_shift &&
3307 board->first_offset == guessed->first_offset;
3308 }
3309
3310 struct serial_private *
3311 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3312 {
3313 struct uart_8250_port uart;
3314 struct serial_private *priv;
3315 struct pci_serial_quirk *quirk;
3316 int rc, nr_ports, i;
3317
3318 nr_ports = board->num_ports;
3319
3320 /*
3321 * Find an init and setup quirks.
3322 */
3323 quirk = find_quirk(dev);
3324
3325 /*
3326 * Run the new-style initialization function.
3327 * The initialization function returns:
3328 * <0 - error
3329 * 0 - use board->num_ports
3330 * >0 - number of ports
3331 */
3332 if (quirk->init) {
3333 rc = quirk->init(dev);
3334 if (rc < 0) {
3335 priv = ERR_PTR(rc);
3336 goto err_out;
3337 }
3338 if (rc)
3339 nr_ports = rc;
3340 }
3341
3342 priv = kzalloc(sizeof(struct serial_private) +
3343 sizeof(unsigned int) * nr_ports,
3344 GFP_KERNEL);
3345 if (!priv) {
3346 priv = ERR_PTR(-ENOMEM);
3347 goto err_deinit;
3348 }
3349
3350 priv->dev = dev;
3351 priv->quirk = quirk;
3352
3353 memset(&uart, 0, sizeof(uart));
3354 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3355 uart.port.uartclk = board->base_baud * 16;
3356 uart.port.irq = get_pci_irq(dev, board);
3357 uart.port.dev = &dev->dev;
3358
3359 for (i = 0; i < nr_ports; i++) {
3360 if (quirk->setup(priv, board, &uart, i))
3361 break;
3362
3363 #ifdef SERIAL_DEBUG_PCI
3364 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
3365 uart.port.iobase, uart.port.irq, uart.port.iotype);
3366 #endif
3367
3368 priv->line[i] = serial8250_register_8250_port(&uart);
3369 if (priv->line[i] < 0) {
3370 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3371 break;
3372 }
3373 }
3374 priv->nr = i;
3375 return priv;
3376
3377 err_deinit:
3378 if (quirk->exit)
3379 quirk->exit(dev);
3380 err_out:
3381 return priv;
3382 }
3383 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3384
3385 void pciserial_remove_ports(struct serial_private *priv)
3386 {
3387 struct pci_serial_quirk *quirk;
3388 int i;
3389
3390 for (i = 0; i < priv->nr; i++)
3391 serial8250_unregister_port(priv->line[i]);
3392
3393 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3394 if (priv->remapped_bar[i])
3395 iounmap(priv->remapped_bar[i]);
3396 priv->remapped_bar[i] = NULL;
3397 }
3398
3399 /*
3400 * Find the exit quirks.
3401 */
3402 quirk = find_quirk(priv->dev);
3403 if (quirk->exit)
3404 quirk->exit(priv->dev);
3405
3406 kfree(priv);
3407 }
3408 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3409
3410 void pciserial_suspend_ports(struct serial_private *priv)
3411 {
3412 int i;
3413
3414 for (i = 0; i < priv->nr; i++)
3415 if (priv->line[i] >= 0)
3416 serial8250_suspend_port(priv->line[i]);
3417
3418 /*
3419 * Ensure that every init quirk is properly torn down
3420 */
3421 if (priv->quirk->exit)
3422 priv->quirk->exit(priv->dev);
3423 }
3424 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3425
3426 void pciserial_resume_ports(struct serial_private *priv)
3427 {
3428 int i;
3429
3430 /*
3431 * Ensure that the board is correctly configured.
3432 */
3433 if (priv->quirk->init)
3434 priv->quirk->init(priv->dev);
3435
3436 for (i = 0; i < priv->nr; i++)
3437 if (priv->line[i] >= 0)
3438 serial8250_resume_port(priv->line[i]);
3439 }
3440 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3441
3442 /*
3443 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3444 * to the arrangement of serial ports on a PCI card.
3445 */
3446 static int
3447 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3448 {
3449 struct pci_serial_quirk *quirk;
3450 struct serial_private *priv;
3451 const struct pciserial_board *board;
3452 struct pciserial_board tmp;
3453 int rc;
3454
3455 quirk = find_quirk(dev);
3456 if (quirk->probe) {
3457 rc = quirk->probe(dev);
3458 if (rc)
3459 return rc;
3460 }
3461
3462 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3463 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3464 ent->driver_data);
3465 return -EINVAL;
3466 }
3467
3468 board = &pci_boards[ent->driver_data];
3469
3470 rc = pci_enable_device(dev);
3471 pci_save_state(dev);
3472 if (rc)
3473 return rc;
3474
3475 if (ent->driver_data == pbn_default) {
3476 /*
3477 * Use a copy of the pci_board entry for this;
3478 * avoid changing entries in the table.
3479 */
3480 memcpy(&tmp, board, sizeof(struct pciserial_board));
3481 board = &tmp;
3482
3483 /*
3484 * We matched one of our class entries. Try to
3485 * determine the parameters of this board.
3486 */
3487 rc = serial_pci_guess_board(dev, &tmp);
3488 if (rc)
3489 goto disable;
3490 } else {
3491 /*
3492 * We matched an explicit entry. If we are able to
3493 * detect this boards settings with our heuristic,
3494 * then we no longer need this entry.
3495 */
3496 memcpy(&tmp, &pci_boards[pbn_default],
3497 sizeof(struct pciserial_board));
3498 rc = serial_pci_guess_board(dev, &tmp);
3499 if (rc == 0 && serial_pci_matches(board, &tmp))
3500 moan_device("Redundant entry in serial pci_table.",
3501 dev);
3502 }
3503
3504 priv = pciserial_init_ports(dev, board);
3505 if (!IS_ERR(priv)) {
3506 pci_set_drvdata(dev, priv);
3507 return 0;
3508 }
3509
3510 rc = PTR_ERR(priv);
3511
3512 disable:
3513 pci_disable_device(dev);
3514 return rc;
3515 }
3516
3517 static void pciserial_remove_one(struct pci_dev *dev)
3518 {
3519 struct serial_private *priv = pci_get_drvdata(dev);
3520
3521 pci_set_drvdata(dev, NULL);
3522
3523 pciserial_remove_ports(priv);
3524
3525 pci_disable_device(dev);
3526 }
3527
3528 #ifdef CONFIG_PM
3529 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3530 {
3531 struct serial_private *priv = pci_get_drvdata(dev);
3532
3533 if (priv)
3534 pciserial_suspend_ports(priv);
3535
3536 pci_save_state(dev);
3537 pci_set_power_state(dev, pci_choose_state(dev, state));
3538 return 0;
3539 }
3540
3541 static int pciserial_resume_one(struct pci_dev *dev)
3542 {
3543 int err;
3544 struct serial_private *priv = pci_get_drvdata(dev);
3545
3546 pci_set_power_state(dev, PCI_D0);
3547 pci_restore_state(dev);
3548
3549 if (priv) {
3550 /*
3551 * The device may have been disabled. Re-enable it.
3552 */
3553 err = pci_enable_device(dev);
3554 /* FIXME: We cannot simply error out here */
3555 if (err)
3556 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3557 pciserial_resume_ports(priv);
3558 }
3559 return 0;
3560 }
3561 #endif
3562
3563 static struct pci_device_id serial_pci_tbl[] = {
3564 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3565 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3566 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3567 pbn_b2_8_921600 },
3568 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3569 PCI_SUBVENDOR_ID_CONNECT_TECH,
3570 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3571 pbn_b1_8_1382400 },
3572 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3573 PCI_SUBVENDOR_ID_CONNECT_TECH,
3574 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3575 pbn_b1_4_1382400 },
3576 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3577 PCI_SUBVENDOR_ID_CONNECT_TECH,
3578 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3579 pbn_b1_2_1382400 },
3580 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3581 PCI_SUBVENDOR_ID_CONNECT_TECH,
3582 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3583 pbn_b1_8_1382400 },
3584 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3585 PCI_SUBVENDOR_ID_CONNECT_TECH,
3586 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3587 pbn_b1_4_1382400 },
3588 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3589 PCI_SUBVENDOR_ID_CONNECT_TECH,
3590 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3591 pbn_b1_2_1382400 },
3592 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3593 PCI_SUBVENDOR_ID_CONNECT_TECH,
3594 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3595 pbn_b1_8_921600 },
3596 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3597 PCI_SUBVENDOR_ID_CONNECT_TECH,
3598 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3599 pbn_b1_8_921600 },
3600 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3601 PCI_SUBVENDOR_ID_CONNECT_TECH,
3602 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3603 pbn_b1_4_921600 },
3604 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3605 PCI_SUBVENDOR_ID_CONNECT_TECH,
3606 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3607 pbn_b1_4_921600 },
3608 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3609 PCI_SUBVENDOR_ID_CONNECT_TECH,
3610 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3611 pbn_b1_2_921600 },
3612 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3613 PCI_SUBVENDOR_ID_CONNECT_TECH,
3614 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3615 pbn_b1_8_921600 },
3616 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3617 PCI_SUBVENDOR_ID_CONNECT_TECH,
3618 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3619 pbn_b1_8_921600 },
3620 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3621 PCI_SUBVENDOR_ID_CONNECT_TECH,
3622 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3623 pbn_b1_4_921600 },
3624 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3625 PCI_SUBVENDOR_ID_CONNECT_TECH,
3626 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3627 pbn_b1_2_1250000 },
3628 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3629 PCI_SUBVENDOR_ID_CONNECT_TECH,
3630 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3631 pbn_b0_2_1843200 },
3632 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3633 PCI_SUBVENDOR_ID_CONNECT_TECH,
3634 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3635 pbn_b0_4_1843200 },
3636 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3637 PCI_VENDOR_ID_AFAVLAB,
3638 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3639 pbn_b0_4_1152000 },
3640 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3641 PCI_SUBVENDOR_ID_CONNECT_TECH,
3642 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3643 pbn_b0_2_1843200_200 },
3644 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3645 PCI_SUBVENDOR_ID_CONNECT_TECH,
3646 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3647 pbn_b0_4_1843200_200 },
3648 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3649 PCI_SUBVENDOR_ID_CONNECT_TECH,
3650 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3651 pbn_b0_8_1843200_200 },
3652 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3653 PCI_SUBVENDOR_ID_CONNECT_TECH,
3654 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3655 pbn_b0_2_1843200_200 },
3656 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3657 PCI_SUBVENDOR_ID_CONNECT_TECH,
3658 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3659 pbn_b0_4_1843200_200 },
3660 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3661 PCI_SUBVENDOR_ID_CONNECT_TECH,
3662 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3663 pbn_b0_8_1843200_200 },
3664 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3665 PCI_SUBVENDOR_ID_CONNECT_TECH,
3666 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3667 pbn_b0_2_1843200_200 },
3668 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3669 PCI_SUBVENDOR_ID_CONNECT_TECH,
3670 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3671 pbn_b0_4_1843200_200 },
3672 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3673 PCI_SUBVENDOR_ID_CONNECT_TECH,
3674 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3675 pbn_b0_8_1843200_200 },
3676 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3677 PCI_SUBVENDOR_ID_CONNECT_TECH,
3678 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3679 pbn_b0_2_1843200_200 },
3680 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3681 PCI_SUBVENDOR_ID_CONNECT_TECH,
3682 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3683 pbn_b0_4_1843200_200 },
3684 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3685 PCI_SUBVENDOR_ID_CONNECT_TECH,
3686 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3687 pbn_b0_8_1843200_200 },
3688 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3689 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3690 0, 0, pbn_exar_ibm_saturn },
3691
3692 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3694 pbn_b2_bt_1_115200 },
3695 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3697 pbn_b2_bt_2_115200 },
3698 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3700 pbn_b2_bt_4_115200 },
3701 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3703 pbn_b2_bt_2_115200 },
3704 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3706 pbn_b2_bt_4_115200 },
3707 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3709 pbn_b2_8_115200 },
3710 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3712 pbn_b2_8_460800 },
3713 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3715 pbn_b2_8_115200 },
3716
3717 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3719 pbn_b2_bt_2_115200 },
3720 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3722 pbn_b2_bt_2_921600 },
3723 /*
3724 * VScom SPCOM800, from sl@s.pl
3725 */
3726 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3728 pbn_b2_8_921600 },
3729 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3731 pbn_b2_4_921600 },
3732 /* Unknown card - subdevice 0x1584 */
3733 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3734 PCI_VENDOR_ID_PLX,
3735 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3736 pbn_b0_4_115200 },
3737 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3738 PCI_SUBVENDOR_ID_KEYSPAN,
3739 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3740 pbn_panacom },
3741 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3743 pbn_panacom4 },
3744 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3746 pbn_panacom2 },
3747 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3748 PCI_VENDOR_ID_ESDGMBH,
3749 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3750 pbn_b2_4_115200 },
3751 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3752 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3753 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3754 pbn_b2_4_460800 },
3755 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3756 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3757 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3758 pbn_b2_8_460800 },
3759 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3760 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3761 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3762 pbn_b2_16_460800 },
3763 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3764 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3765 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3766 pbn_b2_16_460800 },
3767 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3768 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3769 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3770 pbn_b2_4_460800 },
3771 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3772 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3773 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3774 pbn_b2_8_460800 },
3775 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3776 PCI_SUBVENDOR_ID_EXSYS,
3777 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3778 pbn_b2_4_115200 },
3779 /*
3780 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3781 * (Exoray@isys.ca)
3782 */
3783 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3784 0x10b5, 0x106a, 0, 0,
3785 pbn_plx_romulus },
3786 /*
3787 * Quatech cards. These actually have configurable clocks but for
3788 * now we just use the default.
3789 *
3790 * 100 series are RS232, 200 series RS422,
3791 */
3792 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3794 pbn_b1_4_115200 },
3795 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3797 pbn_b1_2_115200 },
3798 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3800 pbn_b2_2_115200 },
3801 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3803 pbn_b1_2_115200 },
3804 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3806 pbn_b2_2_115200 },
3807 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3809 pbn_b1_4_115200 },
3810 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3812 pbn_b1_8_115200 },
3813 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3814 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3815 pbn_b1_8_115200 },
3816 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3818 pbn_b1_4_115200 },
3819 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3821 pbn_b1_2_115200 },
3822 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3823 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3824 pbn_b1_4_115200 },
3825 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3826 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3827 pbn_b1_2_115200 },
3828 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3829 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830 pbn_b2_4_115200 },
3831 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3833 pbn_b2_2_115200 },
3834 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3836 pbn_b2_1_115200 },
3837 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839 pbn_b2_4_115200 },
3840 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3842 pbn_b2_2_115200 },
3843 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845 pbn_b2_1_115200 },
3846 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3848 pbn_b0_8_115200 },
3849
3850 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3851 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3852 0, 0,
3853 pbn_b0_4_921600 },
3854 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3855 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3856 0, 0,
3857 pbn_b0_4_1152000 },
3858 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3860 pbn_b0_bt_2_921600 },
3861
3862 /*
3863 * The below card is a little controversial since it is the
3864 * subject of a PCI vendor/device ID clash. (See
3865 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3866 * For now just used the hex ID 0x950a.
3867 */
3868 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3869 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3870 0, 0, pbn_b0_2_115200 },
3871 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3872 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3873 0, 0, pbn_b0_2_115200 },
3874 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3876 pbn_b0_2_1130000 },
3877 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3878 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3879 pbn_b0_1_921600 },
3880 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882 pbn_b0_4_115200 },
3883 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3885 pbn_b0_bt_2_921600 },
3886 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3887 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3888 pbn_b2_8_1152000 },
3889
3890 /*
3891 * Oxford Semiconductor Inc. Tornado PCI express device range.
3892 */
3893 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3895 pbn_b0_1_4000000 },
3896 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3898 pbn_b0_1_4000000 },
3899 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3901 pbn_oxsemi_1_4000000 },
3902 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3904 pbn_oxsemi_1_4000000 },
3905 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3907 pbn_b0_1_4000000 },
3908 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3910 pbn_b0_1_4000000 },
3911 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3913 pbn_oxsemi_1_4000000 },
3914 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3916 pbn_oxsemi_1_4000000 },
3917 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3919 pbn_b0_1_4000000 },
3920 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3922 pbn_b0_1_4000000 },
3923 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3925 pbn_b0_1_4000000 },
3926 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3928 pbn_b0_1_4000000 },
3929 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931 pbn_oxsemi_2_4000000 },
3932 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3934 pbn_oxsemi_2_4000000 },
3935 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937 pbn_oxsemi_4_4000000 },
3938 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3940 pbn_oxsemi_4_4000000 },
3941 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943 pbn_oxsemi_8_4000000 },
3944 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946 pbn_oxsemi_8_4000000 },
3947 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949 pbn_oxsemi_1_4000000 },
3950 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952 pbn_oxsemi_1_4000000 },
3953 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955 pbn_oxsemi_1_4000000 },
3956 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958 pbn_oxsemi_1_4000000 },
3959 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3961 pbn_oxsemi_1_4000000 },
3962 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3964 pbn_oxsemi_1_4000000 },
3965 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3967 pbn_oxsemi_1_4000000 },
3968 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3970 pbn_oxsemi_1_4000000 },
3971 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3973 pbn_oxsemi_1_4000000 },
3974 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3976 pbn_oxsemi_1_4000000 },
3977 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3979 pbn_oxsemi_1_4000000 },
3980 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3982 pbn_oxsemi_1_4000000 },
3983 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3985 pbn_oxsemi_1_4000000 },
3986 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3988 pbn_oxsemi_1_4000000 },
3989 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3991 pbn_oxsemi_1_4000000 },
3992 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994 pbn_oxsemi_1_4000000 },
3995 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3997 pbn_oxsemi_1_4000000 },
3998 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4000 pbn_oxsemi_1_4000000 },
4001 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4003 pbn_oxsemi_1_4000000 },
4004 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4006 pbn_oxsemi_1_4000000 },
4007 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4009 pbn_oxsemi_1_4000000 },
4010 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4012 pbn_oxsemi_1_4000000 },
4013 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4015 pbn_oxsemi_1_4000000 },
4016 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4018 pbn_oxsemi_1_4000000 },
4019 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4021 pbn_oxsemi_1_4000000 },
4022 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4024 pbn_oxsemi_1_4000000 },
4025 /*
4026 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4027 */
4028 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4029 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4030 pbn_oxsemi_1_4000000 },
4031 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4032 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4033 pbn_oxsemi_2_4000000 },
4034 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4035 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4036 pbn_oxsemi_4_4000000 },
4037 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4038 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4039 pbn_oxsemi_8_4000000 },
4040
4041 /*
4042 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4043 */
4044 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4045 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4046 pbn_oxsemi_2_4000000 },
4047
4048 /*
4049 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4050 * from skokodyn@yahoo.com
4051 */
4052 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4053 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4054 pbn_sbsxrsio },
4055 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4056 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4057 pbn_sbsxrsio },
4058 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4059 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4060 pbn_sbsxrsio },
4061 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4062 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4063 pbn_sbsxrsio },
4064
4065 /*
4066 * Digitan DS560-558, from jimd@esoft.com
4067 */
4068 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 pbn_b1_1_115200 },
4071
4072 /*
4073 * Titan Electronic cards
4074 * The 400L and 800L have a custom setup quirk.
4075 */
4076 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4078 pbn_b0_1_921600 },
4079 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4081 pbn_b0_2_921600 },
4082 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4084 pbn_b0_4_921600 },
4085 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4087 pbn_b0_4_921600 },
4088 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4090 pbn_b1_1_921600 },
4091 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4093 pbn_b1_bt_2_921600 },
4094 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4096 pbn_b0_bt_4_921600 },
4097 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4099 pbn_b0_bt_8_921600 },
4100 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4102 pbn_b4_bt_2_921600 },
4103 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4105 pbn_b4_bt_4_921600 },
4106 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4108 pbn_b4_bt_8_921600 },
4109 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4111 pbn_b0_4_921600 },
4112 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4114 pbn_b0_4_921600 },
4115 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4117 pbn_b0_4_921600 },
4118 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4120 pbn_oxsemi_1_4000000 },
4121 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4123 pbn_oxsemi_2_4000000 },
4124 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4126 pbn_oxsemi_4_4000000 },
4127 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4129 pbn_oxsemi_8_4000000 },
4130 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4132 pbn_oxsemi_2_4000000 },
4133 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4135 pbn_oxsemi_2_4000000 },
4136 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4138 pbn_b0_4_921600 },
4139 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141 pbn_b0_4_921600 },
4142 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144 pbn_b0_4_921600 },
4145 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147 pbn_b0_4_921600 },
4148
4149 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151 pbn_b2_1_460800 },
4152 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 pbn_b2_1_460800 },
4155 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4157 pbn_b2_1_460800 },
4158 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4160 pbn_b2_bt_2_921600 },
4161 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163 pbn_b2_bt_2_921600 },
4164 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4165 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4166 pbn_b2_bt_2_921600 },
4167 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4169 pbn_b2_bt_4_921600 },
4170 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172 pbn_b2_bt_4_921600 },
4173 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4175 pbn_b2_bt_4_921600 },
4176 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4178 pbn_b0_1_921600 },
4179 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4181 pbn_b0_1_921600 },
4182 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184 pbn_b0_1_921600 },
4185 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187 pbn_b0_bt_2_921600 },
4188 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190 pbn_b0_bt_2_921600 },
4191 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4193 pbn_b0_bt_2_921600 },
4194 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196 pbn_b0_bt_4_921600 },
4197 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199 pbn_b0_bt_4_921600 },
4200 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202 pbn_b0_bt_4_921600 },
4203 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205 pbn_b0_bt_8_921600 },
4206 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208 pbn_b0_bt_8_921600 },
4209 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4211 pbn_b0_bt_8_921600 },
4212
4213 /*
4214 * Computone devices submitted by Doug McNash dmcnash@computone.com
4215 */
4216 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4217 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4218 0, 0, pbn_computone_4 },
4219 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4220 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4221 0, 0, pbn_computone_8 },
4222 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4223 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4224 0, 0, pbn_computone_6 },
4225
4226 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_oxsemi },
4229 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4230 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4231 pbn_b0_bt_1_921600 },
4232
4233 /*
4234 * SUNIX (TIMEDIA)
4235 */
4236 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4237 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4238 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4239 pbn_b0_bt_1_921600 },
4240
4241 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4242 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4243 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4244 pbn_b0_bt_1_921600 },
4245
4246 /*
4247 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4248 */
4249 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 pbn_b0_bt_8_115200 },
4252 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 pbn_b0_bt_8_115200 },
4255
4256 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_b0_bt_2_115200 },
4259 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_b0_bt_2_115200 },
4262 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_b0_bt_2_115200 },
4265 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_b0_bt_2_115200 },
4268 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_b0_bt_2_115200 },
4271 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_b0_bt_4_460800 },
4274 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_b0_bt_4_460800 },
4277 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_b0_bt_2_460800 },
4280 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_b0_bt_2_460800 },
4283 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_b0_bt_2_460800 },
4286 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_b0_bt_1_115200 },
4289 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_b0_bt_1_460800 },
4292
4293 /*
4294 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4295 * Cards are identified by their subsystem vendor IDs, which
4296 * (in hex) match the model number.
4297 *
4298 * Note that JC140x are RS422/485 cards which require ox950
4299 * ACR = 0x10, and as such are not currently fully supported.
4300 */
4301 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4302 0x1204, 0x0004, 0, 0,
4303 pbn_b0_4_921600 },
4304 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4305 0x1208, 0x0004, 0, 0,
4306 pbn_b0_4_921600 },
4307 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4308 0x1402, 0x0002, 0, 0,
4309 pbn_b0_2_921600 }, */
4310 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4311 0x1404, 0x0004, 0, 0,
4312 pbn_b0_4_921600 }, */
4313 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4314 0x1208, 0x0004, 0, 0,
4315 pbn_b0_4_921600 },
4316
4317 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4318 0x1204, 0x0004, 0, 0,
4319 pbn_b0_4_921600 },
4320 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4321 0x1208, 0x0004, 0, 0,
4322 pbn_b0_4_921600 },
4323 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4324 0x1208, 0x0004, 0, 0,
4325 pbn_b0_4_921600 },
4326 /*
4327 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4328 */
4329 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 pbn_b1_1_1382400 },
4332
4333 /*
4334 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4335 */
4336 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 pbn_b1_1_1382400 },
4339
4340 /*
4341 * RAStel 2 port modem, gerg@moreton.com.au
4342 */
4343 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b2_bt_2_115200 },
4346
4347 /*
4348 * EKF addition for i960 Boards form EKF with serial port
4349 */
4350 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4351 0xE4BF, PCI_ANY_ID, 0, 0,
4352 pbn_intel_i960 },
4353
4354 /*
4355 * Xircom Cardbus/Ethernet combos
4356 */
4357 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359 pbn_b0_1_115200 },
4360 /*
4361 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4362 */
4363 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365 pbn_b0_1_115200 },
4366
4367 /*
4368 * Untested PCI modems, sent in from various folks...
4369 */
4370
4371 /*
4372 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4373 */
4374 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4375 0x1048, 0x1500, 0, 0,
4376 pbn_b1_1_115200 },
4377
4378 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4379 0xFF00, 0, 0, 0,
4380 pbn_sgi_ioc3 },
4381
4382 /*
4383 * HP Diva card
4384 */
4385 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4386 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4387 pbn_b1_1_115200 },
4388 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390 pbn_b0_5_115200 },
4391 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393 pbn_b2_1_115200 },
4394
4395 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 pbn_b3_2_115200 },
4398 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_b3_4_115200 },
4401 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_b3_8_115200 },
4404
4405 /*
4406 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4407 */
4408 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4409 PCI_ANY_ID, PCI_ANY_ID,
4410 0,
4411 0, pbn_exar_XR17C152 },
4412 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4413 PCI_ANY_ID, PCI_ANY_ID,
4414 0,
4415 0, pbn_exar_XR17C154 },
4416 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4417 PCI_ANY_ID, PCI_ANY_ID,
4418 0,
4419 0, pbn_exar_XR17C158 },
4420 /*
4421 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4422 */
4423 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4424 PCI_ANY_ID, PCI_ANY_ID,
4425 0,
4426 0, pbn_exar_XR17V352 },
4427 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4428 PCI_ANY_ID, PCI_ANY_ID,
4429 0,
4430 0, pbn_exar_XR17V354 },
4431 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4432 PCI_ANY_ID, PCI_ANY_ID,
4433 0,
4434 0, pbn_exar_XR17V358 },
4435
4436 /*
4437 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4438 */
4439 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_b0_1_115200 },
4442 /*
4443 * ITE
4444 */
4445 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4446 PCI_ANY_ID, PCI_ANY_ID,
4447 0, 0,
4448 pbn_b1_bt_1_115200 },
4449
4450 /*
4451 * IntaShield IS-200
4452 */
4453 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4455 pbn_b2_2_115200 },
4456 /*
4457 * IntaShield IS-400
4458 */
4459 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4461 pbn_b2_4_115200 },
4462 /*
4463 * Perle PCI-RAS cards
4464 */
4465 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4466 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4467 0, 0, pbn_b2_4_921600 },
4468 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4469 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4470 0, 0, pbn_b2_8_921600 },
4471
4472 /*
4473 * Mainpine series cards: Fairly standard layout but fools
4474 * parts of the autodetect in some cases and uses otherwise
4475 * unmatched communications subclasses in the PCI Express case
4476 */
4477
4478 { /* RockForceDUO */
4479 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4480 PCI_VENDOR_ID_MAINPINE, 0x0200,
4481 0, 0, pbn_b0_2_115200 },
4482 { /* RockForceQUATRO */
4483 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4484 PCI_VENDOR_ID_MAINPINE, 0x0300,
4485 0, 0, pbn_b0_4_115200 },
4486 { /* RockForceDUO+ */
4487 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4488 PCI_VENDOR_ID_MAINPINE, 0x0400,
4489 0, 0, pbn_b0_2_115200 },
4490 { /* RockForceQUATRO+ */
4491 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4492 PCI_VENDOR_ID_MAINPINE, 0x0500,
4493 0, 0, pbn_b0_4_115200 },
4494 { /* RockForce+ */
4495 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4496 PCI_VENDOR_ID_MAINPINE, 0x0600,
4497 0, 0, pbn_b0_2_115200 },
4498 { /* RockForce+ */
4499 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4500 PCI_VENDOR_ID_MAINPINE, 0x0700,
4501 0, 0, pbn_b0_4_115200 },
4502 { /* RockForceOCTO+ */
4503 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4504 PCI_VENDOR_ID_MAINPINE, 0x0800,
4505 0, 0, pbn_b0_8_115200 },
4506 { /* RockForceDUO+ */
4507 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4508 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4509 0, 0, pbn_b0_2_115200 },
4510 { /* RockForceQUARTRO+ */
4511 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4512 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4513 0, 0, pbn_b0_4_115200 },
4514 { /* RockForceOCTO+ */
4515 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4516 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4517 0, 0, pbn_b0_8_115200 },
4518 { /* RockForceD1 */
4519 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4520 PCI_VENDOR_ID_MAINPINE, 0x2000,
4521 0, 0, pbn_b0_1_115200 },
4522 { /* RockForceF1 */
4523 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4524 PCI_VENDOR_ID_MAINPINE, 0x2100,
4525 0, 0, pbn_b0_1_115200 },
4526 { /* RockForceD2 */
4527 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4528 PCI_VENDOR_ID_MAINPINE, 0x2200,
4529 0, 0, pbn_b0_2_115200 },
4530 { /* RockForceF2 */
4531 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4532 PCI_VENDOR_ID_MAINPINE, 0x2300,
4533 0, 0, pbn_b0_2_115200 },
4534 { /* RockForceD4 */
4535 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4536 PCI_VENDOR_ID_MAINPINE, 0x2400,
4537 0, 0, pbn_b0_4_115200 },
4538 { /* RockForceF4 */
4539 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4540 PCI_VENDOR_ID_MAINPINE, 0x2500,
4541 0, 0, pbn_b0_4_115200 },
4542 { /* RockForceD8 */
4543 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4544 PCI_VENDOR_ID_MAINPINE, 0x2600,
4545 0, 0, pbn_b0_8_115200 },
4546 { /* RockForceF8 */
4547 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4548 PCI_VENDOR_ID_MAINPINE, 0x2700,
4549 0, 0, pbn_b0_8_115200 },
4550 { /* IQ Express D1 */
4551 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4552 PCI_VENDOR_ID_MAINPINE, 0x3000,
4553 0, 0, pbn_b0_1_115200 },
4554 { /* IQ Express F1 */
4555 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4556 PCI_VENDOR_ID_MAINPINE, 0x3100,
4557 0, 0, pbn_b0_1_115200 },
4558 { /* IQ Express D2 */
4559 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4560 PCI_VENDOR_ID_MAINPINE, 0x3200,
4561 0, 0, pbn_b0_2_115200 },
4562 { /* IQ Express F2 */
4563 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4564 PCI_VENDOR_ID_MAINPINE, 0x3300,
4565 0, 0, pbn_b0_2_115200 },
4566 { /* IQ Express D4 */
4567 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4568 PCI_VENDOR_ID_MAINPINE, 0x3400,
4569 0, 0, pbn_b0_4_115200 },
4570 { /* IQ Express F4 */
4571 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4572 PCI_VENDOR_ID_MAINPINE, 0x3500,
4573 0, 0, pbn_b0_4_115200 },
4574 { /* IQ Express D8 */
4575 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4576 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4577 0, 0, pbn_b0_8_115200 },
4578 { /* IQ Express F8 */
4579 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4580 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4581 0, 0, pbn_b0_8_115200 },
4582
4583
4584 /*
4585 * PA Semi PA6T-1682M on-chip UART
4586 */
4587 { PCI_VENDOR_ID_PASEMI, 0xa004,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_pasemi_1682M },
4590
4591 /*
4592 * National Instruments
4593 */
4594 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b1_16_115200 },
4597 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b1_8_115200 },
4600 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b1_bt_4_115200 },
4603 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b1_bt_2_115200 },
4606 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b1_bt_4_115200 },
4609 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b1_bt_2_115200 },
4612 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b1_16_115200 },
4615 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b1_8_115200 },
4618 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b1_bt_4_115200 },
4621 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b1_bt_2_115200 },
4624 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b1_bt_4_115200 },
4627 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b1_bt_2_115200 },
4630 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_ni8430_2 },
4633 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_ni8430_2 },
4636 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_ni8430_4 },
4639 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_ni8430_4 },
4642 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_ni8430_8 },
4645 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_ni8430_8 },
4648 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_ni8430_16 },
4651 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_ni8430_16 },
4654 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_ni8430_2 },
4657 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_ni8430_2 },
4660 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_ni8430_4 },
4663 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_ni8430_4 },
4666
4667 /*
4668 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4669 */
4670 { PCI_VENDOR_ID_ADDIDATA,
4671 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4672 PCI_ANY_ID,
4673 PCI_ANY_ID,
4674 0,
4675 0,
4676 pbn_b0_4_115200 },
4677
4678 { PCI_VENDOR_ID_ADDIDATA,
4679 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4680 PCI_ANY_ID,
4681 PCI_ANY_ID,
4682 0,
4683 0,
4684 pbn_b0_2_115200 },
4685
4686 { PCI_VENDOR_ID_ADDIDATA,
4687 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4688 PCI_ANY_ID,
4689 PCI_ANY_ID,
4690 0,
4691 0,
4692 pbn_b0_1_115200 },
4693
4694 { PCI_VENDOR_ID_ADDIDATA_OLD,
4695 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4696 PCI_ANY_ID,
4697 PCI_ANY_ID,
4698 0,
4699 0,
4700 pbn_b1_8_115200 },
4701
4702 { PCI_VENDOR_ID_ADDIDATA,
4703 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4704 PCI_ANY_ID,
4705 PCI_ANY_ID,
4706 0,
4707 0,
4708 pbn_b0_4_115200 },
4709
4710 { PCI_VENDOR_ID_ADDIDATA,
4711 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4712 PCI_ANY_ID,
4713 PCI_ANY_ID,
4714 0,
4715 0,
4716 pbn_b0_2_115200 },
4717
4718 { PCI_VENDOR_ID_ADDIDATA,
4719 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4720 PCI_ANY_ID,
4721 PCI_ANY_ID,
4722 0,
4723 0,
4724 pbn_b0_1_115200 },
4725
4726 { PCI_VENDOR_ID_ADDIDATA,
4727 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4728 PCI_ANY_ID,
4729 PCI_ANY_ID,
4730 0,
4731 0,
4732 pbn_b0_4_115200 },
4733
4734 { PCI_VENDOR_ID_ADDIDATA,
4735 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4736 PCI_ANY_ID,
4737 PCI_ANY_ID,
4738 0,
4739 0,
4740 pbn_b0_2_115200 },
4741
4742 { PCI_VENDOR_ID_ADDIDATA,
4743 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4744 PCI_ANY_ID,
4745 PCI_ANY_ID,
4746 0,
4747 0,
4748 pbn_b0_1_115200 },
4749
4750 { PCI_VENDOR_ID_ADDIDATA,
4751 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4752 PCI_ANY_ID,
4753 PCI_ANY_ID,
4754 0,
4755 0,
4756 pbn_b0_8_115200 },
4757
4758 { PCI_VENDOR_ID_ADDIDATA,
4759 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4760 PCI_ANY_ID,
4761 PCI_ANY_ID,
4762 0,
4763 0,
4764 pbn_ADDIDATA_PCIe_4_3906250 },
4765
4766 { PCI_VENDOR_ID_ADDIDATA,
4767 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4768 PCI_ANY_ID,
4769 PCI_ANY_ID,
4770 0,
4771 0,
4772 pbn_ADDIDATA_PCIe_2_3906250 },
4773
4774 { PCI_VENDOR_ID_ADDIDATA,
4775 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4776 PCI_ANY_ID,
4777 PCI_ANY_ID,
4778 0,
4779 0,
4780 pbn_ADDIDATA_PCIe_1_3906250 },
4781
4782 { PCI_VENDOR_ID_ADDIDATA,
4783 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4784 PCI_ANY_ID,
4785 PCI_ANY_ID,
4786 0,
4787 0,
4788 pbn_ADDIDATA_PCIe_8_3906250 },
4789
4790 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4791 PCI_VENDOR_ID_IBM, 0x0299,
4792 0, 0, pbn_b0_bt_2_115200 },
4793
4794 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4795 0xA000, 0x1000,
4796 0, 0, pbn_b0_1_115200 },
4797
4798 /* the 9901 is a rebranded 9912 */
4799 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4800 0xA000, 0x1000,
4801 0, 0, pbn_b0_1_115200 },
4802
4803 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4804 0xA000, 0x1000,
4805 0, 0, pbn_b0_1_115200 },
4806
4807 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4808 0xA000, 0x1000,
4809 0, 0, pbn_b0_1_115200 },
4810
4811 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4812 0xA000, 0x1000,
4813 0, 0, pbn_b0_1_115200 },
4814
4815 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4816 0xA000, 0x3002,
4817 0, 0, pbn_NETMOS9900_2s_115200 },
4818
4819 /*
4820 * Best Connectivity and Rosewill PCI Multi I/O cards
4821 */
4822
4823 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4824 0xA000, 0x1000,
4825 0, 0, pbn_b0_1_115200 },
4826
4827 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4828 0xA000, 0x3002,
4829 0, 0, pbn_b0_bt_2_115200 },
4830
4831 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4832 0xA000, 0x3004,
4833 0, 0, pbn_b0_bt_4_115200 },
4834 /* Intel CE4100 */
4835 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4837 pbn_ce4100_1_115200 },
4838
4839 /*
4840 * Cronyx Omega PCI
4841 */
4842 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844 pbn_omegapci },
4845
4846 /*
4847 * Broadcom TruManage
4848 */
4849 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_brcm_trumanage },
4852
4853 /*
4854 * AgeStar as-prs2-009
4855 */
4856 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4857 PCI_ANY_ID, PCI_ANY_ID,
4858 0, 0, pbn_b0_bt_2_115200 },
4859
4860 /*
4861 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4862 * so not listed here.
4863 */
4864 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4865 PCI_ANY_ID, PCI_ANY_ID,
4866 0, 0, pbn_b0_bt_4_115200 },
4867
4868 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4869 PCI_ANY_ID, PCI_ANY_ID,
4870 0, 0, pbn_b0_bt_2_115200 },
4871
4872 /*
4873 * Commtech, Inc. Fastcom adapters
4874 */
4875 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4876 PCI_ANY_ID, PCI_ANY_ID,
4877 0,
4878 0, pbn_b0_2_1152000_200 },
4879 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4880 PCI_ANY_ID, PCI_ANY_ID,
4881 0,
4882 0, pbn_b0_4_1152000_200 },
4883 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4884 PCI_ANY_ID, PCI_ANY_ID,
4885 0,
4886 0, pbn_b0_4_1152000_200 },
4887 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4888 PCI_ANY_ID, PCI_ANY_ID,
4889 0,
4890 0, pbn_b0_8_1152000_200 },
4891 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4892 PCI_ANY_ID, PCI_ANY_ID,
4893 0,
4894 0, pbn_exar_XR17V352 },
4895 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4896 PCI_ANY_ID, PCI_ANY_ID,
4897 0,
4898 0, pbn_exar_XR17V354 },
4899 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4900 PCI_ANY_ID, PCI_ANY_ID,
4901 0,
4902 0, pbn_exar_XR17V358 },
4903
4904 /*
4905 * These entries match devices with class COMMUNICATION_SERIAL,
4906 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4907 */
4908 { PCI_ANY_ID, PCI_ANY_ID,
4909 PCI_ANY_ID, PCI_ANY_ID,
4910 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4911 0xffff00, pbn_default },
4912 { PCI_ANY_ID, PCI_ANY_ID,
4913 PCI_ANY_ID, PCI_ANY_ID,
4914 PCI_CLASS_COMMUNICATION_MODEM << 8,
4915 0xffff00, pbn_default },
4916 { PCI_ANY_ID, PCI_ANY_ID,
4917 PCI_ANY_ID, PCI_ANY_ID,
4918 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4919 0xffff00, pbn_default },
4920 { 0, }
4921 };
4922
4923 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4924 pci_channel_state_t state)
4925 {
4926 struct serial_private *priv = pci_get_drvdata(dev);
4927
4928 if (state == pci_channel_io_perm_failure)
4929 return PCI_ERS_RESULT_DISCONNECT;
4930
4931 if (priv)
4932 pciserial_suspend_ports(priv);
4933
4934 pci_disable_device(dev);
4935
4936 return PCI_ERS_RESULT_NEED_RESET;
4937 }
4938
4939 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4940 {
4941 int rc;
4942
4943 rc = pci_enable_device(dev);
4944
4945 if (rc)
4946 return PCI_ERS_RESULT_DISCONNECT;
4947
4948 pci_restore_state(dev);
4949 pci_save_state(dev);
4950
4951 return PCI_ERS_RESULT_RECOVERED;
4952 }
4953
4954 static void serial8250_io_resume(struct pci_dev *dev)
4955 {
4956 struct serial_private *priv = pci_get_drvdata(dev);
4957
4958 if (priv)
4959 pciserial_resume_ports(priv);
4960 }
4961
4962 static const struct pci_error_handlers serial8250_err_handler = {
4963 .error_detected = serial8250_io_error_detected,
4964 .slot_reset = serial8250_io_slot_reset,
4965 .resume = serial8250_io_resume,
4966 };
4967
4968 static struct pci_driver serial_pci_driver = {
4969 .name = "serial",
4970 .probe = pciserial_init_one,
4971 .remove = pciserial_remove_one,
4972 #ifdef CONFIG_PM
4973 .suspend = pciserial_suspend_one,
4974 .resume = pciserial_resume_one,
4975 #endif
4976 .id_table = serial_pci_tbl,
4977 .err_handler = &serial8250_err_handler,
4978 };
4979
4980 module_pci_driver(serial_pci_driver);
4981
4982 MODULE_LICENSE("GPL");
4983 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4984 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
kernel source for telekom puls (alcatel/mediatek)