drivers/tty/serial/8250/8250_dw.c

   1 /*
   2  * Synopsys DesignWare 8250 driver.
   3  *
   4  * Copyright 2011 Picochip, Jamie Iles.
   5  * Copyright 2013 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  14  * raised, the LCR needs to be rewritten and the uart status register read.
  15  */
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/acpi.h>
  29 #include <linux/clk.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "8250.h"
  33
  34 /* Offsets for the DesignWare specific registers */
  35 #define DW_UART_USR     0x1f /* UART Status Register */
  36 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
  37 #define DW_UART_UCV     0xf8 /* UART Component Version */
  38
  39 /* Component Parameter Register bits */
  40 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
  41 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
  42 #define DW_UART_CPR_THRE_MODE           (1 << 5)
  43 #define DW_UART_CPR_SIR_MODE            (1 << 6)
  44 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
  45 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
  46 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
  47 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
  48 #define DW_UART_CPR_SHADOW              (1 << 11)
  49 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
  50 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
  51 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
  52 /* Helper for fifo size calculation */
  53 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
  54
  55
  56 struct dw8250_data {
  57         int             last_mcr;
  58         int             line;
  59         struct clk      *clk;
  60 };
  61
  62 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
  63 {
  64         struct dw8250_data *d = p->private_data;
  65
  66         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
  67         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
  68                 value |= UART_MSR_CTS;
  69                 value &= ~UART_MSR_DCTS;
  70         }
  71
  72         return value;
  73 }
  74
  75 static void dw8250_force_idle(struct uart_port *p)
  76 {
  77         serial8250_clear_and_reinit_fifos(container_of
  78                                           (p, struct uart_8250_port, port));
  79         (void)p->serial_in(p, UART_RX);
  80 }
  81
  82 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
  83 {
  84         struct dw8250_data *d = p->private_data;
  85
  86         if (offset == UART_MCR)
  87                 d->last_mcr = value;
  88
  89         writeb(value, p->membase + (offset << p->regshift));
  90
  91         /* Make sure LCR write wasn't ignored */
  92         if (offset == UART_LCR) {
  93                 int tries = 1000;
  94                 while (tries--) {
  95                         unsigned int lcr = p->serial_in(p, UART_LCR);
  96                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
  97                                 return;
  98                         dw8250_force_idle(p);
  99                         writeb(value, p->membase + (UART_LCR << p->regshift));
 100                 }
 101                 /*
 102                  * FIXME: this deadlocks if port->lock is already held
 103                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 104                  */
 105         }
 106 }
 107
 108 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
 109 {
 110         unsigned int value = readb(p->membase + (offset << p->regshift));
 111
 112         return dw8250_modify_msr(p, offset, value);
 113 }
 114
 115 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 116 {
 117         struct dw8250_data *d = p->private_data;
 118
 119         if (offset == UART_LCR)
 120                 d->last_lcr = value;
 121
 122         writel(value, p->membase + (offset << p->regshift));
 123
 124         /* Make sure LCR write wasn't ignored */
 125         if (offset == UART_LCR) {
 126                 int tries = 1000;
 127                 while (tries--) {
 128                         unsigned int lcr = p->serial_in(p, UART_LCR);
 129                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 130                                 return;
 131                         dw8250_force_idle(p);
 132                         writel(value, p->membase + (UART_LCR << p->regshift));
 133                 }
 134                 /*
 135                  * FIXME: this deadlocks if port->lock is already held
 136                  * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 137                  */
 138         }
 139 }
 140
 141 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
 142 {
 143         offset <<= p->regshift;
 144
 145         return readl(p->membase + offset);
 146 }
 147
 148 static int dw8250_handle_irq(struct uart_port *p)
 149 {
 150         struct dw8250_data *d = p->private_data;
 151         unsigned int iir = p->serial_in(p, UART_IIR);
 152
 153         if (serial8250_handle_irq(p, iir)) {
 154                 return 1;
 155         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 156                 /* Clear the USR and write the LCR again. */
 157                 (void)p->serial_in(p, DW_UART_USR);
 158                 p->serial_out(p, UART_LCR, d->last_lcr);
 159
 160                 return 1;
 161         }
 162
 163         return 0;
 164 }
 165
 166 static void
 167 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 168 {
 169         if (!state)
 170                 pm_runtime_get_sync(port->dev);
 171
 172         serial8250_do_pm(port, state, old);
 173
 174         if (state)
 175                 pm_runtime_put_sync_suspend(port->dev);
 176 }
 177
 178 static int dw8250_probe_of(struct uart_port *p)
 179 {
 180         struct device_node      *np = p->dev->of_node;
 181         u32                     val;
 182
 183         if (!of_property_read_u32(np, "reg-io-width", &val)) {
 184                 switch (val) {
 185                 case 1:
 186                         break;
 187                 case 4:
 188                         p->iotype = UPIO_MEM32;
 189                         p->serial_in = dw8250_serial_in32;
 190                         p->serial_out = dw8250_serial_out32;
 191                         break;
 192                 default:
 193                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
 194                         return -EINVAL;
 195                 }
 196         }
 197
 198         if (!of_property_read_u32(np, "reg-shift", &val))
 199                 p->regshift = val;
 200
 201         /* clock got configured through clk api, all done */
 202         if (p->uartclk)
 203                 return 0;
 204
 205         /* try to find out clock frequency from DT as fallback */
 206         if (of_property_read_u32(np, "clock-frequency", &val)) {
 207                 dev_err(p->dev, "clk or clock-frequency not defined\n");
 208                 return -EINVAL;
 209         }
 210         p->uartclk = val;
 211
 212         return 0;
 213 }
 214
 215 #ifdef CONFIG_ACPI
 216 static int dw8250_probe_acpi(struct uart_8250_port *up)
 217 {
 218         const struct acpi_device_id *id;
 219         struct uart_port *p = &up->port;
 220
 221         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
 222         if (!id)
 223                 return -ENODEV;
 224
 225         p->iotype = UPIO_MEM32;
 226         p->serial_in = dw8250_serial_in32;
 227         p->serial_out = dw8250_serial_out32;
 228         p->regshift = 2;
 229
 230         if (!p->uartclk)
 231                 p->uartclk = (unsigned int)id->driver_data;
 232
 233         up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
 234         if (!up->dma)
 235                 return -ENOMEM;
 236
 237         up->dma->rxconf.src_maxburst = p->fifosize / 4;
 238         up->dma->txconf.dst_maxburst = p->fifosize / 4;
 239
 240         return 0;
 241 }
 242 #else
 243 static inline int dw8250_probe_acpi(struct uart_8250_port *up)
 244 {
 245         return -ENODEV;
 246 }
 247 #endif /* CONFIG_ACPI */
 248
 249 static void dw8250_setup_port(struct uart_8250_port *up)
 250 {
 251         struct uart_port        *p = &up->port;
 252         u32                     reg = readl(p->membase + DW_UART_UCV);
 253
 254         /*
 255          * If the Component Version Register returns zero, we know that
 256          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 257          */
 258         if (!reg)
 259                 return;
 260
 261         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
 262                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 263
 264         reg = readl(p->membase + DW_UART_CPR);
 265         if (!reg)
 266                 return;
 267
 268         /* Select the type based on fifo */
 269         if (reg & DW_UART_CPR_FIFO_MODE) {
 270                 p->type = PORT_16550A;
 271                 p->flags |= UPF_FIXED_TYPE;
 272                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
 273                 up->tx_loadsz = p->fifosize;
 274                 up->capabilities = UART_CAP_FIFO;
 275         }
 276
 277         if (reg & DW_UART_CPR_AFCE_MODE)
 278                 up->capabilities |= UART_CAP_AFE;
 279 }
 280
 281 static int dw8250_probe(struct platform_device *pdev)
 282 {
 283         struct uart_8250_port uart = {};
 284         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 285         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 286         struct dw8250_data *data;
 287         int err;
 288
 289         if (!regs || !irq) {
 290                 dev_err(&pdev->dev, "no registers/irq defined\n");
 291                 return -EINVAL;
 292         }
 293
 294         spin_lock_init(&uart.port.lock);
 295         uart.port.mapbase = regs->start;
 296         uart.port.irq = irq->start;
 297         uart.port.handle_irq = dw8250_handle_irq;
 298         uart.port.pm = dw8250_do_pm;
 299         uart.port.type = PORT_8250;
 300         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
 301         uart.port.dev = &pdev->dev;
 302
 303         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 304                                          resource_size(regs));
 305         if (!uart.port.membase)
 306                 return -ENOMEM;
 307
 308         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 309         if (!data)
 310                 return -ENOMEM;
 311
 312         data->clk = devm_clk_get(&pdev->dev, NULL);
 313         if (!IS_ERR(data->clk)) {
 314                 clk_prepare_enable(data->clk);
 315                 uart.port.uartclk = clk_get_rate(data->clk);
 316         }
 317
 318         uart.port.iotype = UPIO_MEM;
 319         uart.port.serial_in = dw8250_serial_in;
 320         uart.port.serial_out = dw8250_serial_out;
 321         uart.port.private_data = data;
 322
 323         dw8250_setup_port(&uart);
 324
 325         if (pdev->dev.of_node) {
 326                 err = dw8250_probe_of(&uart.port);
 327                 if (err)
 328                         return err;
 329         } else if (ACPI_HANDLE(&pdev->dev)) {
 330                 err = dw8250_probe_acpi(&uart);
 331                 if (err)
 332                         return err;
 333         } else {
 334                 return -ENODEV;
 335         }
 336
 337         data->line = serial8250_register_8250_port(&uart);
 338         if (data->line < 0)
 339                 return data->line;
 340
 341         platform_set_drvdata(pdev, data);
 342
 343         pm_runtime_set_active(&pdev->dev);
 344         pm_runtime_enable(&pdev->dev);
 345
 346         return 0;
 347 }
 348
 349 static int dw8250_remove(struct platform_device *pdev)
 350 {
 351         struct dw8250_data *data = platform_get_drvdata(pdev);
 352
 353         pm_runtime_get_sync(&pdev->dev);
 354
 355         serial8250_unregister_port(data->line);
 356
 357         if (!IS_ERR(data->clk))
 358                 clk_disable_unprepare(data->clk);
 359
 360         pm_runtime_disable(&pdev->dev);
 361         pm_runtime_put_noidle(&pdev->dev);
 362
 363         return 0;
 364 }
 365
 366 #ifdef CONFIG_PM
 367 static int dw8250_suspend(struct device *dev)
 368 {
 369         struct dw8250_data *data = dev_get_drvdata(dev);
 370
 371         serial8250_suspend_port(data->line);
 372
 373         return 0;
 374 }
 375
 376 static int dw8250_resume(struct device *dev)
 377 {
 378         struct dw8250_data *data = dev_get_drvdata(dev);
 379
 380         serial8250_resume_port(data->line);
 381
 382         return 0;
 383 }
 384 #endif /* CONFIG_PM */
 385
 386 #ifdef CONFIG_PM_RUNTIME
 387 static int dw8250_runtime_suspend(struct device *dev)
 388 {
 389         struct dw8250_data *data = dev_get_drvdata(dev);
 390
 391         if (!IS_ERR(data->clk))
 392                 clk_disable_unprepare(data->clk);
 393
 394         return 0;
 395 }
 396
 397 static int dw8250_runtime_resume(struct device *dev)
 398 {
 399         struct dw8250_data *data = dev_get_drvdata(dev);
 400
 401         if (!IS_ERR(data->clk))
 402                 clk_prepare_enable(data->clk);
 403
 404         return 0;
 405 }
 406 #endif
 407
 408 static const struct dev_pm_ops dw8250_pm_ops = {
 409         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 410         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 411 };
 412
 413 static const struct of_device_id dw8250_of_match[] = {
 414         { .compatible = "snps,dw-apb-uart" },
 415         { /* Sentinel */ }
 416 };
 417 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 418
 419 static const struct acpi_device_id dw8250_acpi_match[] = {
 420         { "INT33C4", 0 },
 421         { "INT33C5", 0 },
 422         { "INT3434", 0 },
 423         { "INT3435", 0 },
 424         { "80860F0A", 0 },
 425         { },
 426 };
 427 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 428
 429 static struct platform_driver dw8250_platform_driver = {
 430         .driver = {
 431                 .name           = "dw-apb-uart",
 432                 .owner          = THIS_MODULE,
 433                 .pm             = &dw8250_pm_ops,
 434                 .of_match_table = dw8250_of_match,
 435                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 436         },
 437         .probe                  = dw8250_probe,
 438         .remove                 = dw8250_remove,
 439 };
 440
 441 module_platform_driver(dw8250_platform_driver);
 442
 443 MODULE_AUTHOR("Jamie Iles");
 444 MODULE_LICENSE("GPL");
 445 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");