drivers/tty/serial/8250/8250_dw.c

   1 /*
   2  * Synopsys DesignWare 8250 driver.
   3  *
   4  * Copyright 2011 Picochip, Jamie Iles.
   5  * Copyright 2013 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  14  * raised, the LCR needs to be rewritten and the uart status register read.
  15  */
  16 #include <linux/device.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/serial_8250.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/of.h>
  24 #include <linux/of_irq.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/acpi.h>
  29 #include <linux/clk.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include "8250.h"
  33
  34 /* Offsets for the DesignWare specific registers */
  35 #define DW_UART_USR     0x1f /* UART Status Register */
  36 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
  37 #define DW_UART_UCV     0xf8 /* UART Component Version */
  38
  39 /* Component Parameter Register bits */
  40 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
  41 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
  42 #define DW_UART_CPR_THRE_MODE           (1 << 5)
  43 #define DW_UART_CPR_SIR_MODE            (1 << 6)
  44 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
  45 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
  46 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
  47 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
  48 #define DW_UART_CPR_SHADOW              (1 << 11)
  49 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
  50 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
  51 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
  52 /* Helper for fifo size calculation */
  53 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
  54
  55
  56 struct dw8250_data {
  57         int             last_mcr;
  58         int             line;
  59         struct clk      *clk;
  60 };
  61
  62 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
  63 {
  64         struct dw8250_data *d = p->private_data;
  65
  66         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
  67         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
  68                 value |= UART_MSR_CTS;
  69                 value &= ~UART_MSR_DCTS;
  70         }
  71
  72         return value;
  73 }
  74
  75 static void dw8250_force_idle(struct uart_port *p)
  76 {
  77         serial8250_clear_and_reinit_fifos(container_of
  78                                           (p, struct uart_8250_port, port));
  79         (void)p->serial_in(p, UART_RX);
  80 }
  81
  82 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
  83 {
  84         struct dw8250_data *d = p->private_data;
  85
  86         if (offset == UART_MCR)
  87                 d->last_mcr = value;
  88
  89         writeb(value, p->membase + (offset << p->regshift));
  90
  91         /* Make sure LCR write wasn't ignored */
  92         if (offset == UART_LCR) {
  93                 int tries = 1000;
  94                 while (tries--) {
  95                         unsigned int lcr = p->serial_in(p, UART_LCR);
  96                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
  97                                 return;
  98                         dw8250_force_idle(p);
  99                         writeb(value, p->membase + (UART_LCR << p->regshift));
 100                 }
 101                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 102         }
 103 }
 104
 105 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
 106 {
 107         unsigned int value = readb(p->membase + (offset << p->regshift));
 108
 109         return dw8250_modify_msr(p, offset, value);
 110 }
 111
 112 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 113 {
 114         struct dw8250_data *d = p->private_data;
 115
 116         if (offset == UART_LCR)
 117                 d->last_lcr = value;
 118
 119         offset <<= p->regshift;
 120         writel(value, p->membase + offset);
 121 }
 122
 123 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
 124 {
 125         offset <<= p->regshift;
 126
 127         return readl(p->membase + offset);
 128 }
 129
 130 static int dw8250_handle_irq(struct uart_port *p)
 131 {
 132         struct dw8250_data *d = p->private_data;
 133         unsigned int iir = p->serial_in(p, UART_IIR);
 134
 135         if (serial8250_handle_irq(p, iir)) {
 136                 return 1;
 137         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 138                 /* Clear the USR and write the LCR again. */
 139                 (void)p->serial_in(p, DW_UART_USR);
 140                 p->serial_out(p, UART_LCR, d->last_lcr);
 141
 142                 return 1;
 143         }
 144
 145         return 0;
 146 }
 147
 148 static void
 149 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 150 {
 151         if (!state)
 152                 pm_runtime_get_sync(port->dev);
 153
 154         serial8250_do_pm(port, state, old);
 155
 156         if (state)
 157                 pm_runtime_put_sync_suspend(port->dev);
 158 }
 159
 160 static int dw8250_probe_of(struct uart_port *p)
 161 {
 162         struct device_node      *np = p->dev->of_node;
 163         u32                     val;
 164
 165         if (!of_property_read_u32(np, "reg-io-width", &val)) {
 166                 switch (val) {
 167                 case 1:
 168                         break;
 169                 case 4:
 170                         p->iotype = UPIO_MEM32;
 171                         p->serial_in = dw8250_serial_in32;
 172                         p->serial_out = dw8250_serial_out32;
 173                         break;
 174                 default:
 175                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
 176                         return -EINVAL;
 177                 }
 178         }
 179
 180         if (!of_property_read_u32(np, "reg-shift", &val))
 181                 p->regshift = val;
 182
 183         /* clock got configured through clk api, all done */
 184         if (p->uartclk)
 185                 return 0;
 186
 187         /* try to find out clock frequency from DT as fallback */
 188         if (of_property_read_u32(np, "clock-frequency", &val)) {
 189                 dev_err(p->dev, "clk or clock-frequency not defined\n");
 190                 return -EINVAL;
 191         }
 192         p->uartclk = val;
 193
 194         return 0;
 195 }
 196
 197 #ifdef CONFIG_ACPI
 198 static int dw8250_probe_acpi(struct uart_8250_port *up)
 199 {
 200         const struct acpi_device_id *id;
 201         struct uart_port *p = &up->port;
 202
 203         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
 204         if (!id)
 205                 return -ENODEV;
 206
 207         p->iotype = UPIO_MEM32;
 208         p->serial_in = dw8250_serial_in32;
 209         p->serial_out = dw8250_serial_out32;
 210         p->regshift = 2;
 211
 212         if (!p->uartclk)
 213                 p->uartclk = (unsigned int)id->driver_data;
 214
 215         up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
 216         if (!up->dma)
 217                 return -ENOMEM;
 218
 219         up->dma->rxconf.src_maxburst = p->fifosize / 4;
 220         up->dma->txconf.dst_maxburst = p->fifosize / 4;
 221
 222         return 0;
 223 }
 224 #else
 225 static inline int dw8250_probe_acpi(struct uart_8250_port *up)
 226 {
 227         return -ENODEV;
 228 }
 229 #endif /* CONFIG_ACPI */
 230
 231 static void dw8250_setup_port(struct uart_8250_port *up)
 232 {
 233         struct uart_port        *p = &up->port;
 234         u32                     reg = readl(p->membase + DW_UART_UCV);
 235
 236         /*
 237          * If the Component Version Register returns zero, we know that
 238          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 239          */
 240         if (!reg)
 241                 return;
 242
 243         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
 244                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 245
 246         reg = readl(p->membase + DW_UART_CPR);
 247         if (!reg)
 248                 return;
 249
 250         /* Select the type based on fifo */
 251         if (reg & DW_UART_CPR_FIFO_MODE) {
 252                 p->type = PORT_16550A;
 253                 p->flags |= UPF_FIXED_TYPE;
 254                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
 255                 up->tx_loadsz = p->fifosize;
 256                 up->capabilities = UART_CAP_FIFO;
 257         }
 258
 259         if (reg & DW_UART_CPR_AFCE_MODE)
 260                 up->capabilities |= UART_CAP_AFE;
 261 }
 262
 263 static int dw8250_probe(struct platform_device *pdev)
 264 {
 265         struct uart_8250_port uart = {};
 266         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 267         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 268         struct dw8250_data *data;
 269         int err;
 270
 271         if (!regs || !irq) {
 272                 dev_err(&pdev->dev, "no registers/irq defined\n");
 273                 return -EINVAL;
 274         }
 275
 276         spin_lock_init(&uart.port.lock);
 277         uart.port.mapbase = regs->start;
 278         uart.port.irq = irq->start;
 279         uart.port.handle_irq = dw8250_handle_irq;
 280         uart.port.pm = dw8250_do_pm;
 281         uart.port.type = PORT_8250;
 282         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
 283         uart.port.dev = &pdev->dev;
 284
 285         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 286                                          resource_size(regs));
 287         if (!uart.port.membase)
 288                 return -ENOMEM;
 289
 290         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 291         if (!data)
 292                 return -ENOMEM;
 293
 294         data->clk = devm_clk_get(&pdev->dev, NULL);
 295         if (!IS_ERR(data->clk)) {
 296                 clk_prepare_enable(data->clk);
 297                 uart.port.uartclk = clk_get_rate(data->clk);
 298         }
 299
 300         uart.port.iotype = UPIO_MEM;
 301         uart.port.serial_in = dw8250_serial_in;
 302         uart.port.serial_out = dw8250_serial_out;
 303         uart.port.private_data = data;
 304
 305         dw8250_setup_port(&uart);
 306
 307         if (pdev->dev.of_node) {
 308                 err = dw8250_probe_of(&uart.port);
 309                 if (err)
 310                         return err;
 311         } else if (ACPI_HANDLE(&pdev->dev)) {
 312                 err = dw8250_probe_acpi(&uart);
 313                 if (err)
 314                         return err;
 315         } else {
 316                 return -ENODEV;
 317         }
 318
 319         data->line = serial8250_register_8250_port(&uart);
 320         if (data->line < 0)
 321                 return data->line;
 322
 323         platform_set_drvdata(pdev, data);
 324
 325         pm_runtime_set_active(&pdev->dev);
 326         pm_runtime_enable(&pdev->dev);
 327
 328         return 0;
 329 }
 330
 331 static int dw8250_remove(struct platform_device *pdev)
 332 {
 333         struct dw8250_data *data = platform_get_drvdata(pdev);
 334
 335         pm_runtime_get_sync(&pdev->dev);
 336
 337         serial8250_unregister_port(data->line);
 338
 339         if (!IS_ERR(data->clk))
 340                 clk_disable_unprepare(data->clk);
 341
 342         pm_runtime_disable(&pdev->dev);
 343         pm_runtime_put_noidle(&pdev->dev);
 344
 345         return 0;
 346 }
 347
 348 #ifdef CONFIG_PM
 349 static int dw8250_suspend(struct device *dev)
 350 {
 351         struct dw8250_data *data = dev_get_drvdata(dev);
 352
 353         serial8250_suspend_port(data->line);
 354
 355         return 0;
 356 }
 357
 358 static int dw8250_resume(struct device *dev)
 359 {
 360         struct dw8250_data *data = dev_get_drvdata(dev);
 361
 362         serial8250_resume_port(data->line);
 363
 364         return 0;
 365 }
 366 #endif /* CONFIG_PM */
 367
 368 #ifdef CONFIG_PM_RUNTIME
 369 static int dw8250_runtime_suspend(struct device *dev)
 370 {
 371         struct dw8250_data *data = dev_get_drvdata(dev);
 372
 373         if (!IS_ERR(data->clk))
 374                 clk_disable_unprepare(data->clk);
 375
 376         return 0;
 377 }
 378
 379 static int dw8250_runtime_resume(struct device *dev)
 380 {
 381         struct dw8250_data *data = dev_get_drvdata(dev);
 382
 383         if (!IS_ERR(data->clk))
 384                 clk_prepare_enable(data->clk);
 385
 386         return 0;
 387 }
 388 #endif
 389
 390 static const struct dev_pm_ops dw8250_pm_ops = {
 391         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 392         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 393 };
 394
 395 static const struct of_device_id dw8250_of_match[] = {
 396         { .compatible = "snps,dw-apb-uart" },
 397         { /* Sentinel */ }
 398 };
 399 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 400
 401 static const struct acpi_device_id dw8250_acpi_match[] = {
 402         { "INT33C4", 0 },
 403         { "INT33C5", 0 },
 404         { "INT3434", 0 },
 405         { "INT3435", 0 },
 406         { "80860F0A", 0 },
 407         { },
 408 };
 409 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 410
 411 static struct platform_driver dw8250_platform_driver = {
 412         .driver = {
 413                 .name           = "dw-apb-uart",
 414                 .owner          = THIS_MODULE,
 415                 .pm             = &dw8250_pm_ops,
 416                 .of_match_table = dw8250_of_match,
 417                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 418         },
 419         .probe                  = dw8250_probe,
 420         .remove                 = dw8250_remove,
 421 };
 422
 423 module_platform_driver(dw8250_platform_driver);
 424
 425 MODULE_AUTHOR("Jamie Iles");
 426 MODULE_LICENSE("GPL");
 427 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");