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Merge branch 'sched-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / wlags49_h2 / hcfdef.h
1
2 // vim:tw=110:ts=4:
3 #ifndef HCFDEFC_H
4 #define HCFDEFC_H 1
5
6 /*************************************************************************************************
7 *
8 * FILE : HCFDEF.H
9 *
10 * DATE : $Date: 2004/08/05 11:47:10 $ $Revision: 1.8 $
11 * Original: 2004/05/28 14:05:35 Revision: 1.59 Tag: hcf7_t20040602_01
12 * Original: 2004/05/13 15:31:45 Revision: 1.53 Tag: hcf7_t7_20040513_01
13 * Original: 2004/04/15 09:24:42 Revision: 1.44 Tag: hcf7_t7_20040415_01
14 * Original: 2004/04/13 14:22:45 Revision: 1.43 Tag: t7_20040413_01
15 * Original: 2004/04/01 15:32:55 Revision: 1.40 Tag: t7_20040401_01
16 * Original: 2004/03/10 15:39:28 Revision: 1.36 Tag: t20040310_01
17 * Original: 2004/03/03 14:10:12 Revision: 1.34 Tag: t20040304_01
18 * Original: 2004/03/02 09:27:12 Revision: 1.32 Tag: t20040302_03
19 * Original: 2004/02/24 13:00:29 Revision: 1.29 Tag: t20040224_01
20 * Original: 2004/02/18 17:13:57 Revision: 1.26 Tag: t20040219_01
21 *
22 * AUTHOR : Nico Valster
23 *
24 * SPECIFICATION: ...........
25 *
26 * DESC : Definitions and Prototypes for HCF only
27 *
28 **************************************************************************************************
29 *
30 *
31 * SOFTWARE LICENSE
32 *
33 * This software is provided subject to the following terms and conditions,
34 * which you should read carefully before using the software. Using this
35 * software indicates your acceptance of these terms and conditions. If you do
36 * not agree with these terms and conditions, do not use the software.
37 *
38 * COPYRIGHT © 1994 - 1995 by AT&T. All Rights Reserved
39 * COPYRIGHT © 1996 - 2000 by Lucent Technologies. All Rights Reserved
40 * COPYRIGHT © 2001 - 2004 by Agere Systems Inc. All Rights Reserved
41 * All rights reserved.
42 *
43 * Redistribution and use in source or binary forms, with or without
44 * modifications, are permitted provided that the following conditions are met:
45 *
46 * . Redistributions of source code must retain the above copyright notice, this
47 * list of conditions and the following Disclaimer as comments in the code as
48 * well as in the documentation and/or other materials provided with the
49 * distribution.
50 *
51 * . Redistributions in binary form must reproduce the above copyright notice,
52 * this list of conditions and the following Disclaimer in the documentation
53 * and/or other materials provided with the distribution.
54 *
55 * . Neither the name of Agere Systems Inc. nor the names of the contributors
56 * may be used to endorse or promote products derived from this software
57 * without specific prior written permission.
58 *
59 * Disclaimer
60 *
61 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
62 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
63 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
64 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
65 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
66 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
67 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
68 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
69 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
70 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
71 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
72 * DAMAGE.
73 *
74 *
75 *************************************************************************************************/
76
77
78 /************************************************************************************************/
79 /********************************* P R E F I X E S ********************************************/
80 /************************************************************************************************/
81 //IFB_ Interface Block
82 //HCMD_ Hermes Command
83 //HFS_ Hermes (Transmit/Receive) Frame Structure
84 //HREG_ Hermes Register
85
86 /*************************************************************************************************/
87
88 #if 0 //
89 #define BIT0 0x0001
90 #define BIT1 0x0002
91 #define BIT2 0x0004
92 #define BIT3 0x0008
93 #define BIT4 0x0010
94 #define BIT5 0x0020
95 #define BIT6 0x0040
96 #define BIT7 0x0080
97 #define BIT8 0x0100
98 #define BIT9 0x0200
99 #define BIT10 0x0400
100 #define BIT11 0x0800
101 #define BIT12 0x1000
102 #define BIT13 0x2000
103 #define BIT14 0x4000
104 #define BIT15 0x8000
105 #define BIT16 0x00010000
106 #define BIT17 0x00020000
107 #define BIT18 0x00040000
108 #define BIT19 0x00080000
109 #define BIT20 0x00100000
110 #define BIT21 0x00200000
111 #define BIT22 0x00400000
112 #define BIT23 0x00800000
113 #define BIT24 0x01000000
114 #define BIT25 0x02000000
115 #define BIT26 0x04000000
116 #define BIT27 0x08000000
117 #define BIT28 0x10000000
118 #define BIT29 0x20000000
119 #define BIT30 0x40000000
120 #define BIT31 0x80000000
121 #endif // 0
122
123 /************************************************************************************************/
124 /********************************* GENERAL EQUATES **********************************************/
125 /************************************************************************************************/
126
127
128 #define HCF_MAGIC 0x7D37 // "}7" Handle validation
129
130 #define PLUG_DATA_OFFSET 0x00000800 //needed by some test tool on top of H-II NDIS driver
131
132 #define INI_TICK_INI 0x00040000L
133
134 #define IO_IN 0 //hcfio_in_string
135 #define IO_OUT 1 //hcfio_out_string
136
137 //DO_ASSERT, create an artificial FALSE to force an ASSERT without the nasty compiler warning
138 #define DO_ASSERT ( assert_ifbp->IFB_Magic != HCF_MAGIC && assert_ifbp->IFB_Magic == HCF_MAGIC )
139 #define NT_ASSERT 0x0000 //, NEVER_TESTED
140 #define NEVER_TESTED MERGE_2( 0xEFFE, 0xFEEF )
141 #define SE_ASSERT 0x5EFF /* Side Effect, HCFASSERT invokation which are only called for the
142 * side effect and which should never trigger */
143 #define DHF_FILE_NAME_OFFSET 10000 //to distinguish DHF from HCF asserts by means of line number
144 #define MMD_FILE_NAME_OFFSET 20000 //to distinguish MMD from HCF asserts by means of line number
145
146 // trace codes used to
147 // 1: profile execution times via HCF_TRACE and HCF_TRACE_VALUE
148 // 2: hierarchical flow information via HCFLOGENTRY / HCFLOGEXIT
149
150 //#define HCF_TRACE_CONNECT useless
151 //#define HCF_TRACE_DISCONNECT useless
152 #define HCF_TRACE_ACTION 0x0000 // 0x0001
153 #define HCF_TRACE_CNTL 0x0001 // 0x0002
154 #define HCF_TRACE_DMA_RX_GET 0x0002 // 0x0004
155 #define HCF_TRACE_DMA_RX_PUT 0x0003 // 0x0008
156 #define HCF_TRACE_DMA_TX_GET 0x0004 // 0x0010
157 #define HCF_TRACE_DMA_TX_PUT 0x0005 // 0x0020
158 #define HCF_TRACE_GET_INFO 0x0006 // 0x0040
159 #define HCF_TRACE_PUT_INFO 0x0007 // 0x0080
160 #define HCF_TRACE_RCV_MSG 0x0008 // 0x0100
161 #define HCF_TRACE_SEND_MSG 0x0009 // 0x0200
162 #define HCF_TRACE_SERVICE_NIC 0x000A // 0x0400
163 // #define HCF_TRACE_ 0x000C // 0x1000
164 // #define HCF_TRACE_ 0x000D // 0x2000
165 // #define HCF_TRACE_ 0x000E // 0x4000
166 // #define HCF_TRACE_ 0x000F // 0x8000
167 // ============================================ HCF_TRACE_... codes below 0x0010 are asserted on re-entry
168 #define HCF_TRACE_ACTION_KLUDGE 0x0010 /* once you start introducing kludges there is no end to it
169 * this is an escape to do not assert on re-entrancy problem caused
170 * by HCF_ACT_INT_FORCE_ON used to get Microsofts NDIS drivers going
171 */
172 #define HCF_TRACE_STRIO 0x0020
173 #define HCF_TRACE_ALLOC 0X0021
174 #define HCF_TRACE_DL 0X0023
175 #define HCF_TRACE_ISR_INFO 0X0024
176 #define HCF_TRACE_CALIBRATE 0x0026
177
178 #define HCF_TRACE_CMD_CPL 0x0040
179 #define HCF_TRACE_CMD_EXE 0x0041
180 #define HCF_TRACE_GET_FID 0x0042
181 #define HCF_TRACE_GET_FRAG 0x0043
182 #define HCF_TRACE_INIT 0x0044
183 #define HCF_TRACE_PUT_FRAG 0x0045
184 #define HCF_TRACE_SETUP_BAP 0x0046
185
186 #define HCF_TRACE_EXIT 0x8000 // Keil C warns "long constant truncated to int"
187
188 //#define BAP_0 HREG_DATA_0 //Used by DMA controller to access NIC RAM
189 #define BAP_1 HREG_DATA_1 //Used by HCF to access NIC RAM
190
191
192 //************************* Hermes Receive/Transmit Frame Structures
193 //HFS_STAT
194 //see MMD.H for HFS_STAT_ERR
195 #define HFS_STAT_MSG_TYPE 0xE000 //Hermes reported Message Type
196 #define HFS_STAT_MIC_KEY_ID 0x1800 //MIC key used (if any)
197 #define HFS_STAT_1042 0x2000 //RFC1042 Encoded
198 #define HFS_STAT_TUNNEL 0x4000 //Bridge-Tunnel Encoded
199 #define HFS_STAT_WMP_MSG 0x6000 //WaveLAN-II Management Protocol Frame
200 #if (HCF_TYPE) & HCF_TYPE_WPA
201 #define HFS_STAT_MIC 0x0010 //Frame contains MIC //;? re-instate when F/W ready
202 #endif
203
204 //************************* Hermes Register Offsets and Command bits
205 #define HREG_IO_RANGE 0x80 //I/O Range used by Hermes
206
207
208 //************************* Command/Status
209 #define HREG_CMD 0x00 //
210 #define HCMD_CMD_CODE 0x3F
211 #define HREG_PARAM_0 0x02 //
212 #define HREG_PARAM_1 0x04 //
213 #define HREG_PARAM_2 0x06 //
214 #define HREG_STAT 0x08 //
215 #define HREG_STAT_CMD_CODE 0x003F //
216 #define HREG_STAT_DIAG_ERR 0x0100
217 #define HREG_STAT_INQUIRE_ERR 0x0500
218 #define HREG_STAT_CMD_RESULT 0x7F00 //
219 #define HREG_RESP_0 0x0A //
220 #define HREG_RESP_1 0x0C //
221 #define HREG_RESP_2 0x0E //
222
223
224 //************************* FID Management
225 #define HREG_INFO_FID 0x10 //
226 #define HREG_RX_FID 0x20 //
227 #define HREG_ALLOC_FID 0x22 //
228 #define HREG_TX_COMPL_FID 0x24 //
229
230
231 //************************* BAP
232 //20031030 HWi Inserted this again because the dongle code uses this (GPIF.C)
233 //#define HREG_SELECT_0 0x18 //
234 //#define HREG_OFFSET_0 0x1C //
235 //#define HREG_DATA_0 0x36 //
236
237 //#define HREG_OFFSET_BUSY 0x8000 // use HCMD_BUSY
238 #define HREG_OFFSET_ERR 0x4000 //
239 //rsrvd #define HREG_OFFSET_DATA_OFFSET 0x0FFF //
240
241 #define HREG_SELECT_1 0x1A //
242 #define HREG_OFFSET_1 0x1E //
243 #define HREG_DATA_1 0x38 //
244
245
246 //************************* Event
247 #define HREG_EV_STAT 0x30 //
248 #define HREG_INT_EN 0x32 //
249 #define HREG_EV_ACK 0x34 //
250
251 #define HREG_EV_TICK 0x8000 //Auxiliary Timer Tick
252 //#define HREG_EV_RES 0x4000 //H-I only: H/W error (Wait Time-out)
253 #define HREG_EV_INFO_DROP 0x2000 //WMAC did not have sufficient RAM to build Unsollicited Frame
254 #if (HCF_TYPE) & HCF_TYPE_HII5
255 #define HREG_EV_ACK_REG_READY 0x0000
256 #else
257 #define HREG_EV_ACK_REG_READY 0x1000 //Workaround Kludge bit for H-II (not H-II.5)
258 #endif // HCF_TYPE_HII5
259 #if (HCF_SLEEP) & ( HCF_CDS | HCF_DDS )
260 #define HREG_EV_SLEEP_REQ 0x0800
261 #else
262 #define HREG_EV_SLEEP_REQ 0x0000
263 #endif // HCF_CDS / HCF_DDS
264 #if HCF_DMA
265 //#define HREG_EV_LPESC 0x0400 // firmware sets this bit and clears it, not for host usage.
266 #define HREG_EV_RDMAD 0x0200 // rx frame in host memory
267 #define HREG_EV_TDMAD 0x0100 // tx frame in host memory processed
268 //#define HREG_EV_RXDMA 0x0040 // firmware kicks off DMA engine (bit is not for host usage)
269 //#define HREG_EV_TXDMA 0x0020 // firmware kicks off DMA engine (bit is not for host usage)
270 #define HREG_EV_FW_DMA 0x0460 // firmware / DMA engine I/F (bits are not for host usage)
271 #else
272 #define HREG_EV_FW_DMA 0x0000
273 #endif // HCF_DMA
274 #define HREG_EV_INFO 0x0080 // Asynchronous Information Frame
275 #define HREG_EV_CMD 0x0010 // Command completed, Status and Response available
276 #define HREG_EV_ALLOC 0x0008 // Asynchronous part of Allocation/Reclaim completed
277 #define HREG_EV_TX_EXC 0x0004 // Asynchronous Transmission unsuccessful completed
278 #define HREG_EV_TX 0x0002 // Asynchronous Transmission successful completed
279 #define HREG_EV_RX 0x0001 // Asynchronous Receive Frame
280
281 #define HREG_EV_TX_EXT ( (HCF_EXT) & (HCF_EXT_INT_TX_EX | HCF_EXT_INT_TICK ) )
282 /* HREG_EV_TX_EXT := 0x0000 or HREG_EV_TX_EXC and/or HREG_EV_TICK
283 * could be extended with HREG_EV_TX */
284 #if HCF_EXT_INT_TX_EX != HREG_EV_TX_EXC
285 err: these values should match;
286 #endif // HCF_EXT_INT_TX_EX / HREG_EV_TX_EXC
287
288 #if HCF_EXT_INT_TICK != HREG_EV_TICK
289 err: these values should match;
290 #endif // HCF_EXT_INT_TICK / HREG_EV_TICK
291
292 //************************* Host Software
293 #define HREG_SW_0 0x28 //
294 #define HREG_SW_1 0x2A //
295 #define HREG_SW_2 0x2C //
296 //rsrvd #define HREG_SW_3 0x2E //
297 //************************* Control and Auxiliary Port
298
299 #define HREG_IO 0x12
300 #define HREG_IO_SRESET 0x0001
301 #define HREG_IO_WAKEUP_ASYNC 0x0002
302 #define HREG_IO_WOKEN_UP 0x0004
303 #define HREG_CNTL 0x14 //
304 //#define HREG_CNTL_WAKEUP_SYNC 0x0001
305 #define HREG_CNTL_AUX_ENA_STAT 0xC000
306 #define HREG_CNTL_AUX_DIS_STAT 0x0000
307 #define HREG_CNTL_AUX_ENA_CNTL 0x8000
308 #define HREG_CNTL_AUX_DIS_CNTL 0x4000
309 #define HREG_CNTL_AUX_DSD 0x2000
310 #define HREG_CNTL_AUX_ENA (HREG_CNTL_AUX_ENA_CNTL | HREG_CNTL_AUX_DIS_CNTL )
311 #define HREG_SPARE 0x16 //
312 #define HREG_AUX_PAGE 0x3A //
313 #define HREG_AUX_OFFSET 0x3C //
314 #define HREG_AUX_DATA 0x3E //
315
316 #if HCF_DMA
317 //************************* DMA (bus mastering)
318 // Be carefull to use these registers only at a genuine 32 bits NIC
319 // On 16 bits NICs, these addresses are mapped into the range 0x00 through 0x3F with all consequences
320 // thereof, e.g. HREG_DMA_CTRL register maps to HREG_CMD.
321 #define HREG_DMA_CTRL 0x0040
322 #define HREG_TXDMA_PTR32 0x0044
323 #define HREG_TXDMA_PRIO_PTR32 0x0048
324 #define HREG_TXDMA_HIPRIO_PTR32 0x004C
325 #define HREG_RXDMA_PTR32 0x0050
326 #define HREG_CARDDETECT_1 0x007C // contains 7D37
327 #define HREG_CARDDETECT_2 0x007E // contains 7DE7
328 #define HREG_FREETIMER 0x0058
329 #define HREG_DMA_RX_CNT 0x0026
330
331 /******************************************************************************
332 * Defines for the bits in the DmaControl register (@40h)
333 ******************************************************************************/
334 #define HREG_DMA_CTRL_RXHWEN 0x80000000 // high word enable bit
335 #define HREG_DMA_CTRL_RXRESET 0x40000000 // tx dma init bit
336 #define HREG_DMA_CTRL_RXBAP1 BIT29
337 #define HREG_DMA_CTRL_RX_STALLED BIT28
338 #define HREG_DMA_CTRL_RXAUTOACK_DMADONE BIT27 // no host involvement req. for TDMADONE event
339 #define HREG_DMA_CTRL_RXAUTOACK_INFO BIT26 // no host involvement req. for alloc event
340 #define HREG_DMA_CTRL_RXAUTOACK_DMAEN 0x02000000 // no host involvement req. for TxDMAen event
341 #define HREG_DMA_CTRL_RXAUTOACK_RX 0x01000000 // no host involvement req. for tx event
342 #define HREG_DMA_CTRL_RX_BUSY BIT23 // read only bit
343 //#define HREG_DMA_CTRL_RX_RBUFCONT_PLAIN 0 // bits 21..20
344 //#define HREG_DMA_CTRL_RX_MODE_PLAIN_DMA 0 // mode 0
345 #define HREG_DMA_CTRL_RX_MODE_SINGLE_PACKET 0x00010000 // mode 1
346 #define HREG_DMA_CTRL_RX_MODE_MULTI_PACKET 0x00020000 // mode 2
347 //#define HREG_DMA_CTRL_RX_MODE_DISABLE (0x00020000|0x00010000) // disable tx dma engine
348 #define HREG_DMA_CTRL_TXHWEN 0x8000 // low word enable bit
349 #define HREG_DMA_CTRL_TXRESET 0x4000 // rx dma init bit
350 #define HREG_DMA_CTRL_TXBAP1 BIT13
351 #define HREG_DMA_CTRL_TXAUTOACK_DMADONE BIT11 // no host involvement req. for RxDMADONE event
352 #define HREG_DMA_CTRL_TXAUTOACK_DMAEN 0x00000400 // no host involvement req. for RxDMAen event
353 #define HREG_DMA_CTRL_TXAUTOACK_DMAALLOC 0x00000200 // no host involvement req. for info event
354 #define HREG_DMA_CTRL_TXAUTOACK_TX 0x00000100 // no host involvement req. for rx event
355 #define HREG_DMA_CTRL_TX_BUSY BIT7 // read only bit
356 //#define HREG_DMA_CTRL_TX_TBUFCONT_PLAIN 0 // bits 6..5
357 //#define HREG_DMA_CTRL_TX_MODE_PLAIN_DMA 0 // mode 0
358 #define HREG_DMA_CTRL_TX_MODE_SINGLE_PACKET BIT0 // mode 1
359 #define HREG_DMA_CTRL_TX_MODE_MULTI_PACKET 0x00000002 // mode 2
360 //#define HREG_DMA_CTRL_TX_MODE_DISABLE (0x00000001|0x00000002) // disable tx dma engine
361
362 //configuration DWORD to configure DMA for mode2 operation, using BAP0 as the DMA BAP.
363 #define DMA_CTRLSTAT_GO (HREG_DMA_CTRL_RXHWEN | HREG_DMA_CTRL_RX_MODE_MULTI_PACKET | \
364 HREG_DMA_CTRL_RXAUTOACK_DMAEN | HREG_DMA_CTRL_RXAUTOACK_RX | \
365 HREG_DMA_CTRL_TXHWEN | /*;?HREG_DMA_CTRL_TX_TBUFCONT_PLAIN |*/ \
366 HREG_DMA_CTRL_TX_MODE_MULTI_PACKET | HREG_DMA_CTRL_TXAUTOACK_DMAEN |\
367 HREG_DMA_CTRL_TXAUTOACK_DMAALLOC)
368
369 //configuration DWORD to reset both the Tx and Rx DMA engines
370 #define DMA_CTRLSTAT_RESET (HREG_DMA_CTRL_RXHWEN | HREG_DMA_CTRL_RXRESET | HREG_DMA_CTRL_TXHWEN | HREG_DMA_CTRL_TXRESET)
371
372 //#define DESC_DMA_OWNED 0x80000000 // BIT31
373 #define DESC_DMA_OWNED 0x8000 // BIT31
374 #define DESC_SOP 0x8000 // BIT15
375 #define DESC_EOP 0x4000 // BIT14
376
377 #define DMA_RX 0
378 #define DMA_TX 1
379
380 // #define IFB_RxFirstDesc IFB_FirstDesc[DMA_RX]
381 // #define IFB_TxFirstDesc IFB_FirstDesc[DMA_TX]
382 // #define IFB_RxLastDesc IFB_LastDesc[DMA_RX]
383 // #define IFB_TxLastDesc IFB_LastDesc[DMA_TX]
384
385 #endif // HCF_DMA
386 //
387 /************************************************************************************************/
388 /********************************** EQUATES ***************************************************/
389 /************************************************************************************************/
390
391
392 // Hermes Command Codes and Qualifier bits
393 #define HCMD_BUSY 0x8000 // Busy bit, applicable for all commands
394 #define HCMD_INI 0x0000 //
395 #define HCMD_ENABLE HCF_CNTL_ENABLE // 0x0001
396 #define HCMD_DISABLE HCF_CNTL_DISABLE // 0x0002
397 #define HCMD_CONNECT HCF_CNTL_CONNECT // 0x0003
398 #define HCMD_EXECUTE 0x0004 //
399 #define HCMD_DISCONNECT HCF_CNTL_DISCONNECT // 0x0005
400 #define HCMD_SLEEP 0x0006 //
401 #define HCMD_CONTINUE HCF_CNTL_CONTINUE // 0x0007
402 #define HCMD_RETRY 0x0100 // Retry bit
403 #define HCMD_ALLOC 0x000A //
404 #define HCMD_TX 0x000B //
405 #define HCMD_RECL 0x0100 // Reclaim bit, applicable for Tx and Inquire
406 #define HCMD_INQUIRE 0x0011 //
407 #define HCMD_ACCESS 0x0021 //
408 #define HCMD_ACCESS_WRITE 0x0100 // Write bit
409 #define HCMD_PROGRAM 0x0022 //
410 #define HCMD_READ_MIF 0x0030
411 #define HCMD_WRITE_MIF 0x0031
412 #define HCMD_THESEUS 0x0038
413 #define HCMD_STARTPREAMBLE 0x0E00 // Start continuous preamble Tx
414 #define HCMD_STOP 0x0F00 // Stop Theseus test mode
415
416
417 //Configuration Management
418 //
419
420 #define CFG_DRV_ACT_RANGES_PRI_3_BOTTOM 1 // Default Bottom Compatibility for Primary Firmware - driver I/F
421 #define CFG_DRV_ACT_RANGES_PRI_3_TOP 1 // Default Top Compatibility for Primary Firmware - driver I/F
422
423 #define CFG_DRV_ACT_RANGES_HSI_4_BOTTOM 1 // Default Bottom Compatibility for H/W - driver I/F
424 #define CFG_DRV_ACT_RANGES_HSI_4_TOP 1 // Default Top Compatibility for H/W - driver I/F
425
426 #define CFG_DRV_ACT_RANGES_HSI_5_BOTTOM 1 // Default Bottom Compatibility for H/W - driver I/F
427 #define CFG_DRV_ACT_RANGES_HSI_5_TOP 1 // Default Top Compatibility for H/W - driver I/F
428
429 #if (HCF_TYPE) & HCF_TYPE_WPA
430 #define CFG_DRV_ACT_RANGES_APF_1_BOTTOM 16 // Default Bottom Compatibility for AP Firmware - driver I/F
431 #define CFG_DRV_ACT_RANGES_APF_1_TOP 16 // Default Top Compatibility for AP Firmware - driver I/F
432 #else //;? is this REALLY O.K.
433 #define CFG_DRV_ACT_RANGES_APF_1_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F
434 #define CFG_DRV_ACT_RANGES_APF_1_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F
435 #endif // HCF_TYPE_WPA
436
437 #define CFG_DRV_ACT_RANGES_APF_2_BOTTOM 2 // Default Bottom Compatibility for AP Firmware - driver I/F
438 #define CFG_DRV_ACT_RANGES_APF_2_TOP 2 // Default Top Compatibility for AP Firmware - driver I/F
439
440 #define CFG_DRV_ACT_RANGES_APF_3_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F
441 #define CFG_DRV_ACT_RANGES_APF_3_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F
442
443 #define CFG_DRV_ACT_RANGES_APF_4_BOTTOM 1 // Default Bottom Compatibility for AP Firmware - driver I/F
444 #define CFG_DRV_ACT_RANGES_APF_4_TOP 1 // Default Top Compatibility for AP Firmware - driver I/F
445
446 #if (HCF_TYPE) & HCF_TYPE_HII5
447 #define CFG_DRV_ACT_RANGES_STA_2_BOTTOM 6 // Default Bottom Compatibility for Station Firmware - driver I/F
448 #define CFG_DRV_ACT_RANGES_STA_2_TOP 6 // Default Top Compatibility for Station Firmware - driver I/F
449 #else // (HCF_TYPE) & HCF_TYPE_HII5
450 #define CFG_DRV_ACT_RANGES_STA_2_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F
451 #define CFG_DRV_ACT_RANGES_STA_2_TOP 2 // Default Top Compatibility for Station Firmware - driver I/F
452 #endif // (HCF_TYPE) & HCF_TYPE_HII5
453
454 #define CFG_DRV_ACT_RANGES_STA_3_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F
455 #define CFG_DRV_ACT_RANGES_STA_3_TOP 1 // Default Top Compatibility for Station Firmware - driver I/F
456
457 #define CFG_DRV_ACT_RANGES_STA_4_BOTTOM 1 // Default Bottom Compatibility for Station Firmware - driver I/F
458 #define CFG_DRV_ACT_RANGES_STA_4_TOP 1 // Default Top Compatibility for Station Firmware - driver I/F
459
460 //---------------------------------------------------------------------------------------------------------------------
461 #if defined HCF_CFG_PRI_1_TOP || defined HCF_CFG_PRI_1_BOTTOM
462 err: PRI_1 not supported for H-I; // Compatibility for Primary Firmware - driver I/F
463 #endif // HCF_CFG_PRI_1_TOP / HCF_CFG_PRI_1_BOTTOM
464
465 #if defined HCF_CFG_PRI_2_TOP || defined HCF_CFG_PRI_2_BOTTOM
466 err: PRI_2 not supported for H-I; // Compatibility for Primary Firmware - driver I/F
467 #endif // HCF_CFG_PRI_2_TOP / HCF_CFG_PRI_2_BOTTOM
468
469 #ifdef HCF_CFG_PRI_3_TOP // Top Compatibility for Primary Firmware - driver I/F
470 #if HCF_CFG_PRI_3_TOP == 0 || \
471 CFG_DRV_ACT_RANGES_PRI_3_BOTTOM <= HCF_CFG_PRI_3_TOP && HCF_CFG_PRI_3_TOP <= CFG_DRV_ACT_RANGES_PRI_3_TOP
472 #undef CFG_DRV_ACT_RANGES_PRI_3_TOP
473 #define CFG_DRV_ACT_RANGES_PRI_3_TOP HCF_CFG_PRI_3_TOP
474 #else
475 err: ;
476 #endif
477 #endif // HCF_CFG_PRI_3_TOP
478
479 #ifdef HCF_CFG_PRI_3_BOTTOM // Bottom Compatibility for Primary Firmware - driver I/F
480 #if CFG_DRV_ACT_RANGES_PRI_3_BOTTOM <= HCF_CFG_PRI_3_BOTTOM && HCF_CFG_PRI_3_BOTTOM <= CFG_DRV_ACT_RANGES_PRI_3_TOP
481 #undef CFG_DRV_ACT_RANGES_PRI_3_BOTTOM
482 #define CFG_DRV_ACT_RANGES_PRI_3_BOTTOM HCF_CFG_PRI_3_BOTTOM
483 #else
484 err: ;
485 #endif
486 #endif // HCF_CFG_PRI_3_BOTTOM
487
488
489 //---------------------------------------------------------------------------------------------------------------------
490 #if defined HCF_CFG_HSI_0_TOP || defined HCF_CFG_HSI_0_BOTTOM
491 err: HSI_0 not supported for H-I; // Compatibility for HSI I/F
492 #endif // HCF_CFG_HSI_0_TOP / HCF_CFG_HSI_0_BOTTOM
493
494 #if defined HCF_CFG_HSI_1_TOP || defined HCF_CFG_HSI_1_BOTTOM
495 err: HSI_1 not supported for H-I; // Compatibility for HSI I/F
496 #endif // HCF_CFG_HSI_1_TOP / HCF_CFG_HSI_1_BOTTOM
497
498 #if defined HCF_CFG_HSI_2_TOP || defined HCF_CFG_HSI_2_BOTTOM
499 err: HSI_2 not supported for H-I; // Compatibility for HSI I/F
500 #endif // HCF_CFG_HSI_2_TOP / HCF_CFG_HSI_2_BOTTOM
501
502 #if defined HCF_CFG_HSI_3_TOP || defined HCF_CFG_HSI_3_BOTTOM
503 err: HSI_3 not supported for H-I; // Compatibility for HSI I/F
504 #endif // HCF_CFG_HSI_3_TOP / HCF_CFG_HSI_3_BOTTOM
505
506 #ifdef HCF_CFG_HSI_4_TOP // Top Compatibility for HSI I/F
507 #if HCF_CFG_HSI_4_TOP == 0 || \
508 CFG_DRV_ACT_RANGES_HSI_4_BOTTOM <= CF_CFG_HSI_4_TOP && HCF_CFG_HSI_4_TOP <= CFG_DRV_ACT_RANGES_HSI_4_TOP
509 #undef CFG_DRV_ACT_RANGES_HSI_4_TOP
510 #define CFG_DRV_ACT_RANGES_HSI_4_TOP HCF_CFG_HSI_4_TOP
511 #else
512 err: ;
513 #endif
514 #endif // HCF_CFG_HSI_4_TOP
515
516 #ifdef HCF_CFG_HSI_4_BOTTOM // Bottom Compatibility for HSI I/F
517 #if CFG_DRV_ACT_RANGES_HSI_4_BOTTOM <= HCF_CFG_HSI_4_BOTTOM && HCF_CFG_HSI_4_BOTTOM <= CFG_DRV_ACT_RANGES_HSI_4_TOP
518 #undef CFG_DRV_ACT_RANGES_HSI_4_BOTTOM
519 #define CFG_DRV_ACT_RANGES_HSI_4_BOTTOM HCF_CFG_HSI_4_BOTTOM
520 #else
521 err: ;
522 #endif
523 #endif // HCF_CFG_HSI_4_BOTTOM
524
525 #ifdef HCF_CFG_HSI_5_TOP // Top Compatibility for HSI I/F
526 #if HCF_CFG_HSI_5_TOP == 0 || \
527 CFG_DRV_ACT_RANGES_HSI_5_BOTTOM <= CF_CFG_HSI_5_TOP && HCF_CFG_HSI_5_TOP <= CFG_DRV_ACT_RANGES_HSI_5_TOP
528 #undef CFG_DRV_ACT_RANGES_HSI_5_TOP
529 #define CFG_DRV_ACT_RANGES_HSI_5_TOP HCF_CFG_HSI_5_TOP
530 #else
531 err: ;
532 #endif
533 #endif // HCF_CFG_HSI_5_TOP
534
535 #ifdef HCF_CFG_HSI_5_BOTTOM // Bottom Compatibility for HSI I/F
536 #if CFG_DRV_ACT_RANGES_HSI_5_BOTTOM <= HCF_CFG_HSI_5_BOTTOM && HCF_CFG_HSI_5_BOTTOM <= CFG_DRV_ACT_RANGES_HSI_5_TOP
537 #undef CFG_DRV_ACT_RANGES_HSI_5_BOTTOM
538 #define CFG_DRV_ACT_RANGES_HSI_5_BOTTOM HCF_CFG_HSI_5_BOTTOM
539 #else
540 err: ;
541 #endif
542 #endif // HCF_CFG_HSI_5_BOTTOM
543 //---------------------------------------------------------------------------------------------------------------------
544 #if defined HCF_CFG_APF_1_TOP || defined HCF_CFG_APF_1_BOTTOM
545 err: APF_1 not supported for H-I; // Compatibility for AP Firmware - driver I/F
546 #endif // HCF_CFG_APF_1_TOP / HCF_CFG_APF_1_BOTTOM
547
548 #ifdef HCF_CFG_APF_2_TOP // Top Compatibility for AP Firmware - driver I/F
549 #if HCF_CFG_APF_2_TOP == 0 || \
550 CFG_DRV_ACT_RANGES_APF_2_BOTTOM <= HCF_CFG_APF_2_TOP && HCF_CFG_APF_2_TOP <= CFG_DRV_ACT_RANGES_APF_2_TOP
551 #undef CFG_DRV_ACT_RANGES_APF_2_TOP
552 #define CFG_DRV_ACT_RANGES_APF_2_TOP HCF_CFG_APF_2_TOP
553 #else
554 err: ;
555 #endif
556 #endif // HCF_CFG_APF_TOP
557
558 #ifdef HCF_CFG_APF_2_BOTTOM // Bottom Compatibility for AP Firmware - driver I/F
559 #if CFG_DRV_ACT_RANGES_APF_2_BOTTOM <= HCF_CFG_APF_2_BOTTOM && HCF_CFG_APF_2_BOTTOM <= CFG_DRV_ACT_RANGES_APF_2_TOP
560 #undef CFG_DRV_ACT_RANGES_APF_2_BOTTOM
561 #define CFG_DRV_ACT_RANGES_APF_2_BOTTOM HCF_CFG_APF_2_BOTTOM
562 #else
563 err: ;
564 #endif
565 #endif // HCF_CFG_APF_BOTTOM
566
567 //---------------------------------------------------------------------------------------------------------------------
568 #if defined HCF_CFG_STA_1_TOP || defined HCF_CFG_STA_1_BOTTOM
569 err: STA_1 not supported for H-I; // Compatibility for Station Firmware - driver I/F
570 #endif // HCF_CFG_STA_1_TOP / HCF_CFG_STA_1_BOTTOM
571
572 #ifdef HCF_CFG_STA_2_TOP // Top Compatibility for Station Firmware - driver I/F
573 #if HCF_CFG_STA_2_TOP == 0 || \
574 CFG_DRV_ACT_RANGES_STA_2_BOTTOM <= HCF_CFG_STA_2_TOP && HCF_CFG_STA_2_TOP <= CFG_DRV_ACT_RANGES_STA_2_TOP
575 #undef CFG_DRV_ACT_RANGES_STA_2_TOP
576 #define CFG_DRV_ACT_RANGES_STA_2_TOP HCF_CFG_STA_2_TOP
577 #else
578 err: ;
579 #endif
580 #endif // HCF_CFG_STA_TOP
581
582 #ifdef HCF_CFG_STA_2_BOTTOM // Bottom Compatibility for Station Firmware - driver I/F
583 #if CFG_DRV_ACT_RANGES_STA_2_BOTTOM <= HCF_CFG_STA_2_BOTTOM && HCF_CFG_STA_2_BOTTOM <= CFG_DRV_ACT_RANGES_STA_2_TOP
584 #undef CFG_DRV_ACT_RANGES_STA_2_BOTTOM
585 #define CFG_DRV_ACT_RANGES_STA_2_BOTTOM HCF_CFG_STA_2_BOTTOM
586 #else
587 err: ;
588 #endif
589 #endif // HCF_CFG_STA_BOTTOM
590
591
592 /************************************************************************************************/
593 /************************************** MACROS ************************************************/
594 /************************************************************************************************/
595
596 #ifdef HCF_SLEEP
597 #if defined MSF_WAIT
598 err: MSF should no longer supply this macro;
599 #else
600 #define MSF_WAIT(x) \
601 { PROT_CNT_INI \
602 HCF_WAIT_WHILE( ( IPW( HREG_IO ) & HREG_IO_WOKEN_UP ) == 0 ); \
603 HCFASSERT( prot_cnt, IPW( HREG_IO ) ) \
604 }
605 #endif // MSF_WAIT
606 #else
607 #define MSF_WAIT(x) /*NOP*/
608 #endif // HCF_SLEEP
609
610 #define LOF(x) (sizeof(x)/sizeof(hcf_16)-1)
611
612 #define MUL_BY_2( x ) ( (x) << 1 ) //used to multiply by 2
613 #define DIV_BY_2( x ) ( (x) >> 1 ) //used to divide by 2
614
615 //resolve problems on for some 16 bits compilers to create 32 bit values
616 #define MERGE_2( hw, lw ) ( ( ((hcf_32)(hw)) << 16 ) | ((hcf_16)(lw)) )
617
618 #if ! defined HCF_STATIC
619 #define HCF_STATIC static
620 #endif // HCF_STATIC
621
622 #if ( (HCF_TYPE) & HCF_TYPE_HII5 ) == 0
623 #define DAWA_ACK( mask) { \
624 OPW( HREG_EV_ACK, mask | HREG_EV_ACK_REG_READY ); \
625 OPW( HREG_EV_ACK, (mask & ~HREG_EV_ALLOC) | HREG_EV_ACK_REG_READY ); }
626 #define DAWA_ZERO_FID(reg) OPW( reg, 0 );
627 #else
628 #define DAWA_ACK( mask) OPW( HREG_EV_ACK, mask );
629 #define DAWA_ZERO_FID(reg)
630 #endif // HCF_TYPE_HII5
631
632 #if (HCF_TYPE) & HCF_TYPE_WPA
633 #define CALC_RX_MIC( p, len ) calc_mic_rx_frag( ifbp, p, len )
634 #define CALC_TX_MIC( p, len ) calc_mic_tx_frag( ifbp, p, len )
635 #define IF_SSN(x) x
636 #define IF_NOT_SSN(x)
637 #else
638 #define CALC_RX_MIC( p, len )
639 #define CALC_TX_MIC( p, len )
640 #define MIC_RX_RTN( mic, dw )
641 #define MIC_TX_RTN( mic, dw )
642 #define IF_SSN(x)
643 #define IF_NOT_SSN(x) x
644 #endif // HCF_TYPE_WPA
645
646 #if HCF_TALLIES & HCF_TALLIES_HCF //HCF tally support
647 #define IF_TALLY(x) x
648 #else
649 #define IF_TALLY(x)
650 #endif // HCF_TALLIES_HCF
651
652
653 #if HCF_DMA
654 #define IF_DMA(x) x
655 #define IF_NOT_DMA(x)
656 #define IF_USE_DMA(x) if ( ifbp->IFB_CntlOpt & USE_DMA ) x
657 #define IF_NOT_USE_DMA(x) if ( !(ifbp->IFB_CntlOpt & USE_DMA) ) x
658 #else
659 #define IF_DMA(x)
660 #define IF_NOT_DMA(x) x
661 #define IF_USE_DMA(x)
662 #define IF_NOT_USE_DMA(x) x
663 #endif // HCF_DMA
664
665
666 #define IPW(x) ((hcf_16)IN_PORT_WORD( ifbp->IFB_IOBase + (x) ) )
667 #define OPW(x, y) OUT_PORT_WORD( ifbp->IFB_IOBase + (x), y )
668 /* make sure the implementation of HCF_WAIT_WHILE is such that there may be multiple HCF_WAIT_WHILE calls
669 * in a row and that when one fails all subsequent fail immediately without reinitialization of prot_cnt
670 */
671 #if HCF_PROT_TIME == 0
672 #define PROT_CNT_INI
673 #define IF_PROT_TIME(x)
674 #if defined HCF_YIELD
675 #define HCF_WAIT_WHILE( x ) while ( (x) && (HCF_YIELD) ) /*NOP*/;
676 #else
677 #define HCF_WAIT_WHILE( x ) while ( x ) /*NOP*/;
678 #endif // HCF_YIELD
679 #else
680 #define PROT_CNT_INI hcf_32 prot_cnt = ifbp->IFB_TickIni;
681 #define IF_PROT_TIME(x) x
682 #if defined HCF_YIELD
683 #define HCF_WAIT_WHILE( x ) while ( prot_cnt && (x) && (HCF_YIELD) ) prot_cnt--;
684 #else
685 #include <linux/delay.h>
686 #define HCF_WAIT_WHILE( x ) while ( prot_cnt && (x) ) { udelay(2); prot_cnt--; }
687 #endif // HCF_YIELD
688 #endif // HCF_PROT_TIME
689
690 #if defined HCF_EX_INT
691 //#if HCF_EX_INT & ~( HCF_EX_INT_TX_EX | HCF_EX_INT_TX_OK | HCF_EX_INT_TICK )
692 ;? out dated checking
693 err: you used an invalid bitmask;
694 // #endif // HCF_EX_INT validation
695 // #else
696 // #define HCF_EX_INT 0x000
697 #endif // HCF_EX_INT
698
699 #if 0 //get compiler going
700 #if HCF_EX_INT_TICK != HREG_EV_TICK
701 ;? out dated checking
702 err: someone redefined these macros while the implemenation assumes they are equal;
703 #endif
704 #if HCF_EX_INT_TX_OK != HFS_TX_CNTL_TX_OK || HFS_TX_CNTL_TX_OK != HREG_EV_TX_OK
705 ;? out dated checking
706 err: someone redefined these macros while the implemenation assumes they are equal;
707 #endif
708 #if HCF_EX_INT_TX_EX != HFS_TX_CNTL_TX_EX || HFS_TX_CNTL_TX_EX != HREG_EV_TX_EX
709 ;? out dated checking
710 err: someone redefined these macros while the implemenation assumes they are equal;
711 #endif
712 #endif // 0 get compiler going
713
714
715 /* The assert in HCFLOGENTRY checks against re-entrancy. Re-entrancy could be caused by MSF logic at
716 * task-level calling hcf_functions without shielding with HCF_ACT_ON/_OFF. When an interrupt occurs,
717 * the ISR could (either directly or indirectly) cause re-entering of the interrupted HCF-routine.
718 *
719 * The "(ifbp->IFB_AssertWhere = where)" test in HCFLOGENTRY services ALSO as a statement to get around:
720 * #pragma warning: conditional expression is constant
721 * on the if-statement
722 */
723 #if HCF_ASSERT
724 #define HCFASSERT(x,q) {if (!(x)) {mdd_assert( ifbp, __LINE__ , q );}}
725 #define MMDASSERT(x,q) {if (!(x)) {mdd_assert( assert_ifbp, __LINE__ + FILE_NAME_OFFSET, q );}}
726
727 #define HCFLOGENTRY( where, what ) \
728 {if ( (ifbp->IFB_AssertWhere = where) <= 15 ) { \
729 HCF_ENTRY( ifbp ); \
730 HCFASSERT( (ifbp->IFB_AssertTrace & 1<<((where)&0xF)) == 0, ifbp->IFB_AssertTrace ); \
731 ifbp->IFB_AssertTrace |= 1<<((where)&0xF); \
732 } \
733 HCFTRACE(ifbp, where ) \
734 HCFTRACEVALUE(ifbp, what ) \
735 }
736
737 #define HCFLOGEXIT( where ) \
738 {if ( (ifbp->IFB_AssertWhere = where) <= 15 ) { \
739 HCF_EXIT( ifbp ); \
740 ifbp->IFB_AssertTrace &= ~(1<<((where)&0xF)); \
741 } \
742 HCFTRACE(ifbp, (where)|HCF_TRACE_EXIT ) \
743 }
744
745 #else // HCF_ASSERT
746 #define HCFASSERT( x, q )
747 #define MMDASSERT( x, q )
748 #define HCFLOGENTRY( where, what ) {HCF_ENTRY( ifbp );}
749 #define HCFLOGEXIT( where ) {HCF_EXIT( ifbp );}
750 #endif // HCF_ASSERT
751
752 #if HCF_INT_ON
753 /* ;? HCFASSERT_INT
754 * #if (HCF_SLEEP) & HCF_DDS
755 * #define HCFASSERT_INT HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFF && ifbp->IFB_IntOffCnt != 0xFFFE, \
756 * ifbp->IFB_IntOffCnt )
757 * #else
758 */
759 #define HCFASSERT_INT HCFASSERT( ifbp->IFB_IntOffCnt != 0xFFFF, ifbp->IFB_IntOffCnt )
760 // #endif // HCF_DDS
761 #else
762 #define HCFASSERT_INT
763 #endif // HCF_INT_ON
764
765
766 #if defined HCF_TRACE
767 #define HCFTRACE(ifbp, where ) {OPW( HREG_SW_1, where );}
768 //#define HCFTRACE(ifbp, where ) {HCFASSERT( DO_ASSERT, where );}
769 #define HCFTRACEVALUE(ifbp, what ) {OPW( HREG_SW_2, what );}
770 //#define HCFTRACEVALUE(ifbp, what ) {HCFASSERT( DO_ASSERT, what );}
771 #else
772 #define HCFTRACE(ifbp, where )
773 #define HCFTRACEVALUE(ifbp, what )
774 #endif // HCF_TRACE
775
776
777 #if HCF_BIG_ENDIAN
778 #define BE_PAR(x) ,x
779 #else
780 #define BE_PAR(x)
781 #endif // HCF_BIG_ENDIAN
782
783 /************************************************************************************************/
784 /************************************** END OF MACROS *****************************************/
785 /************************************************************************************************/
786
787 /************************************************************************************************/
788 /*************************************** PROTOTYPES *******************************************/
789 /************************************************************************************************/
790
791 #if HCF_ASSERT
792 extern IFBP BASED assert_ifbp; //to make asserts easily work under MMD and DHF
793 EXTERN_C void mdd_assert (IFBP ifbp, unsigned int line_number, hcf_32 q );
794 #endif //HCF_ASSERT
795
796 #if ! ( (HCF_IO) & HCF_IO_32BITS ) // defined 16 bits only
797 #undef OUT_PORT_STRING_32
798 #undef IN_PORT_STRING_32
799 #endif // HCF_IO
800 #endif //HCFDEFC_H
801
kernel source for telekom puls (alcatel/mediatek)