drivers/staging/rts_pstor/rtsx_chip.h

   1 /* Driver for Realtek PCI-Express card reader
   2  * Header file
   3  *
   4  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2, or (at your option) any
   9  * later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  * Author:
  20  *   wwang (wei_wang@realsil.com.cn)
  21  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  22  */
  23
  24 #ifndef __REALTEK_RTSX_CHIP_H
  25 #define __REALTEK_RTSX_CHIP_H
  26
  27 #include "rtsx.h"
  28
  29 #define SUPPORT_CPRM
  30 #define SUPPORT_OCP
  31 #define SUPPORT_SDIO_ASPM
  32 #define SUPPORT_MAGIC_GATE
  33 #define SUPPORT_MSXC
  34 #define SUPPORT_SD_LOCK
  35 /* Hardware switch bus_ctl and cd_ctl automatically */
  36 #define HW_AUTO_SWITCH_SD_BUS
  37 /* Enable hardware interrupt write clear */
  38 #define HW_INT_WRITE_CLR
  39 /* #define LED_AUTO_BLINK */
  40 /* #define DISABLE_CARD_INT */
  41
  42 #ifdef SUPPORT_MAGIC_GATE
  43         /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */
  44         #define MG_SET_ICV_SLOW
  45         /* HW may miss ERR/CMDNK signal when sampling INT status. */
  46         #define MS_SAMPLE_INT_ERR
  47         /* HW DO NOT support Wait_INT function during READ_BYTES transfer mode */
  48         #define READ_BYTES_WAIT_INT
  49 #endif
  50
  51 #ifdef SUPPORT_MSXC
  52 #define XC_POWERCLASS
  53 #define SUPPORT_PCGL_1P18
  54 #endif
  55
  56 #ifndef LED_AUTO_BLINK
  57 #define REGULAR_BLINK
  58 #endif
  59
  60 #define LED_BLINK_SPEED         5
  61 #define LED_TOGGLE_INTERVAL     6
  62 #define GPIO_TOGGLE_THRESHOLD   1024
  63 #define LED_GPIO                0
  64
  65 #define POLLING_INTERVAL        30
  66
  67 #define TRACE_ITEM_CNT          64
  68
  69 #ifndef STATUS_SUCCESS
  70 #define STATUS_SUCCESS          0
  71 #endif
  72 #ifndef STATUS_FAIL
  73 #define STATUS_FAIL             1
  74 #endif
  75 #ifndef STATUS_TIMEDOUT
  76 #define STATUS_TIMEDOUT         2
  77 #endif
  78 #ifndef STATUS_NOMEM
  79 #define STATUS_NOMEM            3
  80 #endif
  81 #ifndef STATUS_READ_FAIL
  82 #define STATUS_READ_FAIL        4
  83 #endif
  84 #ifndef STATUS_WRITE_FAIL
  85 #define STATUS_WRITE_FAIL       5
  86 #endif
  87 #ifndef STATUS_ERROR
  88 #define STATUS_ERROR            10
  89 #endif
  90
  91 #define PM_S1                   1
  92 #define PM_S3                   3
  93
  94 /*
  95  * Transport return codes
  96  */
  97
  98 #define TRANSPORT_GOOD          0   /* Transport good, command good        */
  99 #define TRANSPORT_FAILED        1   /* Transport good, command failed   */
 100 #define TRANSPORT_NO_SENSE      2  /* Command failed, no auto-sense    */
 101 #define TRANSPORT_ERROR         3   /* Transport bad (i.e. device dead) */
 102
 103
 104 /*-----------------------------------
 105     Start-Stop-Unit
 106 -----------------------------------*/
 107 #define STOP_MEDIUM                     0x00    /* access disable         */
 108 #define MAKE_MEDIUM_READY               0x01    /* access enable          */
 109 #define UNLOAD_MEDIUM                   0x02    /* unload                 */
 110 #define LOAD_MEDIUM                     0x03    /* load                   */
 111
 112 /*-----------------------------------
 113     STANDARD_INQUIRY
 114 -----------------------------------*/
 115 #define QULIFIRE                0x00
 116 #define AENC_FNC                0x00
 117 #define TRML_IOP                0x00
 118 #define REL_ADR                 0x00
 119 #define WBUS_32                 0x00
 120 #define WBUS_16                 0x00
 121 #define SYNC                    0x00
 122 #define LINKED                  0x00
 123 #define CMD_QUE                 0x00
 124 #define SFT_RE                  0x00
 125
 126 #define VEN_ID_LEN              8               /* Vendor ID Length         */
 127 #define PRDCT_ID_LEN            16              /* Product ID Length        */
 128 #define PRDCT_REV_LEN           4               /* Product LOT Length       */
 129
 130 /* Dynamic flag definitions: used in set_bit() etc. */
 131 #define RTSX_FLIDX_TRANS_ACTIVE         18  /* 0x00040000  transfer is active */
 132 #define RTSX_FLIDX_ABORTING             20  /* 0x00100000  abort is in progress */
 133 #define RTSX_FLIDX_DISCONNECTING        21  /* 0x00200000  disconnect in progress */
 134 #define ABORTING_OR_DISCONNECTING       ((1UL << US_FLIDX_ABORTING) | \
 135                                          (1UL << US_FLIDX_DISCONNECTING))
 136 #define RTSX_FLIDX_RESETTING            22  /* 0x00400000  device reset in progress */
 137 #define RTSX_FLIDX_TIMED_OUT            23  /* 0x00800000  SCSI midlayer timed out  */
 138
 139 #define DRCT_ACCESS_DEV         0x00    /* Direct Access Device      */
 140 #define RMB_DISC                0x80    /* The Device is Removable   */
 141 #define ANSI_SCSI2              0x02    /* Based on ANSI-SCSI2       */
 142
 143 #define SCSI                    0x00    /* Interface ID              */
 144
 145 #define WRITE_PROTECTED_MEDIA 0x07
 146
 147 /*---- sense key ----*/
 148 #define ILI                     0x20    /* ILI bit is on                    */
 149
 150 #define NO_SENSE                0x00    /* not exist sense key              */
 151 #define RECOVER_ERR             0x01    /* Target/Logical unit is recoverd  */
 152 #define NOT_READY               0x02    /* Logical unit is not ready        */
 153 #define MEDIA_ERR               0x03    /* medium/data error                */
 154 #define HARDWARE_ERR            0x04    /* hardware error                   */
 155 #define ILGAL_REQ               0x05    /* CDB/parameter/identify msg error */
 156 #define UNIT_ATTENTION          0x06    /* unit attention condition occur   */
 157 #define DAT_PRTCT               0x07    /* read/write is desable            */
 158 #define BLNC_CHK                0x08    /* find blank/DOF in read           */
 159                                         /* write to unblank area            */
 160 #define CPY_ABRT                0x0a    /* Copy/Compare/Copy&Verify illgal  */
 161 #define ABRT_CMD                0x0b    /* Target make the command in error */
 162 #define EQUAL                   0x0c    /* Search Data end with Equal       */
 163 #define VLM_OVRFLW              0x0d    /* Some data are left in buffer     */
 164 #define MISCMP                  0x0e    /* find inequality                  */
 165
 166 #define READ_ERR                -1
 167 #define WRITE_ERR               -2
 168
 169 #define FIRST_RESET             0x01
 170 #define USED_EXIST              0x02
 171
 172 /*-----------------------------------
 173     SENSE_DATA
 174 -----------------------------------*/
 175 /*---- valid ----*/
 176 #define SENSE_VALID             0x80    /* Sense data is valid as SCSI2     */
 177 #define SENSE_INVALID           0x00    /* Sense data is invalid as SCSI2   */
 178
 179 /*---- error code ----*/
 180 #define CUR_ERR                 0x70    /* current error                    */
 181 #define DEF_ERR                 0x71    /* specific command error           */
 182
 183 /*---- sense key Information ----*/
 184 #define SNSKEYINFO_LEN          3       /* length of sense key information   */
 185
 186 #define SKSV                    0x80
 187 #define CDB_ILLEGAL             0x40
 188 #define DAT_ILLEGAL             0x00
 189 #define BPV                     0x08
 190 #define BIT_ILLEGAL0            0       /* bit0 is illegal                  */
 191 #define BIT_ILLEGAL1            1       /* bit1 is illegal                  */
 192 #define BIT_ILLEGAL2            2       /* bit2 is illegal                  */
 193 #define BIT_ILLEGAL3            3       /* bit3 is illegal                  */
 194 #define BIT_ILLEGAL4            4       /* bit4 is illegal                  */
 195 #define BIT_ILLEGAL5            5       /* bit5 is illegal                  */
 196 #define BIT_ILLEGAL6            6       /* bit6 is illegal                  */
 197 #define BIT_ILLEGAL7            7       /* bit7 is illegal                  */
 198
 199 /*---- ASC ----*/
 200 #define ASC_NO_INFO             0x00
 201 #define ASC_MISCMP              0x1d
 202 #define ASC_INVLD_CDB           0x24
 203 #define ASC_INVLD_PARA          0x26
 204 #define ASC_LU_NOT_READY        0x04
 205 #define ASC_WRITE_ERR           0x0c
 206 #define ASC_READ_ERR            0x11
 207 #define ASC_LOAD_EJCT_ERR       0x53
 208 #define ASC_MEDIA_NOT_PRESENT   0x3A
 209 #define ASC_MEDIA_CHANGED       0x28
 210 #define ASC_MEDIA_IN_PROCESS    0x04
 211 #define ASC_WRITE_PROTECT       0x27
 212 #define ASC_LUN_NOT_SUPPORTED   0x25
 213
 214 /*---- ASQC ----*/
 215 #define ASCQ_NO_INFO            0x00
 216 #define ASCQ_MEDIA_IN_PROCESS   0x01
 217 #define ASCQ_MISCMP             0x00
 218 #define ASCQ_INVLD_CDB          0x00
 219 #define ASCQ_INVLD_PARA         0x02
 220 #define ASCQ_LU_NOT_READY       0x02
 221 #define ASCQ_WRITE_ERR          0x02
 222 #define ASCQ_READ_ERR           0x00
 223 #define ASCQ_LOAD_EJCT_ERR      0x00
 224 #define ASCQ_WRITE_PROTECT      0x00
 225
 226
 227 struct sense_data_t {
 228     unsigned char   err_code;           /* error code */
 229                                                 /* bit7 : valid                    */
 230                                                 /*   (1 : SCSI2)                    */
 231                                                 /*   (0 : Vendor specific)          */
 232                                                 /* bit6-0 : error code             */
 233                                                 /*  (0x70 : current error)          */
 234                                                 /*  (0x71 : specific command error) */
 235     unsigned char   seg_no;             /* segment No.                      */
 236     unsigned char   sense_key;          /* byte5 : ILI                      */
 237                                                 /* bit3-0 : sense key              */
 238     unsigned char   info[4];            /* information                       */
 239     unsigned char   ad_sense_len;       /* additional sense data length     */
 240     unsigned char   cmd_info[4];        /* command specific information      */
 241     unsigned char   asc;                /* ASC                              */
 242     unsigned char   ascq;               /* ASCQ                             */
 243     unsigned char   rfu;                /* FRU                              */
 244     unsigned char   sns_key_info[3];    /* sense key specific information    */
 245 };
 246
 247 /* PCI Operation Register Address */
 248 #define RTSX_HCBAR              0x00
 249 #define RTSX_HCBCTLR            0x04
 250 #define RTSX_HDBAR              0x08
 251 #define RTSX_HDBCTLR            0x0C
 252 #define RTSX_HAIMR              0x10
 253 #define RTSX_BIPR               0x14
 254 #define RTSX_BIER               0x18
 255
 256 /* Host command buffer control register */
 257 #define STOP_CMD                (0x01 << 28)
 258
 259 /* Host data buffer control register */
 260 #define SDMA_MODE               0x00
 261 #define ADMA_MODE               (0x02 << 26)
 262 #define STOP_DMA                (0x01 << 28)
 263 #define TRIG_DMA                (0x01 << 31)
 264
 265 /* Bus interrupt pending register */
 266 #define CMD_DONE_INT            (1 << 31)
 267 #define DATA_DONE_INT           (1 << 30)
 268 #define TRANS_OK_INT            (1 << 29)
 269 #define TRANS_FAIL_INT          (1 << 28)
 270 #define XD_INT                  (1 << 27)
 271 #define MS_INT                  (1 << 26)
 272 #define SD_INT                  (1 << 25)
 273 #define GPIO0_INT               (1 << 24)
 274 #define OC_INT                  (1 << 23)
 275 #define SD_WRITE_PROTECT        (1 << 19)
 276 #define XD_EXIST                (1 << 18)
 277 #define MS_EXIST                (1 << 17)
 278 #define SD_EXIST                (1 << 16)
 279 #define DELINK_INT              GPIO0_INT
 280 #define MS_OC_INT               (1 << 23)
 281 #define SD_OC_INT               (1 << 22)
 282
 283 #define CARD_INT                (XD_INT | MS_INT | SD_INT)
 284 #define NEED_COMPLETE_INT       (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT)
 285 #define RTSX_INT                (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | GPIO0_INT | OC_INT)
 286
 287 #define CARD_EXIST              (XD_EXIST | MS_EXIST | SD_EXIST)
 288
 289 /* Bus interrupt enable register */
 290 #define CMD_DONE_INT_EN         (1 << 31)
 291 #define DATA_DONE_INT_EN        (1 << 30)
 292 #define TRANS_OK_INT_EN         (1 << 29)
 293 #define TRANS_FAIL_INT_EN       (1 << 28)
 294 #define XD_INT_EN               (1 << 27)
 295 #define MS_INT_EN               (1 << 26)
 296 #define SD_INT_EN               (1 << 25)
 297 #define GPIO0_INT_EN            (1 << 24)
 298 #define OC_INT_EN               (1 << 23)
 299 #define DELINK_INT_EN           GPIO0_INT_EN
 300 #define MS_OC_INT_EN            (1 << 23)
 301 #define SD_OC_INT_EN            (1 << 22)
 302
 303
 304 #define READ_REG_CMD            0
 305 #define WRITE_REG_CMD           1
 306 #define CHECK_REG_CMD           2
 307
 308 #define HOST_TO_DEVICE          0
 309 #define DEVICE_TO_HOST          1
 310
 311
 312 #define RTSX_RESV_BUF_LEN       4096
 313 #define HOST_CMDS_BUF_LEN       1024
 314 #define HOST_SG_TBL_BUF_LEN     (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN)
 315
 316 #define SD_NR           2
 317 #define MS_NR           3
 318 #define XD_NR           4
 319 #define SPI_NR          7
 320 #define SD_CARD         (1 << SD_NR)
 321 #define MS_CARD         (1 << MS_NR)
 322 #define XD_CARD         (1 << XD_NR)
 323 #define SPI_CARD        (1 << SPI_NR)
 324
 325 #define MAX_ALLOWED_LUN_CNT     8
 326
 327 #define XD_FREE_TABLE_CNT       1200
 328 #define MS_FREE_TABLE_CNT       512
 329
 330
 331 /* Bit Operation */
 332 #define SET_BIT(data, idx)      ((data) |= 1 << (idx))
 333 #define CLR_BIT(data, idx)      ((data) &= ~(1 << (idx)))
 334 #define CHK_BIT(data, idx)      ((data) & (1 << (idx)))
 335
 336 /* SG descriptor */
 337 #define SG_INT                  0x04
 338 #define SG_END                  0x02
 339 #define SG_VALID                0x01
 340
 341 #define SG_NO_OP                0x00
 342 #define SG_TRANS_DATA           (0x02 << 4)
 343 #define SG_LINK_DESC            (0x03 << 4)
 344
 345 struct rtsx_chip;
 346
 347 typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 sec_addr, u16 sec_cnt);
 348
 349 /* Supported Clock */
 350 enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, CLK_80, CLK_100, CLK_120, CLK_150, CLK_200};
 351
 352 enum RTSX_STAT  {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS,
 353                 RTSX_STAT_DELINK, RTSX_STAT_SUSPEND, RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT};
 354 enum IC_VER     {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3};
 355
 356 #define MAX_RESET_CNT           3
 357
 358 /* For MS Card */
 359 #define MAX_DEFECTIVE_BLOCK     10
 360
 361 struct zone_entry {
 362         u16 *l2p_table;
 363         u16 *free_table;
 364         u16 defect_list[MAX_DEFECTIVE_BLOCK];  /* For MS card only */
 365         int set_index;
 366         int get_index;
 367         int unused_blk_cnt;
 368         int disable_count;
 369         /* To indicate whether the L2P table of this zone has been built. */
 370         int build_flag;
 371 };
 372
 373 #define TYPE_SD                 0x0000
 374 #define TYPE_MMC                0x0001
 375
 376 /* TYPE_SD */
 377 #define SD_HS                   0x0100
 378 #define SD_SDR50                0x0200
 379 #define SD_DDR50                0x0400
 380 #define SD_SDR104               0x0800
 381 #define SD_HCXC                 0x1000
 382
 383 /* TYPE_MMC */
 384 #define MMC_26M                 0x0100
 385 #define MMC_52M                 0x0200
 386 #define MMC_4BIT                0x0400
 387 #define MMC_8BIT                0x0800
 388 #define MMC_SECTOR_MODE         0x1000
 389 #define MMC_DDR52               0x2000
 390
 391 /* SD card */
 392 #define CHK_SD(sd_card)                 (((sd_card)->sd_type & 0xFF) == TYPE_SD)
 393 #define CHK_SD_HS(sd_card)              (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS))
 394 #define CHK_SD_SDR50(sd_card)           (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50))
 395 #define CHK_SD_DDR50(sd_card)           (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50))
 396 #define CHK_SD_SDR104(sd_card)          (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104))
 397 #define CHK_SD_HCXC(sd_card)            (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC))
 398 #define CHK_SD_HC(sd_card)              (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity <= 0x4000000))
 399 #define CHK_SD_XC(sd_card)              (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity > 0x4000000))
 400 #define CHK_SD30_SPEED(sd_card)         (CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) || CHK_SD_SDR104(sd_card))
 401
 402 #define SET_SD(sd_card)                 ((sd_card)->sd_type = TYPE_SD)
 403 #define SET_SD_HS(sd_card)              ((sd_card)->sd_type |= SD_HS)
 404 #define SET_SD_SDR50(sd_card)           ((sd_card)->sd_type |= SD_SDR50)
 405 #define SET_SD_DDR50(sd_card)           ((sd_card)->sd_type |= SD_DDR50)
 406 #define SET_SD_SDR104(sd_card)          ((sd_card)->sd_type |= SD_SDR104)
 407 #define SET_SD_HCXC(sd_card)            ((sd_card)->sd_type |= SD_HCXC)
 408
 409 #define CLR_SD_HS(sd_card)              ((sd_card)->sd_type &= ~SD_HS)
 410 #define CLR_SD_SDR50(sd_card)           ((sd_card)->sd_type &= ~SD_SDR50)
 411 #define CLR_SD_DDR50(sd_card)           ((sd_card)->sd_type &= ~SD_DDR50)
 412 #define CLR_SD_SDR104(sd_card)          ((sd_card)->sd_type &= ~SD_SDR104)
 413 #define CLR_SD_HCXC(sd_card)            ((sd_card)->sd_type &= ~SD_HCXC)
 414
 415 /* MMC card */
 416 #define CHK_MMC(sd_card)                (((sd_card)->sd_type & 0xFF) == TYPE_MMC)
 417 #define CHK_MMC_26M(sd_card)            (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M))
 418 #define CHK_MMC_52M(sd_card)            (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M))
 419 #define CHK_MMC_4BIT(sd_card)           (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT))
 420 #define CHK_MMC_8BIT(sd_card)           (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT))
 421 #define CHK_MMC_SECTOR_MODE(sd_card)    (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE))
 422 #define CHK_MMC_DDR52(sd_card)          (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52))
 423
 424 #define SET_MMC(sd_card)                ((sd_card)->sd_type = TYPE_MMC)
 425 #define SET_MMC_26M(sd_card)            ((sd_card)->sd_type |= MMC_26M)
 426 #define SET_MMC_52M(sd_card)            ((sd_card)->sd_type |= MMC_52M)
 427 #define SET_MMC_4BIT(sd_card)           ((sd_card)->sd_type |= MMC_4BIT)
 428 #define SET_MMC_8BIT(sd_card)           ((sd_card)->sd_type |= MMC_8BIT)
 429 #define SET_MMC_SECTOR_MODE(sd_card)    ((sd_card)->sd_type |= MMC_SECTOR_MODE)
 430 #define SET_MMC_DDR52(sd_card)          ((sd_card)->sd_type |= MMC_DDR52)
 431
 432 #define CLR_MMC_26M(sd_card)            ((sd_card)->sd_type &= ~MMC_26M)
 433 #define CLR_MMC_52M(sd_card)            ((sd_card)->sd_type &= ~MMC_52M)
 434 #define CLR_MMC_4BIT(sd_card)           ((sd_card)->sd_type &= ~MMC_4BIT)
 435 #define CLR_MMC_8BIT(sd_card)           ((sd_card)->sd_type &= ~MMC_8BIT)
 436 #define CLR_MMC_SECTOR_MODE(sd_card)    ((sd_card)->sd_type &= ~MMC_SECTOR_MODE)
 437 #define CLR_MMC_DDR52(sd_card)          ((sd_card)->sd_type &= ~MMC_DDR52)
 438
 439 #define CHK_MMC_HS(sd_card)             (CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card))
 440 #define CLR_MMC_HS(sd_card)                     \
 441 do {                                            \
 442         CLR_MMC_DDR52(sd_card);                 \
 443         CLR_MMC_52M(sd_card);                   \
 444         CLR_MMC_26M(sd_card);                   \
 445 } while (0)
 446
 447 #define SD_SUPPORT_CLASS_TEN            0x01
 448 #define SD_SUPPORT_1V8                  0x02
 449
 450 #define SD_SET_CLASS_TEN(sd_card)       ((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN)
 451 #define SD_CHK_CLASS_TEN(sd_card)       ((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN)
 452 #define SD_CLR_CLASS_TEN(sd_card)       ((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN)
 453 #define SD_SET_1V8(sd_card)             ((sd_card)->sd_setting |= SD_SUPPORT_1V8)
 454 #define SD_CHK_1V8(sd_card)             ((sd_card)->sd_setting & SD_SUPPORT_1V8)
 455 #define SD_CLR_1V8(sd_card)             ((sd_card)->sd_setting &= ~SD_SUPPORT_1V8)
 456
 457 struct sd_info {
 458         u16 sd_type;
 459         u8 err_code;
 460         u8 sd_data_buf_ready;
 461         u32 sd_addr;
 462         u32 capacity;
 463
 464         u8 raw_csd[16];
 465         u8 raw_scr[8];
 466
 467         /* Sequential RW */
 468         int seq_mode;
 469         enum dma_data_direction pre_dir;
 470         u32 pre_sec_addr;
 471         u16 pre_sec_cnt;
 472
 473         int cleanup_counter;
 474
 475         int sd_clock;
 476
 477         int mmc_dont_switch_bus;
 478
 479 #ifdef SUPPORT_CPRM
 480         int sd_pass_thru_en;
 481         int pre_cmd_err;
 482         u8 last_rsp_type;
 483         u8 rsp[17];
 484 #endif
 485
 486         u8 func_group1_mask;
 487         u8 func_group2_mask;
 488         u8 func_group3_mask;
 489         u8 func_group4_mask;
 490
 491         u8 sd_switch_fail;
 492         u8 sd_read_phase;
 493
 494 #ifdef SUPPORT_SD_LOCK
 495         u8 sd_lock_status;
 496         u8 sd_erase_status;
 497         u8 sd_lock_notify;
 498 #endif
 499         int need_retune;
 500 };
 501
 502 struct xd_delay_write_tag {
 503         u32 old_phyblock;
 504         u32 new_phyblock;
 505         u32 logblock;
 506         u8 pageoff;
 507         u8 delay_write_flag;
 508 };
 509
 510 struct xd_info {
 511         u8 maker_code;
 512         u8 device_code;
 513         u8 block_shift;
 514         u8 page_off;
 515         u8 addr_cycle;
 516         u16 cis_block;
 517         u8 multi_flag;
 518         u8 err_code;
 519         u32 capacity;
 520
 521         struct zone_entry *zone;
 522         int zone_cnt;
 523
 524         struct xd_delay_write_tag delay_write;
 525         int cleanup_counter;
 526
 527         int xd_clock;
 528 };
 529
 530 #define MODE_512_SEQ            0x01
 531 #define MODE_2K_SEQ             0x02
 532
 533 #define TYPE_MS                 0x0000
 534 #define TYPE_MSPRO              0x0001
 535
 536 #define MS_4BIT                 0x0100
 537 #define MS_8BIT                 0x0200
 538 #define MS_HG                   0x0400
 539 #define MS_XC                   0x0800
 540
 541 #define HG8BIT                  (MS_HG | MS_8BIT)
 542
 543 #define CHK_MSPRO(ms_card)      (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO)
 544 #define CHK_HG8BIT(ms_card)     (CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT))
 545 #define CHK_MSXC(ms_card)       (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC))
 546 #define CHK_MSHG(ms_card)       (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG))
 547
 548 #define CHK_MS8BIT(ms_card)     (((ms_card)->ms_type & MS_8BIT))
 549 #define CHK_MS4BIT(ms_card)     (((ms_card)->ms_type & MS_4BIT))
 550
 551 struct ms_delay_write_tag {
 552         u16 old_phyblock;
 553         u16 new_phyblock;
 554         u16 logblock;
 555         u8 pageoff;
 556         u8 delay_write_flag;
 557 };
 558
 559 struct ms_info {
 560         u16 ms_type;
 561         u8 block_shift;
 562         u8 page_off;
 563         u16 total_block;
 564         u16 boot_block;
 565         u32 capacity;
 566
 567         u8 check_ms_flow;
 568         u8 switch_8bit_fail;
 569         u8 err_code;
 570
 571         struct zone_entry *segment;
 572         int segment_cnt;
 573
 574         int pro_under_formatting;
 575         int format_status;
 576         u16 progress;
 577         u8 raw_sys_info[96];
 578 #ifdef SUPPORT_PCGL_1P18
 579         u8 raw_model_name[48];
 580 #endif
 581
 582         u8 multi_flag;
 583
 584         /* Sequential RW */
 585         u8 seq_mode;
 586         enum dma_data_direction pre_dir;
 587         u32 pre_sec_addr;
 588         u16 pre_sec_cnt;
 589         u32 total_sec_cnt;
 590
 591         struct ms_delay_write_tag delay_write;
 592
 593         int cleanup_counter;
 594
 595         int ms_clock;
 596
 597 #ifdef SUPPORT_MAGIC_GATE
 598         u8 magic_gate_id[16];
 599         u8 mg_entry_num;
 600         int mg_auth;    /* flag to indicate authentication process */
 601 #endif
 602 };
 603
 604 struct spi_info {
 605         u8 use_clk;
 606         u8 write_en;
 607         u16 clk_div;
 608         u8 err_code;
 609
 610         int spi_clock;
 611 };
 612
 613
 614 #ifdef _MSG_TRACE
 615 struct trace_msg_t {
 616         u16 line;
 617 #define MSG_FUNC_LEN 64
 618         char func[MSG_FUNC_LEN];
 619 #define MSG_FILE_LEN 32
 620         char file[MSG_FILE_LEN];
 621 #define TIME_VAL_LEN 16
 622         u8 timeval_buf[TIME_VAL_LEN];
 623         u8 valid;
 624 };
 625 #endif
 626
 627 /************/
 628 /* LUN mode */
 629 /************/
 630 /* Single LUN, support xD/SD/MS */
 631 #define DEFAULT_SINGLE          0
 632 /* 2 LUN mode, support SD/MS */
 633 #define SD_MS_2LUN              1
 634 /* Single LUN, but only support SD/MS, for Barossa LQFP */
 635 #define SD_MS_1LUN              2
 636
 637 #define LAST_LUN_MODE           2
 638
 639 /* Barossa package */
 640 #define QFN             0
 641 #define LQFP            1
 642
 643 /******************/
 644 /* sd_ctl bit map */
 645 /******************/
 646 /* SD push point control, bit 0, 1 */
 647 #define SD_PUSH_POINT_CTL_MASK          0x03
 648 #define SD_PUSH_POINT_DELAY             0x01
 649 #define SD_PUSH_POINT_AUTO              0x02
 650 /* SD sample point control, bit 2, 3 */
 651 #define SD_SAMPLE_POINT_CTL_MASK        0x0C
 652 #define SD_SAMPLE_POINT_DELAY           0x04
 653 #define SD_SAMPLE_POINT_AUTO            0x08
 654 /* SD DDR Tx phase set by user, bit 4 */
 655 #define SD_DDR_TX_PHASE_SET_BY_USER     0x10
 656 /* MMC DDR Tx phase set by user, bit 5 */
 657 #define MMC_DDR_TX_PHASE_SET_BY_USER    0x20
 658 /* Support MMC DDR mode, bit 6 */
 659 #define SUPPORT_MMC_DDR_MODE            0x40
 660 /* Reset MMC at first */
 661 #define RESET_MMC_FIRST                 0x80
 662
 663 #define SEQ_START_CRITERIA              0x20
 664
 665 /* MS Power Class En */
 666 #define POWER_CLASS_2_EN                0x02
 667 #define POWER_CLASS_1_EN                0x01
 668
 669 #define MAX_SHOW_CNT                    10
 670 #define MAX_RESET_CNT                   3
 671
 672 #define SDIO_EXIST                      0x01
 673 #define SDIO_IGNORED                    0x02
 674
 675 #define CHK_SDIO_EXIST(chip)            ((chip)->sdio_func_exist & SDIO_EXIST)
 676 #define SET_SDIO_EXIST(chip)            ((chip)->sdio_func_exist |= SDIO_EXIST)
 677 #define CLR_SDIO_EXIST(chip)            ((chip)->sdio_func_exist &= ~SDIO_EXIST)
 678
 679 #define CHK_SDIO_IGNORED(chip)          ((chip)->sdio_func_exist & SDIO_IGNORED)
 680 #define SET_SDIO_IGNORED(chip)          ((chip)->sdio_func_exist |= SDIO_IGNORED)
 681 #define CLR_SDIO_IGNORED(chip)          ((chip)->sdio_func_exist &= ~SDIO_IGNORED)
 682
 683 struct rtsx_chip {
 684         rtsx_dev_t              *rtsx;
 685
 686         u32                     int_reg;                /* Bus interrupt pending register */
 687         char                    max_lun;
 688         void                    *context;
 689
 690         void                    *host_cmds_ptr;         /* host commands buffer pointer */
 691         dma_addr_t              host_cmds_addr;
 692         int                     ci;                     /* Command Index */
 693
 694         void                    *host_sg_tbl_ptr;       /* SG descriptor table */
 695         dma_addr_t              host_sg_tbl_addr;
 696         int                     sgi;                    /* SG entry index */
 697
 698         struct scsi_cmnd        *srb;                   /* current srb */
 699         struct sense_data_t     sense_buffer[MAX_ALLOWED_LUN_CNT];
 700
 701         int                     cur_clk;                /* current card clock */
 702
 703         /* Current accessed card */
 704         int                     cur_card;
 705
 706         unsigned long           need_release;           /* need release bit map */
 707         unsigned long           need_reset;             /* need reset bit map */
 708         /* Flag to indicate that this card is just resumed from SS state,
 709          * and need released before being resetted
 710          */
 711         unsigned long           need_reinit;
 712
 713         int                     rw_need_retry;
 714
 715 #ifdef SUPPORT_OCP
 716         u32                     ocp_int;
 717         u8                      ocp_stat;
 718 #endif
 719
 720         u8                      card_exist;             /* card exist bit map (physical exist) */
 721         u8                      card_ready;             /* card ready bit map (reset successfully) */
 722         u8                      card_fail;              /* card reset fail bit map */
 723         u8                      card_ejected;           /* card ejected bit map */
 724         u8                      card_wp;                /* card write protected bit map */
 725
 726         u8                      lun_mc;                 /* flag to indicate whether to answer MediaChange */
 727
 728 #ifndef LED_AUTO_BLINK
 729         int                     led_toggle_counter;
 730 #endif
 731
 732         int                     sd_reset_counter;
 733         int                     xd_reset_counter;
 734         int                     ms_reset_counter;
 735
 736         /* card bus width */
 737         u8                      card_bus_width[MAX_ALLOWED_LUN_CNT];
 738         /* card capacity */
 739         u32                     capacity[MAX_ALLOWED_LUN_CNT];
 740         /* read/write card function pointer */
 741         card_rw_func            rw_card[MAX_ALLOWED_LUN_CNT];
 742         /* read/write capacity, used for GPIO Toggle */
 743         u32                     rw_cap[MAX_ALLOWED_LUN_CNT];
 744         /* card to lun mapping table */
 745         u8                      card2lun[32];
 746         /* lun to card mapping table */
 747         u8                      lun2card[MAX_ALLOWED_LUN_CNT];
 748
 749         int                     rw_fail_cnt[MAX_ALLOWED_LUN_CNT];
 750
 751         int                     sd_show_cnt;
 752         int                     xd_show_cnt;
 753         int                     ms_show_cnt;
 754
 755         /* card information */
 756         struct sd_info          sd_card;
 757         struct xd_info          xd_card;
 758         struct ms_info          ms_card;
 759
 760         struct spi_info         spi;
 761
 762 #ifdef _MSG_TRACE
 763         struct trace_msg_t      trace_msg[TRACE_ITEM_CNT];
 764         int                     msg_idx;
 765 #endif
 766
 767         int                     auto_delink_cnt;
 768         int                     auto_delink_allowed;
 769
 770         int                     aspm_enabled;
 771
 772         int                     sdio_aspm;
 773         int                     sdio_idle;
 774         int                     sdio_counter;
 775         u8                      sdio_raw_data[12];
 776
 777         u8                      sd_io;
 778         u8                      sd_int;
 779
 780         u8                      rtsx_flag;
 781
 782         int                     ss_counter;
 783         int                     idle_counter;
 784         enum RTSX_STAT          rtsx_stat;
 785
 786         u16                     vendor_id;
 787         u16                     product_id;
 788         u8                      ic_version;
 789
 790         int                     driver_first_load;
 791
 792 #ifdef HW_AUTO_SWITCH_SD_BUS
 793         int                     sdio_in_charge;
 794 #endif
 795
 796         u8                      aspm_level[2];
 797
 798         int                     chip_insert_with_sdio;
 799
 800         /* Options */
 801
 802         int adma_mode;
 803
 804         int auto_delink_en;
 805         int ss_en;
 806         u8 lun_mode;
 807         u8 aspm_l0s_l1_en;
 808
 809         int power_down_in_ss;
 810
 811         int sdr104_en;
 812         int ddr50_en;
 813         int sdr50_en;
 814
 815         int baro_pkg;
 816
 817         int asic_code;
 818         int phy_debug_mode;
 819         int hw_bypass_sd;
 820         int sdio_func_exist;
 821         int aux_pwr_exist;
 822         u8 ms_power_class_en;
 823
 824         int mspro_formatter_enable;
 825
 826         int remote_wakeup_en;
 827
 828         int ignore_sd;
 829         int use_hw_setting;
 830
 831         int ss_idle_period;
 832
 833         int dynamic_aspm;
 834
 835         int fpga_sd_sdr104_clk;
 836         int fpga_sd_ddr50_clk;
 837         int fpga_sd_sdr50_clk;
 838         int fpga_sd_hs_clk;
 839         int fpga_mmc_52m_clk;
 840         int fpga_ms_hg_clk;
 841         int fpga_ms_4bit_clk;
 842         int fpga_ms_1bit_clk;
 843
 844         int asic_sd_sdr104_clk;
 845         int asic_sd_ddr50_clk;
 846         int asic_sd_sdr50_clk;
 847         int asic_sd_hs_clk;
 848         int asic_mmc_52m_clk;
 849         int asic_ms_hg_clk;
 850         int asic_ms_4bit_clk;
 851         int asic_ms_1bit_clk;
 852
 853         u8 ssc_depth_sd_sdr104;
 854         u8 ssc_depth_sd_ddr50;
 855         u8 ssc_depth_sd_sdr50;
 856         u8 ssc_depth_sd_hs;
 857         u8 ssc_depth_mmc_52m;
 858         u8 ssc_depth_ms_hg;
 859         u8 ssc_depth_ms_4bit;
 860         u8 ssc_depth_low_speed;
 861
 862         u8 card_drive_sel;
 863         u8 sd30_drive_sel_1v8;
 864         u8 sd30_drive_sel_3v3;
 865
 866         u8 sd_400mA_ocp_thd;
 867         u8 sd_800mA_ocp_thd;
 868         u8 ms_ocp_thd;
 869
 870         int ssc_en;
 871         int msi_en;
 872
 873         int xd_timeout;
 874         int sd_timeout;
 875         int ms_timeout;
 876         int mspro_timeout;
 877
 878         int auto_power_down;
 879
 880         int sd_ddr_tx_phase;
 881         int mmc_ddr_tx_phase;
 882         int sd_default_tx_phase;
 883         int sd_default_rx_phase;
 884
 885         int pmos_pwr_on_interval;
 886         int sd_voltage_switch_delay;
 887         int s3_pwr_off_delay;
 888
 889         int force_clkreq_0;
 890         int ft2_fast_mode;
 891
 892         int do_delink_before_power_down;
 893         int polling_config;
 894         int sdio_retry_cnt;
 895
 896         int delink_stage1_step;
 897         int delink_stage2_step;
 898         int delink_stage3_step;
 899
 900         int auto_delink_in_L1;
 901         int hp_watch_bios_hotplug;
 902         int support_ms_8bit;
 903
 904         u8 blink_led;
 905         u8 phy_voltage;
 906         u8 max_payload;
 907
 908         u32 sd_speed_prior;
 909         u32 sd_current_prior;
 910         u32 sd_ctl;
 911 };
 912
 913 #define rtsx_set_stat(chip, stat)                               \
 914 do {                                                            \
 915         if ((stat) != RTSX_STAT_IDLE) {                         \
 916                 (chip)->idle_counter = 0;                       \
 917         }                                                       \
 918         (chip)->rtsx_stat = (enum RTSX_STAT)(stat);             \
 919 } while (0)
 920 #define rtsx_get_stat(chip)             ((chip)->rtsx_stat)
 921 #define rtsx_chk_stat(chip, stat)       ((chip)->rtsx_stat == (stat))
 922
 923 #define RTSX_SET_DELINK(chip)   ((chip)->rtsx_flag |= 0x01)
 924 #define RTSX_CLR_DELINK(chip)   ((chip)->rtsx_flag &= 0xFE)
 925 #define RTSX_TST_DELINK(chip)   ((chip)->rtsx_flag & 0x01)
 926
 927 #define CHECK_PID(chip, pid)            ((chip)->product_id == (pid))
 928 #define CHECK_BARO_PKG(chip, pkg)       ((chip)->baro_pkg == (pkg))
 929 #define CHECK_LUN_MODE(chip, mode)      ((chip)->lun_mode == (mode))
 930
 931 /* Power down control */
 932 #define SSC_PDCTL               0x01
 933 #define OC_PDCTL                0x02
 934
 935 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl);
 936 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl);
 937
 938 void rtsx_disable_card_int(struct rtsx_chip *chip);
 939 void rtsx_enable_card_int(struct rtsx_chip *chip);
 940 void rtsx_enable_bus_int(struct rtsx_chip *chip);
 941 void rtsx_disable_bus_int(struct rtsx_chip *chip);
 942 int rtsx_reset_chip(struct rtsx_chip *chip);
 943 int rtsx_init_chip(struct rtsx_chip *chip);
 944 void rtsx_release_chip(struct rtsx_chip *chip);
 945 void rtsx_polling_func(struct rtsx_chip *chip);
 946 void rtsx_undo_delink(struct rtsx_chip *chip);
 947 void rtsx_stop_cmd(struct rtsx_chip *chip, int card);
 948 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data);
 949 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data);
 950 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val);
 951 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val);
 952 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len);
 953 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len);
 954 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val);
 955 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val);
 956 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val);
 957 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val);
 958 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
 959 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit);
 960 int rtsx_check_link_ready(struct rtsx_chip *chip);
 961 void rtsx_enter_ss(struct rtsx_chip *chip);
 962 void rtsx_exit_ss(struct rtsx_chip *chip);
 963 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip);
 964 void rtsx_enter_L1(struct rtsx_chip *chip);
 965 void rtsx_exit_L1(struct rtsx_chip *chip);
 966 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat);
 967 void rtsx_enable_aspm(struct rtsx_chip *chip);
 968 void rtsx_disable_aspm(struct rtsx_chip *chip);
 969 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
 970 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len);
 971 int rtsx_check_chip_exist(struct rtsx_chip *chip);
 972
 973 #define RTSX_WRITE_REG(chip, addr, mask, data)                                  \
 974 do {                                                                            \
 975         int retval = rtsx_write_register((chip), (addr), (mask), (data));       \
 976         if (retval != STATUS_SUCCESS) {                                         \
 977                 TRACE_RET((chip), retval);                                      \
 978         }                                                                       \
 979 } while (0)
 980
 981 #define RTSX_READ_REG(chip, addr, data)                                         \
 982 do {                                                                            \
 983         int retval = rtsx_read_register((chip), (addr), (data));                \
 984         if (retval != STATUS_SUCCESS) {                                         \
 985                 TRACE_RET((chip), retval);                                      \
 986         }                                                                       \
 987 } while (0)
 988
 989 #endif  /* __REALTEK_RTSX_CHIP_H */