Merge tag 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / imx-drm / ipuv3-crtc.c
1 /*
2 * i.MX IPUv3 Graphics driver
3 *
4 * Copyright (C) 2011 Sascha Hauer, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20 #include <linux/module.h>
21 #include <linux/export.h>
22 #include <linux/device.h>
23 #include <linux/platform_device.h>
24 #include <drm/drmP.h>
25 #include <drm/drm_fb_helper.h>
26 #include <drm/drm_crtc_helper.h>
27 #include <linux/fb.h>
28 #include <linux/clk.h>
29 #include <drm/drm_gem_cma_helper.h>
30 #include <drm/drm_fb_cma_helper.h>
31
32 #include "ipu-v3/imx-ipu-v3.h"
33 #include "imx-drm.h"
34
35 #define DRIVER_DESC "i.MX IPUv3 Graphics"
36
37 struct ipu_framebuffer {
38 struct drm_framebuffer base;
39 void *virt;
40 dma_addr_t phys;
41 size_t len;
42 };
43
44 struct ipu_crtc {
45 struct drm_fb_helper fb_helper;
46 struct ipu_framebuffer ifb;
47 int num_crtcs;
48 struct device *dev;
49 struct drm_crtc base;
50 struct imx_drm_crtc *imx_crtc;
51 struct ipuv3_channel *ipu_ch;
52 struct ipu_dc *dc;
53 struct ipu_dp *dp;
54 struct dmfc_channel *dmfc;
55 struct ipu_di *di;
56 int enabled;
57 struct ipu_priv *ipu_priv;
58 struct drm_pending_vblank_event *page_flip_event;
59 struct drm_framebuffer *newfb;
60 int irq;
61 u32 interface_pix_fmt;
62 unsigned long di_clkflags;
63 int di_hsync_pin;
64 int di_vsync_pin;
65 };
66
67 #define to_ipu_crtc(x) container_of(x, struct ipu_crtc, base)
68
69 static int calc_vref(struct drm_display_mode *mode)
70 {
71 unsigned long htotal, vtotal;
72
73 htotal = mode->htotal;
74 vtotal = mode->vtotal;
75
76 if (!htotal || !vtotal)
77 return 60;
78
79 return mode->clock * 1000 / vtotal / htotal;
80 }
81
82 static int calc_bandwidth(struct drm_display_mode *mode, unsigned int vref)
83 {
84 return mode->hdisplay * mode->vdisplay * vref;
85 }
86
87 static void ipu_fb_enable(struct ipu_crtc *ipu_crtc)
88 {
89 if (ipu_crtc->enabled)
90 return;
91
92 ipu_di_enable(ipu_crtc->di);
93 ipu_dmfc_enable_channel(ipu_crtc->dmfc);
94 ipu_idmac_enable_channel(ipu_crtc->ipu_ch);
95 ipu_dc_enable_channel(ipu_crtc->dc);
96 if (ipu_crtc->dp)
97 ipu_dp_enable_channel(ipu_crtc->dp);
98
99 ipu_crtc->enabled = 1;
100 }
101
102 static void ipu_fb_disable(struct ipu_crtc *ipu_crtc)
103 {
104 if (!ipu_crtc->enabled)
105 return;
106
107 if (ipu_crtc->dp)
108 ipu_dp_disable_channel(ipu_crtc->dp);
109 ipu_dc_disable_channel(ipu_crtc->dc);
110 ipu_idmac_disable_channel(ipu_crtc->ipu_ch);
111 ipu_dmfc_disable_channel(ipu_crtc->dmfc);
112 ipu_di_disable(ipu_crtc->di);
113
114 ipu_crtc->enabled = 0;
115 }
116
117 static void ipu_crtc_dpms(struct drm_crtc *crtc, int mode)
118 {
119 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
120
121 dev_dbg(ipu_crtc->dev, "%s mode: %d\n", __func__, mode);
122
123 switch (mode) {
124 case DRM_MODE_DPMS_ON:
125 ipu_fb_enable(ipu_crtc);
126 break;
127 case DRM_MODE_DPMS_STANDBY:
128 case DRM_MODE_DPMS_SUSPEND:
129 case DRM_MODE_DPMS_OFF:
130 ipu_fb_disable(ipu_crtc);
131 break;
132 }
133 }
134
135 static int ipu_page_flip(struct drm_crtc *crtc,
136 struct drm_framebuffer *fb,
137 struct drm_pending_vblank_event *event)
138 {
139 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
140 int ret;
141
142 if (ipu_crtc->newfb)
143 return -EBUSY;
144
145 ret = imx_drm_crtc_vblank_get(ipu_crtc->imx_crtc);
146 if (ret) {
147 dev_dbg(ipu_crtc->dev, "failed to acquire vblank counter\n");
148 list_del(&event->base.link);
149
150 return ret;
151 }
152
153 ipu_crtc->newfb = fb;
154 ipu_crtc->page_flip_event = event;
155
156 return 0;
157 }
158
159 static const struct drm_crtc_funcs ipu_crtc_funcs = {
160 .set_config = drm_crtc_helper_set_config,
161 .destroy = drm_crtc_cleanup,
162 .page_flip = ipu_page_flip,
163 };
164
165 static int ipu_drm_set_base(struct drm_crtc *crtc, int x, int y)
166 {
167 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
168 struct drm_gem_cma_object *cma_obj;
169 struct drm_framebuffer *fb = crtc->fb;
170 unsigned long phys;
171
172 cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
173 if (!cma_obj) {
174 DRM_LOG_KMS("entry is null.\n");
175 return -EFAULT;
176 }
177
178 phys = cma_obj->paddr;
179 phys += x * (fb->bits_per_pixel >> 3);
180 phys += y * fb->pitches[0];
181
182 dev_dbg(ipu_crtc->dev, "%s: phys: 0x%lx\n", __func__, phys);
183 dev_dbg(ipu_crtc->dev, "%s: xy: %dx%d\n", __func__, x, y);
184
185 ipu_cpmem_set_stride(ipu_get_cpmem(ipu_crtc->ipu_ch), fb->pitches[0]);
186 ipu_cpmem_set_buffer(ipu_get_cpmem(ipu_crtc->ipu_ch),
187 0, phys);
188
189 return 0;
190 }
191
192 static int ipu_crtc_mode_set(struct drm_crtc *crtc,
193 struct drm_display_mode *orig_mode,
194 struct drm_display_mode *mode,
195 int x, int y,
196 struct drm_framebuffer *old_fb)
197 {
198 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
199 struct drm_framebuffer *fb = ipu_crtc->base.fb;
200 int ret;
201 struct ipu_di_signal_cfg sig_cfg = {};
202 u32 out_pixel_fmt;
203 struct ipu_ch_param __iomem *cpmem = ipu_get_cpmem(ipu_crtc->ipu_ch);
204 int bpp;
205 u32 v4l2_fmt;
206
207 dev_dbg(ipu_crtc->dev, "%s: mode->hdisplay: %d\n", __func__,
208 mode->hdisplay);
209 dev_dbg(ipu_crtc->dev, "%s: mode->vdisplay: %d\n", __func__,
210 mode->vdisplay);
211
212 ipu_ch_param_zero(cpmem);
213
214 switch (fb->pixel_format) {
215 case DRM_FORMAT_XRGB8888:
216 case DRM_FORMAT_ARGB8888:
217 v4l2_fmt = V4L2_PIX_FMT_RGB32;
218 bpp = 32;
219 break;
220 case DRM_FORMAT_RGB565:
221 v4l2_fmt = V4L2_PIX_FMT_RGB565;
222 bpp = 16;
223 break;
224 case DRM_FORMAT_RGB888:
225 v4l2_fmt = V4L2_PIX_FMT_RGB24;
226 bpp = 24;
227 break;
228 default:
229 dev_err(ipu_crtc->dev, "unsupported pixel format 0x%08x\n",
230 fb->pixel_format);
231 return -EINVAL;
232 }
233
234 out_pixel_fmt = ipu_crtc->interface_pix_fmt;
235
236 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
237 sig_cfg.interlaced = 1;
238 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
239 sig_cfg.Hsync_pol = 1;
240 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
241 sig_cfg.Vsync_pol = 1;
242
243 sig_cfg.enable_pol = 1;
244 sig_cfg.clk_pol = 0;
245 sig_cfg.width = mode->hdisplay;
246 sig_cfg.height = mode->vdisplay;
247 sig_cfg.pixel_fmt = out_pixel_fmt;
248 sig_cfg.h_start_width = mode->htotal - mode->hsync_end;
249 sig_cfg.h_sync_width = mode->hsync_end - mode->hsync_start;
250 sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay;
251
252 sig_cfg.v_start_width = mode->vtotal - mode->vsync_end;
253 sig_cfg.v_sync_width = mode->vsync_end - mode->vsync_start;
254 sig_cfg.v_end_width = mode->vsync_start - mode->vdisplay;
255 sig_cfg.pixelclock = mode->clock * 1000;
256 sig_cfg.clkflags = ipu_crtc->di_clkflags;
257
258 sig_cfg.v_to_h_sync = 0;
259
260 sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
261 sig_cfg.vsync_pin = ipu_crtc->di_vsync_pin;
262
263 if (ipu_crtc->dp) {
264 ret = ipu_dp_setup_channel(ipu_crtc->dp, IPUV3_COLORSPACE_RGB,
265 IPUV3_COLORSPACE_RGB);
266 if (ret) {
267 dev_err(ipu_crtc->dev,
268 "initializing display processor failed with %d\n",
269 ret);
270 return ret;
271 }
272 ipu_dp_set_global_alpha(ipu_crtc->dp, 1, 0, 1);
273 }
274
275 ret = ipu_dc_init_sync(ipu_crtc->dc, ipu_crtc->di, sig_cfg.interlaced,
276 out_pixel_fmt, mode->hdisplay);
277 if (ret) {
278 dev_err(ipu_crtc->dev,
279 "initializing display controller failed with %d\n",
280 ret);
281 return ret;
282 }
283
284 ret = ipu_di_init_sync_panel(ipu_crtc->di, &sig_cfg);
285 if (ret) {
286 dev_err(ipu_crtc->dev,
287 "initializing panel failed with %d\n", ret);
288 return ret;
289 }
290
291 ipu_cpmem_set_resolution(cpmem, mode->hdisplay, mode->vdisplay);
292 ipu_cpmem_set_fmt(cpmem, v4l2_fmt);
293 ipu_cpmem_set_high_priority(ipu_crtc->ipu_ch);
294
295 ret = ipu_dmfc_init_channel(ipu_crtc->dmfc, mode->hdisplay);
296 if (ret) {
297 dev_err(ipu_crtc->dev,
298 "initializing dmfc channel failed with %d\n",
299 ret);
300 return ret;
301 }
302
303 ret = ipu_dmfc_alloc_bandwidth(ipu_crtc->dmfc,
304 calc_bandwidth(mode, calc_vref(mode)), 64);
305 if (ret) {
306 dev_err(ipu_crtc->dev,
307 "allocating dmfc bandwidth failed with %d\n",
308 ret);
309 return ret;
310 }
311
312 ipu_drm_set_base(crtc, x, y);
313
314 return 0;
315 }
316
317 static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
318 {
319 struct drm_pending_vblank_event *e;
320 struct timeval now;
321 unsigned long flags;
322 struct drm_device *drm = ipu_crtc->base.dev;
323
324 spin_lock_irqsave(&drm->event_lock, flags);
325
326 e = ipu_crtc->page_flip_event;
327 if (!e) {
328 spin_unlock_irqrestore(&drm->event_lock, flags);
329 return;
330 }
331
332 do_gettimeofday(&now);
333 e->event.sequence = 0;
334 e->event.tv_sec = now.tv_sec;
335 e->event.tv_usec = now.tv_usec;
336 ipu_crtc->page_flip_event = NULL;
337
338 imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
339
340 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
341
342 wake_up_interruptible(&e->base.file_priv->event_wait);
343
344 spin_unlock_irqrestore(&drm->event_lock, flags);
345 }
346
347 static irqreturn_t ipu_irq_handler(int irq, void *dev_id)
348 {
349 struct ipu_crtc *ipu_crtc = dev_id;
350
351 imx_drm_handle_vblank(ipu_crtc->imx_crtc);
352
353 if (ipu_crtc->newfb) {
354 ipu_crtc->base.fb = ipu_crtc->newfb;
355 ipu_crtc->newfb = NULL;
356 ipu_drm_set_base(&ipu_crtc->base, 0, 0);
357 ipu_crtc_handle_pageflip(ipu_crtc);
358 }
359
360 return IRQ_HANDLED;
361 }
362
363 static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc,
364 const struct drm_display_mode *mode,
365 struct drm_display_mode *adjusted_mode)
366 {
367 return true;
368 }
369
370 static void ipu_crtc_prepare(struct drm_crtc *crtc)
371 {
372 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
373
374 ipu_fb_disable(ipu_crtc);
375 }
376
377 static void ipu_crtc_commit(struct drm_crtc *crtc)
378 {
379 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
380
381 ipu_fb_enable(ipu_crtc);
382 }
383
384 static void ipu_crtc_load_lut(struct drm_crtc *crtc)
385 {
386 }
387
388 static struct drm_crtc_helper_funcs ipu_helper_funcs = {
389 .dpms = ipu_crtc_dpms,
390 .mode_fixup = ipu_crtc_mode_fixup,
391 .mode_set = ipu_crtc_mode_set,
392 .prepare = ipu_crtc_prepare,
393 .commit = ipu_crtc_commit,
394 .load_lut = ipu_crtc_load_lut,
395 };
396
397 static int ipu_enable_vblank(struct drm_crtc *crtc)
398 {
399 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
400
401 enable_irq(ipu_crtc->irq);
402
403 return 0;
404 }
405
406 static void ipu_disable_vblank(struct drm_crtc *crtc)
407 {
408 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
409
410 disable_irq(ipu_crtc->irq);
411 }
412
413 static int ipu_set_interface_pix_fmt(struct drm_crtc *crtc, u32 encoder_type,
414 u32 pixfmt, int hsync_pin, int vsync_pin)
415 {
416 struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc);
417
418 ipu_crtc->interface_pix_fmt = pixfmt;
419 ipu_crtc->di_hsync_pin = hsync_pin;
420 ipu_crtc->di_vsync_pin = vsync_pin;
421
422 switch (encoder_type) {
423 case DRM_MODE_ENCODER_DAC:
424 case DRM_MODE_ENCODER_TVDAC:
425 case DRM_MODE_ENCODER_LVDS:
426 ipu_crtc->di_clkflags = IPU_DI_CLKMODE_SYNC |
427 IPU_DI_CLKMODE_EXT;
428 break;
429 case DRM_MODE_ENCODER_NONE:
430 ipu_crtc->di_clkflags = 0;
431 break;
432 }
433
434 return 0;
435 }
436
437 static const struct imx_drm_crtc_helper_funcs ipu_crtc_helper_funcs = {
438 .enable_vblank = ipu_enable_vblank,
439 .disable_vblank = ipu_disable_vblank,
440 .set_interface_pix_fmt = ipu_set_interface_pix_fmt,
441 .crtc_funcs = &ipu_crtc_funcs,
442 .crtc_helper_funcs = &ipu_helper_funcs,
443 };
444
445 static void ipu_put_resources(struct ipu_crtc *ipu_crtc)
446 {
447 if (!IS_ERR_OR_NULL(ipu_crtc->ipu_ch))
448 ipu_idmac_put(ipu_crtc->ipu_ch);
449 if (!IS_ERR_OR_NULL(ipu_crtc->dmfc))
450 ipu_dmfc_put(ipu_crtc->dmfc);
451 if (!IS_ERR_OR_NULL(ipu_crtc->dp))
452 ipu_dp_put(ipu_crtc->dp);
453 if (!IS_ERR_OR_NULL(ipu_crtc->di))
454 ipu_di_put(ipu_crtc->di);
455 }
456
457 static int ipu_get_resources(struct ipu_crtc *ipu_crtc,
458 struct ipu_client_platformdata *pdata)
459 {
460 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
461 int ret;
462
463 ipu_crtc->ipu_ch = ipu_idmac_get(ipu, pdata->dma[0]);
464 if (IS_ERR(ipu_crtc->ipu_ch)) {
465 ret = PTR_ERR(ipu_crtc->ipu_ch);
466 goto err_out;
467 }
468
469 ipu_crtc->dc = ipu_dc_get(ipu, pdata->dc);
470 if (IS_ERR(ipu_crtc->dc)) {
471 ret = PTR_ERR(ipu_crtc->dc);
472 goto err_out;
473 }
474
475 ipu_crtc->dmfc = ipu_dmfc_get(ipu, pdata->dma[0]);
476 if (IS_ERR(ipu_crtc->dmfc)) {
477 ret = PTR_ERR(ipu_crtc->dmfc);
478 goto err_out;
479 }
480
481 if (pdata->dp >= 0) {
482 ipu_crtc->dp = ipu_dp_get(ipu, pdata->dp);
483 if (IS_ERR(ipu_crtc->dp)) {
484 ret = PTR_ERR(ipu_crtc->dp);
485 goto err_out;
486 }
487 }
488
489 ipu_crtc->di = ipu_di_get(ipu, pdata->di);
490 if (IS_ERR(ipu_crtc->di)) {
491 ret = PTR_ERR(ipu_crtc->di);
492 goto err_out;
493 }
494
495 return 0;
496 err_out:
497 ipu_put_resources(ipu_crtc);
498
499 return ret;
500 }
501
502 static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
503 struct ipu_client_platformdata *pdata)
504 {
505 struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent);
506 int ret;
507
508 ret = ipu_get_resources(ipu_crtc, pdata);
509 if (ret) {
510 dev_err(ipu_crtc->dev, "getting resources failed with %d.\n",
511 ret);
512 return ret;
513 }
514
515 ret = imx_drm_add_crtc(&ipu_crtc->base,
516 &ipu_crtc->imx_crtc,
517 &ipu_crtc_helper_funcs, THIS_MODULE,
518 ipu_crtc->dev->parent->of_node, pdata->di);
519 if (ret) {
520 dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
521 goto err_put_resources;
522 }
523
524 ipu_crtc->irq = ipu_idmac_channel_irq(ipu, ipu_crtc->ipu_ch,
525 IPU_IRQ_EOF);
526 ret = devm_request_irq(ipu_crtc->dev, ipu_crtc->irq, ipu_irq_handler, 0,
527 "imx_drm", ipu_crtc);
528 if (ret < 0) {
529 dev_err(ipu_crtc->dev, "irq request failed with %d.\n", ret);
530 goto err_put_resources;
531 }
532
533 disable_irq(ipu_crtc->irq);
534
535 return 0;
536
537 err_put_resources:
538 ipu_put_resources(ipu_crtc);
539
540 return ret;
541 }
542
543 static int ipu_drm_probe(struct platform_device *pdev)
544 {
545 struct ipu_client_platformdata *pdata = pdev->dev.platform_data;
546 struct ipu_crtc *ipu_crtc;
547 int ret;
548
549 if (!pdata)
550 return -EINVAL;
551
552 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
553
554 ipu_crtc = devm_kzalloc(&pdev->dev, sizeof(*ipu_crtc), GFP_KERNEL);
555 if (!ipu_crtc)
556 return -ENOMEM;
557
558 ipu_crtc->dev = &pdev->dev;
559
560 ret = ipu_crtc_init(ipu_crtc, pdata);
561 if (ret)
562 return ret;
563
564 platform_set_drvdata(pdev, ipu_crtc);
565
566 return 0;
567 }
568
569 static int ipu_drm_remove(struct platform_device *pdev)
570 {
571 struct ipu_crtc *ipu_crtc = platform_get_drvdata(pdev);
572
573 imx_drm_remove_crtc(ipu_crtc->imx_crtc);
574
575 ipu_put_resources(ipu_crtc);
576
577 return 0;
578 }
579
580 static struct platform_driver ipu_drm_driver = {
581 .driver = {
582 .name = "imx-ipuv3-crtc",
583 },
584 .probe = ipu_drm_probe,
585 .remove = ipu_drm_remove,
586 };
587 module_platform_driver(ipu_drm_driver);
588
589 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
590 MODULE_DESCRIPTION(DRIVER_DESC);
591 MODULE_LICENSE("GPL");