drivers/staging/imx-drm/imx-tve.c

   1 /*
   2  * i.MX drm driver - Television Encoder (TVEv2)
   3  *
   4  * Copyright (C) 2013 Philipp Zabel, Pengutronix
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  18  * MA 02110-1301, USA.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/module.h>
  24 #include <linux/of_i2c.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/regmap.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/spinlock.h>
  29 #include <linux/videodev2.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_fb_helper.h>
  32 #include <drm/drm_crtc_helper.h>
  33
  34 #include "imx-drm.h"
  35
  36 #define TVE_COM_CONF_REG        0x00
  37 #define TVE_TVDAC0_CONT_REG     0x28
  38 #define TVE_TVDAC1_CONT_REG     0x2c
  39 #define TVE_TVDAC2_CONT_REG     0x30
  40 #define TVE_CD_CONT_REG         0x34
  41 #define TVE_INT_CONT_REG        0x64
  42 #define TVE_STAT_REG            0x68
  43 #define TVE_TST_MODE_REG        0x6c
  44 #define TVE_MV_CONT_REG         0xdc
  45
  46 /* TVE_COM_CONF_REG */
  47 #define TVE_SYNC_CH_2_EN        BIT(22)
  48 #define TVE_SYNC_CH_1_EN        BIT(21)
  49 #define TVE_SYNC_CH_0_EN        BIT(20)
  50 #define TVE_TV_OUT_MODE_MASK    (0x7 << 12)
  51 #define TVE_TV_OUT_DISABLE      (0x0 << 12)
  52 #define TVE_TV_OUT_CVBS_0       (0x1 << 12)
  53 #define TVE_TV_OUT_CVBS_2       (0x2 << 12)
  54 #define TVE_TV_OUT_CVBS_0_2     (0x3 << 12)
  55 #define TVE_TV_OUT_SVIDEO_0_1   (0x4 << 12)
  56 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2   (0x5 << 12)
  57 #define TVE_TV_OUT_YPBPR        (0x6 << 12)
  58 #define TVE_TV_OUT_RGB          (0x7 << 12)
  59 #define TVE_TV_STAND_MASK       (0xf << 8)
  60 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
  61 #define TVE_P2I_CONV_EN         BIT(7)
  62 #define TVE_INP_VIDEO_FORM      BIT(6)
  63 #define TVE_INP_YCBCR_422       (0x0 << 6)
  64 #define TVE_INP_YCBCR_444       (0x1 << 6)
  65 #define TVE_DATA_SOURCE_MASK    (0x3 << 4)
  66 #define TVE_DATA_SOURCE_BUS1    (0x0 << 4)
  67 #define TVE_DATA_SOURCE_BUS2    (0x1 << 4)
  68 #define TVE_DATA_SOURCE_EXT     (0x2 << 4)
  69 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
  70 #define TVE_IPU_CLK_EN_OFS      3
  71 #define TVE_IPU_CLK_EN          BIT(3)
  72 #define TVE_DAC_SAMP_RATE_OFS   1
  73 #define TVE_DAC_SAMP_RATE_WIDTH 2
  74 #define TVE_DAC_SAMP_RATE_MASK  (0x3 << 1)
  75 #define TVE_DAC_FULL_RATE       (0x0 << 1)
  76 #define TVE_DAC_DIV2_RATE       (0x1 << 1)
  77 #define TVE_DAC_DIV4_RATE       (0x2 << 1)
  78 #define TVE_EN                  BIT(0)
  79
  80 /* TVE_TVDACx_CONT_REG */
  81 #define TVE_TVDAC_GAIN_MASK     (0x3f << 0)
  82
  83 /* TVE_CD_CONT_REG */
  84 #define TVE_CD_CH_2_SM_EN       BIT(22)
  85 #define TVE_CD_CH_1_SM_EN       BIT(21)
  86 #define TVE_CD_CH_0_SM_EN       BIT(20)
  87 #define TVE_CD_CH_2_LM_EN       BIT(18)
  88 #define TVE_CD_CH_1_LM_EN       BIT(17)
  89 #define TVE_CD_CH_0_LM_EN       BIT(16)
  90 #define TVE_CD_CH_2_REF_LVL     BIT(10)
  91 #define TVE_CD_CH_1_REF_LVL     BIT(9)
  92 #define TVE_CD_CH_0_REF_LVL     BIT(8)
  93 #define TVE_CD_EN               BIT(0)
  94
  95 /* TVE_INT_CONT_REG */
  96 #define TVE_FRAME_END_IEN       BIT(13)
  97 #define TVE_CD_MON_END_IEN      BIT(2)
  98 #define TVE_CD_SM_IEN           BIT(1)
  99 #define TVE_CD_LM_IEN           BIT(0)
 100
 101 /* TVE_TST_MODE_REG */
 102 #define TVE_TVDAC_TEST_MODE_MASK        (0x7 << 0)
 103
 104 #define con_to_tve(x) container_of(x, struct imx_tve, connector)
 105 #define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
 106
 107 enum {
 108         TVE_MODE_TVOUT,
 109         TVE_MODE_VGA,
 110 };
 111
 112 struct imx_tve {
 113         struct drm_connector connector;
 114         struct imx_drm_connector *imx_drm_connector;
 115         struct drm_encoder encoder;
 116         struct imx_drm_encoder *imx_drm_encoder;
 117         struct device *dev;
 118         spinlock_t enable_lock; /* serializes tve_enable/disable */
 119         spinlock_t lock;        /* register lock */
 120         bool enabled;
 121         int mode;
 122
 123         struct regmap *regmap;
 124         struct regulator *dac_reg;
 125         struct i2c_adapter *ddc;
 126         struct clk *clk;
 127         struct clk *di_sel_clk;
 128         struct clk_hw clk_hw_di;
 129         struct clk *di_clk;
 130         int vsync_pin;
 131         int hsync_pin;
 132 };
 133
 134 static void tve_lock(void *__tve)
 135 {
 136         struct imx_tve *tve = __tve;
 137         spin_lock(&tve->lock);
 138 }
 139
 140 static void tve_unlock(void *__tve)
 141 {
 142         struct imx_tve *tve = __tve;
 143         spin_unlock(&tve->lock);
 144 }
 145
 146 static void tve_enable(struct imx_tve *tve)
 147 {
 148         unsigned long flags;
 149         int ret;
 150
 151         spin_lock_irqsave(&tve->enable_lock, flags);
 152         if (!tve->enabled) {
 153                 tve->enabled = 1;
 154                 clk_prepare_enable(tve->clk);
 155                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 156                                          TVE_IPU_CLK_EN | TVE_EN,
 157                                          TVE_IPU_CLK_EN | TVE_EN);
 158         }
 159
 160         /* clear interrupt status register */
 161         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 162
 163         /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
 164         if (tve->mode == TVE_MODE_VGA)
 165                 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
 166         else
 167                 regmap_write(tve->regmap, TVE_INT_CONT_REG,
 168                              TVE_CD_SM_IEN | TVE_CD_LM_IEN | TVE_CD_MON_END_IEN);
 169         spin_unlock_irqrestore(&tve->enable_lock, flags);
 170 }
 171
 172 static void tve_disable(struct imx_tve *tve)
 173 {
 174         unsigned long flags;
 175         int ret;
 176
 177         spin_lock_irqsave(&tve->enable_lock, flags);
 178         if (tve->enabled) {
 179                 tve->enabled = 0;
 180                 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 181                                          TVE_IPU_CLK_EN | TVE_EN, 0);
 182                 clk_disable_unprepare(tve->clk);
 183         }
 184         spin_unlock_irqrestore(&tve->enable_lock, flags);
 185 }
 186
 187 static int tve_setup_tvout(struct imx_tve *tve)
 188 {
 189         return -ENOTSUPP;
 190 }
 191
 192 static int tve_setup_vga(struct imx_tve *tve)
 193 {
 194         unsigned int mask;
 195         unsigned int val;
 196         int ret;
 197
 198         /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
 199         ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
 200                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 201         ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
 202                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 203         ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
 204                                  TVE_TVDAC_GAIN_MASK, 0x0a);
 205
 206         /* set configuration register */
 207         mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
 208         val  = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
 209         mask |= TVE_TV_STAND_MASK       | TVE_P2I_CONV_EN;
 210         val  |= TVE_TV_STAND_HD_1080P30 | 0;
 211         mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
 212         val  |= TVE_TV_OUT_RGB       | TVE_SYNC_CH_0_EN;
 213         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
 214         if (ret < 0) {
 215                 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
 216                 return ret;
 217         }
 218
 219         /* set test mode (as documented) */
 220         ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
 221                                  TVE_TVDAC_TEST_MODE_MASK, 1);
 222
 223         return 0;
 224 }
 225
 226 static enum drm_connector_status imx_tve_connector_detect(
 227                                 struct drm_connector *connector, bool force)
 228 {
 229         return connector_status_connected;
 230 }
 231
 232 static void imx_tve_connector_destroy(struct drm_connector *connector)
 233 {
 234         /* do not free here */
 235 }
 236
 237 static int imx_tve_connector_get_modes(struct drm_connector *connector)
 238 {
 239         struct imx_tve *tve = con_to_tve(connector);
 240         struct edid *edid;
 241         int ret = 0;
 242
 243         if (!tve->ddc)
 244                 return 0;
 245
 246         edid = drm_get_edid(connector, tve->ddc);
 247         if (edid) {
 248                 drm_mode_connector_update_edid_property(connector, edid);
 249                 ret = drm_add_edid_modes(connector, edid);
 250                 kfree(edid);
 251         }
 252
 253         return ret;
 254 }
 255
 256 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
 257                                         struct drm_display_mode *mode)
 258 {
 259         struct imx_tve *tve = con_to_tve(connector);
 260         unsigned long rate;
 261
 262         /* pixel clock with 2x oversampling */
 263         rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
 264         if (rate == mode->clock)
 265                 return MODE_OK;
 266
 267         /* pixel clock without oversampling */
 268         rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
 269         if (rate == mode->clock)
 270                 return MODE_OK;
 271
 272         dev_warn(tve->dev, "ignoring mode %dx%d\n",
 273                  mode->hdisplay, mode->vdisplay);
 274
 275         return MODE_BAD;
 276 }
 277
 278 static struct drm_encoder *imx_tve_connector_best_encoder(
 279                 struct drm_connector *connector)
 280 {
 281         struct imx_tve *tve = con_to_tve(connector);
 282
 283         return &tve->encoder;
 284 }
 285
 286 static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
 287 {
 288         struct imx_tve *tve = enc_to_tve(encoder);
 289         int ret;
 290
 291         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
 292                                  TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
 293         if (ret < 0)
 294                 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
 295 }
 296
 297 static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
 298                                        const struct drm_display_mode *mode,
 299                                        struct drm_display_mode *adjusted_mode)
 300 {
 301         return true;
 302 }
 303
 304 static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
 305 {
 306         struct imx_tve *tve = enc_to_tve(encoder);
 307
 308         tve_disable(tve);
 309
 310         switch (tve->mode) {
 311         case TVE_MODE_VGA:
 312                 imx_drm_crtc_panel_format_pins(encoder->crtc,
 313                                 DRM_MODE_ENCODER_DAC, IPU_PIX_FMT_GBR24,
 314                                 tve->hsync_pin, tve->vsync_pin);
 315                 break;
 316         case TVE_MODE_TVOUT:
 317                 imx_drm_crtc_panel_format(encoder->crtc, DRM_MODE_ENCODER_TVDAC,
 318                                           V4L2_PIX_FMT_YUV444);
 319                 break;
 320         }
 321 }
 322
 323 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
 324                                      struct drm_display_mode *mode,
 325                                      struct drm_display_mode *adjusted_mode)
 326 {
 327         struct imx_tve *tve = enc_to_tve(encoder);
 328         unsigned long rounded_rate;
 329         unsigned long rate;
 330         int div = 1;
 331         int ret;
 332
 333         /*
 334          * FIXME
 335          * we should try 4k * mode->clock first,
 336          * and enable 4x oversampling for lower resolutions
 337          */
 338         rate = 2000UL * mode->clock;
 339         clk_set_rate(tve->clk, rate);
 340         rounded_rate = clk_get_rate(tve->clk);
 341         if (rounded_rate >= rate)
 342                 div = 2;
 343         clk_set_rate(tve->di_clk, rounded_rate / div);
 344
 345         ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
 346         if (ret < 0) {
 347                 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
 348                         ret);
 349         }
 350
 351         if (tve->mode == TVE_MODE_VGA)
 352                 tve_setup_vga(tve);
 353         else
 354                 tve_setup_tvout(tve);
 355 }
 356
 357 static void imx_tve_encoder_commit(struct drm_encoder *encoder)
 358 {
 359         struct imx_tve *tve = enc_to_tve(encoder);
 360
 361         tve_enable(tve);
 362 }
 363
 364 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
 365 {
 366         struct imx_tve *tve = enc_to_tve(encoder);
 367
 368         tve_disable(tve);
 369 }
 370
 371 static void imx_tve_encoder_destroy(struct drm_encoder *encoder)
 372 {
 373         /* do not free here */
 374 }
 375
 376 static struct drm_connector_funcs imx_tve_connector_funcs = {
 377         .dpms = drm_helper_connector_dpms,
 378         .fill_modes = drm_helper_probe_single_connector_modes,
 379         .detect = imx_tve_connector_detect,
 380         .destroy = imx_tve_connector_destroy,
 381 };
 382
 383 static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
 384         .get_modes = imx_tve_connector_get_modes,
 385         .best_encoder = imx_tve_connector_best_encoder,
 386         .mode_valid = imx_tve_connector_mode_valid,
 387 };
 388
 389 static struct drm_encoder_funcs imx_tve_encoder_funcs = {
 390         .destroy = imx_tve_encoder_destroy,
 391 };
 392
 393 static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
 394         .dpms = imx_tve_encoder_dpms,
 395         .mode_fixup = imx_tve_encoder_mode_fixup,
 396         .prepare = imx_tve_encoder_prepare,
 397         .mode_set = imx_tve_encoder_mode_set,
 398         .commit = imx_tve_encoder_commit,
 399         .disable = imx_tve_encoder_disable,
 400 };
 401
 402 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
 403 {
 404         struct imx_tve *tve = data;
 405         unsigned int val;
 406
 407         regmap_read(tve->regmap, TVE_STAT_REG, &val);
 408
 409         /* clear interrupt status register */
 410         regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
 411
 412         return IRQ_HANDLED;
 413 }
 414
 415 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
 416                                             unsigned long parent_rate)
 417 {
 418         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 419         unsigned int val;
 420         int ret;
 421
 422         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 423         if (ret < 0)
 424                 return 0;
 425
 426         switch (val & TVE_DAC_SAMP_RATE_MASK) {
 427         case TVE_DAC_DIV4_RATE:
 428                 return parent_rate / 4;
 429         case TVE_DAC_DIV2_RATE:
 430                 return parent_rate / 2;
 431         case TVE_DAC_FULL_RATE:
 432         default:
 433                 return parent_rate;
 434         }
 435
 436         return 0;
 437 }
 438
 439 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
 440                                   unsigned long *prate)
 441 {
 442         unsigned long div;
 443
 444         div = *prate / rate;
 445         if (div >= 4)
 446                 return *prate / 4;
 447         else if (div >= 2)
 448                 return *prate / 2;
 449         else
 450                 return *prate;
 451 }
 452
 453 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
 454                                unsigned long parent_rate)
 455 {
 456         struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
 457         unsigned long div;
 458         u32 val;
 459         int ret;
 460
 461         div = parent_rate / rate;
 462         if (div >= 4)
 463                 val = TVE_DAC_DIV4_RATE;
 464         else if (div >= 2)
 465                 val = TVE_DAC_DIV2_RATE;
 466         else
 467                 val = TVE_DAC_FULL_RATE;
 468
 469         ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_DAC_SAMP_RATE_MASK, val);
 470         if (ret < 0) {
 471                 dev_err(tve->dev, "failed to set divider: %d\n", ret);
 472                 return ret;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static struct clk_ops clk_tve_di_ops = {
 479         .round_rate = clk_tve_di_round_rate,
 480         .set_rate = clk_tve_di_set_rate,
 481         .recalc_rate = clk_tve_di_recalc_rate,
 482 };
 483
 484 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
 485 {
 486         const char *tve_di_parent[1];
 487         struct clk_init_data init = {
 488                 .name = "tve_di",
 489                 .ops = &clk_tve_di_ops,
 490                 .num_parents = 1,
 491                 .flags = 0,
 492         };
 493
 494         tve_di_parent[0] = __clk_get_name(tve->clk);
 495         init.parent_names = (const char **)&tve_di_parent;
 496
 497         tve->clk_hw_di.init = &init;
 498         tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
 499         if (IS_ERR(tve->di_clk)) {
 500                 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
 501                         PTR_ERR(tve->di_clk));
 502                 return PTR_ERR(tve->di_clk);
 503         }
 504
 505         return 0;
 506 }
 507
 508 static int imx_tve_register(struct imx_tve *tve)
 509 {
 510         int ret;
 511
 512         tve->connector.funcs = &imx_tve_connector_funcs;
 513         tve->encoder.funcs = &imx_tve_encoder_funcs;
 514
 515         tve->encoder.encoder_type = DRM_MODE_ENCODER_NONE;
 516         tve->connector.connector_type = DRM_MODE_CONNECTOR_VGA;
 517
 518         drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
 519         ret = imx_drm_add_encoder(&tve->encoder, &tve->imx_drm_encoder,
 520                         THIS_MODULE);
 521         if (ret) {
 522                 dev_err(tve->dev, "adding encoder failed with %d\n", ret);
 523                 return ret;
 524         }
 525
 526         drm_connector_helper_add(&tve->connector,
 527                         &imx_tve_connector_helper_funcs);
 528
 529         ret = imx_drm_add_connector(&tve->connector,
 530                         &tve->imx_drm_connector, THIS_MODULE);
 531         if (ret) {
 532                 imx_drm_remove_encoder(tve->imx_drm_encoder);
 533                 dev_err(tve->dev, "adding connector failed with %d\n", ret);
 534                 return ret;
 535         }
 536
 537         drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
 538
 539         return 0;
 540 }
 541
 542 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
 543 {
 544         return (reg % 4 == 0) && (reg <= 0xdc);
 545 }
 546
 547 static struct regmap_config tve_regmap_config = {
 548         .reg_bits = 32,
 549         .val_bits = 32,
 550         .reg_stride = 4,
 551
 552         .readable_reg = imx_tve_readable_reg,
 553
 554         .lock = tve_lock,
 555         .unlock = tve_unlock,
 556
 557         .max_register = 0xdc,
 558 };
 559
 560 static const char *imx_tve_modes[] = {
 561         [TVE_MODE_TVOUT]  = "tvout",
 562         [TVE_MODE_VGA] = "vga",
 563 };
 564
 565 const int of_get_tve_mode(struct device_node *np)
 566 {
 567         const char *bm;
 568         int ret, i;
 569
 570         ret = of_property_read_string(np, "fsl,tve-mode", &bm);
 571         if (ret < 0)
 572                 return ret;
 573
 574         for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
 575                 if (!strcasecmp(bm, imx_tve_modes[i]))
 576                         return i;
 577
 578         return -EINVAL;
 579 }
 580
 581 static int imx_tve_probe(struct platform_device *pdev)
 582 {
 583         struct device_node *np = pdev->dev.of_node;
 584         struct device_node *ddc_node;
 585         struct imx_tve *tve;
 586         struct resource *res;
 587         void __iomem *base;
 588         unsigned int val;
 589         int irq;
 590         int ret;
 591
 592         tve = devm_kzalloc(&pdev->dev, sizeof(*tve), GFP_KERNEL);
 593         if (!tve)
 594                 return -ENOMEM;
 595
 596         tve->dev = &pdev->dev;
 597         spin_lock_init(&tve->lock);
 598         spin_lock_init(&tve->enable_lock);
 599
 600         ddc_node = of_parse_phandle(np, "ddc", 0);
 601         if (ddc_node) {
 602                 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
 603                 of_node_put(ddc_node);
 604         }
 605
 606         tve->mode = of_get_tve_mode(np);
 607         if (tve->mode != TVE_MODE_VGA) {
 608                 dev_err(&pdev->dev, "only VGA mode supported, currently\n");
 609                 return -EINVAL;
 610         }
 611
 612         if (tve->mode == TVE_MODE_VGA) {
 613                 struct pinctrl *pinctrl;
 614
 615                 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
 616                 if (IS_ERR(pinctrl)) {
 617                         ret = PTR_ERR(pinctrl);
 618                         dev_warn(&pdev->dev, "failed to setup pinctrl: %d", ret);
 619                         return ret;
 620                 }
 621
 622                 ret = of_property_read_u32(np, "fsl,hsync-pin", &tve->hsync_pin);
 623                 if (ret < 0) {
 624                         dev_err(&pdev->dev, "failed to get vsync pin\n");
 625                         return ret;
 626                 }
 627
 628                 ret |= of_property_read_u32(np, "fsl,vsync-pin", &tve->vsync_pin);
 629                 if (ret < 0) {
 630                         dev_err(&pdev->dev, "failed to get vsync pin\n");
 631                         return ret;
 632                 }
 633         }
 634
 635         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 636         if (!res) {
 637                 dev_err(&pdev->dev, "failed to get memory region\n");
 638                 return -ENOENT;
 639         }
 640
 641         base = devm_request_and_ioremap(&pdev->dev, res);
 642         if (!base) {
 643                 dev_err(&pdev->dev, "failed to remap memory region\n");
 644                 return -ENOENT;
 645         }
 646
 647         tve_regmap_config.lock_arg = tve;
 648         tve->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "tve", base,
 649                                                 &tve_regmap_config);
 650         if (IS_ERR(tve->regmap)) {
 651                 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
 652                         PTR_ERR(tve->regmap));
 653                 return PTR_ERR(tve->regmap);
 654         }
 655
 656         irq = platform_get_irq(pdev, 0);
 657         if (irq < 0) {
 658                 dev_err(&pdev->dev, "failed to get irq\n");
 659                 return irq;
 660         }
 661
 662         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
 663                                         imx_tve_irq_handler, IRQF_ONESHOT,
 664                                         "imx-tve", tve);
 665         if (ret < 0) {
 666                 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
 667                 return ret;
 668         }
 669
 670         tve->dac_reg = devm_regulator_get(&pdev->dev, "dac");
 671         if (!IS_ERR(tve->dac_reg)) {
 672                 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
 673                 regulator_enable(tve->dac_reg);
 674         }
 675
 676         tve->clk = devm_clk_get(&pdev->dev, "tve");
 677         if (IS_ERR(tve->clk)) {
 678                 dev_err(&pdev->dev, "failed to get high speed tve clock: %ld\n",
 679                         PTR_ERR(tve->clk));
 680                 return PTR_ERR(tve->clk);
 681         }
 682
 683         /* this is the IPU DI clock input selector, can be parented to tve_di */
 684         tve->di_sel_clk = devm_clk_get(&pdev->dev, "di_sel");
 685         if (IS_ERR(tve->di_sel_clk)) {
 686                 dev_err(&pdev->dev, "failed to get ipu di mux clock: %ld\n",
 687                         PTR_ERR(tve->di_sel_clk));
 688                 return PTR_ERR(tve->di_sel_clk);
 689         }
 690
 691         ret = tve_clk_init(tve, base);
 692         if (ret < 0)
 693                 return ret;
 694
 695         ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
 696         if (ret < 0) {
 697                 dev_err(&pdev->dev, "failed to read configuration register: %d\n", ret);
 698                 return ret;
 699         }
 700         if (val != 0x00100000) {
 701                 dev_err(&pdev->dev, "configuration register default value indicates this is not a TVEv2\n");
 702                 return -ENODEV;
 703         };
 704
 705         /* disable cable detection for VGA mode */
 706         ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
 707
 708         ret = imx_tve_register(tve);
 709         if (ret)
 710                 return ret;
 711
 712         ret = imx_drm_encoder_add_possible_crtcs(tve->imx_drm_encoder, np);
 713
 714         platform_set_drvdata(pdev, tve);
 715
 716         return 0;
 717 }
 718
 719 static int imx_tve_remove(struct platform_device *pdev)
 720 {
 721         struct imx_tve *tve = platform_get_drvdata(pdev);
 722         struct drm_connector *connector = &tve->connector;
 723         struct drm_encoder *encoder = &tve->encoder;
 724
 725         drm_mode_connector_detach_encoder(connector, encoder);
 726
 727         imx_drm_remove_connector(tve->imx_drm_connector);
 728         imx_drm_remove_encoder(tve->imx_drm_encoder);
 729
 730         if (!IS_ERR(tve->dac_reg))
 731                 regulator_disable(tve->dac_reg);
 732
 733         return 0;
 734 }
 735
 736 static const struct of_device_id imx_tve_dt_ids[] = {
 737         { .compatible = "fsl,imx53-tve", },
 738         { /* sentinel */ }
 739 };
 740
 741 static struct platform_driver imx_tve_driver = {
 742         .probe          = imx_tve_probe,
 743         .remove         = imx_tve_remove,
 744         .driver         = {
 745                 .of_match_table = imx_tve_dt_ids,
 746                 .name   = "imx-tve",
 747                 .owner  = THIS_MODULE,
 748         },
 749 };
 750
 751 module_platform_driver(imx_tve_driver);
 752
 753 MODULE_DESCRIPTION("i.MX Television Encoder driver");
 754 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
 755 MODULE_LICENSE("GPL");