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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_pcidio.c
1 /*
2 comedi/drivers/ni_pcidio.c
3 driver for National Instruments PCI-DIO-32HS
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22 */
23 /*
24 Driver: ni_pcidio
25 Description: National Instruments PCI-DIO32HS, PCI-6533
26 Author: ds
27 Status: works
28 Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
29 [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
30 [National Instruments] PCI-6534 (pci-6534)
31 Updated: Mon, 09 Jan 2012 14:27:23 +0000
32
33 The DIO32HS board appears as one subdevice, with 32 channels.
34 Each channel is individually I/O configurable. The channel order
35 is 0=A0, 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only
36 supports simple digital I/O; no handshaking is supported.
37
38 DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
39
40 The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
41 scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
42 scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
43 trailing edge.
44
45 This driver could be easily modified to support AT-MIO32HS and
46 AT-MIO96.
47
48 The PCI-6534 requires a firmware upload after power-up to work, the
49 firmware data and instructions for loading it with comedi_config
50 it are contained in the
51 comedi_nonfree_firmware tarball available from http://www.comedi.org
52 */
53
54 #define USE_DMA
55 /* #define DEBUG 1 */
56 /* #define DEBUG_FLAGS */
57
58 #include <linux/delay.h>
59 #include <linux/interrupt.h>
60 #include <linux/sched.h>
61 #include <linux/firmware.h>
62
63 #include "../comedidev.h"
64
65 #include "comedi_fc.h"
66 #include "mite.h"
67
68 #undef DPRINTK
69 #ifdef DEBUG
70 #define DPRINTK(format, args...) pr_debug(format, ## args)
71 #else
72 #define DPRINTK(format, args...) do { } while (0)
73 #endif
74
75 #define PCI_DIO_SIZE 4096
76 #define PCI_MITE_SIZE 4096
77
78 /* defines for the PCI-DIO-32HS */
79
80 #define Window_Address 4 /* W */
81 #define Interrupt_And_Window_Status 4 /* R */
82 #define IntStatus1 (1<<0)
83 #define IntStatus2 (1<<1)
84 #define WindowAddressStatus_mask 0x7c
85
86 #define Master_DMA_And_Interrupt_Control 5 /* W */
87 #define InterruptLine(x) ((x)&3)
88 #define OpenInt (1<<2)
89 #define Group_Status 5 /* R */
90 #define DataLeft (1<<0)
91 #define Req (1<<2)
92 #define StopTrig (1<<3)
93
94 #define Group_1_Flags 6 /* R */
95 #define Group_2_Flags 7 /* R */
96 #define TransferReady (1<<0)
97 #define CountExpired (1<<1)
98 #define Waited (1<<5)
99 #define PrimaryTC (1<<6)
100 #define SecondaryTC (1<<7)
101 /* #define SerialRose */
102 /* #define ReqRose */
103 /* #define Paused */
104
105 #define Group_1_First_Clear 6 /* W */
106 #define Group_2_First_Clear 7 /* W */
107 #define ClearWaited (1<<3)
108 #define ClearPrimaryTC (1<<4)
109 #define ClearSecondaryTC (1<<5)
110 #define DMAReset (1<<6)
111 #define FIFOReset (1<<7)
112 #define ClearAll 0xf8
113
114 #define Group_1_FIFO 8 /* W */
115 #define Group_2_FIFO 12 /* W */
116
117 #define Transfer_Count 20
118 #define Chip_ID_D 24
119 #define Chip_ID_I 25
120 #define Chip_ID_O 26
121 #define Chip_Version 27
122 #define Port_IO(x) (28+(x))
123 #define Port_Pin_Directions(x) (32+(x))
124 #define Port_Pin_Mask(x) (36+(x))
125 #define Port_Pin_Polarities(x) (40+(x))
126
127 #define Master_Clock_Routing 45
128 #define RTSIClocking(x) (((x)&3)<<4)
129
130 #define Group_1_Second_Clear 46 /* W */
131 #define Group_2_Second_Clear 47 /* W */
132 #define ClearExpired (1<<0)
133
134 #define Port_Pattern(x) (48+(x))
135
136 #define Data_Path 64
137 #define FIFOEnableA (1<<0)
138 #define FIFOEnableB (1<<1)
139 #define FIFOEnableC (1<<2)
140 #define FIFOEnableD (1<<3)
141 #define Funneling(x) (((x)&3)<<4)
142 #define GroupDirection (1<<7)
143
144 #define Protocol_Register_1 65
145 #define OpMode Protocol_Register_1
146 #define RunMode(x) ((x)&7)
147 #define Numbered (1<<3)
148
149 #define Protocol_Register_2 66
150 #define ClockReg Protocol_Register_2
151 #define ClockLine(x) (((x)&3)<<5)
152 #define InvertStopTrig (1<<7)
153 #define DataLatching(x) (((x)&3)<<5)
154
155 #define Protocol_Register_3 67
156 #define Sequence Protocol_Register_3
157
158 #define Protocol_Register_14 68 /* 16 bit */
159 #define ClockSpeed Protocol_Register_14
160
161 #define Protocol_Register_4 70
162 #define ReqReg Protocol_Register_4
163 #define ReqConditioning(x) (((x)&7)<<3)
164
165 #define Protocol_Register_5 71
166 #define BlockMode Protocol_Register_5
167
168 #define FIFO_Control 72
169 #define ReadyLevel(x) ((x)&7)
170
171 #define Protocol_Register_6 73
172 #define LinePolarities Protocol_Register_6
173 #define InvertAck (1<<0)
174 #define InvertReq (1<<1)
175 #define InvertClock (1<<2)
176 #define InvertSerial (1<<3)
177 #define OpenAck (1<<4)
178 #define OpenClock (1<<5)
179
180 #define Protocol_Register_7 74
181 #define AckSer Protocol_Register_7
182 #define AckLine(x) (((x)&3)<<2)
183 #define ExchangePins (1<<7)
184
185 #define Interrupt_Control 75
186 /* bits same as flags */
187
188 #define DMA_Line_Control_Group1 76
189 #define DMA_Line_Control_Group2 108
190 /* channel zero is none */
191 static inline unsigned primary_DMAChannel_bits(unsigned channel)
192 {
193 return channel & 0x3;
194 }
195
196 static inline unsigned secondary_DMAChannel_bits(unsigned channel)
197 {
198 return (channel << 2) & 0xc;
199 }
200
201 #define Transfer_Size_Control 77
202 #define TransferWidth(x) ((x)&3)
203 #define TransferLength(x) (((x)&3)<<3)
204 #define RequireRLevel (1<<5)
205
206 #define Protocol_Register_15 79
207 #define DAQOptions Protocol_Register_15
208 #define StartSource(x) ((x)&0x3)
209 #define InvertStart (1<<2)
210 #define StopSource(x) (((x)&0x3)<<3)
211 #define ReqStart (1<<6)
212 #define PreStart (1<<7)
213
214 #define Pattern_Detection 81
215 #define DetectionMethod (1<<0)
216 #define InvertMatch (1<<1)
217 #define IE_Pattern_Detection (1<<2)
218
219 #define Protocol_Register_9 82
220 #define ReqDelay Protocol_Register_9
221
222 #define Protocol_Register_10 83
223 #define ReqNotDelay Protocol_Register_10
224
225 #define Protocol_Register_11 84
226 #define AckDelay Protocol_Register_11
227
228 #define Protocol_Register_12 85
229 #define AckNotDelay Protocol_Register_12
230
231 #define Protocol_Register_13 86
232 #define Data1Delay Protocol_Register_13
233
234 #define Protocol_Register_8 88 /* 32 bit */
235 #define StartDelay Protocol_Register_8
236
237 /* Firmware files for PCI-6524 */
238 #define FW_PCI_6534_MAIN "ni6534a.bin"
239 #define FW_PCI_6534_SCARAB_DI "niscrb01.bin"
240 #define FW_PCI_6534_SCARAB_DO "niscrb02.bin"
241 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
242 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
243 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
244
245 enum pci_6534_firmware_registers { /* 16 bit */
246 Firmware_Control_Register = 0x100,
247 Firmware_Status_Register = 0x104,
248 Firmware_Data_Register = 0x108,
249 Firmware_Mask_Register = 0x10c,
250 Firmware_Debug_Register = 0x110,
251 };
252 /* main fpga registers (32 bit)*/
253 enum pci_6534_fpga_registers {
254 FPGA_Control1_Register = 0x200,
255 FPGA_Control2_Register = 0x204,
256 FPGA_Irq_Mask_Register = 0x208,
257 FPGA_Status_Register = 0x20c,
258 FPGA_Signature_Register = 0x210,
259 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */
260 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */
261 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */
262 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */
263 FPGA_Temp_Control_Register = 0x2a0,
264 FPGA_DAR_Register = 0x2a8,
265 FPGA_ELC_Read_Register = 0x2b8,
266 FPGA_ELC_Write_Register = 0x2bc,
267 };
268 enum FPGA_Control_Bits {
269 FPGA_Enable_Bit = 0x8000,
270 };
271
272 #define TIMER_BASE 50 /* nanoseconds */
273
274 #ifdef USE_DMA
275 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
276 #else
277 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
278 #endif
279
280 static int ni_pcidio_cancel(struct comedi_device *dev,
281 struct comedi_subdevice *s);
282
283 enum nidio_boardid {
284 BOARD_PCIDIO_32HS,
285 BOARD_PXI6533,
286 BOARD_PCI6534,
287 };
288
289 struct nidio_board {
290 const char *name;
291 unsigned int uses_firmware:1;
292 };
293
294 static const struct nidio_board nidio_boards[] = {
295 [BOARD_PCIDIO_32HS] = {
296 .name = "pci-dio-32hs",
297 },
298 [BOARD_PXI6533] = {
299 .name = "pxi-6533",
300 },
301 [BOARD_PCI6534] = {
302 .name = "pci-6534",
303 .uses_firmware = 1,
304 },
305 };
306
307 struct nidio96_private {
308 struct mite_struct *mite;
309 int boardtype;
310 int dio;
311 unsigned short OpModeBits;
312 struct mite_channel *di_mite_chan;
313 struct mite_dma_descriptor_ring *di_mite_ring;
314 spinlock_t mite_channel_lock;
315 };
316
317 static int ni_pcidio_cmdtest(struct comedi_device *dev,
318 struct comedi_subdevice *s,
319 struct comedi_cmd *cmd);
320 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
321 static int ni_pcidio_inttrig(struct comedi_device *dev,
322 struct comedi_subdevice *s, unsigned int trignum);
323 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode);
324 static int setup_mite_dma(struct comedi_device *dev,
325 struct comedi_subdevice *s);
326
327 #ifdef DEBUG_FLAGS
328 static void ni_pcidio_print_flags(unsigned int flags);
329 static void ni_pcidio_print_status(unsigned int status);
330 #else
331 #define ni_pcidio_print_flags(x)
332 #define ni_pcidio_print_status(x)
333 #endif
334
335 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
336 {
337 struct nidio96_private *devpriv = dev->private;
338 unsigned long flags;
339
340 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
341 BUG_ON(devpriv->di_mite_chan);
342 devpriv->di_mite_chan =
343 mite_request_channel_in_range(devpriv->mite,
344 devpriv->di_mite_ring, 1, 2);
345 if (devpriv->di_mite_chan == NULL) {
346 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
347 comedi_error(dev, "failed to reserve mite dma channel.");
348 return -EBUSY;
349 }
350 devpriv->di_mite_chan->dir = COMEDI_INPUT;
351 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
352 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
353 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
354 mmiowb();
355 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
356 return 0;
357 }
358
359 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
360 {
361 struct nidio96_private *devpriv = dev->private;
362 unsigned long flags;
363
364 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
365 if (devpriv->di_mite_chan) {
366 mite_dma_disarm(devpriv->di_mite_chan);
367 mite_dma_reset(devpriv->di_mite_chan);
368 mite_release_channel(devpriv->di_mite_chan);
369 devpriv->di_mite_chan = NULL;
370 writeb(primary_DMAChannel_bits(0) |
371 secondary_DMAChannel_bits(0),
372 devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
373 mmiowb();
374 }
375 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
376 }
377
378 static void ni_pcidio_event(struct comedi_device *dev,
379 struct comedi_subdevice *s)
380 {
381 if (s->
382 async->events & (COMEDI_CB_EOA | COMEDI_CB_ERROR |
383 COMEDI_CB_OVERFLOW)) {
384 ni_pcidio_cancel(dev, s);
385 }
386 comedi_event(dev, s);
387 }
388
389 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
390 {
391 struct nidio96_private *devpriv = dev->private;
392 unsigned long irq_flags;
393 int count;
394
395 spin_lock_irqsave(&dev->spinlock, irq_flags);
396 spin_lock(&devpriv->mite_channel_lock);
397 if (devpriv->di_mite_chan)
398 mite_sync_input_dma(devpriv->di_mite_chan, s->async);
399 spin_unlock(&devpriv->mite_channel_lock);
400 count = s->async->buf_write_count - s->async->buf_read_count;
401 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
402 return count;
403 }
404
405 static irqreturn_t nidio_interrupt(int irq, void *d)
406 {
407 struct comedi_device *dev = d;
408 struct nidio96_private *devpriv = dev->private;
409 struct comedi_subdevice *s = &dev->subdevices[0];
410 struct comedi_async *async = s->async;
411 struct mite_struct *mite = devpriv->mite;
412
413 /* int i, j; */
414 long int AuxData = 0;
415 short data1 = 0;
416 short data2 = 0;
417 int flags;
418 int status;
419 int work = 0;
420 unsigned int m_status = 0;
421
422 /* interrupcions parasites */
423 if (!dev->attached) {
424 /* assume it's from another card */
425 return IRQ_NONE;
426 }
427
428 /* Lock to avoid race with comedi_poll */
429 spin_lock(&dev->spinlock);
430
431 status = readb(devpriv->mite->daq_io_addr +
432 Interrupt_And_Window_Status);
433 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
434
435 DPRINTK("ni_pcidio_interrupt: status=0x%02x,flags=0x%02x\n",
436 status, flags);
437 ni_pcidio_print_flags(flags);
438 ni_pcidio_print_status(status);
439
440 spin_lock(&devpriv->mite_channel_lock);
441 if (devpriv->di_mite_chan)
442 m_status = mite_get_status(devpriv->di_mite_chan);
443 #ifdef MITE_DEBUG
444 mite_print_chsr(m_status);
445 #endif
446
447 /* mite_dump_regs(mite); */
448 if (m_status & CHSR_INT) {
449 if (m_status & CHSR_LINKC) {
450 writel(CHOR_CLRLC,
451 mite->mite_io_addr +
452 MITE_CHOR(devpriv->di_mite_chan->channel));
453 mite_sync_input_dma(devpriv->di_mite_chan, s->async);
454 /* XXX need to byteswap */
455 }
456 if (m_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_DRDY |
457 CHSR_DRQ1 | CHSR_MRDY)) {
458 DPRINTK("unknown mite interrupt, disabling IRQ\n");
459 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
460 disable_irq(dev->irq);
461 }
462 }
463 spin_unlock(&devpriv->mite_channel_lock);
464
465 while (status & DataLeft) {
466 work++;
467 if (work > 20) {
468 DPRINTK("too much work in interrupt\n");
469 writeb(0x00,
470 devpriv->mite->daq_io_addr +
471 Master_DMA_And_Interrupt_Control);
472 break;
473 }
474
475 flags &= IntEn;
476
477 if (flags & TransferReady) {
478 /* DPRINTK("TransferReady\n"); */
479 while (flags & TransferReady) {
480 work++;
481 if (work > 100) {
482 DPRINTK("too much work in interrupt\n");
483 writeb(0x00,
484 devpriv->mite->daq_io_addr +
485 Master_DMA_And_Interrupt_Control
486 );
487 goto out;
488 }
489 AuxData =
490 readl(devpriv->mite->daq_io_addr +
491 Group_1_FIFO);
492 data1 = AuxData & 0xffff;
493 data2 = (AuxData & 0xffff0000) >> 16;
494 comedi_buf_put(async, data1);
495 comedi_buf_put(async, data2);
496 /* DPRINTK("read:%d, %d\n",data1,data2); */
497 flags = readb(devpriv->mite->daq_io_addr +
498 Group_1_Flags);
499 }
500 /* DPRINTK("buf_int_count: %d\n",
501 async->buf_int_count); */
502 /* DPRINTK("1) IntEn=%d,flags=%d,status=%d\n",
503 IntEn,flags,status); */
504 /* ni_pcidio_print_flags(flags); */
505 /* ni_pcidio_print_status(status); */
506 async->events |= COMEDI_CB_BLOCK;
507 }
508
509 if (flags & CountExpired) {
510 DPRINTK("CountExpired\n");
511 writeb(ClearExpired,
512 devpriv->mite->daq_io_addr +
513 Group_1_Second_Clear);
514 async->events |= COMEDI_CB_EOA;
515
516 writeb(0x00, devpriv->mite->daq_io_addr + OpMode);
517 break;
518 } else if (flags & Waited) {
519 DPRINTK("Waited\n");
520 writeb(ClearWaited,
521 devpriv->mite->daq_io_addr +
522 Group_1_First_Clear);
523 async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
524 break;
525 } else if (flags & PrimaryTC) {
526 DPRINTK("PrimaryTC\n");
527 writeb(ClearPrimaryTC,
528 devpriv->mite->daq_io_addr +
529 Group_1_First_Clear);
530 async->events |= COMEDI_CB_EOA;
531 } else if (flags & SecondaryTC) {
532 DPRINTK("SecondaryTC\n");
533 writeb(ClearSecondaryTC,
534 devpriv->mite->daq_io_addr +
535 Group_1_First_Clear);
536 async->events |= COMEDI_CB_EOA;
537 }
538 #if 0
539 else {
540 DPRINTK("ni_pcidio: unknown interrupt\n");
541 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
542 writeb(0x00,
543 devpriv->mite->daq_io_addr +
544 Master_DMA_And_Interrupt_Control);
545 }
546 #endif
547 flags = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
548 status = readb(devpriv->mite->daq_io_addr +
549 Interrupt_And_Window_Status);
550 /* DPRINTK("loop end: IntEn=0x%02x,flags=0x%02x,"
551 "status=0x%02x\n", IntEn, flags, status); */
552 /* ni_pcidio_print_flags(flags); */
553 /* ni_pcidio_print_status(status); */
554 }
555
556 out:
557 ni_pcidio_event(dev, s);
558 #if 0
559 if (!tag) {
560 writeb(0x03,
561 devpriv->mite->daq_io_addr +
562 Master_DMA_And_Interrupt_Control);
563 }
564 #endif
565
566 spin_unlock(&dev->spinlock);
567 return IRQ_HANDLED;
568 }
569
570 #ifdef DEBUG_FLAGS
571 static const char *bit_set_string(unsigned int bits, unsigned int bit,
572 const char *const strings[])
573 {
574 return (bits & (1U << bit)) ? strings[bit] : "";
575 }
576
577 static const char *const flags_strings[] = {
578 " TransferReady", " CountExpired", " 2", " 3",
579 " 4", " Waited", " PrimaryTC", " SecondaryTC",
580 };
581
582
583 static void ni_pcidio_print_flags(unsigned int flags)
584 {
585 pr_debug("group_1_flags:%s%s%s%s%s%s%s%s\n",
586 bit_set_string(flags, 7, flags_strings),
587 bit_set_string(flags, 6, flags_strings),
588 bit_set_string(flags, 5, flags_strings),
589 bit_set_string(flags, 4, flags_strings),
590 bit_set_string(flags, 3, flags_strings),
591 bit_set_string(flags, 2, flags_strings),
592 bit_set_string(flags, 1, flags_strings),
593 bit_set_string(flags, 0, flags_strings));
594 }
595
596 static const char *const status_strings[] = {
597 " DataLeft1", " Reserved1", " Req1", " StopTrig1",
598 " DataLeft2", " Reserved2", " Req2", " StopTrig2",
599 };
600
601 static void ni_pcidio_print_status(unsigned int flags)
602 {
603 pr_debug("group_status:%s%s%s%s%s%s%s%s\n",
604 bit_set_string(flags, 7, status_strings),
605 bit_set_string(flags, 6, status_strings),
606 bit_set_string(flags, 5, status_strings),
607 bit_set_string(flags, 4, status_strings),
608 bit_set_string(flags, 3, status_strings),
609 bit_set_string(flags, 2, status_strings),
610 bit_set_string(flags, 1, status_strings),
611 bit_set_string(flags, 0, status_strings));
612 }
613 #endif
614
615 #ifdef unused
616 static void debug_int(struct comedi_device *dev)
617 {
618 struct nidio96_private *devpriv = dev->private;
619 int a, b;
620 static int n_int;
621 struct timeval tv;
622
623 do_gettimeofday(&tv);
624 a = readb(devpriv->mite->daq_io_addr + Group_Status);
625 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
626
627 if (n_int < 10) {
628 DPRINTK("status 0x%02x flags 0x%02x time %06d\n", a, b,
629 (int)tv.tv_usec);
630 }
631
632 while (b & 1) {
633 writew(0xff, devpriv->mite->daq_io_addr + Group_1_FIFO);
634 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
635 }
636
637 b = readb(devpriv->mite->daq_io_addr + Group_1_Flags);
638
639 if (n_int < 10) {
640 DPRINTK("new status 0x%02x\n", b);
641 n_int++;
642 }
643 }
644 #endif
645
646 static int ni_pcidio_insn_config(struct comedi_device *dev,
647 struct comedi_subdevice *s,
648 struct comedi_insn *insn, unsigned int *data)
649 {
650 struct nidio96_private *devpriv = dev->private;
651
652 if (insn->n != 1)
653 return -EINVAL;
654 switch (data[0]) {
655 case INSN_CONFIG_DIO_OUTPUT:
656 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
657 break;
658 case INSN_CONFIG_DIO_INPUT:
659 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
660 break;
661 case INSN_CONFIG_DIO_QUERY:
662 data[1] =
663 (s->
664 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
665 COMEDI_INPUT;
666 return insn->n;
667 break;
668 default:
669 return -EINVAL;
670 }
671 writel(s->io_bits, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
672
673 return 1;
674 }
675
676 static int ni_pcidio_insn_bits(struct comedi_device *dev,
677 struct comedi_subdevice *s,
678 struct comedi_insn *insn, unsigned int *data)
679 {
680 struct nidio96_private *devpriv = dev->private;
681
682 if (data[0]) {
683 s->state &= ~data[0];
684 s->state |= (data[0] & data[1]);
685 writel(s->state, devpriv->mite->daq_io_addr + Port_IO(0));
686 }
687 data[1] = readl(devpriv->mite->daq_io_addr + Port_IO(0));
688
689 return insn->n;
690 }
691
692 static int ni_pcidio_cmdtest(struct comedi_device *dev,
693 struct comedi_subdevice *s, struct comedi_cmd *cmd)
694 {
695 int err = 0;
696 int tmp;
697
698 /* Step 1 : check if triggers are trivially valid */
699
700 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
701 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
702 TRIG_TIMER | TRIG_EXT);
703 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
704 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
705 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
706
707 if (err)
708 return 1;
709
710 /* Step 2a : make sure trigger sources are unique */
711
712 err |= cfc_check_trigger_is_unique(cmd->start_src);
713 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
714 err |= cfc_check_trigger_is_unique(cmd->stop_src);
715
716 /* Step 2b : and mutually compatible */
717
718 if (err)
719 return 2;
720
721 /* Step 3: check if arguments are trivially valid */
722
723 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
724
725 #define MAX_SPEED (TIMER_BASE) /* in nanoseconds */
726
727 if (cmd->scan_begin_src == TRIG_TIMER) {
728 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
729 MAX_SPEED);
730 /* no minimum speed */
731 } else {
732 /* TRIG_EXT */
733 /* should be level/edge, hi/lo specification here */
734 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
735 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
736 err |= -EINVAL;
737 }
738 }
739
740 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
741 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
742
743 if (cmd->stop_src == TRIG_COUNT) {
744 /* no limit */
745 } else { /* TRIG_NONE */
746 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
747 }
748
749 if (err)
750 return 3;
751
752 /* step 4: fix up any arguments */
753
754 if (cmd->scan_begin_src == TRIG_TIMER) {
755 tmp = cmd->scan_begin_arg;
756 ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
757 cmd->flags & TRIG_ROUND_MASK);
758 if (tmp != cmd->scan_begin_arg)
759 err++;
760 }
761
762 if (err)
763 return 4;
764
765 return 0;
766 }
767
768 static int ni_pcidio_ns_to_timer(int *nanosec, int round_mode)
769 {
770 int divider, base;
771
772 base = TIMER_BASE;
773
774 switch (round_mode) {
775 case TRIG_ROUND_NEAREST:
776 default:
777 divider = (*nanosec + base / 2) / base;
778 break;
779 case TRIG_ROUND_DOWN:
780 divider = (*nanosec) / base;
781 break;
782 case TRIG_ROUND_UP:
783 divider = (*nanosec + base - 1) / base;
784 break;
785 }
786
787 *nanosec = base * divider;
788 return divider;
789 }
790
791 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
792 {
793 struct nidio96_private *devpriv = dev->private;
794 struct comedi_cmd *cmd = &s->async->cmd;
795
796 /* XXX configure ports for input */
797 writel(0x0000, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
798
799 if (1) {
800 /* enable fifos A B C D */
801 writeb(0x0f, devpriv->mite->daq_io_addr + Data_Path);
802
803 /* set transfer width a 32 bits */
804 writeb(TransferWidth(0) | TransferLength(0),
805 devpriv->mite->daq_io_addr + Transfer_Size_Control);
806 } else {
807 writeb(0x03, devpriv->mite->daq_io_addr + Data_Path);
808 writeb(TransferWidth(3) | TransferLength(0),
809 devpriv->mite->daq_io_addr + Transfer_Size_Control);
810 }
811
812 /* protocol configuration */
813 if (cmd->scan_begin_src == TRIG_TIMER) {
814 /* page 4-5, "input with internal REQs" */
815 writeb(0, devpriv->mite->daq_io_addr + OpMode);
816 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
817 writeb(1, devpriv->mite->daq_io_addr + Sequence);
818 writeb(0x04, devpriv->mite->daq_io_addr + ReqReg);
819 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
820 writeb(3, devpriv->mite->daq_io_addr + LinePolarities);
821 writeb(0xc0, devpriv->mite->daq_io_addr + AckSer);
822 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
823 TRIG_ROUND_NEAREST),
824 devpriv->mite->daq_io_addr + StartDelay);
825 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
826 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
827 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
828 writeb(0x0b, devpriv->mite->daq_io_addr + AckNotDelay);
829 writeb(0x01, devpriv->mite->daq_io_addr + Data1Delay);
830 /* manual, page 4-5: ClockSpeed comment is incorrectly listed
831 * on DAQOptions */
832 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
833 writeb(0, devpriv->mite->daq_io_addr + DAQOptions);
834 } else {
835 /* TRIG_EXT */
836 /* page 4-5, "input with external REQs" */
837 writeb(0, devpriv->mite->daq_io_addr + OpMode);
838 writeb(0x00, devpriv->mite->daq_io_addr + ClockReg);
839 writeb(0, devpriv->mite->daq_io_addr + Sequence);
840 writeb(0x00, devpriv->mite->daq_io_addr + ReqReg);
841 writeb(4, devpriv->mite->daq_io_addr + BlockMode);
842 if (!(cmd->scan_begin_arg & CR_INVERT)) {
843 /* Leading Edge pulse mode */
844 writeb(0, devpriv->mite->daq_io_addr + LinePolarities);
845 } else {
846 /* Trailing Edge pulse mode */
847 writeb(2, devpriv->mite->daq_io_addr + LinePolarities);
848 }
849 writeb(0x00, devpriv->mite->daq_io_addr + AckSer);
850 writel(1, devpriv->mite->daq_io_addr + StartDelay);
851 writeb(1, devpriv->mite->daq_io_addr + ReqDelay);
852 writeb(1, devpriv->mite->daq_io_addr + ReqNotDelay);
853 writeb(1, devpriv->mite->daq_io_addr + AckDelay);
854 writeb(0x0C, devpriv->mite->daq_io_addr + AckNotDelay);
855 writeb(0x10, devpriv->mite->daq_io_addr + Data1Delay);
856 writew(0, devpriv->mite->daq_io_addr + ClockSpeed);
857 writeb(0x60, devpriv->mite->daq_io_addr + DAQOptions);
858 }
859
860 if (cmd->stop_src == TRIG_COUNT) {
861 writel(cmd->stop_arg,
862 devpriv->mite->daq_io_addr + Transfer_Count);
863 } else {
864 /* XXX */
865 }
866
867 #ifdef USE_DMA
868 writeb(ClearPrimaryTC | ClearSecondaryTC,
869 devpriv->mite->daq_io_addr + Group_1_First_Clear);
870
871 {
872 int retval = setup_mite_dma(dev, s);
873 if (retval)
874 return retval;
875 }
876 #else
877 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group1);
878 #endif
879 writeb(0x00, devpriv->mite->daq_io_addr + DMA_Line_Control_Group2);
880
881 /* clear and enable interrupts */
882 writeb(0xff, devpriv->mite->daq_io_addr + Group_1_First_Clear);
883 /* writeb(ClearExpired,
884 devpriv->mite->daq_io_addr+Group_1_Second_Clear); */
885
886 writeb(IntEn, devpriv->mite->daq_io_addr + Interrupt_Control);
887 writeb(0x03,
888 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
889
890 if (cmd->stop_src == TRIG_NONE) {
891 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
892 } else { /* TRIG_TIMER */
893 devpriv->OpModeBits = Numbered | RunMode(7);
894 }
895 if (cmd->start_src == TRIG_NOW) {
896 /* start */
897 writeb(devpriv->OpModeBits,
898 devpriv->mite->daq_io_addr + OpMode);
899 s->async->inttrig = NULL;
900 } else {
901 /* TRIG_INT */
902 s->async->inttrig = ni_pcidio_inttrig;
903 }
904
905 DPRINTK("ni_pcidio: command started\n");
906 return 0;
907 }
908
909 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
910 {
911 struct nidio96_private *devpriv = dev->private;
912 int retval;
913 unsigned long flags;
914
915 retval = ni_pcidio_request_di_mite_channel(dev);
916 if (retval)
917 return retval;
918
919 /* write alloc the entire buffer */
920 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
921
922 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
923 if (devpriv->di_mite_chan) {
924 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
925 mite_dma_arm(devpriv->di_mite_chan);
926 } else
927 retval = -EIO;
928 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
929
930 return retval;
931 }
932
933 static int ni_pcidio_inttrig(struct comedi_device *dev,
934 struct comedi_subdevice *s, unsigned int trignum)
935 {
936 struct nidio96_private *devpriv = dev->private;
937
938 if (trignum != 0)
939 return -EINVAL;
940
941 writeb(devpriv->OpModeBits, devpriv->mite->daq_io_addr + OpMode);
942 s->async->inttrig = NULL;
943
944 return 1;
945 }
946
947 static int ni_pcidio_cancel(struct comedi_device *dev,
948 struct comedi_subdevice *s)
949 {
950 struct nidio96_private *devpriv = dev->private;
951
952 writeb(0x00,
953 devpriv->mite->daq_io_addr + Master_DMA_And_Interrupt_Control);
954 ni_pcidio_release_di_mite_channel(dev);
955
956 return 0;
957 }
958
959 static int ni_pcidio_change(struct comedi_device *dev,
960 struct comedi_subdevice *s, unsigned long new_size)
961 {
962 struct nidio96_private *devpriv = dev->private;
963 int ret;
964
965 ret = mite_buf_change(devpriv->di_mite_ring, s->async);
966 if (ret < 0)
967 return ret;
968
969 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
970
971 return 0;
972 }
973
974 static int pci_6534_load_fpga(struct comedi_device *dev, int fpga_index,
975 const u8 *data, size_t data_len)
976 {
977 struct nidio96_private *devpriv = dev->private;
978 static const int timeout = 1000;
979 int i;
980 size_t j;
981
982 writew(0x80 | fpga_index,
983 devpriv->mite->daq_io_addr + Firmware_Control_Register);
984 writew(0xc0 | fpga_index,
985 devpriv->mite->daq_io_addr + Firmware_Control_Register);
986 for (i = 0;
987 (readw(devpriv->mite->daq_io_addr +
988 Firmware_Status_Register) & 0x2) == 0 && i < timeout; ++i) {
989 udelay(1);
990 }
991 if (i == timeout) {
992 dev_warn(dev->class_dev,
993 "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
994 fpga_index);
995 return -EIO;
996 }
997 writew(0x80 | fpga_index,
998 devpriv->mite->daq_io_addr + Firmware_Control_Register);
999 for (i = 0;
1000 readw(devpriv->mite->daq_io_addr + Firmware_Status_Register) !=
1001 0x3 && i < timeout; ++i) {
1002 udelay(1);
1003 }
1004 if (i == timeout) {
1005 dev_warn(dev->class_dev,
1006 "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
1007 fpga_index);
1008 return -EIO;
1009 }
1010 for (j = 0; j + 1 < data_len;) {
1011 unsigned int value = data[j++];
1012 value |= data[j++] << 8;
1013 writew(value,
1014 devpriv->mite->daq_io_addr + Firmware_Data_Register);
1015 for (i = 0;
1016 (readw(devpriv->mite->daq_io_addr +
1017 Firmware_Status_Register) & 0x2) == 0
1018 && i < timeout; ++i) {
1019 udelay(1);
1020 }
1021 if (i == timeout) {
1022 dev_warn(dev->class_dev,
1023 "ni_pcidio: failed to load word into fpga %i\n",
1024 fpga_index);
1025 return -EIO;
1026 }
1027 if (need_resched())
1028 schedule();
1029 }
1030 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1031 return 0;
1032 }
1033
1034 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
1035 {
1036 return pci_6534_load_fpga(dev, fpga_index, NULL, 0);
1037 }
1038
1039 static int pci_6534_reset_fpgas(struct comedi_device *dev)
1040 {
1041 struct nidio96_private *devpriv = dev->private;
1042 int ret;
1043 int i;
1044
1045 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Control_Register);
1046 for (i = 0; i < 3; ++i) {
1047 ret = pci_6534_reset_fpga(dev, i);
1048 if (ret < 0)
1049 break;
1050 }
1051 writew(0x0, devpriv->mite->daq_io_addr + Firmware_Mask_Register);
1052 return ret;
1053 }
1054
1055 static void pci_6534_init_main_fpga(struct comedi_device *dev)
1056 {
1057 struct nidio96_private *devpriv = dev->private;
1058
1059 writel(0, devpriv->mite->daq_io_addr + FPGA_Control1_Register);
1060 writel(0, devpriv->mite->daq_io_addr + FPGA_Control2_Register);
1061 writel(0, devpriv->mite->daq_io_addr + FPGA_SCALS_Counter_Register);
1062 writel(0, devpriv->mite->daq_io_addr + FPGA_SCAMS_Counter_Register);
1063 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBLS_Counter_Register);
1064 writel(0, devpriv->mite->daq_io_addr + FPGA_SCBMS_Counter_Register);
1065 }
1066
1067 static int pci_6534_upload_firmware(struct comedi_device *dev)
1068 {
1069 struct nidio96_private *devpriv = dev->private;
1070 int ret;
1071 const struct firmware *fw;
1072 static const char *const fw_file[3] = {
1073 FW_PCI_6534_SCARAB_DI, /* loaded into scarab A for DI */
1074 FW_PCI_6534_SCARAB_DO, /* loaded into scarab B for DO */
1075 FW_PCI_6534_MAIN, /* loaded into main FPGA */
1076 };
1077 int n;
1078
1079 ret = pci_6534_reset_fpgas(dev);
1080 if (ret < 0)
1081 return ret;
1082 /* load main FPGA first, then the two scarabs */
1083 for (n = 2; n >= 0; n--) {
1084 ret = request_firmware(&fw, fw_file[n],
1085 &devpriv->mite->pcidev->dev);
1086 if (ret == 0) {
1087 ret = pci_6534_load_fpga(dev, n, fw->data, fw->size);
1088 if (ret == 0 && n == 2)
1089 pci_6534_init_main_fpga(dev);
1090 release_firmware(fw);
1091 }
1092 if (ret < 0)
1093 break;
1094 }
1095 return ret;
1096 }
1097
1098 static int nidio_auto_attach(struct comedi_device *dev,
1099 unsigned long context)
1100 {
1101 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1102 const struct nidio_board *board = NULL;
1103 struct nidio96_private *devpriv;
1104 struct comedi_subdevice *s;
1105 int ret;
1106 unsigned int irq;
1107
1108 if (context < ARRAY_SIZE(nidio_boards))
1109 board = &nidio_boards[context];
1110 if (!board)
1111 return -ENODEV;
1112 dev->board_ptr = board;
1113 dev->board_name = board->name;
1114
1115 ret = comedi_pci_enable(dev);
1116 if (ret)
1117 return ret;
1118
1119 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
1120 if (!devpriv)
1121 return -ENOMEM;
1122 dev->private = devpriv;
1123
1124 spin_lock_init(&devpriv->mite_channel_lock);
1125
1126 devpriv->mite = mite_alloc(pcidev);
1127 if (!devpriv->mite)
1128 return -ENOMEM;
1129
1130 ret = mite_setup(devpriv->mite);
1131 if (ret < 0) {
1132 dev_warn(dev->class_dev, "error setting up mite\n");
1133 return ret;
1134 }
1135
1136 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
1137 if (devpriv->di_mite_ring == NULL)
1138 return -ENOMEM;
1139
1140 irq = mite_irq(devpriv->mite);
1141 if (board->uses_firmware) {
1142 ret = pci_6534_upload_firmware(dev);
1143 if (ret < 0)
1144 return ret;
1145 }
1146
1147 ret = comedi_alloc_subdevices(dev, 1);
1148 if (ret)
1149 return ret;
1150
1151 dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
1152 readb(devpriv->mite->daq_io_addr + Chip_Version));
1153
1154 s = &dev->subdevices[0];
1155
1156 dev->read_subdev = s;
1157 s->type = COMEDI_SUBD_DIO;
1158 s->subdev_flags =
1159 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
1160 SDF_CMD_READ;
1161 s->n_chan = 32;
1162 s->range_table = &range_digital;
1163 s->maxdata = 1;
1164 s->insn_config = &ni_pcidio_insn_config;
1165 s->insn_bits = &ni_pcidio_insn_bits;
1166 s->do_cmd = &ni_pcidio_cmd;
1167 s->do_cmdtest = &ni_pcidio_cmdtest;
1168 s->cancel = &ni_pcidio_cancel;
1169 s->len_chanlist = 32; /* XXX */
1170 s->buf_change = &ni_pcidio_change;
1171 s->async_dma_dir = DMA_BIDIRECTIONAL;
1172 s->poll = &ni_pcidio_poll;
1173
1174 writel(0, devpriv->mite->daq_io_addr + Port_IO(0));
1175 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Directions(0));
1176 writel(0, devpriv->mite->daq_io_addr + Port_Pin_Mask(0));
1177
1178 /* disable interrupts on board */
1179 writeb(0x00,
1180 devpriv->mite->daq_io_addr +
1181 Master_DMA_And_Interrupt_Control);
1182
1183 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
1184 "ni_pcidio", dev);
1185 if (ret < 0)
1186 dev_warn(dev->class_dev, "irq not available\n");
1187
1188 dev->irq = irq;
1189
1190 return 0;
1191 }
1192
1193 static void nidio_detach(struct comedi_device *dev)
1194 {
1195 struct nidio96_private *devpriv = dev->private;
1196
1197 if (dev->irq)
1198 free_irq(dev->irq, dev);
1199 if (devpriv) {
1200 if (devpriv->di_mite_ring) {
1201 mite_free_ring(devpriv->di_mite_ring);
1202 devpriv->di_mite_ring = NULL;
1203 }
1204 if (devpriv->mite) {
1205 mite_unsetup(devpriv->mite);
1206 mite_free(devpriv->mite);
1207 }
1208 }
1209 comedi_pci_disable(dev);
1210 }
1211
1212 static struct comedi_driver ni_pcidio_driver = {
1213 .driver_name = "ni_pcidio",
1214 .module = THIS_MODULE,
1215 .auto_attach = nidio_auto_attach,
1216 .detach = nidio_detach,
1217 };
1218
1219 static int ni_pcidio_pci_probe(struct pci_dev *dev,
1220 const struct pci_device_id *id)
1221 {
1222 return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
1223 }
1224
1225 static DEFINE_PCI_DEVICE_TABLE(ni_pcidio_pci_table) = {
1226 { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
1227 { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
1228 { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
1229 { 0 }
1230 };
1231 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1232
1233 static struct pci_driver ni_pcidio_pci_driver = {
1234 .name = "ni_pcidio",
1235 .id_table = ni_pcidio_pci_table,
1236 .probe = ni_pcidio_pci_probe,
1237 .remove = comedi_pci_auto_unconfig,
1238 };
1239 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1240
1241 MODULE_AUTHOR("Comedi http://www.comedi.org");
1242 MODULE_DESCRIPTION("Comedi low-level driver");
1243 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)