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xenbus_client.c: correct exit path for xenbus_map_ring_valloc_hvm
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23 */
24
25 /*
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
28
29 Interrupt support originally added by Truxton Fulton
30 <trux@truxton.com>
31
32 References (from ftp://ftp.natinst.com/support/manuals):
33
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
38 release_ni611x.pdf
39 release_ni67xx.pdf
40 Other possibly relevant info:
41
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
44 320889a.pdf delete
45 320906c.pdf maximum signal ratings
46 321066a.pdf about 16x
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
51
52 ISSUES:
53
54 - the interrupt routine needs to be cleaned up
55
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
58 */
59
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
63
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
66 #include "8255.h"
67 #include "mite.h"
68 #include "comedi_fc.h"
69
70 #ifndef MDPRINTK
71 #define MDPRINTK(format, args...)
72 #endif
73
74 /* A timeout count */
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
77
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
91 };
92
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
94 RANGE(-10, 10),
95 RANGE(-5, 5),
96 RANGE(-2.5, 2.5),
97 RANGE(-1, 1),
98 RANGE(-0.5, 0.5),
99 RANGE(-0.25, 0.25),
100 RANGE(-0.1, 0.1),
101 RANGE(-0.05, 0.05),
102 RANGE(0, 20),
103 RANGE(0, 10),
104 RANGE(0, 5),
105 RANGE(0, 2),
106 RANGE(0, 1),
107 RANGE(0, 0.5),
108 RANGE(0, 0.2),
109 RANGE(0, 0.1),
110 }
111 };
112
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
114 RANGE(-10, 10),
115 RANGE(-5, 5),
116 RANGE(-1, 1),
117 RANGE(-0.1,
118 0.1),
119 RANGE(0, 10),
120 RANGE(0, 5),
121 RANGE(0, 1),
122 RANGE(0, 0.1),
123 }
124 };
125
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
127 RANGE(-10,
128 10),
129 RANGE(-5, 5),
130 RANGE(-2, 2),
131 RANGE(-1, 1),
132 RANGE(-0.5,
133 0.5),
134 RANGE(-0.2,
135 0.2),
136 RANGE(-0.1,
137 0.1),
138 RANGE(0, 10),
139 RANGE(0, 5),
140 RANGE(0, 2),
141 RANGE(0, 1),
142 RANGE(0,
143 0.5),
144 RANGE(0,
145 0.2),
146 RANGE(0,
147 0.1),
148 }
149 };
150
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
152 RANGE(-10, 10),
153 RANGE(-5, 5),
154 RANGE(-0.5,
155 0.5),
156 RANGE(-0.05,
157 0.05),
158 }
159 };
160
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
162 RANGE(-50, 50),
163 RANGE(-20, 20),
164 RANGE(-10, 10),
165 RANGE(-5, 5),
166 RANGE(-2, 2),
167 RANGE(-1, 1),
168 RANGE(-0.5, 0.5),
169 RANGE(-0.2, 0.2),
170 }
171 };
172
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
174 RANGE(-10, 10),
175 RANGE(-5, 5),
176 RANGE(-1, 1),
177 RANGE(-0.2, 0.2),
178 }
179 };
180
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
182 RANGE(-10, 10),
183 RANGE(-5, 5),
184 RANGE(-2, 2),
185 RANGE(-1, 1),
186 RANGE(-0.5, 0.5),
187 RANGE(-0.2, 0.2),
188 RANGE(-0.1, 0.1),
189 }
190 };
191
192 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
193 RANGE(-10, 10),
194 RANGE(0, 10),
195 RANGE_ext(-1, 1),
196 RANGE_ext(0, 1),
197 }
198 };
199
200 static const struct comedi_lrange *const ni_range_lkup[] = {
201 [ai_gain_16] = &range_ni_E_ai,
202 [ai_gain_8] = &range_ni_E_ai_limited,
203 [ai_gain_14] = &range_ni_E_ai_limited14,
204 [ai_gain_4] = &range_ni_E_ai_bipolar4,
205 [ai_gain_611x] = &range_ni_E_ai_611x,
206 [ai_gain_622x] = &range_ni_M_ai_622x,
207 [ai_gain_628x] = &range_ni_M_ai_628x,
208 [ai_gain_6143] = &range_bipolar5
209 };
210
211 static int ni_dio_insn_config(struct comedi_device *dev,
212 struct comedi_subdevice *s,
213 struct comedi_insn *insn, unsigned int *data);
214 static int ni_dio_insn_bits(struct comedi_device *dev,
215 struct comedi_subdevice *s,
216 struct comedi_insn *insn, unsigned int *data);
217 static int ni_cdio_cmdtest(struct comedi_device *dev,
218 struct comedi_subdevice *s, struct comedi_cmd *cmd);
219 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
220 static int ni_cdio_cancel(struct comedi_device *dev,
221 struct comedi_subdevice *s);
222 static void handle_cdio_interrupt(struct comedi_device *dev);
223 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
224 unsigned int trignum);
225
226 static int ni_serial_insn_config(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_insn *insn, unsigned int *data);
229 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 unsigned char data_out,
232 unsigned char *data_in);
233 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 unsigned char data_out,
236 unsigned char *data_in);
237
238 static int ni_calib_insn_read(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 struct comedi_insn *insn, unsigned int *data);
241 static int ni_calib_insn_write(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_insn *insn, unsigned int *data);
244
245 static int ni_eeprom_insn_read(struct comedi_device *dev,
246 struct comedi_subdevice *s,
247 struct comedi_insn *insn, unsigned int *data);
248 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
249 struct comedi_subdevice *s,
250 struct comedi_insn *insn,
251 unsigned int *data);
252
253 static int ni_pfi_insn_bits(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn, unsigned int *data);
256 static int ni_pfi_insn_config(struct comedi_device *dev,
257 struct comedi_subdevice *s,
258 struct comedi_insn *insn, unsigned int *data);
259 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
260 unsigned chan);
261
262 static void ni_rtsi_init(struct comedi_device *dev);
263 static int ni_rtsi_insn_bits(struct comedi_device *dev,
264 struct comedi_subdevice *s,
265 struct comedi_insn *insn, unsigned int *data);
266 static int ni_rtsi_insn_config(struct comedi_device *dev,
267 struct comedi_subdevice *s,
268 struct comedi_insn *insn, unsigned int *data);
269
270 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
271 static int ni_read_eeprom(struct comedi_device *dev, int addr);
272
273 #ifdef DEBUG_STATUS_A
274 static void ni_mio_print_status_a(int status);
275 #else
276 #define ni_mio_print_status_a(a)
277 #endif
278 #ifdef DEBUG_STATUS_B
279 static void ni_mio_print_status_b(int status);
280 #else
281 #define ni_mio_print_status_b(a)
282 #endif
283
284 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
285 #ifndef PCIDMA
286 static void ni_handle_fifo_half_full(struct comedi_device *dev);
287 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
288 struct comedi_subdevice *s);
289 #endif
290 static void ni_handle_fifo_dregs(struct comedi_device *dev);
291 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
292 unsigned int trignum);
293 static void ni_load_channelgain_list(struct comedi_device *dev,
294 unsigned int n_chan, unsigned int *list);
295 static void shutdown_ai_command(struct comedi_device *dev);
296
297 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
298 unsigned int trignum);
299
300 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
301
302 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
303
304 static int ni_gpct_insn_write(struct comedi_device *dev,
305 struct comedi_subdevice *s,
306 struct comedi_insn *insn, unsigned int *data);
307 static int ni_gpct_insn_read(struct comedi_device *dev,
308 struct comedi_subdevice *s,
309 struct comedi_insn *insn, unsigned int *data);
310 static int ni_gpct_insn_config(struct comedi_device *dev,
311 struct comedi_subdevice *s,
312 struct comedi_insn *insn, unsigned int *data);
313 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
314 static int ni_gpct_cmdtest(struct comedi_device *dev,
315 struct comedi_subdevice *s, struct comedi_cmd *cmd);
316 static int ni_gpct_cancel(struct comedi_device *dev,
317 struct comedi_subdevice *s);
318 static void handle_gpct_interrupt(struct comedi_device *dev,
319 unsigned short counter_index);
320
321 static int init_cs5529(struct comedi_device *dev);
322 static int cs5529_do_conversion(struct comedi_device *dev,
323 unsigned short *data);
324 static int cs5529_ai_insn_read(struct comedi_device *dev,
325 struct comedi_subdevice *s,
326 struct comedi_insn *insn, unsigned int *data);
327 #ifdef NI_CS5529_DEBUG
328 static unsigned int cs5529_config_read(struct comedi_device *dev,
329 unsigned int reg_select_bits);
330 #endif
331 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
332 unsigned int reg_select_bits);
333
334 static int ni_m_series_pwm_config(struct comedi_device *dev,
335 struct comedi_subdevice *s,
336 struct comedi_insn *insn, unsigned int *data);
337 static int ni_6143_pwm_config(struct comedi_device *dev,
338 struct comedi_subdevice *s,
339 struct comedi_insn *insn, unsigned int *data);
340
341 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
342 unsigned period_ns);
343 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
344 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
345
346 enum aimodes {
347 AIMODE_NONE = 0,
348 AIMODE_HALF_FULL = 1,
349 AIMODE_SCAN = 2,
350 AIMODE_SAMPLE = 3,
351 };
352
353 enum ni_common_subdevices {
354 NI_AI_SUBDEV,
355 NI_AO_SUBDEV,
356 NI_DIO_SUBDEV,
357 NI_8255_DIO_SUBDEV,
358 NI_UNUSED_SUBDEV,
359 NI_CALIBRATION_SUBDEV,
360 NI_EEPROM_SUBDEV,
361 NI_PFI_DIO_SUBDEV,
362 NI_CS5529_CALIBRATION_SUBDEV,
363 NI_SERIAL_SUBDEV,
364 NI_RTSI_SUBDEV,
365 NI_GPCT0_SUBDEV,
366 NI_GPCT1_SUBDEV,
367 NI_FREQ_OUT_SUBDEV,
368 NI_NUM_SUBDEVICES
369 };
370 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
371 {
372 switch (counter_index) {
373 case 0:
374 return NI_GPCT0_SUBDEV;
375 break;
376 case 1:
377 return NI_GPCT1_SUBDEV;
378 break;
379 default:
380 break;
381 }
382 BUG();
383 return NI_GPCT0_SUBDEV;
384 }
385
386 enum timebase_nanoseconds {
387 TIMEBASE_1_NS = 50,
388 TIMEBASE_2_NS = 10000
389 };
390
391 #define SERIAL_DISABLED 0
392 #define SERIAL_600NS 600
393 #define SERIAL_1_2US 1200
394 #define SERIAL_10US 10000
395
396 static const int num_adc_stages_611x = 3;
397
398 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
399 unsigned ai_mite_status);
400 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
401 unsigned ao_mite_status);
402 static void get_last_sample_611x(struct comedi_device *dev);
403 static void get_last_sample_6143(struct comedi_device *dev);
404
405 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
406 unsigned bit_mask, unsigned bit_values)
407 {
408 struct ni_private *devpriv = dev->private;
409 unsigned long flags;
410
411 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
412 switch (reg) {
413 case Interrupt_A_Enable_Register:
414 devpriv->int_a_enable_reg &= ~bit_mask;
415 devpriv->int_a_enable_reg |= bit_values & bit_mask;
416 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
417 Interrupt_A_Enable_Register);
418 break;
419 case Interrupt_B_Enable_Register:
420 devpriv->int_b_enable_reg &= ~bit_mask;
421 devpriv->int_b_enable_reg |= bit_values & bit_mask;
422 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
423 Interrupt_B_Enable_Register);
424 break;
425 case IO_Bidirection_Pin_Register:
426 devpriv->io_bidirection_pin_reg &= ~bit_mask;
427 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
428 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
429 IO_Bidirection_Pin_Register);
430 break;
431 case AI_AO_Select:
432 devpriv->ai_ao_select_reg &= ~bit_mask;
433 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
434 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
435 break;
436 case G0_G1_Select:
437 devpriv->g0_g1_select_reg &= ~bit_mask;
438 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
439 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
440 break;
441 default:
442 printk("Warning %s() called with invalid register\n", __func__);
443 printk("reg is %d\n", reg);
444 break;
445 }
446 mmiowb();
447 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
448 }
449
450 #ifdef PCIDMA
451 static int ni_ai_drain_dma(struct comedi_device *dev);
452
453 /* DMA channel setup */
454
455 /* negative channel means no channel */
456 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
457 {
458 unsigned bitfield;
459
460 if (channel >= 0) {
461 bitfield =
462 (ni_stc_dma_channel_select_bitfield(channel) <<
463 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
464 } else {
465 bitfield = 0;
466 }
467 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
468 }
469
470 /* negative channel means no channel */
471 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
472 {
473 unsigned bitfield;
474
475 if (channel >= 0) {
476 bitfield =
477 (ni_stc_dma_channel_select_bitfield(channel) <<
478 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
479 } else {
480 bitfield = 0;
481 }
482 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
483 }
484
485 /* negative mite_channel means no channel */
486 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
487 unsigned gpct_index,
488 int mite_channel)
489 {
490 unsigned bitfield;
491
492 if (mite_channel >= 0) {
493 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
494 } else {
495 bitfield = 0;
496 }
497 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
498 bitfield);
499 }
500
501 /* negative mite_channel means no channel */
502 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
503 int mite_channel)
504 {
505 struct ni_private *devpriv = dev->private;
506 unsigned long flags;
507
508 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
509 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
510 if (mite_channel >= 0) {
511 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
512 under the assumption the cdio dma selection works just like ai/ao/gpct.
513 Definitely works for dma channels 0 and 1. */
514 devpriv->cdio_dma_select_reg |=
515 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
516 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
517 }
518 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
519 mmiowb();
520 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
521 }
522
523 static int ni_request_ai_mite_channel(struct comedi_device *dev)
524 {
525 struct ni_private *devpriv = dev->private;
526 unsigned long flags;
527
528 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
529 BUG_ON(devpriv->ai_mite_chan);
530 devpriv->ai_mite_chan =
531 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
532 if (devpriv->ai_mite_chan == NULL) {
533 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
534 comedi_error(dev,
535 "failed to reserve mite dma channel for analog input.");
536 return -EBUSY;
537 }
538 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
539 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
540 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
541 return 0;
542 }
543
544 static int ni_request_ao_mite_channel(struct comedi_device *dev)
545 {
546 struct ni_private *devpriv = dev->private;
547 unsigned long flags;
548
549 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
550 BUG_ON(devpriv->ao_mite_chan);
551 devpriv->ao_mite_chan =
552 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
553 if (devpriv->ao_mite_chan == NULL) {
554 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
555 comedi_error(dev,
556 "failed to reserve mite dma channel for analog outut.");
557 return -EBUSY;
558 }
559 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
560 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
561 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
562 return 0;
563 }
564
565 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
566 unsigned gpct_index,
567 enum comedi_io_direction direction)
568 {
569 struct ni_private *devpriv = dev->private;
570 unsigned long flags;
571 struct mite_channel *mite_chan;
572
573 BUG_ON(gpct_index >= NUM_GPCT);
574 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
575 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
576 mite_chan =
577 mite_request_channel(devpriv->mite,
578 devpriv->gpct_mite_ring[gpct_index]);
579 if (mite_chan == NULL) {
580 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
581 comedi_error(dev,
582 "failed to reserve mite dma channel for counter.");
583 return -EBUSY;
584 }
585 mite_chan->dir = direction;
586 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
587 mite_chan);
588 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
589 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
590 return 0;
591 }
592
593 #endif /* PCIDMA */
594
595 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
596 {
597 #ifdef PCIDMA
598 struct ni_private *devpriv = dev->private;
599 unsigned long flags;
600
601 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
602 BUG_ON(devpriv->cdo_mite_chan);
603 devpriv->cdo_mite_chan =
604 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
605 if (devpriv->cdo_mite_chan == NULL) {
606 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
607 comedi_error(dev,
608 "failed to reserve mite dma channel for correlated digital outut.");
609 return -EBUSY;
610 }
611 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
612 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
613 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
614 #endif /* PCIDMA */
615 return 0;
616 }
617
618 static void ni_release_ai_mite_channel(struct comedi_device *dev)
619 {
620 #ifdef PCIDMA
621 struct ni_private *devpriv = dev->private;
622 unsigned long flags;
623
624 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
625 if (devpriv->ai_mite_chan) {
626 ni_set_ai_dma_channel(dev, -1);
627 mite_release_channel(devpriv->ai_mite_chan);
628 devpriv->ai_mite_chan = NULL;
629 }
630 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
631 #endif /* PCIDMA */
632 }
633
634 static void ni_release_ao_mite_channel(struct comedi_device *dev)
635 {
636 #ifdef PCIDMA
637 struct ni_private *devpriv = dev->private;
638 unsigned long flags;
639
640 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
641 if (devpriv->ao_mite_chan) {
642 ni_set_ao_dma_channel(dev, -1);
643 mite_release_channel(devpriv->ao_mite_chan);
644 devpriv->ao_mite_chan = NULL;
645 }
646 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
647 #endif /* PCIDMA */
648 }
649
650 #ifdef PCIDMA
651 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
652 unsigned gpct_index)
653 {
654 struct ni_private *devpriv = dev->private;
655 unsigned long flags;
656
657 BUG_ON(gpct_index >= NUM_GPCT);
658 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
659 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
660 struct mite_channel *mite_chan =
661 devpriv->counter_dev->counters[gpct_index].mite_chan;
662
663 ni_set_gpct_dma_channel(dev, gpct_index, -1);
664 ni_tio_set_mite_channel(&devpriv->
665 counter_dev->counters[gpct_index],
666 NULL);
667 mite_release_channel(mite_chan);
668 }
669 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
670 }
671 #endif /* PCIDMA */
672
673 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
674 {
675 #ifdef PCIDMA
676 struct ni_private *devpriv = dev->private;
677 unsigned long flags;
678
679 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
680 if (devpriv->cdo_mite_chan) {
681 ni_set_cdo_dma_channel(dev, -1);
682 mite_release_channel(devpriv->cdo_mite_chan);
683 devpriv->cdo_mite_chan = NULL;
684 }
685 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
686 #endif /* PCIDMA */
687 }
688
689 /* e-series boards use the second irq signals to generate dma requests for their counters */
690 #ifdef PCIDMA
691 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
692 unsigned gpct_index, short enable)
693 {
694 const struct ni_board_struct *board = comedi_board(dev);
695 struct ni_private *devpriv = dev->private;
696
697 if (board->reg_type & ni_reg_m_series_mask)
698 return;
699 switch (gpct_index) {
700 case 0:
701 if (enable) {
702 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
703 Second_IRQ_A_Enable_Register);
704 } else {
705 devpriv->stc_writew(dev, 0,
706 Second_IRQ_A_Enable_Register);
707 }
708 break;
709 case 1:
710 if (enable) {
711 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
712 Second_IRQ_B_Enable_Register);
713 } else {
714 devpriv->stc_writew(dev, 0,
715 Second_IRQ_B_Enable_Register);
716 }
717 break;
718 default:
719 BUG();
720 break;
721 }
722 }
723 #endif /* PCIDMA */
724
725 static void ni_clear_ai_fifo(struct comedi_device *dev)
726 {
727 const struct ni_board_struct *board = comedi_board(dev);
728 struct ni_private *devpriv = dev->private;
729
730 if (board->reg_type == ni_reg_6143) {
731 /* Flush the 6143 data FIFO */
732 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
733 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
734 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
735 } else {
736 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
737 if (board->reg_type == ni_reg_625x) {
738 ni_writeb(0, M_Offset_Static_AI_Control(0));
739 ni_writeb(1, M_Offset_Static_AI_Control(0));
740 #if 0
741 /* the NI example code does 3 convert pulses for 625x boards,
742 but that appears to be wrong in practice. */
743 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
744 AI_Command_1_Register);
745 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
746 AI_Command_1_Register);
747 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
748 AI_Command_1_Register);
749 #endif
750 }
751 }
752 }
753
754 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
755 {
756 struct ni_private *devpriv = dev->private;
757
758 devpriv->stc_writew(dev, data >> 16, reg);
759 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
760 }
761
762 static uint32_t win_in2(struct comedi_device *dev, int reg)
763 {
764 struct ni_private *devpriv = dev->private;
765 uint32_t bits;
766
767 bits = devpriv->stc_readw(dev, reg) << 16;
768 bits |= devpriv->stc_readw(dev, reg + 1);
769 return bits;
770 }
771
772 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
773 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
774 int addr)
775 {
776 struct ni_private *devpriv = dev->private;
777 unsigned long flags;
778
779 spin_lock_irqsave(&devpriv->window_lock, flags);
780 ni_writew(addr, AO_Window_Address_611x);
781 ni_writew(data, AO_Window_Data_611x);
782 spin_unlock_irqrestore(&devpriv->window_lock, flags);
783 }
784
785 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
786 int addr)
787 {
788 struct ni_private *devpriv = dev->private;
789 unsigned long flags;
790
791 spin_lock_irqsave(&devpriv->window_lock, flags);
792 ni_writew(addr, AO_Window_Address_611x);
793 ni_writel(data, AO_Window_Data_611x);
794 spin_unlock_irqrestore(&devpriv->window_lock, flags);
795 }
796
797 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
798 {
799 struct ni_private *devpriv = dev->private;
800 unsigned long flags;
801 unsigned short data;
802
803 spin_lock_irqsave(&devpriv->window_lock, flags);
804 ni_writew(addr, AO_Window_Address_611x);
805 data = ni_readw(AO_Window_Data_611x);
806 spin_unlock_irqrestore(&devpriv->window_lock, flags);
807 return data;
808 }
809
810 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
811 * share registers (such as Interrupt_A_Register) without interfering with
812 * each other.
813 *
814 * NOTE: the switch/case statements are optimized out for a constant argument
815 * so this is actually quite fast--- If you must wrap another function around this
816 * make it inline to avoid a large speed penalty.
817 *
818 * value should only be 1 or 0.
819 */
820 static inline void ni_set_bits(struct comedi_device *dev, int reg,
821 unsigned bits, unsigned value)
822 {
823 unsigned bit_values;
824
825 if (value)
826 bit_values = bits;
827 else
828 bit_values = 0;
829 ni_set_bitfield(dev, reg, bits, bit_values);
830 }
831
832 static irqreturn_t ni_E_interrupt(int irq, void *d)
833 {
834 struct comedi_device *dev = d;
835 struct ni_private *devpriv = dev->private;
836 unsigned short a_status;
837 unsigned short b_status;
838 unsigned int ai_mite_status = 0;
839 unsigned int ao_mite_status = 0;
840 unsigned long flags;
841 #ifdef PCIDMA
842 struct mite_struct *mite = devpriv->mite;
843 #endif
844
845 if (!dev->attached)
846 return IRQ_NONE;
847 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
848
849 /* lock to avoid race with comedi_poll */
850 spin_lock_irqsave(&dev->spinlock, flags);
851 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
852 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
853 #ifdef PCIDMA
854 if (mite) {
855 unsigned long flags_too;
856
857 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
858 if (devpriv->ai_mite_chan) {
859 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
860 if (ai_mite_status & CHSR_LINKC)
861 writel(CHOR_CLRLC,
862 devpriv->mite->mite_io_addr +
863 MITE_CHOR(devpriv->
864 ai_mite_chan->channel));
865 }
866 if (devpriv->ao_mite_chan) {
867 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
868 if (ao_mite_status & CHSR_LINKC)
869 writel(CHOR_CLRLC,
870 mite->mite_io_addr +
871 MITE_CHOR(devpriv->
872 ao_mite_chan->channel));
873 }
874 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
875 }
876 #endif
877 ack_a_interrupt(dev, a_status);
878 ack_b_interrupt(dev, b_status);
879 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
880 handle_a_interrupt(dev, a_status, ai_mite_status);
881 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
882 handle_b_interrupt(dev, b_status, ao_mite_status);
883 handle_gpct_interrupt(dev, 0);
884 handle_gpct_interrupt(dev, 1);
885 handle_cdio_interrupt(dev);
886
887 spin_unlock_irqrestore(&dev->spinlock, flags);
888 return IRQ_HANDLED;
889 }
890
891 #ifdef PCIDMA
892 static void ni_sync_ai_dma(struct comedi_device *dev)
893 {
894 struct ni_private *devpriv = dev->private;
895 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
896 unsigned long flags;
897
898 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
899 if (devpriv->ai_mite_chan)
900 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
901 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
902 }
903
904 static void mite_handle_b_linkc(struct mite_struct *mite,
905 struct comedi_device *dev)
906 {
907 struct ni_private *devpriv = dev->private;
908 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
909 unsigned long flags;
910
911 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
912 if (devpriv->ao_mite_chan) {
913 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
914 }
915 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
916 }
917
918 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
919 {
920 struct ni_private *devpriv = dev->private;
921 static const int timeout = 10000;
922 int i;
923 for (i = 0; i < timeout; i++) {
924 unsigned short b_status;
925
926 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
927 if (b_status & AO_FIFO_Half_Full_St)
928 break;
929 /* if we poll too often, the pci bus activity seems
930 to slow the dma transfer down */
931 udelay(10);
932 }
933 if (i == timeout) {
934 comedi_error(dev, "timed out waiting for dma load");
935 return -EPIPE;
936 }
937 return 0;
938 }
939
940 #endif /* PCIDMA */
941 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
942 {
943 struct ni_private *devpriv = dev->private;
944
945 if (devpriv->aimode == AIMODE_SCAN) {
946 #ifdef PCIDMA
947 static const int timeout = 10;
948 int i;
949
950 for (i = 0; i < timeout; i++) {
951 ni_sync_ai_dma(dev);
952 if ((s->async->events & COMEDI_CB_EOS))
953 break;
954 udelay(1);
955 }
956 #else
957 ni_handle_fifo_dregs(dev);
958 s->async->events |= COMEDI_CB_EOS;
959 #endif
960 }
961 /* handle special case of single scan using AI_End_On_End_Of_Scan */
962 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
963 shutdown_ai_command(dev);
964 }
965 }
966
967 static void shutdown_ai_command(struct comedi_device *dev)
968 {
969 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
970
971 #ifdef PCIDMA
972 ni_ai_drain_dma(dev);
973 #endif
974 ni_handle_fifo_dregs(dev);
975 get_last_sample_611x(dev);
976 get_last_sample_6143(dev);
977
978 s->async->events |= COMEDI_CB_EOA;
979 }
980
981 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
982 {
983 if (s->
984 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
985 COMEDI_CB_EOA)) {
986 switch (s->index) {
987 case NI_AI_SUBDEV:
988 ni_ai_reset(dev, s);
989 break;
990 case NI_AO_SUBDEV:
991 ni_ao_reset(dev, s);
992 break;
993 case NI_GPCT0_SUBDEV:
994 case NI_GPCT1_SUBDEV:
995 ni_gpct_cancel(dev, s);
996 break;
997 case NI_DIO_SUBDEV:
998 ni_cdio_cancel(dev, s);
999 break;
1000 default:
1001 break;
1002 }
1003 }
1004 comedi_event(dev, s);
1005 }
1006
1007 static void handle_gpct_interrupt(struct comedi_device *dev,
1008 unsigned short counter_index)
1009 {
1010 #ifdef PCIDMA
1011 struct ni_private *devpriv = dev->private;
1012 struct comedi_subdevice *s;
1013
1014 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1015
1016 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1017 s);
1018 if (s->async->events)
1019 ni_event(dev, s);
1020 #endif
1021 }
1022
1023 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1024 {
1025 struct ni_private *devpriv = dev->private;
1026 unsigned short ack = 0;
1027
1028 if (a_status & AI_SC_TC_St) {
1029 ack |= AI_SC_TC_Interrupt_Ack;
1030 }
1031 if (a_status & AI_START1_St) {
1032 ack |= AI_START1_Interrupt_Ack;
1033 }
1034 if (a_status & AI_START_St) {
1035 ack |= AI_START_Interrupt_Ack;
1036 }
1037 if (a_status & AI_STOP_St) {
1038 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1039 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1040 }
1041 if (ack)
1042 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1043 }
1044
1045 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1046 unsigned ai_mite_status)
1047 {
1048 struct ni_private *devpriv = dev->private;
1049 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1050
1051 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1052 if (s->type == COMEDI_SUBD_UNUSED)
1053 return;
1054
1055 #ifdef DEBUG_INTERRUPT
1056 printk
1057 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1058 status, ai_mite_status);
1059 ni_mio_print_status_a(status);
1060 #endif
1061 #ifdef PCIDMA
1062 if (ai_mite_status & CHSR_LINKC) {
1063 ni_sync_ai_dma(dev);
1064 }
1065
1066 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1067 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1068 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1069 printk
1070 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1071 ai_mite_status);
1072 /* mite_print_chsr(ai_mite_status); */
1073 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1074 /* disable_irq(dev->irq); */
1075 }
1076 #endif
1077
1078 /* test for all uncommon interrupt events at the same time */
1079 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1080 AI_SC_TC_St | AI_START1_St)) {
1081 if (status == 0xffff) {
1082 printk
1083 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1084 /* we probably aren't even running a command now,
1085 * so it's a good idea to be careful. */
1086 if (comedi_is_subdevice_running(s)) {
1087 s->async->events |=
1088 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1089 ni_event(dev, s);
1090 }
1091 return;
1092 }
1093 if (status & (AI_Overrun_St | AI_Overflow_St |
1094 AI_SC_TC_Error_St)) {
1095 printk("ni_mio_common: ai error a_status=%04x\n",
1096 status);
1097 ni_mio_print_status_a(status);
1098
1099 shutdown_ai_command(dev);
1100
1101 s->async->events |= COMEDI_CB_ERROR;
1102 if (status & (AI_Overrun_St | AI_Overflow_St))
1103 s->async->events |= COMEDI_CB_OVERFLOW;
1104
1105 ni_event(dev, s);
1106
1107 return;
1108 }
1109 if (status & AI_SC_TC_St) {
1110 #ifdef DEBUG_INTERRUPT
1111 printk("ni_mio_common: SC_TC interrupt\n");
1112 #endif
1113 if (!devpriv->ai_continuous) {
1114 shutdown_ai_command(dev);
1115 }
1116 }
1117 }
1118 #ifndef PCIDMA
1119 if (status & AI_FIFO_Half_Full_St) {
1120 int i;
1121 static const int timeout = 10;
1122 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1123 *fail to get the fifo less than half full, so loop to be sure.*/
1124 for (i = 0; i < timeout; ++i) {
1125 ni_handle_fifo_half_full(dev);
1126 if ((devpriv->stc_readw(dev,
1127 AI_Status_1_Register) &
1128 AI_FIFO_Half_Full_St) == 0)
1129 break;
1130 }
1131 }
1132 #endif /* !PCIDMA */
1133
1134 if ((status & AI_STOP_St)) {
1135 ni_handle_eos(dev, s);
1136 }
1137
1138 ni_event(dev, s);
1139
1140 #ifdef DEBUG_INTERRUPT
1141 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1142 if (status & Interrupt_A_St) {
1143 printk
1144 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1145 status);
1146 }
1147 #endif
1148 }
1149
1150 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1151 {
1152 struct ni_private *devpriv = dev->private;
1153 unsigned short ack = 0;
1154
1155 if (b_status & AO_BC_TC_St) {
1156 ack |= AO_BC_TC_Interrupt_Ack;
1157 }
1158 if (b_status & AO_Overrun_St) {
1159 ack |= AO_Error_Interrupt_Ack;
1160 }
1161 if (b_status & AO_START_St) {
1162 ack |= AO_START_Interrupt_Ack;
1163 }
1164 if (b_status & AO_START1_St) {
1165 ack |= AO_START1_Interrupt_Ack;
1166 }
1167 if (b_status & AO_UC_TC_St) {
1168 ack |= AO_UC_TC_Interrupt_Ack;
1169 }
1170 if (b_status & AO_UI2_TC_St) {
1171 ack |= AO_UI2_TC_Interrupt_Ack;
1172 }
1173 if (b_status & AO_UPDATE_St) {
1174 ack |= AO_UPDATE_Interrupt_Ack;
1175 }
1176 if (ack)
1177 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1178 }
1179
1180 static void handle_b_interrupt(struct comedi_device *dev,
1181 unsigned short b_status, unsigned ao_mite_status)
1182 {
1183 struct ni_private *devpriv = dev->private;
1184 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1185 /* unsigned short ack=0; */
1186
1187 #ifdef DEBUG_INTERRUPT
1188 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1189 b_status, ao_mite_status);
1190 ni_mio_print_status_b(b_status);
1191 #endif
1192
1193 #ifdef PCIDMA
1194 /* Currently, mite.c requires us to handle LINKC */
1195 if (ao_mite_status & CHSR_LINKC) {
1196 mite_handle_b_linkc(devpriv->mite, dev);
1197 }
1198
1199 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1200 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1201 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1202 printk
1203 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1204 ao_mite_status);
1205 /* mite_print_chsr(ao_mite_status); */
1206 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1207 }
1208 #endif
1209
1210 if (b_status == 0xffff)
1211 return;
1212 if (b_status & AO_Overrun_St) {
1213 printk
1214 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1215 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1216 s->async->events |= COMEDI_CB_OVERFLOW;
1217 }
1218
1219 if (b_status & AO_BC_TC_St) {
1220 MDPRINTK
1221 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1222 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1223 s->async->events |= COMEDI_CB_EOA;
1224 }
1225 #ifndef PCIDMA
1226 if (b_status & AO_FIFO_Request_St) {
1227 int ret;
1228
1229 ret = ni_ao_fifo_half_empty(dev, s);
1230 if (!ret) {
1231 printk("ni_mio_common: AO buffer underrun\n");
1232 ni_set_bits(dev, Interrupt_B_Enable_Register,
1233 AO_FIFO_Interrupt_Enable |
1234 AO_Error_Interrupt_Enable, 0);
1235 s->async->events |= COMEDI_CB_OVERFLOW;
1236 }
1237 }
1238 #endif
1239
1240 ni_event(dev, s);
1241 }
1242
1243 #ifdef DEBUG_STATUS_A
1244 static const char *const status_a_strings[] = {
1245 "passthru0", "fifo", "G0_gate", "G0_TC",
1246 "stop", "start", "sc_tc", "start1",
1247 "start2", "sc_tc_error", "overflow", "overrun",
1248 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1249 };
1250
1251 static void ni_mio_print_status_a(int status)
1252 {
1253 int i;
1254
1255 printk("A status:");
1256 for (i = 15; i >= 0; i--) {
1257 if (status & (1 << i)) {
1258 printk(" %s", status_a_strings[i]);
1259 }
1260 }
1261 printk("\n");
1262 }
1263 #endif
1264
1265 #ifdef DEBUG_STATUS_B
1266 static const char *const status_b_strings[] = {
1267 "passthru1", "fifo", "G1_gate", "G1_TC",
1268 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1269 "start1", "overrun", "start", "bc_tc_error",
1270 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1271 };
1272
1273 static void ni_mio_print_status_b(int status)
1274 {
1275 int i;
1276
1277 printk("B status:");
1278 for (i = 15; i >= 0; i--) {
1279 if (status & (1 << i)) {
1280 printk(" %s", status_b_strings[i]);
1281 }
1282 }
1283 printk("\n");
1284 }
1285 #endif
1286
1287 #ifndef PCIDMA
1288
1289 static void ni_ao_fifo_load(struct comedi_device *dev,
1290 struct comedi_subdevice *s, int n)
1291 {
1292 const struct ni_board_struct *board = comedi_board(dev);
1293 struct comedi_async *async = s->async;
1294 struct comedi_cmd *cmd = &async->cmd;
1295 int chan;
1296 int i;
1297 short d;
1298 u32 packed_data;
1299 int range;
1300 int err = 1;
1301
1302 chan = async->cur_chan;
1303 for (i = 0; i < n; i++) {
1304 err &= comedi_buf_get(async, &d);
1305 if (err == 0)
1306 break;
1307
1308 range = CR_RANGE(cmd->chanlist[chan]);
1309
1310 if (board->reg_type & ni_reg_6xxx_mask) {
1311 packed_data = d & 0xffff;
1312 /* 6711 only has 16 bit wide ao fifo */
1313 if (board->reg_type != ni_reg_6711) {
1314 err &= comedi_buf_get(async, &d);
1315 if (err == 0)
1316 break;
1317 chan++;
1318 i++;
1319 packed_data |= (d << 16) & 0xffff0000;
1320 }
1321 ni_writel(packed_data, DAC_FIFO_Data_611x);
1322 } else {
1323 ni_writew(d, DAC_FIFO_Data);
1324 }
1325 chan++;
1326 chan %= cmd->chanlist_len;
1327 }
1328 async->cur_chan = chan;
1329 if (err == 0) {
1330 async->events |= COMEDI_CB_OVERFLOW;
1331 }
1332 }
1333
1334 /*
1335 * There's a small problem if the FIFO gets really low and we
1336 * don't have the data to fill it. Basically, if after we fill
1337 * the FIFO with all the data available, the FIFO is _still_
1338 * less than half full, we never clear the interrupt. If the
1339 * IRQ is in edge mode, we never get another interrupt, because
1340 * this one wasn't cleared. If in level mode, we get flooded
1341 * with interrupts that we can't fulfill, because nothing ever
1342 * gets put into the buffer.
1343 *
1344 * This kind of situation is recoverable, but it is easier to
1345 * just pretend we had a FIFO underrun, since there is a good
1346 * chance it will happen anyway. This is _not_ the case for
1347 * RT code, as RT code might purposely be running close to the
1348 * metal. Needs to be fixed eventually.
1349 */
1350 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1351 struct comedi_subdevice *s)
1352 {
1353 const struct ni_board_struct *board = comedi_board(dev);
1354 int n;
1355
1356 n = comedi_buf_read_n_available(s->async);
1357 if (n == 0) {
1358 s->async->events |= COMEDI_CB_OVERFLOW;
1359 return 0;
1360 }
1361
1362 n /= sizeof(short);
1363 if (n > board->ao_fifo_depth / 2)
1364 n = board->ao_fifo_depth / 2;
1365
1366 ni_ao_fifo_load(dev, s, n);
1367
1368 s->async->events |= COMEDI_CB_BLOCK;
1369
1370 return 1;
1371 }
1372
1373 static int ni_ao_prep_fifo(struct comedi_device *dev,
1374 struct comedi_subdevice *s)
1375 {
1376 const struct ni_board_struct *board = comedi_board(dev);
1377 struct ni_private *devpriv = dev->private;
1378 int n;
1379
1380 /* reset fifo */
1381 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1382 if (board->reg_type & ni_reg_6xxx_mask)
1383 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1384
1385 /* load some data */
1386 n = comedi_buf_read_n_available(s->async);
1387 if (n == 0)
1388 return 0;
1389
1390 n /= sizeof(short);
1391 if (n > board->ao_fifo_depth)
1392 n = board->ao_fifo_depth;
1393
1394 ni_ao_fifo_load(dev, s, n);
1395
1396 return n;
1397 }
1398
1399 static void ni_ai_fifo_read(struct comedi_device *dev,
1400 struct comedi_subdevice *s, int n)
1401 {
1402 const struct ni_board_struct *board = comedi_board(dev);
1403 struct ni_private *devpriv = dev->private;
1404 struct comedi_async *async = s->async;
1405 int i;
1406
1407 if (board->reg_type == ni_reg_611x) {
1408 short data[2];
1409 u32 dl;
1410
1411 for (i = 0; i < n / 2; i++) {
1412 dl = ni_readl(ADC_FIFO_Data_611x);
1413 /* This may get the hi/lo data in the wrong order */
1414 data[0] = (dl >> 16) & 0xffff;
1415 data[1] = dl & 0xffff;
1416 cfc_write_array_to_buffer(s, data, sizeof(data));
1417 }
1418 /* Check if there's a single sample stuck in the FIFO */
1419 if (n % 2) {
1420 dl = ni_readl(ADC_FIFO_Data_611x);
1421 data[0] = dl & 0xffff;
1422 cfc_write_to_buffer(s, data[0]);
1423 }
1424 } else if (board->reg_type == ni_reg_6143) {
1425 short data[2];
1426 u32 dl;
1427
1428 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1429 for (i = 0; i < n / 2; i++) {
1430 dl = ni_readl(AIFIFO_Data_6143);
1431
1432 data[0] = (dl >> 16) & 0xffff;
1433 data[1] = dl & 0xffff;
1434 cfc_write_array_to_buffer(s, data, sizeof(data));
1435 }
1436 if (n % 2) {
1437 /* Assume there is a single sample stuck in the FIFO */
1438 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1439 dl = ni_readl(AIFIFO_Data_6143);
1440 data[0] = (dl >> 16) & 0xffff;
1441 cfc_write_to_buffer(s, data[0]);
1442 }
1443 } else {
1444 if (n > sizeof(devpriv->ai_fifo_buffer) /
1445 sizeof(devpriv->ai_fifo_buffer[0])) {
1446 comedi_error(dev, "bug! ai_fifo_buffer too small");
1447 async->events |= COMEDI_CB_ERROR;
1448 return;
1449 }
1450 for (i = 0; i < n; i++) {
1451 devpriv->ai_fifo_buffer[i] =
1452 ni_readw(ADC_FIFO_Data_Register);
1453 }
1454 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1455 n *
1456 sizeof(devpriv->ai_fifo_buffer[0]));
1457 }
1458 }
1459
1460 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1461 {
1462 const struct ni_board_struct *board = comedi_board(dev);
1463 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1464 int n;
1465
1466 n = board->ai_fifo_depth / 2;
1467
1468 ni_ai_fifo_read(dev, s, n);
1469 }
1470 #endif
1471
1472 #ifdef PCIDMA
1473 static int ni_ai_drain_dma(struct comedi_device *dev)
1474 {
1475 struct ni_private *devpriv = dev->private;
1476 int i;
1477 static const int timeout = 10000;
1478 unsigned long flags;
1479 int retval = 0;
1480
1481 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1482 if (devpriv->ai_mite_chan) {
1483 for (i = 0; i < timeout; i++) {
1484 if ((devpriv->stc_readw(dev,
1485 AI_Status_1_Register) &
1486 AI_FIFO_Empty_St)
1487 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1488 0)
1489 break;
1490 udelay(5);
1491 }
1492 if (i == timeout) {
1493 printk("ni_mio_common: wait for dma drain timed out\n");
1494 printk
1495 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1496 mite_bytes_in_transit(devpriv->ai_mite_chan),
1497 devpriv->stc_readw(dev, AI_Status_1_Register));
1498 retval = -1;
1499 }
1500 }
1501 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1502
1503 ni_sync_ai_dma(dev);
1504
1505 return retval;
1506 }
1507 #endif
1508 /*
1509 Empties the AI fifo
1510 */
1511 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1512 {
1513 const struct ni_board_struct *board = comedi_board(dev);
1514 struct ni_private *devpriv = dev->private;
1515 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1516 short data[2];
1517 u32 dl;
1518 short fifo_empty;
1519 int i;
1520
1521 if (board->reg_type == ni_reg_611x) {
1522 while ((devpriv->stc_readw(dev,
1523 AI_Status_1_Register) &
1524 AI_FIFO_Empty_St) == 0) {
1525 dl = ni_readl(ADC_FIFO_Data_611x);
1526
1527 /* This may get the hi/lo data in the wrong order */
1528 data[0] = (dl >> 16);
1529 data[1] = (dl & 0xffff);
1530 cfc_write_array_to_buffer(s, data, sizeof(data));
1531 }
1532 } else if (board->reg_type == ni_reg_6143) {
1533 i = 0;
1534 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1535 dl = ni_readl(AIFIFO_Data_6143);
1536
1537 /* This may get the hi/lo data in the wrong order */
1538 data[0] = (dl >> 16);
1539 data[1] = (dl & 0xffff);
1540 cfc_write_array_to_buffer(s, data, sizeof(data));
1541 i += 2;
1542 }
1543 /* Check if stranded sample is present */
1544 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1545 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1546 dl = ni_readl(AIFIFO_Data_6143);
1547 data[0] = (dl >> 16) & 0xffff;
1548 cfc_write_to_buffer(s, data[0]);
1549 }
1550
1551 } else {
1552 fifo_empty =
1553 devpriv->stc_readw(dev,
1554 AI_Status_1_Register) & AI_FIFO_Empty_St;
1555 while (fifo_empty == 0) {
1556 for (i = 0;
1557 i <
1558 sizeof(devpriv->ai_fifo_buffer) /
1559 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1560 fifo_empty =
1561 devpriv->stc_readw(dev,
1562 AI_Status_1_Register) &
1563 AI_FIFO_Empty_St;
1564 if (fifo_empty)
1565 break;
1566 devpriv->ai_fifo_buffer[i] =
1567 ni_readw(ADC_FIFO_Data_Register);
1568 }
1569 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1570 i *
1571 sizeof(devpriv->
1572 ai_fifo_buffer[0]));
1573 }
1574 }
1575 }
1576
1577 static void get_last_sample_611x(struct comedi_device *dev)
1578 {
1579 const struct ni_board_struct *board = comedi_board(dev);
1580 struct ni_private *devpriv __maybe_unused = dev->private;
1581 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1582 short data;
1583 u32 dl;
1584
1585 if (board->reg_type != ni_reg_611x)
1586 return;
1587
1588 /* Check if there's a single sample stuck in the FIFO */
1589 if (ni_readb(XXX_Status) & 0x80) {
1590 dl = ni_readl(ADC_FIFO_Data_611x);
1591 data = (dl & 0xffff);
1592 cfc_write_to_buffer(s, data);
1593 }
1594 }
1595
1596 static void get_last_sample_6143(struct comedi_device *dev)
1597 {
1598 const struct ni_board_struct *board = comedi_board(dev);
1599 struct ni_private *devpriv __maybe_unused = dev->private;
1600 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1601 short data;
1602 u32 dl;
1603
1604 if (board->reg_type != ni_reg_6143)
1605 return;
1606
1607 /* Check if there's a single sample stuck in the FIFO */
1608 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1609 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1610 dl = ni_readl(AIFIFO_Data_6143);
1611
1612 /* This may get the hi/lo data in the wrong order */
1613 data = (dl >> 16) & 0xffff;
1614 cfc_write_to_buffer(s, data);
1615 }
1616 }
1617
1618 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1619 void *data, unsigned int num_bytes,
1620 unsigned int chan_index)
1621 {
1622 struct ni_private *devpriv = dev->private;
1623 struct comedi_async *async = s->async;
1624 unsigned int i;
1625 unsigned int length = num_bytes / bytes_per_sample(s);
1626 short *array = data;
1627 unsigned int *larray = data;
1628
1629 for (i = 0; i < length; i++) {
1630 #ifdef PCIDMA
1631 if (s->subdev_flags & SDF_LSAMPL)
1632 larray[i] = le32_to_cpu(larray[i]);
1633 else
1634 array[i] = le16_to_cpu(array[i]);
1635 #endif
1636 if (s->subdev_flags & SDF_LSAMPL)
1637 larray[i] += devpriv->ai_offset[chan_index];
1638 else
1639 array[i] += devpriv->ai_offset[chan_index];
1640 chan_index++;
1641 chan_index %= async->cmd.chanlist_len;
1642 }
1643 }
1644
1645 #ifdef PCIDMA
1646
1647 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1648 {
1649 const struct ni_board_struct *board = comedi_board(dev);
1650 struct ni_private *devpriv = dev->private;
1651 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1652 int retval;
1653 unsigned long flags;
1654
1655 retval = ni_request_ai_mite_channel(dev);
1656 if (retval)
1657 return retval;
1658 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1659
1660 /* write alloc the entire buffer */
1661 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1662
1663 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1664 if (devpriv->ai_mite_chan == NULL) {
1665 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1666 return -EIO;
1667 }
1668
1669 switch (board->reg_type) {
1670 case ni_reg_611x:
1671 case ni_reg_6143:
1672 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1673 break;
1674 case ni_reg_628x:
1675 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1676 break;
1677 default:
1678 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1679 break;
1680 }
1681 /*start the MITE */
1682 mite_dma_arm(devpriv->ai_mite_chan);
1683 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1684
1685 return 0;
1686 }
1687
1688 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1689 {
1690 const struct ni_board_struct *board = comedi_board(dev);
1691 struct ni_private *devpriv = dev->private;
1692 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1693 int retval;
1694 unsigned long flags;
1695
1696 retval = ni_request_ao_mite_channel(dev);
1697 if (retval)
1698 return retval;
1699
1700 /* read alloc the entire buffer */
1701 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1702
1703 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1704 if (devpriv->ao_mite_chan) {
1705 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1706 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1707 } else {
1708 /* doing 32 instead of 16 bit wide transfers from memory
1709 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1710 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1711 }
1712 mite_dma_arm(devpriv->ao_mite_chan);
1713 } else
1714 retval = -EIO;
1715 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1716
1717 return retval;
1718 }
1719
1720 #endif /* PCIDMA */
1721
1722 /*
1723 used for both cancel ioctl and board initialization
1724
1725 this is pretty harsh for a cancel, but it works...
1726 */
1727
1728 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1729 {
1730 const struct ni_board_struct *board = comedi_board(dev);
1731 struct ni_private *devpriv = dev->private;
1732
1733 ni_release_ai_mite_channel(dev);
1734 /* ai configuration */
1735 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1736 Joint_Reset_Register);
1737
1738 ni_set_bits(dev, Interrupt_A_Enable_Register,
1739 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1740 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1741 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1742 AI_FIFO_Interrupt_Enable, 0);
1743
1744 ni_clear_ai_fifo(dev);
1745
1746 if (board->reg_type != ni_reg_6143)
1747 ni_writeb(0, Misc_Command);
1748
1749 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1750 devpriv->stc_writew(dev,
1751 AI_Start_Stop | AI_Mode_1_Reserved
1752 /*| AI_Trigger_Once */ ,
1753 AI_Mode_1_Register);
1754 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1755 /* generate FIFO interrupts on non-empty */
1756 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1757 if (board->reg_type == ni_reg_611x) {
1758 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1759 AI_SOC_Polarity |
1760 AI_LOCALMUX_CLK_Pulse_Width,
1761 AI_Personal_Register);
1762 devpriv->stc_writew(dev,
1763 AI_SCAN_IN_PROG_Output_Select(3) |
1764 AI_EXTMUX_CLK_Output_Select(0) |
1765 AI_LOCALMUX_CLK_Output_Select(2) |
1766 AI_SC_TC_Output_Select(3) |
1767 AI_CONVERT_Output_Select
1768 (AI_CONVERT_Output_Enable_High),
1769 AI_Output_Control_Register);
1770 } else if (board->reg_type == ni_reg_6143) {
1771 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1772 AI_SOC_Polarity |
1773 AI_LOCALMUX_CLK_Pulse_Width,
1774 AI_Personal_Register);
1775 devpriv->stc_writew(dev,
1776 AI_SCAN_IN_PROG_Output_Select(3) |
1777 AI_EXTMUX_CLK_Output_Select(0) |
1778 AI_LOCALMUX_CLK_Output_Select(2) |
1779 AI_SC_TC_Output_Select(3) |
1780 AI_CONVERT_Output_Select
1781 (AI_CONVERT_Output_Enable_Low),
1782 AI_Output_Control_Register);
1783 } else {
1784 unsigned ai_output_control_bits;
1785 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1786 AI_SOC_Polarity |
1787 AI_CONVERT_Pulse_Width |
1788 AI_LOCALMUX_CLK_Pulse_Width,
1789 AI_Personal_Register);
1790 ai_output_control_bits =
1791 AI_SCAN_IN_PROG_Output_Select(3) |
1792 AI_EXTMUX_CLK_Output_Select(0) |
1793 AI_LOCALMUX_CLK_Output_Select(2) |
1794 AI_SC_TC_Output_Select(3);
1795 if (board->reg_type == ni_reg_622x)
1796 ai_output_control_bits |=
1797 AI_CONVERT_Output_Select
1798 (AI_CONVERT_Output_Enable_High);
1799 else
1800 ai_output_control_bits |=
1801 AI_CONVERT_Output_Select
1802 (AI_CONVERT_Output_Enable_Low);
1803 devpriv->stc_writew(dev, ai_output_control_bits,
1804 AI_Output_Control_Register);
1805 }
1806 /* the following registers should not be changed, because there
1807 * are no backup registers in devpriv. If you want to change
1808 * any of these, add a backup register and other appropriate code:
1809 * AI_Mode_1_Register
1810 * AI_Mode_3_Register
1811 * AI_Personal_Register
1812 * AI_Output_Control_Register
1813 */
1814 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1815
1816 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1817
1818 return 0;
1819 }
1820
1821 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1822 {
1823 unsigned long flags;
1824 int count;
1825
1826 /* lock to avoid race with interrupt handler */
1827 spin_lock_irqsave(&dev->spinlock, flags);
1828 #ifndef PCIDMA
1829 ni_handle_fifo_dregs(dev);
1830 #else
1831 ni_sync_ai_dma(dev);
1832 #endif
1833 count = s->async->buf_write_count - s->async->buf_read_count;
1834 spin_unlock_irqrestore(&dev->spinlock, flags);
1835
1836 return count;
1837 }
1838
1839 static int ni_ai_insn_read(struct comedi_device *dev,
1840 struct comedi_subdevice *s, struct comedi_insn *insn,
1841 unsigned int *data)
1842 {
1843 const struct ni_board_struct *board = comedi_board(dev);
1844 struct ni_private *devpriv = dev->private;
1845 int i, n;
1846 const unsigned int mask = (1 << board->adbits) - 1;
1847 unsigned signbits;
1848 unsigned short d;
1849 unsigned long dl;
1850
1851 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1852
1853 ni_clear_ai_fifo(dev);
1854
1855 signbits = devpriv->ai_offset[0];
1856 if (board->reg_type == ni_reg_611x) {
1857 for (n = 0; n < num_adc_stages_611x; n++) {
1858 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1859 AI_Command_1_Register);
1860 udelay(1);
1861 }
1862 for (n = 0; n < insn->n; n++) {
1863 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1864 AI_Command_1_Register);
1865 /* The 611x has screwy 32-bit FIFOs. */
1866 d = 0;
1867 for (i = 0; i < NI_TIMEOUT; i++) {
1868 if (ni_readb(XXX_Status) & 0x80) {
1869 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1870 & 0xffff;
1871 break;
1872 }
1873 if (!(devpriv->stc_readw(dev,
1874 AI_Status_1_Register) &
1875 AI_FIFO_Empty_St)) {
1876 d = ni_readl(ADC_FIFO_Data_611x) &
1877 0xffff;
1878 break;
1879 }
1880 }
1881 if (i == NI_TIMEOUT) {
1882 printk
1883 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1884 return -ETIME;
1885 }
1886 d += signbits;
1887 data[n] = d;
1888 }
1889 } else if (board->reg_type == ni_reg_6143) {
1890 for (n = 0; n < insn->n; n++) {
1891 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1892 AI_Command_1_Register);
1893
1894 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1895 dl = 0;
1896 for (i = 0; i < NI_TIMEOUT; i++) {
1897 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1898 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1899 dl = ni_readl(AIFIFO_Data_6143);
1900 break;
1901 }
1902 }
1903 if (i == NI_TIMEOUT) {
1904 printk
1905 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1906 return -ETIME;
1907 }
1908 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1909 }
1910 } else {
1911 for (n = 0; n < insn->n; n++) {
1912 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1913 AI_Command_1_Register);
1914 for (i = 0; i < NI_TIMEOUT; i++) {
1915 if (!(devpriv->stc_readw(dev,
1916 AI_Status_1_Register) &
1917 AI_FIFO_Empty_St))
1918 break;
1919 }
1920 if (i == NI_TIMEOUT) {
1921 printk
1922 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1923 return -ETIME;
1924 }
1925 if (board->reg_type & ni_reg_m_series_mask) {
1926 data[n] =
1927 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1928 } else {
1929 d = ni_readw(ADC_FIFO_Data_Register);
1930 d += signbits; /* subtle: needs to be short addition */
1931 data[n] = d;
1932 }
1933 }
1934 }
1935 return insn->n;
1936 }
1937
1938 static void ni_prime_channelgain_list(struct comedi_device *dev)
1939 {
1940 struct ni_private *devpriv = dev->private;
1941 int i;
1942
1943 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1944 for (i = 0; i < NI_TIMEOUT; ++i) {
1945 if (!(devpriv->stc_readw(dev,
1946 AI_Status_1_Register) &
1947 AI_FIFO_Empty_St)) {
1948 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1949 return;
1950 }
1951 udelay(1);
1952 }
1953 printk("ni_mio_common: timeout loading channel/gain list\n");
1954 }
1955
1956 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1957 unsigned int n_chan,
1958 unsigned int *list)
1959 {
1960 const struct ni_board_struct *board = comedi_board(dev);
1961 struct ni_private *devpriv = dev->private;
1962 unsigned int chan, range, aref;
1963 unsigned int i;
1964 unsigned offset;
1965 unsigned int dither;
1966 unsigned range_code;
1967
1968 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1969
1970 /* offset = 1 << (board->adbits - 1); */
1971 if ((list[0] & CR_ALT_SOURCE)) {
1972 unsigned bypass_bits;
1973 chan = CR_CHAN(list[0]);
1974 range = CR_RANGE(list[0]);
1975 range_code = ni_gainlkup[board->gainlkup][range];
1976 dither = ((list[0] & CR_ALT_FILTER) != 0);
1977 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1978 bypass_bits |= chan;
1979 bypass_bits |=
1980 (devpriv->ai_calib_source) &
1981 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1982 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1983 MSeries_AI_Bypass_Mode_Mux_Mask |
1984 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1985 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1986 if (dither)
1987 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1988 /* don't use 2's complement encoding */
1989 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1990 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1991 } else {
1992 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1993 }
1994 offset = 0;
1995 for (i = 0; i < n_chan; i++) {
1996 unsigned config_bits = 0;
1997 chan = CR_CHAN(list[i]);
1998 aref = CR_AREF(list[i]);
1999 range = CR_RANGE(list[i]);
2000 dither = ((list[i] & CR_ALT_FILTER) != 0);
2001
2002 range_code = ni_gainlkup[board->gainlkup][range];
2003 devpriv->ai_offset[i] = offset;
2004 switch (aref) {
2005 case AREF_DIFF:
2006 config_bits |=
2007 MSeries_AI_Config_Channel_Type_Differential_Bits;
2008 break;
2009 case AREF_COMMON:
2010 config_bits |=
2011 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2012 break;
2013 case AREF_GROUND:
2014 config_bits |=
2015 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2016 break;
2017 case AREF_OTHER:
2018 break;
2019 }
2020 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2021 config_bits |=
2022 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2023 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2024 if (i == n_chan - 1)
2025 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2026 if (dither)
2027 config_bits |= MSeries_AI_Config_Dither_Bit;
2028 /* don't use 2's complement encoding */
2029 config_bits |= MSeries_AI_Config_Polarity_Bit;
2030 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2031 }
2032 ni_prime_channelgain_list(dev);
2033 }
2034
2035 /*
2036 * Notes on the 6110 and 6111:
2037 * These boards a slightly different than the rest of the series, since
2038 * they have multiple A/D converters.
2039 * From the driver side, the configuration memory is a
2040 * little different.
2041 * Configuration Memory Low:
2042 * bits 15-9: same
2043 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2044 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2045 * 1001 gain=0.1 (+/- 50)
2046 * 1010 0.2
2047 * 1011 0.1
2048 * 0001 1
2049 * 0010 2
2050 * 0011 5
2051 * 0100 10
2052 * 0101 20
2053 * 0110 50
2054 * Configuration Memory High:
2055 * bits 12-14: Channel Type
2056 * 001 for differential
2057 * 000 for calibration
2058 * bit 11: coupling (this is not currently handled)
2059 * 1 AC coupling
2060 * 0 DC coupling
2061 * bits 0-2: channel
2062 * valid channels are 0-3
2063 */
2064 static void ni_load_channelgain_list(struct comedi_device *dev,
2065 unsigned int n_chan, unsigned int *list)
2066 {
2067 const struct ni_board_struct *board = comedi_board(dev);
2068 struct ni_private *devpriv = dev->private;
2069 unsigned int chan, range, aref;
2070 unsigned int i;
2071 unsigned int hi, lo;
2072 unsigned offset;
2073 unsigned int dither;
2074
2075 if (board->reg_type & ni_reg_m_series_mask) {
2076 ni_m_series_load_channelgain_list(dev, n_chan, list);
2077 return;
2078 }
2079 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2080 && (board->reg_type != ni_reg_6143)) {
2081 if (devpriv->changain_state
2082 && devpriv->changain_spec == list[0]) {
2083 /* ready to go. */
2084 return;
2085 }
2086 devpriv->changain_state = 1;
2087 devpriv->changain_spec = list[0];
2088 } else {
2089 devpriv->changain_state = 0;
2090 }
2091
2092 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2093
2094 /* Set up Calibration mode if required */
2095 if (board->reg_type == ni_reg_6143) {
2096 if ((list[0] & CR_ALT_SOURCE)
2097 && !devpriv->ai_calib_source_enabled) {
2098 /* Strobe Relay enable bit */
2099 ni_writew(devpriv->ai_calib_source |
2100 Calibration_Channel_6143_RelayOn,
2101 Calibration_Channel_6143);
2102 ni_writew(devpriv->ai_calib_source,
2103 Calibration_Channel_6143);
2104 devpriv->ai_calib_source_enabled = 1;
2105 msleep_interruptible(100); /* Allow relays to change */
2106 } else if (!(list[0] & CR_ALT_SOURCE)
2107 && devpriv->ai_calib_source_enabled) {
2108 /* Strobe Relay disable bit */
2109 ni_writew(devpriv->ai_calib_source |
2110 Calibration_Channel_6143_RelayOff,
2111 Calibration_Channel_6143);
2112 ni_writew(devpriv->ai_calib_source,
2113 Calibration_Channel_6143);
2114 devpriv->ai_calib_source_enabled = 0;
2115 msleep_interruptible(100); /* Allow relays to change */
2116 }
2117 }
2118
2119 offset = 1 << (board->adbits - 1);
2120 for (i = 0; i < n_chan; i++) {
2121 if ((board->reg_type != ni_reg_6143)
2122 && (list[i] & CR_ALT_SOURCE)) {
2123 chan = devpriv->ai_calib_source;
2124 } else {
2125 chan = CR_CHAN(list[i]);
2126 }
2127 aref = CR_AREF(list[i]);
2128 range = CR_RANGE(list[i]);
2129 dither = ((list[i] & CR_ALT_FILTER) != 0);
2130
2131 /* fix the external/internal range differences */
2132 range = ni_gainlkup[board->gainlkup][range];
2133 if (board->reg_type == ni_reg_611x)
2134 devpriv->ai_offset[i] = offset;
2135 else
2136 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2137
2138 hi = 0;
2139 if ((list[i] & CR_ALT_SOURCE)) {
2140 if (board->reg_type == ni_reg_611x)
2141 ni_writew(CR_CHAN(list[i]) & 0x0003,
2142 Calibration_Channel_Select_611x);
2143 } else {
2144 if (board->reg_type == ni_reg_611x)
2145 aref = AREF_DIFF;
2146 else if (board->reg_type == ni_reg_6143)
2147 aref = AREF_OTHER;
2148 switch (aref) {
2149 case AREF_DIFF:
2150 hi |= AI_DIFFERENTIAL;
2151 break;
2152 case AREF_COMMON:
2153 hi |= AI_COMMON;
2154 break;
2155 case AREF_GROUND:
2156 hi |= AI_GROUND;
2157 break;
2158 case AREF_OTHER:
2159 break;
2160 }
2161 }
2162 hi |= AI_CONFIG_CHANNEL(chan);
2163
2164 ni_writew(hi, Configuration_Memory_High);
2165
2166 if (board->reg_type != ni_reg_6143) {
2167 lo = range;
2168 if (i == n_chan - 1)
2169 lo |= AI_LAST_CHANNEL;
2170 if (dither)
2171 lo |= AI_DITHER;
2172
2173 ni_writew(lo, Configuration_Memory_Low);
2174 }
2175 }
2176
2177 /* prime the channel/gain list */
2178 if ((board->reg_type != ni_reg_611x)
2179 && (board->reg_type != ni_reg_6143)) {
2180 ni_prime_channelgain_list(dev);
2181 }
2182 }
2183
2184 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2185 int round_mode)
2186 {
2187 struct ni_private *devpriv = dev->private;
2188 int divider;
2189
2190 switch (round_mode) {
2191 case TRIG_ROUND_NEAREST:
2192 default:
2193 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2194 break;
2195 case TRIG_ROUND_DOWN:
2196 divider = (nanosec) / devpriv->clock_ns;
2197 break;
2198 case TRIG_ROUND_UP:
2199 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2200 break;
2201 }
2202 return divider - 1;
2203 }
2204
2205 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2206 {
2207 struct ni_private *devpriv = dev->private;
2208
2209 return devpriv->clock_ns * (timer + 1);
2210 }
2211
2212 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2213 unsigned num_channels)
2214 {
2215 const struct ni_board_struct *board = comedi_board(dev);
2216
2217 switch (board->reg_type) {
2218 case ni_reg_611x:
2219 case ni_reg_6143:
2220 /* simultaneously-sampled inputs */
2221 return board->ai_speed;
2222 break;
2223 default:
2224 /* multiplexed inputs */
2225 break;
2226 }
2227 return board->ai_speed * num_channels;
2228 }
2229
2230 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2231 struct comedi_cmd *cmd)
2232 {
2233 const struct ni_board_struct *board = comedi_board(dev);
2234 struct ni_private *devpriv = dev->private;
2235 int err = 0;
2236 int tmp;
2237 unsigned int sources;
2238
2239 /* Step 1 : check if triggers are trivially valid */
2240
2241 if ((cmd->flags & CMDF_WRITE))
2242 cmd->flags &= ~CMDF_WRITE;
2243
2244 err |= cfc_check_trigger_src(&cmd->start_src,
2245 TRIG_NOW | TRIG_INT | TRIG_EXT);
2246 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2247 TRIG_TIMER | TRIG_EXT);
2248
2249 sources = TRIG_TIMER | TRIG_EXT;
2250 if (board->reg_type == ni_reg_611x ||
2251 board->reg_type == ni_reg_6143)
2252 sources |= TRIG_NOW;
2253 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2254
2255 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2256 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2257
2258 if (err)
2259 return 1;
2260
2261 /* Step 2a : make sure trigger sources are unique */
2262
2263 err |= cfc_check_trigger_is_unique(cmd->start_src);
2264 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2265 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2266 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2267
2268 /* Step 2b : and mutually compatible */
2269
2270 if (err)
2271 return 2;
2272
2273 /* Step 3: check if arguments are trivially valid */
2274
2275 if (cmd->start_src == TRIG_EXT) {
2276 /* external trigger */
2277 unsigned int tmp = CR_CHAN(cmd->start_arg);
2278
2279 if (tmp > 16)
2280 tmp = 16;
2281 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2282 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2283 } else {
2284 /* true for both TRIG_NOW and TRIG_INT */
2285 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2286 }
2287
2288 if (cmd->scan_begin_src == TRIG_TIMER) {
2289 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2290 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2291 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2292 devpriv->clock_ns * 0xffffff);
2293 } else if (cmd->scan_begin_src == TRIG_EXT) {
2294 /* external trigger */
2295 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2296
2297 if (tmp > 16)
2298 tmp = 16;
2299 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2300 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2301 } else { /* TRIG_OTHER */
2302 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2303 }
2304
2305 if (cmd->convert_src == TRIG_TIMER) {
2306 if ((board->reg_type == ni_reg_611x)
2307 || (board->reg_type == ni_reg_6143)) {
2308 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2309 } else {
2310 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2311 board->ai_speed);
2312 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2313 devpriv->clock_ns * 0xffff);
2314 }
2315 } else if (cmd->convert_src == TRIG_EXT) {
2316 /* external trigger */
2317 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2318
2319 if (tmp > 16)
2320 tmp = 16;
2321 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2322 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2323 } else if (cmd->convert_src == TRIG_NOW) {
2324 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2325 }
2326
2327 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2328
2329 if (cmd->stop_src == TRIG_COUNT) {
2330 unsigned int max_count = 0x01000000;
2331
2332 if (board->reg_type == ni_reg_611x)
2333 max_count -= num_adc_stages_611x;
2334 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2335 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2336 } else {
2337 /* TRIG_NONE */
2338 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2339 }
2340
2341 if (err)
2342 return 3;
2343
2344 /* step 4: fix up any arguments */
2345
2346 if (cmd->scan_begin_src == TRIG_TIMER) {
2347 tmp = cmd->scan_begin_arg;
2348 cmd->scan_begin_arg =
2349 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2350 cmd->scan_begin_arg,
2351 cmd->
2352 flags &
2353 TRIG_ROUND_MASK));
2354 if (tmp != cmd->scan_begin_arg)
2355 err++;
2356 }
2357 if (cmd->convert_src == TRIG_TIMER) {
2358 if ((board->reg_type != ni_reg_611x)
2359 && (board->reg_type != ni_reg_6143)) {
2360 tmp = cmd->convert_arg;
2361 cmd->convert_arg =
2362 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2363 cmd->convert_arg,
2364 cmd->
2365 flags &
2366 TRIG_ROUND_MASK));
2367 if (tmp != cmd->convert_arg)
2368 err++;
2369 if (cmd->scan_begin_src == TRIG_TIMER &&
2370 cmd->scan_begin_arg <
2371 cmd->convert_arg * cmd->scan_end_arg) {
2372 cmd->scan_begin_arg =
2373 cmd->convert_arg * cmd->scan_end_arg;
2374 err++;
2375 }
2376 }
2377 }
2378
2379 if (err)
2380 return 4;
2381
2382 return 0;
2383 }
2384
2385 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2386 {
2387 const struct ni_board_struct *board = comedi_board(dev);
2388 struct ni_private *devpriv = dev->private;
2389 const struct comedi_cmd *cmd = &s->async->cmd;
2390 int timer;
2391 int mode1 = 0; /* mode1 is needed for both stop and convert */
2392 int mode2 = 0;
2393 int start_stop_select = 0;
2394 unsigned int stop_count;
2395 int interrupt_a_enable = 0;
2396
2397 MDPRINTK("ni_ai_cmd\n");
2398 if (dev->irq == 0) {
2399 comedi_error(dev, "cannot run command without an irq");
2400 return -EIO;
2401 }
2402 ni_clear_ai_fifo(dev);
2403
2404 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2405
2406 /* start configuration */
2407 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2408
2409 /* disable analog triggering for now, since it
2410 * interferes with the use of pfi0 */
2411 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2412 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2413 Analog_Trigger_Etc_Register);
2414
2415 switch (cmd->start_src) {
2416 case TRIG_INT:
2417 case TRIG_NOW:
2418 devpriv->stc_writew(dev, AI_START2_Select(0) |
2419 AI_START1_Sync | AI_START1_Edge |
2420 AI_START1_Select(0),
2421 AI_Trigger_Select_Register);
2422 break;
2423 case TRIG_EXT:
2424 {
2425 int chan = CR_CHAN(cmd->start_arg);
2426 unsigned int bits = AI_START2_Select(0) |
2427 AI_START1_Sync | AI_START1_Select(chan + 1);
2428
2429 if (cmd->start_arg & CR_INVERT)
2430 bits |= AI_START1_Polarity;
2431 if (cmd->start_arg & CR_EDGE)
2432 bits |= AI_START1_Edge;
2433 devpriv->stc_writew(dev, bits,
2434 AI_Trigger_Select_Register);
2435 break;
2436 }
2437 }
2438
2439 mode2 &= ~AI_Pre_Trigger;
2440 mode2 &= ~AI_SC_Initial_Load_Source;
2441 mode2 &= ~AI_SC_Reload_Mode;
2442 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2443
2444 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2445 || (board->reg_type == ni_reg_6143)) {
2446 start_stop_select |= AI_STOP_Polarity;
2447 start_stop_select |= AI_STOP_Select(31); /* logic low */
2448 start_stop_select |= AI_STOP_Sync;
2449 } else {
2450 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2451 }
2452 devpriv->stc_writew(dev, start_stop_select,
2453 AI_START_STOP_Select_Register);
2454
2455 devpriv->ai_cmd2 = 0;
2456 switch (cmd->stop_src) {
2457 case TRIG_COUNT:
2458 stop_count = cmd->stop_arg - 1;
2459
2460 if (board->reg_type == ni_reg_611x) {
2461 /* have to take 3 stage adc pipeline into account */
2462 stop_count += num_adc_stages_611x;
2463 }
2464 /* stage number of scans */
2465 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2466
2467 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2468 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2469 /* load SC (Scan Count) */
2470 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2471
2472 devpriv->ai_continuous = 0;
2473 if (stop_count == 0) {
2474 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2475 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2476 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2477 if (cmd->chanlist_len > 1)
2478 start_stop_select |=
2479 AI_STOP_Polarity | AI_STOP_Edge;
2480 }
2481 break;
2482 case TRIG_NONE:
2483 /* stage number of scans */
2484 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2485
2486 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2487 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2488
2489 /* load SC (Scan Count) */
2490 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2491
2492 devpriv->ai_continuous = 1;
2493
2494 break;
2495 }
2496
2497 switch (cmd->scan_begin_src) {
2498 case TRIG_TIMER:
2499 /*
2500 stop bits for non 611x boards
2501 AI_SI_Special_Trigger_Delay=0
2502 AI_Pre_Trigger=0
2503 AI_START_STOP_Select_Register:
2504 AI_START_Polarity=0 (?) rising edge
2505 AI_START_Edge=1 edge triggered
2506 AI_START_Sync=1 (?)
2507 AI_START_Select=0 SI_TC
2508 AI_STOP_Polarity=0 rising edge
2509 AI_STOP_Edge=0 level
2510 AI_STOP_Sync=1
2511 AI_STOP_Select=19 external pin (configuration mem)
2512 */
2513 start_stop_select |= AI_START_Edge | AI_START_Sync;
2514 devpriv->stc_writew(dev, start_stop_select,
2515 AI_START_STOP_Select_Register);
2516
2517 mode2 |= AI_SI_Reload_Mode(0);
2518 /* AI_SI_Initial_Load_Source=A */
2519 mode2 &= ~AI_SI_Initial_Load_Source;
2520 /* mode2 |= AI_SC_Reload_Mode; */
2521 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2522
2523 /* load SI */
2524 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2525 TRIG_ROUND_NEAREST);
2526 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2527 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2528 break;
2529 case TRIG_EXT:
2530 if (cmd->scan_begin_arg & CR_EDGE)
2531 start_stop_select |= AI_START_Edge;
2532 /* AI_START_Polarity==1 is falling edge */
2533 if (cmd->scan_begin_arg & CR_INVERT)
2534 start_stop_select |= AI_START_Polarity;
2535 if (cmd->scan_begin_src != cmd->convert_src ||
2536 (cmd->scan_begin_arg & ~CR_EDGE) !=
2537 (cmd->convert_arg & ~CR_EDGE))
2538 start_stop_select |= AI_START_Sync;
2539 start_stop_select |=
2540 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2541 devpriv->stc_writew(dev, start_stop_select,
2542 AI_START_STOP_Select_Register);
2543 break;
2544 }
2545
2546 switch (cmd->convert_src) {
2547 case TRIG_TIMER:
2548 case TRIG_NOW:
2549 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2550 timer = 1;
2551 else
2552 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2553 TRIG_ROUND_NEAREST);
2554 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2555 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2556
2557 /* AI_SI2_Reload_Mode = alternate */
2558 /* AI_SI2_Initial_Load_Source = A */
2559 mode2 &= ~AI_SI2_Initial_Load_Source;
2560 mode2 |= AI_SI2_Reload_Mode;
2561 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2562
2563 /* AI_SI2_Load */
2564 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2565
2566 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2567 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2568
2569 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2570 break;
2571 case TRIG_EXT:
2572 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2573 if ((cmd->convert_arg & CR_INVERT) == 0)
2574 mode1 |= AI_CONVERT_Source_Polarity;
2575 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2576
2577 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2578 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2579
2580 break;
2581 }
2582
2583 if (dev->irq) {
2584
2585 /* interrupt on FIFO, errors, SC_TC */
2586 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2587 AI_SC_TC_Interrupt_Enable;
2588
2589 #ifndef PCIDMA
2590 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2591 #endif
2592
2593 if (cmd->flags & TRIG_WAKE_EOS
2594 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2595 /* wake on end-of-scan */
2596 devpriv->aimode = AIMODE_SCAN;
2597 } else {
2598 devpriv->aimode = AIMODE_HALF_FULL;
2599 }
2600
2601 switch (devpriv->aimode) {
2602 case AIMODE_HALF_FULL:
2603 /*generate FIFO interrupts and DMA requests on half-full */
2604 #ifdef PCIDMA
2605 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2606 AI_Mode_3_Register);
2607 #else
2608 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2609 AI_Mode_3_Register);
2610 #endif
2611 break;
2612 case AIMODE_SAMPLE:
2613 /*generate FIFO interrupts on non-empty */
2614 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2615 AI_Mode_3_Register);
2616 break;
2617 case AIMODE_SCAN:
2618 #ifdef PCIDMA
2619 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2620 AI_Mode_3_Register);
2621 #else
2622 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2623 AI_Mode_3_Register);
2624 #endif
2625 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2626 break;
2627 default:
2628 break;
2629 }
2630
2631 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2632
2633 ni_set_bits(dev, Interrupt_A_Enable_Register,
2634 interrupt_a_enable, 1);
2635
2636 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2637 devpriv->int_a_enable_reg);
2638 } else {
2639 /* interrupt on nothing */
2640 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2641
2642 /* XXX start polling if necessary */
2643 MDPRINTK("interrupting on nothing\n");
2644 }
2645
2646 /* end configuration */
2647 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2648
2649 switch (cmd->scan_begin_src) {
2650 case TRIG_TIMER:
2651 devpriv->stc_writew(dev,
2652 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2653 AI_SC_Arm, AI_Command_1_Register);
2654 break;
2655 case TRIG_EXT:
2656 /* XXX AI_SI_Arm? */
2657 devpriv->stc_writew(dev,
2658 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2659 AI_SC_Arm, AI_Command_1_Register);
2660 break;
2661 }
2662
2663 #ifdef PCIDMA
2664 {
2665 int retval = ni_ai_setup_MITE_dma(dev);
2666 if (retval)
2667 return retval;
2668 }
2669 /* mite_dump_regs(devpriv->mite); */
2670 #endif
2671
2672 switch (cmd->start_src) {
2673 case TRIG_NOW:
2674 /* AI_START1_Pulse */
2675 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2676 AI_Command_2_Register);
2677 s->async->inttrig = NULL;
2678 break;
2679 case TRIG_EXT:
2680 s->async->inttrig = NULL;
2681 break;
2682 case TRIG_INT:
2683 s->async->inttrig = &ni_ai_inttrig;
2684 break;
2685 }
2686
2687 MDPRINTK("exit ni_ai_cmd\n");
2688
2689 return 0;
2690 }
2691
2692 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2693 unsigned int trignum)
2694 {
2695 struct ni_private *devpriv = dev->private;
2696
2697 if (trignum != 0)
2698 return -EINVAL;
2699
2700 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2701 AI_Command_2_Register);
2702 s->async->inttrig = NULL;
2703
2704 return 1;
2705 }
2706
2707 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2708 struct comedi_subdevice *s,
2709 struct comedi_insn *insn,
2710 unsigned int *data);
2711
2712 static int ni_ai_insn_config(struct comedi_device *dev,
2713 struct comedi_subdevice *s,
2714 struct comedi_insn *insn, unsigned int *data)
2715 {
2716 const struct ni_board_struct *board = comedi_board(dev);
2717 struct ni_private *devpriv = dev->private;
2718
2719 if (insn->n < 1)
2720 return -EINVAL;
2721
2722 switch (data[0]) {
2723 case INSN_CONFIG_ANALOG_TRIG:
2724 return ni_ai_config_analog_trig(dev, s, insn, data);
2725 case INSN_CONFIG_ALT_SOURCE:
2726 if (board->reg_type & ni_reg_m_series_mask) {
2727 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2728 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2729 MSeries_AI_Bypass_Mode_Mux_Mask |
2730 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2731 return -EINVAL;
2732 }
2733 devpriv->ai_calib_source = data[1];
2734 } else if (board->reg_type == ni_reg_6143) {
2735 unsigned int calib_source;
2736
2737 calib_source = data[1] & 0xf;
2738
2739 if (calib_source > 0xF)
2740 return -EINVAL;
2741
2742 devpriv->ai_calib_source = calib_source;
2743 ni_writew(calib_source, Calibration_Channel_6143);
2744 } else {
2745 unsigned int calib_source;
2746 unsigned int calib_source_adjust;
2747
2748 calib_source = data[1] & 0xf;
2749 calib_source_adjust = (data[1] >> 4) & 0xff;
2750
2751 if (calib_source >= 8)
2752 return -EINVAL;
2753 devpriv->ai_calib_source = calib_source;
2754 if (board->reg_type == ni_reg_611x) {
2755 ni_writeb(calib_source_adjust,
2756 Cal_Gain_Select_611x);
2757 }
2758 }
2759 return 2;
2760 default:
2761 break;
2762 }
2763
2764 return -EINVAL;
2765 }
2766
2767 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2768 struct comedi_subdevice *s,
2769 struct comedi_insn *insn,
2770 unsigned int *data)
2771 {
2772 const struct ni_board_struct *board = comedi_board(dev);
2773 struct ni_private *devpriv = dev->private;
2774 unsigned int a, b, modebits;
2775 int err = 0;
2776
2777 /* data[1] is flags
2778 * data[2] is analog line
2779 * data[3] is set level
2780 * data[4] is reset level */
2781 if (!board->has_analog_trig)
2782 return -EINVAL;
2783 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2784 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2785 err++;
2786 }
2787 if (data[2] >= board->n_adchan) {
2788 data[2] = board->n_adchan - 1;
2789 err++;
2790 }
2791 if (data[3] > 255) { /* a */
2792 data[3] = 255;
2793 err++;
2794 }
2795 if (data[4] > 255) { /* b */
2796 data[4] = 255;
2797 err++;
2798 }
2799 /*
2800 * 00 ignore
2801 * 01 set
2802 * 10 reset
2803 *
2804 * modes:
2805 * 1 level: +b- +a-
2806 * high mode 00 00 01 10
2807 * low mode 00 00 10 01
2808 * 2 level: (a<b)
2809 * hysteresis low mode 10 00 00 01
2810 * hysteresis high mode 01 00 00 10
2811 * middle mode 10 01 01 10
2812 */
2813
2814 a = data[3];
2815 b = data[4];
2816 modebits = data[1] & 0xff;
2817 if (modebits & 0xf0) {
2818 /* two level mode */
2819 if (b < a) {
2820 /* swap order */
2821 a = data[4];
2822 b = data[3];
2823 modebits =
2824 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2825 }
2826 devpriv->atrig_low = a;
2827 devpriv->atrig_high = b;
2828 switch (modebits) {
2829 case 0x81: /* low hysteresis mode */
2830 devpriv->atrig_mode = 6;
2831 break;
2832 case 0x42: /* high hysteresis mode */
2833 devpriv->atrig_mode = 3;
2834 break;
2835 case 0x96: /* middle window mode */
2836 devpriv->atrig_mode = 2;
2837 break;
2838 default:
2839 data[1] &= ~0xff;
2840 err++;
2841 }
2842 } else {
2843 /* one level mode */
2844 if (b != 0) {
2845 data[4] = 0;
2846 err++;
2847 }
2848 switch (modebits) {
2849 case 0x06: /* high window mode */
2850 devpriv->atrig_high = a;
2851 devpriv->atrig_mode = 0;
2852 break;
2853 case 0x09: /* low window mode */
2854 devpriv->atrig_low = a;
2855 devpriv->atrig_mode = 1;
2856 break;
2857 default:
2858 data[1] &= ~0xff;
2859 err++;
2860 }
2861 }
2862 if (err)
2863 return -EAGAIN;
2864 return 5;
2865 }
2866
2867 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2868 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2869 void *data, unsigned int num_bytes,
2870 unsigned int chan_index)
2871 {
2872 const struct ni_board_struct *board = comedi_board(dev);
2873 struct comedi_async *async = s->async;
2874 unsigned int range;
2875 unsigned int i;
2876 unsigned int offset;
2877 unsigned int length = num_bytes / sizeof(short);
2878 short *array = data;
2879
2880 offset = 1 << (board->aobits - 1);
2881 for (i = 0; i < length; i++) {
2882 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2883 if (board->ao_unipolar == 0 || (range & 1) == 0)
2884 array[i] -= offset;
2885 #ifdef PCIDMA
2886 array[i] = cpu_to_le16(array[i]);
2887 #endif
2888 chan_index++;
2889 chan_index %= async->cmd.chanlist_len;
2890 }
2891 }
2892
2893 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2894 struct comedi_subdevice *s,
2895 unsigned int chanspec[],
2896 unsigned int n_chans, int timed)
2897 {
2898 const struct ni_board_struct *board = comedi_board(dev);
2899 struct ni_private *devpriv = dev->private;
2900 unsigned int range;
2901 unsigned int chan;
2902 unsigned int conf;
2903 int i;
2904 int invert = 0;
2905
2906 if (timed) {
2907 for (i = 0; i < board->n_aochan; ++i) {
2908 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2909 ni_writeb(devpriv->ao_conf[i],
2910 M_Offset_AO_Config_Bank(i));
2911 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2912 }
2913 }
2914 for (i = 0; i < n_chans; i++) {
2915 const struct comedi_krange *krange;
2916 chan = CR_CHAN(chanspec[i]);
2917 range = CR_RANGE(chanspec[i]);
2918 krange = s->range_table->range + range;
2919 invert = 0;
2920 conf = 0;
2921 switch (krange->max - krange->min) {
2922 case 20000000:
2923 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2924 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2925 break;
2926 case 10000000:
2927 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2928 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2929 break;
2930 case 4000000:
2931 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2932 ni_writeb(MSeries_Attenuate_x5_Bit,
2933 M_Offset_AO_Reference_Attenuation(chan));
2934 break;
2935 case 2000000:
2936 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2937 ni_writeb(MSeries_Attenuate_x5_Bit,
2938 M_Offset_AO_Reference_Attenuation(chan));
2939 break;
2940 default:
2941 printk("%s: bug! unhandled ao reference voltage\n",
2942 __func__);
2943 break;
2944 }
2945 switch (krange->max + krange->min) {
2946 case 0:
2947 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2948 break;
2949 case 10000000:
2950 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2951 break;
2952 default:
2953 printk("%s: bug! unhandled ao offset voltage\n",
2954 __func__);
2955 break;
2956 }
2957 if (timed)
2958 conf |= MSeries_AO_Update_Timed_Bit;
2959 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2960 devpriv->ao_conf[chan] = conf;
2961 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2962 }
2963 return invert;
2964 }
2965
2966 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2967 struct comedi_subdevice *s,
2968 unsigned int chanspec[],
2969 unsigned int n_chans)
2970 {
2971 const struct ni_board_struct *board = comedi_board(dev);
2972 struct ni_private *devpriv = dev->private;
2973 unsigned int range;
2974 unsigned int chan;
2975 unsigned int conf;
2976 int i;
2977 int invert = 0;
2978
2979 for (i = 0; i < n_chans; i++) {
2980 chan = CR_CHAN(chanspec[i]);
2981 range = CR_RANGE(chanspec[i]);
2982 conf = AO_Channel(chan);
2983
2984 if (board->ao_unipolar) {
2985 if ((range & 1) == 0) {
2986 conf |= AO_Bipolar;
2987 invert = (1 << (board->aobits - 1));
2988 } else {
2989 invert = 0;
2990 }
2991 if (range & 2)
2992 conf |= AO_Ext_Ref;
2993 } else {
2994 conf |= AO_Bipolar;
2995 invert = (1 << (board->aobits - 1));
2996 }
2997
2998 /* not all boards can deglitch, but this shouldn't hurt */
2999 if (chanspec[i] & CR_DEGLITCH)
3000 conf |= AO_Deglitch;
3001
3002 /* analog reference */
3003 /* AREF_OTHER connects AO ground to AI ground, i think */
3004 conf |= (CR_AREF(chanspec[i]) ==
3005 AREF_OTHER) ? AO_Ground_Ref : 0;
3006
3007 ni_writew(conf, AO_Configuration);
3008 devpriv->ao_conf[chan] = conf;
3009 }
3010 return invert;
3011 }
3012
3013 static int ni_ao_config_chanlist(struct comedi_device *dev,
3014 struct comedi_subdevice *s,
3015 unsigned int chanspec[], unsigned int n_chans,
3016 int timed)
3017 {
3018 const struct ni_board_struct *board = comedi_board(dev);
3019
3020 if (board->reg_type & ni_reg_m_series_mask)
3021 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3022 timed);
3023 else
3024 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3025 }
3026
3027 static int ni_ao_insn_read(struct comedi_device *dev,
3028 struct comedi_subdevice *s, struct comedi_insn *insn,
3029 unsigned int *data)
3030 {
3031 struct ni_private *devpriv = dev->private;
3032
3033 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3034
3035 return 1;
3036 }
3037
3038 static int ni_ao_insn_write(struct comedi_device *dev,
3039 struct comedi_subdevice *s,
3040 struct comedi_insn *insn, unsigned int *data)
3041 {
3042 const struct ni_board_struct *board = comedi_board(dev);
3043 struct ni_private *devpriv = dev->private;
3044 unsigned int chan = CR_CHAN(insn->chanspec);
3045 unsigned int invert;
3046
3047 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3048
3049 devpriv->ao[chan] = data[0];
3050
3051 if (board->reg_type & ni_reg_m_series_mask) {
3052 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3053 } else
3054 ni_writew(data[0] ^ invert,
3055 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3056
3057 return 1;
3058 }
3059
3060 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3061 struct comedi_subdevice *s,
3062 struct comedi_insn *insn, unsigned int *data)
3063 {
3064 const struct ni_board_struct *board = comedi_board(dev);
3065 struct ni_private *devpriv = dev->private;
3066 unsigned int chan = CR_CHAN(insn->chanspec);
3067 unsigned int invert;
3068
3069 ao_win_out(1 << chan, AO_Immediate_671x);
3070 invert = 1 << (board->aobits - 1);
3071
3072 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3073
3074 devpriv->ao[chan] = data[0];
3075 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3076
3077 return 1;
3078 }
3079
3080 static int ni_ao_insn_config(struct comedi_device *dev,
3081 struct comedi_subdevice *s,
3082 struct comedi_insn *insn, unsigned int *data)
3083 {
3084 const struct ni_board_struct *board = comedi_board(dev);
3085 struct ni_private *devpriv = dev->private;
3086
3087 switch (data[0]) {
3088 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3089 switch (data[1]) {
3090 case COMEDI_OUTPUT:
3091 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3092 if (devpriv->mite)
3093 data[2] += devpriv->mite->fifo_size;
3094 break;
3095 case COMEDI_INPUT:
3096 data[2] = 0;
3097 break;
3098 default:
3099 return -EINVAL;
3100 break;
3101 }
3102 return 0;
3103 default:
3104 break;
3105 }
3106
3107 return -EINVAL;
3108 }
3109
3110 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3111 unsigned int trignum)
3112 {
3113 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3114 struct ni_private *devpriv = dev->private;
3115 int ret;
3116 int interrupt_b_bits;
3117 int i;
3118 static const int timeout = 1000;
3119
3120 if (trignum != 0)
3121 return -EINVAL;
3122
3123 /* Null trig at beginning prevent ao start trigger from executing more than
3124 once per command (and doing things like trying to allocate the ao dma channel
3125 multiple times) */
3126 s->async->inttrig = NULL;
3127
3128 ni_set_bits(dev, Interrupt_B_Enable_Register,
3129 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3130 interrupt_b_bits = AO_Error_Interrupt_Enable;
3131 #ifdef PCIDMA
3132 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3133 if (board->reg_type & ni_reg_6xxx_mask)
3134 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3135 ret = ni_ao_setup_MITE_dma(dev);
3136 if (ret)
3137 return ret;
3138 ret = ni_ao_wait_for_dma_load(dev);
3139 if (ret < 0)
3140 return ret;
3141 #else
3142 ret = ni_ao_prep_fifo(dev, s);
3143 if (ret == 0)
3144 return -EPIPE;
3145
3146 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3147 #endif
3148
3149 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3150 AO_Mode_3_Register);
3151 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3152 /* wait for DACs to be loaded */
3153 for (i = 0; i < timeout; i++) {
3154 udelay(1);
3155 if ((devpriv->stc_readw(dev,
3156 Joint_Status_2_Register) &
3157 AO_TMRDACWRs_In_Progress_St) == 0)
3158 break;
3159 }
3160 if (i == timeout) {
3161 comedi_error(dev,
3162 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3163 return -EIO;
3164 }
3165 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3166 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3167 Interrupt_B_Ack_Register);
3168
3169 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3170
3171 devpriv->stc_writew(dev,
3172 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3173 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3174 AO_Command_1_Register);
3175
3176 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3177 AO_Command_2_Register);
3178
3179 return 0;
3180 }
3181
3182 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3183 {
3184 const struct ni_board_struct *board = comedi_board(dev);
3185 struct ni_private *devpriv = dev->private;
3186 const struct comedi_cmd *cmd = &s->async->cmd;
3187 int bits;
3188 int i;
3189 unsigned trigvar;
3190
3191 if (dev->irq == 0) {
3192 comedi_error(dev, "cannot run command without an irq");
3193 return -EIO;
3194 }
3195
3196 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3197
3198 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3199
3200 if (board->reg_type & ni_reg_6xxx_mask) {
3201 ao_win_out(CLEAR_WG, AO_Misc_611x);
3202
3203 bits = 0;
3204 for (i = 0; i < cmd->chanlist_len; i++) {
3205 int chan;
3206
3207 chan = CR_CHAN(cmd->chanlist[i]);
3208 bits |= 1 << chan;
3209 ao_win_out(chan, AO_Waveform_Generation_611x);
3210 }
3211 ao_win_out(bits, AO_Timed_611x);
3212 }
3213
3214 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3215
3216 if (cmd->stop_src == TRIG_NONE) {
3217 devpriv->ao_mode1 |= AO_Continuous;
3218 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3219 } else {
3220 devpriv->ao_mode1 &= ~AO_Continuous;
3221 devpriv->ao_mode1 |= AO_Trigger_Once;
3222 }
3223 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3224 switch (cmd->start_src) {
3225 case TRIG_INT:
3226 case TRIG_NOW:
3227 devpriv->ao_trigger_select &=
3228 ~(AO_START1_Polarity | AO_START1_Select(-1));
3229 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3230 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3231 AO_Trigger_Select_Register);
3232 break;
3233 case TRIG_EXT:
3234 devpriv->ao_trigger_select =
3235 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3236 if (cmd->start_arg & CR_INVERT)
3237 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3238 if (cmd->start_arg & CR_EDGE)
3239 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3240 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3241 AO_Trigger_Select_Register);
3242 break;
3243 default:
3244 BUG();
3245 break;
3246 }
3247 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3248 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3249
3250 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3251 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3252 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3253 if (cmd->stop_src == TRIG_NONE) {
3254 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3255 } else {
3256 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3257 }
3258 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3259 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3260 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3261 switch (cmd->stop_src) {
3262 case TRIG_COUNT:
3263 if (board->reg_type & ni_reg_m_series_mask) {
3264 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3265 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3266 AO_UC_Load_A_Register);
3267 devpriv->stc_writew(dev, AO_UC_Load,
3268 AO_Command_1_Register);
3269 } else {
3270 devpriv->stc_writel(dev, cmd->stop_arg,
3271 AO_UC_Load_A_Register);
3272 devpriv->stc_writew(dev, AO_UC_Load,
3273 AO_Command_1_Register);
3274 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3275 AO_UC_Load_A_Register);
3276 }
3277 break;
3278 case TRIG_NONE:
3279 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3280 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3281 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3282 break;
3283 default:
3284 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3285 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3286 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3287 }
3288
3289 devpriv->ao_mode1 &=
3290 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3291 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3292 switch (cmd->scan_begin_src) {
3293 case TRIG_TIMER:
3294 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3295 trigvar =
3296 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3297 TRIG_ROUND_NEAREST);
3298 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3299 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3300 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3301 break;
3302 case TRIG_EXT:
3303 devpriv->ao_mode1 |=
3304 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3305 if (cmd->scan_begin_arg & CR_INVERT)
3306 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3307 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3308 break;
3309 default:
3310 BUG();
3311 break;
3312 }
3313 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3314 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3315 devpriv->ao_mode2 &=
3316 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3317 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3318
3319 if (cmd->scan_end_arg > 1) {
3320 devpriv->ao_mode1 |= AO_Multiple_Channels;
3321 devpriv->stc_writew(dev,
3322 AO_Number_Of_Channels(cmd->scan_end_arg -
3323 1) |
3324 AO_UPDATE_Output_Select
3325 (AO_Update_Output_High_Z),
3326 AO_Output_Control_Register);
3327 } else {
3328 unsigned bits;
3329 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3330 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3331 if (board->reg_type &
3332 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3333 bits |= AO_Number_Of_Channels(0);
3334 } else {
3335 bits |=
3336 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3337 }
3338 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3339 }
3340 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3341
3342 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3343 AO_Command_1_Register);
3344
3345 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3346 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3347
3348 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3349 #ifdef PCIDMA
3350 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3351 #else
3352 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3353 #endif
3354 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3355 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3356
3357 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3358 AO_TMRDACWR_Pulse_Width;
3359 if (board->ao_fifo_depth)
3360 bits |= AO_FIFO_Enable;
3361 else
3362 bits |= AO_DMA_PIO_Control;
3363 #if 0
3364 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3365 verified with bus analyzer. */
3366 if (board->reg_type & ni_reg_m_series_mask)
3367 bits |= AO_Number_Of_DAC_Packages;
3368 #endif
3369 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3370 /* enable sending of ao dma requests */
3371 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3372
3373 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3374
3375 if (cmd->stop_src == TRIG_COUNT) {
3376 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3377 Interrupt_B_Ack_Register);
3378 ni_set_bits(dev, Interrupt_B_Enable_Register,
3379 AO_BC_TC_Interrupt_Enable, 1);
3380 }
3381
3382 s->async->inttrig = &ni_ao_inttrig;
3383
3384 return 0;
3385 }
3386
3387 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3388 struct comedi_cmd *cmd)
3389 {
3390 const struct ni_board_struct *board = comedi_board(dev);
3391 struct ni_private *devpriv = dev->private;
3392 int err = 0;
3393 int tmp;
3394
3395 /* Step 1 : check if triggers are trivially valid */
3396
3397 if ((cmd->flags & CMDF_WRITE) == 0)
3398 cmd->flags |= CMDF_WRITE;
3399
3400 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3401 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3402 TRIG_TIMER | TRIG_EXT);
3403 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3404 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3405 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3406
3407 if (err)
3408 return 1;
3409
3410 /* Step 2a : make sure trigger sources are unique */
3411
3412 err |= cfc_check_trigger_is_unique(cmd->start_src);
3413 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3414 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3415
3416 /* Step 2b : and mutually compatible */
3417
3418 if (err)
3419 return 2;
3420
3421 /* Step 3: check if arguments are trivially valid */
3422
3423 if (cmd->start_src == TRIG_EXT) {
3424 /* external trigger */
3425 unsigned int tmp = CR_CHAN(cmd->start_arg);
3426
3427 if (tmp > 18)
3428 tmp = 18;
3429 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3430 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3431 } else {
3432 /* true for both TRIG_NOW and TRIG_INT */
3433 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3434 }
3435
3436 if (cmd->scan_begin_src == TRIG_TIMER) {
3437 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3438 board->ao_speed);
3439 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3440 devpriv->clock_ns * 0xffffff);
3441 }
3442
3443 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3444 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3445
3446 if (cmd->stop_src == TRIG_COUNT)
3447 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3448 else /* TRIG_NONE */
3449 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3450
3451 if (err)
3452 return 3;
3453
3454 /* step 4: fix up any arguments */
3455 if (cmd->scan_begin_src == TRIG_TIMER) {
3456 tmp = cmd->scan_begin_arg;
3457 cmd->scan_begin_arg =
3458 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3459 cmd->scan_begin_arg,
3460 cmd->
3461 flags &
3462 TRIG_ROUND_MASK));
3463 if (tmp != cmd->scan_begin_arg)
3464 err++;
3465 }
3466 if (err)
3467 return 4;
3468
3469 /* step 5: fix up chanlist */
3470
3471 if (err)
3472 return 5;
3473
3474 return 0;
3475 }
3476
3477 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3478 {
3479 const struct ni_board_struct *board = comedi_board(dev);
3480 struct ni_private *devpriv = dev->private;
3481
3482 /* devpriv->ao0p=0x0000; */
3483 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3484
3485 /* devpriv->ao1p=AO_Channel(1); */
3486 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3487
3488 ni_release_ao_mite_channel(dev);
3489
3490 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3491 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3492 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3493 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3494 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3495 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3496 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3497 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3498 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3499 devpriv->ao_cmd1 = 0;
3500 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3501 devpriv->ao_cmd2 = 0;
3502 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3503 devpriv->ao_mode1 = 0;
3504 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3505 devpriv->ao_mode2 = 0;
3506 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3507 if (board->reg_type & ni_reg_m_series_mask)
3508 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3509 else
3510 devpriv->ao_mode3 = 0;
3511 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3512 devpriv->ao_trigger_select = 0;
3513 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3514 AO_Trigger_Select_Register);
3515 if (board->reg_type & ni_reg_6xxx_mask) {
3516 unsigned immediate_bits = 0;
3517 unsigned i;
3518 for (i = 0; i < s->n_chan; ++i) {
3519 immediate_bits |= 1 << i;
3520 }
3521 ao_win_out(immediate_bits, AO_Immediate_671x);
3522 ao_win_out(CLEAR_WG, AO_Misc_611x);
3523 }
3524 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3525
3526 return 0;
3527 }
3528
3529 /* digital io */
3530
3531 static int ni_dio_insn_config(struct comedi_device *dev,
3532 struct comedi_subdevice *s,
3533 struct comedi_insn *insn, unsigned int *data)
3534 {
3535 struct ni_private *devpriv = dev->private;
3536
3537 #ifdef DEBUG_DIO
3538 printk("ni_dio_insn_config() chan=%d io=%d\n",
3539 CR_CHAN(insn->chanspec), data[0]);
3540 #endif
3541 switch (data[0]) {
3542 case INSN_CONFIG_DIO_OUTPUT:
3543 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3544 break;
3545 case INSN_CONFIG_DIO_INPUT:
3546 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3547 break;
3548 case INSN_CONFIG_DIO_QUERY:
3549 data[1] =
3550 (s->
3551 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3552 COMEDI_INPUT;
3553 return insn->n;
3554 break;
3555 default:
3556 return -EINVAL;
3557 }
3558
3559 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3560 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3561 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3562
3563 return 1;
3564 }
3565
3566 static int ni_dio_insn_bits(struct comedi_device *dev,
3567 struct comedi_subdevice *s,
3568 struct comedi_insn *insn, unsigned int *data)
3569 {
3570 struct ni_private *devpriv = dev->private;
3571
3572 #ifdef DEBUG_DIO
3573 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3574 #endif
3575
3576 if (data[0]) {
3577 /* Perform check to make sure we're not using the
3578 serial part of the dio */
3579 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3580 && devpriv->serial_interval_ns)
3581 return -EBUSY;
3582
3583 s->state &= ~data[0];
3584 s->state |= (data[0] & data[1]);
3585 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3586 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3587 devpriv->stc_writew(dev, devpriv->dio_output,
3588 DIO_Output_Register);
3589 }
3590 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3591
3592 return insn->n;
3593 }
3594
3595 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3596 struct comedi_subdevice *s,
3597 struct comedi_insn *insn,
3598 unsigned int *data)
3599 {
3600 struct ni_private *devpriv __maybe_unused = dev->private;
3601
3602 #ifdef DEBUG_DIO
3603 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3604 CR_CHAN(insn->chanspec), data[0]);
3605 #endif
3606 switch (data[0]) {
3607 case INSN_CONFIG_DIO_OUTPUT:
3608 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3609 break;
3610 case INSN_CONFIG_DIO_INPUT:
3611 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3612 break;
3613 case INSN_CONFIG_DIO_QUERY:
3614 data[1] =
3615 (s->
3616 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3617 COMEDI_INPUT;
3618 return insn->n;
3619 break;
3620 default:
3621 return -EINVAL;
3622 }
3623
3624 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3625
3626 return 1;
3627 }
3628
3629 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3630 struct comedi_subdevice *s,
3631 struct comedi_insn *insn,
3632 unsigned int *data)
3633 {
3634 struct ni_private *devpriv __maybe_unused = dev->private;
3635
3636 #ifdef DEBUG_DIO
3637 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3638 data[1]);
3639 #endif
3640
3641 if (data[0]) {
3642 s->state &= ~data[0];
3643 s->state |= (data[0] & data[1]);
3644 ni_writel(s->state, M_Offset_Static_Digital_Output);
3645 }
3646 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3647
3648 return insn->n;
3649 }
3650
3651 static int ni_cdio_cmdtest(struct comedi_device *dev,
3652 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3653 {
3654 int err = 0;
3655 int tmp;
3656 unsigned i;
3657
3658 /* Step 1 : check if triggers are trivially valid */
3659
3660 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3661 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3662 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3663 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3664 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3665
3666 if (err)
3667 return 1;
3668
3669 /* Step 2a : make sure trigger sources are unique */
3670 /* Step 2b : and mutually compatible */
3671
3672 if (err)
3673 return 2;
3674
3675 /* Step 3: check if arguments are trivially valid */
3676
3677 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3678
3679 tmp = cmd->scan_begin_arg;
3680 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3681 if (tmp != cmd->scan_begin_arg)
3682 err |= -EINVAL;
3683
3684 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3685 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3686 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3687
3688 if (err)
3689 return 3;
3690
3691 /* step 4: fix up any arguments */
3692
3693 if (err)
3694 return 4;
3695
3696 /* step 5: check chanlist */
3697
3698 for (i = 0; i < cmd->chanlist_len; ++i) {
3699 if (cmd->chanlist[i] != i)
3700 err = 1;
3701 }
3702
3703 if (err)
3704 return 5;
3705
3706 return 0;
3707 }
3708
3709 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3710 {
3711 struct ni_private *devpriv __maybe_unused = dev->private;
3712 const struct comedi_cmd *cmd = &s->async->cmd;
3713 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3714 int retval;
3715
3716 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3717 switch (cmd->scan_begin_src) {
3718 case TRIG_EXT:
3719 cdo_mode_bits |=
3720 CR_CHAN(cmd->scan_begin_arg) &
3721 CDO_Sample_Source_Select_Mask;
3722 break;
3723 default:
3724 BUG();
3725 break;
3726 }
3727 if (cmd->scan_begin_arg & CR_INVERT)
3728 cdo_mode_bits |= CDO_Polarity_Bit;
3729 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3730 if (s->io_bits) {
3731 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3732 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3733 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3734 } else {
3735 comedi_error(dev,
3736 "attempted to run digital output command with no lines configured as outputs");
3737 return -EIO;
3738 }
3739 retval = ni_request_cdo_mite_channel(dev);
3740 if (retval < 0) {
3741 return retval;
3742 }
3743 s->async->inttrig = &ni_cdo_inttrig;
3744 return 0;
3745 }
3746
3747 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3748 unsigned int trignum)
3749 {
3750 #ifdef PCIDMA
3751 struct ni_private *devpriv = dev->private;
3752 unsigned long flags;
3753 #endif
3754 int retval = 0;
3755 unsigned i;
3756 const unsigned timeout = 1000;
3757
3758 s->async->inttrig = NULL;
3759
3760 /* read alloc the entire buffer */
3761 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3762
3763 #ifdef PCIDMA
3764 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3765 if (devpriv->cdo_mite_chan) {
3766 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3767 mite_dma_arm(devpriv->cdo_mite_chan);
3768 } else {
3769 comedi_error(dev, "BUG: no cdo mite channel?");
3770 retval = -EIO;
3771 }
3772 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3773 if (retval < 0)
3774 return retval;
3775 #endif
3776 /*
3777 * XXX not sure what interrupt C group does
3778 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3779 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3780 */
3781 for (i = 0; i < timeout; ++i) {
3782 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3783 break;
3784 udelay(10);
3785 }
3786 if (i == timeout) {
3787 comedi_error(dev, "dma failed to fill cdo fifo!");
3788 ni_cdio_cancel(dev, s);
3789 return -EIO;
3790 }
3791 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3792 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3793 M_Offset_CDIO_Command);
3794 return retval;
3795 }
3796
3797 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3798 {
3799 struct ni_private *devpriv __maybe_unused = dev->private;
3800
3801 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3802 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3803 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3804 M_Offset_CDIO_Command);
3805 /*
3806 * XXX not sure what interrupt C group does ni_writeb(0,
3807 * M_Offset_Interrupt_C_Enable);
3808 */
3809 ni_writel(0, M_Offset_CDO_Mask_Enable);
3810 ni_release_cdo_mite_channel(dev);
3811 return 0;
3812 }
3813
3814 static void handle_cdio_interrupt(struct comedi_device *dev)
3815 {
3816 const struct ni_board_struct *board = comedi_board(dev);
3817 struct ni_private *devpriv __maybe_unused = dev->private;
3818 unsigned cdio_status;
3819 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3820 #ifdef PCIDMA
3821 unsigned long flags;
3822 #endif
3823
3824 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3825 return;
3826 }
3827 #ifdef PCIDMA
3828 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3829 if (devpriv->cdo_mite_chan) {
3830 unsigned cdo_mite_status =
3831 mite_get_status(devpriv->cdo_mite_chan);
3832 if (cdo_mite_status & CHSR_LINKC) {
3833 writel(CHOR_CLRLC,
3834 devpriv->mite->mite_io_addr +
3835 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3836 }
3837 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3838 }
3839 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3840 #endif
3841
3842 cdio_status = ni_readl(M_Offset_CDIO_Status);
3843 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3844 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3845 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3846 s->async->events |= COMEDI_CB_OVERFLOW;
3847 }
3848 if (cdio_status & CDO_FIFO_Empty_Bit) {
3849 /* printk("cdio fifo empty\n"); */
3850 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3851 M_Offset_CDIO_Command);
3852 /* s->async->events |= COMEDI_CB_EOA; */
3853 }
3854 ni_event(dev, s);
3855 }
3856
3857 static int ni_serial_insn_config(struct comedi_device *dev,
3858 struct comedi_subdevice *s,
3859 struct comedi_insn *insn, unsigned int *data)
3860 {
3861 struct ni_private *devpriv = dev->private;
3862 int err = insn->n;
3863 unsigned char byte_out, byte_in = 0;
3864
3865 if (insn->n != 2)
3866 return -EINVAL;
3867
3868 switch (data[0]) {
3869 case INSN_CONFIG_SERIAL_CLOCK:
3870
3871 #ifdef DEBUG_DIO
3872 printk("SPI serial clock Config cd\n", data[1]);
3873 #endif
3874 devpriv->serial_hw_mode = 1;
3875 devpriv->dio_control |= DIO_HW_Serial_Enable;
3876
3877 if (data[1] == SERIAL_DISABLED) {
3878 devpriv->serial_hw_mode = 0;
3879 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3880 DIO_Software_Serial_Control);
3881 data[1] = SERIAL_DISABLED;
3882 devpriv->serial_interval_ns = data[1];
3883 } else if (data[1] <= SERIAL_600NS) {
3884 /* Warning: this clock speed is too fast to reliably
3885 control SCXI. */
3886 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3887 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3888 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3889 data[1] = SERIAL_600NS;
3890 devpriv->serial_interval_ns = data[1];
3891 } else if (data[1] <= SERIAL_1_2US) {
3892 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3893 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3894 DIO_Serial_Out_Divide_By_2;
3895 data[1] = SERIAL_1_2US;
3896 devpriv->serial_interval_ns = data[1];
3897 } else if (data[1] <= SERIAL_10US) {
3898 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3899 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3900 DIO_Serial_Out_Divide_By_2;
3901 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3902 600ns/1.2us. If you turn divide_by_2 off with the
3903 slow clock, you will still get 10us, except then
3904 all your delays are wrong. */
3905 data[1] = SERIAL_10US;
3906 devpriv->serial_interval_ns = data[1];
3907 } else {
3908 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3909 DIO_Software_Serial_Control);
3910 devpriv->serial_hw_mode = 0;
3911 data[1] = (data[1] / 1000) * 1000;
3912 devpriv->serial_interval_ns = data[1];
3913 }
3914
3915 devpriv->stc_writew(dev, devpriv->dio_control,
3916 DIO_Control_Register);
3917 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3918 Clock_and_FOUT_Register);
3919 return 1;
3920
3921 break;
3922
3923 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3924
3925 if (devpriv->serial_interval_ns == 0) {
3926 return -EINVAL;
3927 }
3928
3929 byte_out = data[1] & 0xFF;
3930
3931 if (devpriv->serial_hw_mode) {
3932 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3933 &byte_in);
3934 } else if (devpriv->serial_interval_ns > 0) {
3935 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3936 &byte_in);
3937 } else {
3938 printk("ni_serial_insn_config: serial disabled!\n");
3939 return -EINVAL;
3940 }
3941 if (err < 0)
3942 return err;
3943 data[1] = byte_in & 0xFF;
3944 return insn->n;
3945
3946 break;
3947 default:
3948 return -EINVAL;
3949 }
3950
3951 }
3952
3953 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3954 struct comedi_subdevice *s,
3955 unsigned char data_out,
3956 unsigned char *data_in)
3957 {
3958 struct ni_private *devpriv = dev->private;
3959 unsigned int status1;
3960 int err = 0, count = 20;
3961
3962 #ifdef DEBUG_DIO
3963 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3964 #endif
3965
3966 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3967 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3968 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3969
3970 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3971 if (status1 & DIO_Serial_IO_In_Progress_St) {
3972 err = -EBUSY;
3973 goto Error;
3974 }
3975
3976 devpriv->dio_control |= DIO_HW_Serial_Start;
3977 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3978 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3979
3980 /* Wait until STC says we're done, but don't loop infinitely. */
3981 while ((status1 =
3982 devpriv->stc_readw(dev,
3983 Joint_Status_1_Register)) &
3984 DIO_Serial_IO_In_Progress_St) {
3985 /* Delay one bit per loop */
3986 udelay((devpriv->serial_interval_ns + 999) / 1000);
3987 if (--count < 0) {
3988 printk
3989 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3990 err = -ETIME;
3991 goto Error;
3992 }
3993 }
3994
3995 /* Delay for last bit. This delay is absolutely necessary, because
3996 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3997 udelay((devpriv->serial_interval_ns + 999) / 1000);
3998
3999 if (data_in != NULL) {
4000 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4001 #ifdef DEBUG_DIO
4002 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4003 #endif
4004 }
4005
4006 Error:
4007 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4008
4009 return err;
4010 }
4011
4012 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4013 struct comedi_subdevice *s,
4014 unsigned char data_out,
4015 unsigned char *data_in)
4016 {
4017 struct ni_private *devpriv = dev->private;
4018 unsigned char mask, input = 0;
4019
4020 #ifdef DEBUG_DIO
4021 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4022 #endif
4023
4024 /* Wait for one bit before transfer */
4025 udelay((devpriv->serial_interval_ns + 999) / 1000);
4026
4027 for (mask = 0x80; mask; mask >>= 1) {
4028 /* Output current bit; note that we cannot touch s->state
4029 because it is a per-subdevice field, and serial is
4030 a separate subdevice from DIO. */
4031 devpriv->dio_output &= ~DIO_SDOUT;
4032 if (data_out & mask) {
4033 devpriv->dio_output |= DIO_SDOUT;
4034 }
4035 devpriv->stc_writew(dev, devpriv->dio_output,
4036 DIO_Output_Register);
4037
4038 /* Assert SDCLK (active low, inverted), wait for half of
4039 the delay, deassert SDCLK, and wait for the other half. */
4040 devpriv->dio_control |= DIO_Software_Serial_Control;
4041 devpriv->stc_writew(dev, devpriv->dio_control,
4042 DIO_Control_Register);
4043
4044 udelay((devpriv->serial_interval_ns + 999) / 2000);
4045
4046 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4047 devpriv->stc_writew(dev, devpriv->dio_control,
4048 DIO_Control_Register);
4049
4050 udelay((devpriv->serial_interval_ns + 999) / 2000);
4051
4052 /* Input current bit */
4053 if (devpriv->stc_readw(dev,
4054 DIO_Parallel_Input_Register) & DIO_SDIN)
4055 {
4056 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4057 input |= mask;
4058 }
4059 }
4060 #ifdef DEBUG_DIO
4061 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4062 #endif
4063 if (data_in)
4064 *data_in = input;
4065
4066 return 0;
4067 }
4068
4069 static void mio_common_detach(struct comedi_device *dev)
4070 {
4071 struct ni_private *devpriv = dev->private;
4072
4073 if (devpriv) {
4074 if (devpriv->counter_dev) {
4075 ni_gpct_device_destroy(devpriv->counter_dev);
4076 }
4077 }
4078 comedi_spriv_free(dev, NI_8255_DIO_SUBDEV);
4079 }
4080
4081 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4082 {
4083 int i;
4084
4085 for (i = 0; i < s->n_chan; i++) {
4086 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4087 AO_Configuration_2_67xx);
4088 }
4089 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4090 }
4091
4092 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4093 {
4094 unsigned stc_register;
4095 switch (reg) {
4096 case NITIO_G0_Autoincrement_Reg:
4097 stc_register = G_Autoincrement_Register(0);
4098 break;
4099 case NITIO_G1_Autoincrement_Reg:
4100 stc_register = G_Autoincrement_Register(1);
4101 break;
4102 case NITIO_G0_Command_Reg:
4103 stc_register = G_Command_Register(0);
4104 break;
4105 case NITIO_G1_Command_Reg:
4106 stc_register = G_Command_Register(1);
4107 break;
4108 case NITIO_G0_HW_Save_Reg:
4109 stc_register = G_HW_Save_Register(0);
4110 break;
4111 case NITIO_G1_HW_Save_Reg:
4112 stc_register = G_HW_Save_Register(1);
4113 break;
4114 case NITIO_G0_SW_Save_Reg:
4115 stc_register = G_Save_Register(0);
4116 break;
4117 case NITIO_G1_SW_Save_Reg:
4118 stc_register = G_Save_Register(1);
4119 break;
4120 case NITIO_G0_Mode_Reg:
4121 stc_register = G_Mode_Register(0);
4122 break;
4123 case NITIO_G1_Mode_Reg:
4124 stc_register = G_Mode_Register(1);
4125 break;
4126 case NITIO_G0_LoadA_Reg:
4127 stc_register = G_Load_A_Register(0);
4128 break;
4129 case NITIO_G1_LoadA_Reg:
4130 stc_register = G_Load_A_Register(1);
4131 break;
4132 case NITIO_G0_LoadB_Reg:
4133 stc_register = G_Load_B_Register(0);
4134 break;
4135 case NITIO_G1_LoadB_Reg:
4136 stc_register = G_Load_B_Register(1);
4137 break;
4138 case NITIO_G0_Input_Select_Reg:
4139 stc_register = G_Input_Select_Register(0);
4140 break;
4141 case NITIO_G1_Input_Select_Reg:
4142 stc_register = G_Input_Select_Register(1);
4143 break;
4144 case NITIO_G01_Status_Reg:
4145 stc_register = G_Status_Register;
4146 break;
4147 case NITIO_G01_Joint_Reset_Reg:
4148 stc_register = Joint_Reset_Register;
4149 break;
4150 case NITIO_G01_Joint_Status1_Reg:
4151 stc_register = Joint_Status_1_Register;
4152 break;
4153 case NITIO_G01_Joint_Status2_Reg:
4154 stc_register = Joint_Status_2_Register;
4155 break;
4156 case NITIO_G0_Interrupt_Acknowledge_Reg:
4157 stc_register = Interrupt_A_Ack_Register;
4158 break;
4159 case NITIO_G1_Interrupt_Acknowledge_Reg:
4160 stc_register = Interrupt_B_Ack_Register;
4161 break;
4162 case NITIO_G0_Status_Reg:
4163 stc_register = AI_Status_1_Register;
4164 break;
4165 case NITIO_G1_Status_Reg:
4166 stc_register = AO_Status_1_Register;
4167 break;
4168 case NITIO_G0_Interrupt_Enable_Reg:
4169 stc_register = Interrupt_A_Enable_Register;
4170 break;
4171 case NITIO_G1_Interrupt_Enable_Reg:
4172 stc_register = Interrupt_B_Enable_Register;
4173 break;
4174 default:
4175 printk("%s: unhandled register 0x%x in switch.\n",
4176 __func__, reg);
4177 BUG();
4178 return 0;
4179 break;
4180 }
4181 return stc_register;
4182 }
4183
4184 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4185 enum ni_gpct_register reg)
4186 {
4187 struct comedi_device *dev = counter->counter_dev->dev;
4188 struct ni_private *devpriv = dev->private;
4189 unsigned stc_register;
4190 /* bits in the join reset register which are relevant to counters */
4191 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4192 static const unsigned gpct_interrupt_a_enable_mask =
4193 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4194 static const unsigned gpct_interrupt_b_enable_mask =
4195 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4196
4197 switch (reg) {
4198 /* m-series-only registers */
4199 case NITIO_G0_Counting_Mode_Reg:
4200 ni_writew(bits, M_Offset_G0_Counting_Mode);
4201 break;
4202 case NITIO_G1_Counting_Mode_Reg:
4203 ni_writew(bits, M_Offset_G1_Counting_Mode);
4204 break;
4205 case NITIO_G0_Second_Gate_Reg:
4206 ni_writew(bits, M_Offset_G0_Second_Gate);
4207 break;
4208 case NITIO_G1_Second_Gate_Reg:
4209 ni_writew(bits, M_Offset_G1_Second_Gate);
4210 break;
4211 case NITIO_G0_DMA_Config_Reg:
4212 ni_writew(bits, M_Offset_G0_DMA_Config);
4213 break;
4214 case NITIO_G1_DMA_Config_Reg:
4215 ni_writew(bits, M_Offset_G1_DMA_Config);
4216 break;
4217 case NITIO_G0_ABZ_Reg:
4218 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4219 break;
4220 case NITIO_G1_ABZ_Reg:
4221 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4222 break;
4223
4224 /* 32 bit registers */
4225 case NITIO_G0_LoadA_Reg:
4226 case NITIO_G1_LoadA_Reg:
4227 case NITIO_G0_LoadB_Reg:
4228 case NITIO_G1_LoadB_Reg:
4229 stc_register = ni_gpct_to_stc_register(reg);
4230 devpriv->stc_writel(dev, bits, stc_register);
4231 break;
4232
4233 /* 16 bit registers */
4234 case NITIO_G0_Interrupt_Enable_Reg:
4235 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4236 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4237 gpct_interrupt_a_enable_mask, bits);
4238 break;
4239 case NITIO_G1_Interrupt_Enable_Reg:
4240 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4241 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4242 gpct_interrupt_b_enable_mask, bits);
4243 break;
4244 case NITIO_G01_Joint_Reset_Reg:
4245 BUG_ON(bits & ~gpct_joint_reset_mask);
4246 /* fall-through */
4247 default:
4248 stc_register = ni_gpct_to_stc_register(reg);
4249 devpriv->stc_writew(dev, bits, stc_register);
4250 }
4251 }
4252
4253 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4254 enum ni_gpct_register reg)
4255 {
4256 struct comedi_device *dev = counter->counter_dev->dev;
4257 struct ni_private *devpriv = dev->private;
4258 unsigned stc_register;
4259
4260 switch (reg) {
4261 /* m-series only registers */
4262 case NITIO_G0_DMA_Status_Reg:
4263 return ni_readw(M_Offset_G0_DMA_Status);
4264 break;
4265 case NITIO_G1_DMA_Status_Reg:
4266 return ni_readw(M_Offset_G1_DMA_Status);
4267 break;
4268
4269 /* 32 bit registers */
4270 case NITIO_G0_HW_Save_Reg:
4271 case NITIO_G1_HW_Save_Reg:
4272 case NITIO_G0_SW_Save_Reg:
4273 case NITIO_G1_SW_Save_Reg:
4274 stc_register = ni_gpct_to_stc_register(reg);
4275 return devpriv->stc_readl(dev, stc_register);
4276 break;
4277
4278 /* 16 bit registers */
4279 default:
4280 stc_register = ni_gpct_to_stc_register(reg);
4281 return devpriv->stc_readw(dev, stc_register);
4282 break;
4283 }
4284 return 0;
4285 }
4286
4287 static int ni_freq_out_insn_read(struct comedi_device *dev,
4288 struct comedi_subdevice *s,
4289 struct comedi_insn *insn, unsigned int *data)
4290 {
4291 struct ni_private *devpriv = dev->private;
4292
4293 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4294 return 1;
4295 }
4296
4297 static int ni_freq_out_insn_write(struct comedi_device *dev,
4298 struct comedi_subdevice *s,
4299 struct comedi_insn *insn, unsigned int *data)
4300 {
4301 struct ni_private *devpriv = dev->private;
4302
4303 devpriv->clock_and_fout &= ~FOUT_Enable;
4304 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4305 Clock_and_FOUT_Register);
4306 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4307 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4308 devpriv->clock_and_fout |= FOUT_Enable;
4309 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4310 Clock_and_FOUT_Register);
4311 return insn->n;
4312 }
4313
4314 static int ni_set_freq_out_clock(struct comedi_device *dev,
4315 unsigned int clock_source)
4316 {
4317 struct ni_private *devpriv = dev->private;
4318
4319 switch (clock_source) {
4320 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4321 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4322 break;
4323 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4324 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4325 break;
4326 default:
4327 return -EINVAL;
4328 }
4329 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4330 Clock_and_FOUT_Register);
4331 return 3;
4332 }
4333
4334 static void ni_get_freq_out_clock(struct comedi_device *dev,
4335 unsigned int *clock_source,
4336 unsigned int *clock_period_ns)
4337 {
4338 struct ni_private *devpriv = dev->private;
4339
4340 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4341 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4342 *clock_period_ns = TIMEBASE_2_NS;
4343 } else {
4344 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4345 *clock_period_ns = TIMEBASE_1_NS * 2;
4346 }
4347 }
4348
4349 static int ni_freq_out_insn_config(struct comedi_device *dev,
4350 struct comedi_subdevice *s,
4351 struct comedi_insn *insn, unsigned int *data)
4352 {
4353 switch (data[0]) {
4354 case INSN_CONFIG_SET_CLOCK_SRC:
4355 return ni_set_freq_out_clock(dev, data[1]);
4356 break;
4357 case INSN_CONFIG_GET_CLOCK_SRC:
4358 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4359 return 3;
4360 default:
4361 break;
4362 }
4363 return -EINVAL;
4364 }
4365
4366 static int ni_alloc_private(struct comedi_device *dev)
4367 {
4368 struct ni_private *devpriv;
4369
4370 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4371 if (!devpriv)
4372 return -ENOMEM;
4373 dev->private = devpriv;
4374
4375 spin_lock_init(&devpriv->window_lock);
4376 spin_lock_init(&devpriv->soft_reg_copy_lock);
4377 spin_lock_init(&devpriv->mite_channel_lock);
4378
4379 return 0;
4380 };
4381
4382 static int ni_E_init(struct comedi_device *dev)
4383 {
4384 const struct ni_board_struct *board = comedi_board(dev);
4385 struct ni_private *devpriv = dev->private;
4386 struct comedi_subdevice *s;
4387 unsigned j;
4388 enum ni_gpct_variant counter_variant;
4389 int ret;
4390
4391 if (board->n_aochan > MAX_N_AO_CHAN) {
4392 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4393 return -EINVAL;
4394 }
4395
4396 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4397 if (ret)
4398 return ret;
4399
4400 /* analog input subdevice */
4401
4402 s = &dev->subdevices[NI_AI_SUBDEV];
4403 dev->read_subdev = s;
4404 if (board->n_adchan) {
4405 s->type = COMEDI_SUBD_AI;
4406 s->subdev_flags =
4407 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4408 if (board->reg_type != ni_reg_611x)
4409 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4410 if (board->adbits > 16)
4411 s->subdev_flags |= SDF_LSAMPL;
4412 if (board->reg_type & ni_reg_m_series_mask)
4413 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4414 s->n_chan = board->n_adchan;
4415 s->len_chanlist = 512;
4416 s->maxdata = (1 << board->adbits) - 1;
4417 s->range_table = ni_range_lkup[board->gainlkup];
4418 s->insn_read = &ni_ai_insn_read;
4419 s->insn_config = &ni_ai_insn_config;
4420 s->do_cmdtest = &ni_ai_cmdtest;
4421 s->do_cmd = &ni_ai_cmd;
4422 s->cancel = &ni_ai_reset;
4423 s->poll = &ni_ai_poll;
4424 s->munge = &ni_ai_munge;
4425 #ifdef PCIDMA
4426 s->async_dma_dir = DMA_FROM_DEVICE;
4427 #endif
4428 } else {
4429 s->type = COMEDI_SUBD_UNUSED;
4430 }
4431
4432 /* analog output subdevice */
4433
4434 s = &dev->subdevices[NI_AO_SUBDEV];
4435 if (board->n_aochan) {
4436 s->type = COMEDI_SUBD_AO;
4437 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4438 if (board->reg_type & ni_reg_m_series_mask)
4439 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4440 s->n_chan = board->n_aochan;
4441 s->maxdata = (1 << board->aobits) - 1;
4442 s->range_table = board->ao_range_table;
4443 s->insn_read = &ni_ao_insn_read;
4444 if (board->reg_type & ni_reg_6xxx_mask) {
4445 s->insn_write = &ni_ao_insn_write_671x;
4446 } else {
4447 s->insn_write = &ni_ao_insn_write;
4448 }
4449 s->insn_config = &ni_ao_insn_config;
4450 #ifdef PCIDMA
4451 if (board->n_aochan) {
4452 s->async_dma_dir = DMA_TO_DEVICE;
4453 #else
4454 if (board->ao_fifo_depth) {
4455 #endif
4456 dev->write_subdev = s;
4457 s->subdev_flags |= SDF_CMD_WRITE;
4458 s->do_cmd = &ni_ao_cmd;
4459 s->do_cmdtest = &ni_ao_cmdtest;
4460 s->len_chanlist = board->n_aochan;
4461 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4462 s->munge = ni_ao_munge;
4463 }
4464 s->cancel = &ni_ao_reset;
4465 } else {
4466 s->type = COMEDI_SUBD_UNUSED;
4467 }
4468 if ((board->reg_type & ni_reg_67xx_mask))
4469 init_ao_67xx(dev, s);
4470
4471 /* digital i/o subdevice */
4472
4473 s = &dev->subdevices[NI_DIO_SUBDEV];
4474 s->type = COMEDI_SUBD_DIO;
4475 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4476 s->maxdata = 1;
4477 s->io_bits = 0; /* all bits input */
4478 s->range_table = &range_digital;
4479 s->n_chan = board->num_p0_dio_channels;
4480 if (board->reg_type & ni_reg_m_series_mask) {
4481 s->subdev_flags |=
4482 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4483 s->insn_bits = &ni_m_series_dio_insn_bits;
4484 s->insn_config = &ni_m_series_dio_insn_config;
4485 s->do_cmd = &ni_cdio_cmd;
4486 s->do_cmdtest = &ni_cdio_cmdtest;
4487 s->cancel = &ni_cdio_cancel;
4488 s->async_dma_dir = DMA_BIDIRECTIONAL;
4489 s->len_chanlist = s->n_chan;
4490
4491 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4492 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4493 } else {
4494 s->insn_bits = &ni_dio_insn_bits;
4495 s->insn_config = &ni_dio_insn_config;
4496 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4497 ni_writew(devpriv->dio_control, DIO_Control_Register);
4498 }
4499
4500 /* 8255 device */
4501 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4502 if (board->has_8255) {
4503 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4504 } else {
4505 s->type = COMEDI_SUBD_UNUSED;
4506 }
4507
4508 /* formerly general purpose counter/timer device, but no longer used */
4509 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4510 s->type = COMEDI_SUBD_UNUSED;
4511
4512 /* calibration subdevice -- ai and ao */
4513 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4514 s->type = COMEDI_SUBD_CALIB;
4515 if (board->reg_type & ni_reg_m_series_mask) {
4516 /* internal PWM analog output used for AI nonlinearity calibration */
4517 s->subdev_flags = SDF_INTERNAL;
4518 s->insn_config = &ni_m_series_pwm_config;
4519 s->n_chan = 1;
4520 s->maxdata = 0;
4521 ni_writel(0x0, M_Offset_Cal_PWM);
4522 } else if (board->reg_type == ni_reg_6143) {
4523 /* internal PWM analog output used for AI nonlinearity calibration */
4524 s->subdev_flags = SDF_INTERNAL;
4525 s->insn_config = &ni_6143_pwm_config;
4526 s->n_chan = 1;
4527 s->maxdata = 0;
4528 } else {
4529 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4530 s->insn_read = &ni_calib_insn_read;
4531 s->insn_write = &ni_calib_insn_write;
4532 caldac_setup(dev, s);
4533 }
4534
4535 /* EEPROM */
4536 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4537 s->type = COMEDI_SUBD_MEMORY;
4538 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4539 s->maxdata = 0xff;
4540 if (board->reg_type & ni_reg_m_series_mask) {
4541 s->n_chan = M_SERIES_EEPROM_SIZE;
4542 s->insn_read = &ni_m_series_eeprom_insn_read;
4543 } else {
4544 s->n_chan = 512;
4545 s->insn_read = &ni_eeprom_insn_read;
4546 }
4547
4548 /* PFI */
4549 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4550 s->type = COMEDI_SUBD_DIO;
4551 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4552 if (board->reg_type & ni_reg_m_series_mask) {
4553 unsigned i;
4554 s->n_chan = 16;
4555 ni_writew(s->state, M_Offset_PFI_DO);
4556 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4557 ni_writew(devpriv->pfi_output_select_reg[i],
4558 M_Offset_PFI_Output_Select(i + 1));
4559 }
4560 } else {
4561 s->n_chan = 10;
4562 }
4563 s->maxdata = 1;
4564 if (board->reg_type & ni_reg_m_series_mask) {
4565 s->insn_bits = &ni_pfi_insn_bits;
4566 }
4567 s->insn_config = &ni_pfi_insn_config;
4568 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4569
4570 /* cs5529 calibration adc */
4571 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4572 if (board->reg_type & ni_reg_67xx_mask) {
4573 s->type = COMEDI_SUBD_AI;
4574 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4575 /* one channel for each analog output channel */
4576 s->n_chan = board->n_aochan;
4577 s->maxdata = (1 << 16) - 1;
4578 s->range_table = &range_unknown; /* XXX */
4579 s->insn_read = cs5529_ai_insn_read;
4580 s->insn_config = NULL;
4581 init_cs5529(dev);
4582 } else {
4583 s->type = COMEDI_SUBD_UNUSED;
4584 }
4585
4586 /* Serial */
4587 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4588 s->type = COMEDI_SUBD_SERIAL;
4589 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4590 s->n_chan = 1;
4591 s->maxdata = 0xff;
4592 s->insn_config = ni_serial_insn_config;
4593 devpriv->serial_interval_ns = 0;
4594 devpriv->serial_hw_mode = 0;
4595
4596 /* RTSI */
4597 s = &dev->subdevices[NI_RTSI_SUBDEV];
4598 s->type = COMEDI_SUBD_DIO;
4599 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4600 s->n_chan = 8;
4601 s->maxdata = 1;
4602 s->insn_bits = ni_rtsi_insn_bits;
4603 s->insn_config = ni_rtsi_insn_config;
4604 ni_rtsi_init(dev);
4605
4606 if (board->reg_type & ni_reg_m_series_mask) {
4607 counter_variant = ni_gpct_variant_m_series;
4608 } else {
4609 counter_variant = ni_gpct_variant_e_series;
4610 }
4611 devpriv->counter_dev = ni_gpct_device_construct(dev,
4612 &ni_gpct_write_register,
4613 &ni_gpct_read_register,
4614 counter_variant,
4615 NUM_GPCT);
4616 /* General purpose counters */
4617 for (j = 0; j < NUM_GPCT; ++j) {
4618 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4619 s->type = COMEDI_SUBD_COUNTER;
4620 s->subdev_flags =
4621 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_CMD_READ
4622 /* | SDF_CMD_WRITE */ ;
4623 s->n_chan = 3;
4624 if (board->reg_type & ni_reg_m_series_mask)
4625 s->maxdata = 0xffffffff;
4626 else
4627 s->maxdata = 0xffffff;
4628 s->insn_read = &ni_gpct_insn_read;
4629 s->insn_write = &ni_gpct_insn_write;
4630 s->insn_config = &ni_gpct_insn_config;
4631 s->do_cmd = &ni_gpct_cmd;
4632 s->len_chanlist = 1;
4633 s->do_cmdtest = &ni_gpct_cmdtest;
4634 s->cancel = &ni_gpct_cancel;
4635 s->async_dma_dir = DMA_BIDIRECTIONAL;
4636 s->private = &devpriv->counter_dev->counters[j];
4637
4638 devpriv->counter_dev->counters[j].chip_index = 0;
4639 devpriv->counter_dev->counters[j].counter_index = j;
4640 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4641 }
4642
4643 /* Frequency output */
4644 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4645 s->type = COMEDI_SUBD_COUNTER;
4646 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4647 s->n_chan = 1;
4648 s->maxdata = 0xf;
4649 s->insn_read = &ni_freq_out_insn_read;
4650 s->insn_write = &ni_freq_out_insn_write;
4651 s->insn_config = &ni_freq_out_insn_config;
4652
4653 /* ai configuration */
4654 s = &dev->subdevices[NI_AI_SUBDEV];
4655 ni_ai_reset(dev, s);
4656 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4657 /* BEAM is this needed for PCI-6143 ?? */
4658 devpriv->clock_and_fout =
4659 Slow_Internal_Time_Divide_By_2 |
4660 Slow_Internal_Timebase |
4661 Clock_To_Board_Divide_By_2 |
4662 Clock_To_Board |
4663 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4664 } else {
4665 devpriv->clock_and_fout =
4666 Slow_Internal_Time_Divide_By_2 |
4667 Slow_Internal_Timebase |
4668 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4669 }
4670 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4671 Clock_and_FOUT_Register);
4672
4673 /* analog output configuration */
4674 s = &dev->subdevices[NI_AO_SUBDEV];
4675 ni_ao_reset(dev, s);
4676
4677 if (dev->irq) {
4678 devpriv->stc_writew(dev,
4679 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4680 0) | (Interrupt_Output_On_3_Pins & 0) |
4681 Interrupt_A_Enable | Interrupt_B_Enable |
4682 Interrupt_A_Output_Select(interrupt_pin
4683 (dev->irq)) |
4684 Interrupt_B_Output_Select(interrupt_pin
4685 (dev->irq)),
4686 Interrupt_Control_Register);
4687 }
4688
4689 /* DMA setup */
4690 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4691 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4692
4693 if (board->reg_type & ni_reg_6xxx_mask) {
4694 ni_writeb(0, Magic_611x);
4695 } else if (board->reg_type & ni_reg_m_series_mask) {
4696 int channel;
4697 for (channel = 0; channel < board->n_aochan; ++channel) {
4698 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4699 ni_writeb(0x0,
4700 M_Offset_AO_Reference_Attenuation(channel));
4701 }
4702 ni_writeb(0x0, M_Offset_AO_Calibration);
4703 }
4704
4705 printk("\n");
4706 return 0;
4707 }
4708
4709 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4710 {
4711 struct comedi_device *dev = (struct comedi_device *)arg;
4712 struct ni_private *devpriv __maybe_unused = dev->private;
4713
4714 if (dir) {
4715 ni_writeb(data, Port_A + 2 * port);
4716 return 0;
4717 } else {
4718 return ni_readb(Port_A + 2 * port);
4719 }
4720 }
4721
4722 /*
4723 presents the EEPROM as a subdevice
4724 */
4725
4726 static int ni_eeprom_insn_read(struct comedi_device *dev,
4727 struct comedi_subdevice *s,
4728 struct comedi_insn *insn, unsigned int *data)
4729 {
4730 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4731
4732 return 1;
4733 }
4734
4735 /*
4736 reads bytes out of eeprom
4737 */
4738
4739 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4740 {
4741 struct ni_private *devpriv __maybe_unused = dev->private;
4742 int bit;
4743 int bitstring;
4744
4745 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4746 ni_writeb(0x04, Serial_Command);
4747 for (bit = 0x8000; bit; bit >>= 1) {
4748 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4749 Serial_Command);
4750 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4751 Serial_Command);
4752 }
4753 bitstring = 0;
4754 for (bit = 0x80; bit; bit >>= 1) {
4755 ni_writeb(0x04, Serial_Command);
4756 ni_writeb(0x05, Serial_Command);
4757 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4758 }
4759 ni_writeb(0x00, Serial_Command);
4760
4761 return bitstring;
4762 }
4763
4764 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4765 struct comedi_subdevice *s,
4766 struct comedi_insn *insn,
4767 unsigned int *data)
4768 {
4769 struct ni_private *devpriv = dev->private;
4770
4771 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4772
4773 return 1;
4774 }
4775
4776 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4777 {
4778 struct ni_private *devpriv = dev->private;
4779
4780 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4781 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4782 return 3;
4783 }
4784
4785 static int ni_m_series_pwm_config(struct comedi_device *dev,
4786 struct comedi_subdevice *s,
4787 struct comedi_insn *insn, unsigned int *data)
4788 {
4789 struct ni_private *devpriv = dev->private;
4790 unsigned up_count, down_count;
4791
4792 switch (data[0]) {
4793 case INSN_CONFIG_PWM_OUTPUT:
4794 switch (data[1]) {
4795 case TRIG_ROUND_NEAREST:
4796 up_count =
4797 (data[2] +
4798 devpriv->clock_ns / 2) / devpriv->clock_ns;
4799 break;
4800 case TRIG_ROUND_DOWN:
4801 up_count = data[2] / devpriv->clock_ns;
4802 break;
4803 case TRIG_ROUND_UP:
4804 up_count =
4805 (data[2] + devpriv->clock_ns -
4806 1) / devpriv->clock_ns;
4807 break;
4808 default:
4809 return -EINVAL;
4810 break;
4811 }
4812 switch (data[3]) {
4813 case TRIG_ROUND_NEAREST:
4814 down_count =
4815 (data[4] +
4816 devpriv->clock_ns / 2) / devpriv->clock_ns;
4817 break;
4818 case TRIG_ROUND_DOWN:
4819 down_count = data[4] / devpriv->clock_ns;
4820 break;
4821 case TRIG_ROUND_UP:
4822 down_count =
4823 (data[4] + devpriv->clock_ns -
4824 1) / devpriv->clock_ns;
4825 break;
4826 default:
4827 return -EINVAL;
4828 break;
4829 }
4830 if (up_count * devpriv->clock_ns != data[2] ||
4831 down_count * devpriv->clock_ns != data[4]) {
4832 data[2] = up_count * devpriv->clock_ns;
4833 data[4] = down_count * devpriv->clock_ns;
4834 return -EAGAIN;
4835 }
4836 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4837 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4838 M_Offset_Cal_PWM);
4839 devpriv->pwm_up_count = up_count;
4840 devpriv->pwm_down_count = down_count;
4841 return 5;
4842 break;
4843 case INSN_CONFIG_GET_PWM_OUTPUT:
4844 return ni_get_pwm_config(dev, data);
4845 break;
4846 default:
4847 return -EINVAL;
4848 break;
4849 }
4850 return 0;
4851 }
4852
4853 static int ni_6143_pwm_config(struct comedi_device *dev,
4854 struct comedi_subdevice *s,
4855 struct comedi_insn *insn, unsigned int *data)
4856 {
4857 struct ni_private *devpriv = dev->private;
4858 unsigned up_count, down_count;
4859
4860 switch (data[0]) {
4861 case INSN_CONFIG_PWM_OUTPUT:
4862 switch (data[1]) {
4863 case TRIG_ROUND_NEAREST:
4864 up_count =
4865 (data[2] +
4866 devpriv->clock_ns / 2) / devpriv->clock_ns;
4867 break;
4868 case TRIG_ROUND_DOWN:
4869 up_count = data[2] / devpriv->clock_ns;
4870 break;
4871 case TRIG_ROUND_UP:
4872 up_count =
4873 (data[2] + devpriv->clock_ns -
4874 1) / devpriv->clock_ns;
4875 break;
4876 default:
4877 return -EINVAL;
4878 break;
4879 }
4880 switch (data[3]) {
4881 case TRIG_ROUND_NEAREST:
4882 down_count =
4883 (data[4] +
4884 devpriv->clock_ns / 2) / devpriv->clock_ns;
4885 break;
4886 case TRIG_ROUND_DOWN:
4887 down_count = data[4] / devpriv->clock_ns;
4888 break;
4889 case TRIG_ROUND_UP:
4890 down_count =
4891 (data[4] + devpriv->clock_ns -
4892 1) / devpriv->clock_ns;
4893 break;
4894 default:
4895 return -EINVAL;
4896 break;
4897 }
4898 if (up_count * devpriv->clock_ns != data[2] ||
4899 down_count * devpriv->clock_ns != data[4]) {
4900 data[2] = up_count * devpriv->clock_ns;
4901 data[4] = down_count * devpriv->clock_ns;
4902 return -EAGAIN;
4903 }
4904 ni_writel(up_count, Calibration_HighTime_6143);
4905 devpriv->pwm_up_count = up_count;
4906 ni_writel(down_count, Calibration_LowTime_6143);
4907 devpriv->pwm_down_count = down_count;
4908 return 5;
4909 break;
4910 case INSN_CONFIG_GET_PWM_OUTPUT:
4911 return ni_get_pwm_config(dev, data);
4912 default:
4913 return -EINVAL;
4914 break;
4915 }
4916 return 0;
4917 }
4918
4919 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4920 /*
4921 calibration subdevice
4922 */
4923 static int ni_calib_insn_write(struct comedi_device *dev,
4924 struct comedi_subdevice *s,
4925 struct comedi_insn *insn, unsigned int *data)
4926 {
4927 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4928
4929 return 1;
4930 }
4931
4932 static int ni_calib_insn_read(struct comedi_device *dev,
4933 struct comedi_subdevice *s,
4934 struct comedi_insn *insn, unsigned int *data)
4935 {
4936 struct ni_private *devpriv = dev->private;
4937
4938 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4939
4940 return 1;
4941 }
4942
4943 static int pack_mb88341(int addr, int val, int *bitstring);
4944 static int pack_dac8800(int addr, int val, int *bitstring);
4945 static int pack_dac8043(int addr, int val, int *bitstring);
4946 static int pack_ad8522(int addr, int val, int *bitstring);
4947 static int pack_ad8804(int addr, int val, int *bitstring);
4948 static int pack_ad8842(int addr, int val, int *bitstring);
4949
4950 struct caldac_struct {
4951 int n_chans;
4952 int n_bits;
4953 int (*packbits) (int, int, int *);
4954 };
4955
4956 static struct caldac_struct caldacs[] = {
4957 [mb88341] = {12, 8, pack_mb88341},
4958 [dac8800] = {8, 8, pack_dac8800},
4959 [dac8043] = {1, 12, pack_dac8043},
4960 [ad8522] = {2, 12, pack_ad8522},
4961 [ad8804] = {12, 8, pack_ad8804},
4962 [ad8842] = {8, 8, pack_ad8842},
4963 [ad8804_debug] = {16, 8, pack_ad8804},
4964 };
4965
4966 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4967 {
4968 const struct ni_board_struct *board = comedi_board(dev);
4969 struct ni_private *devpriv = dev->private;
4970 int i, j;
4971 int n_dacs;
4972 int n_chans = 0;
4973 int n_bits;
4974 int diffbits = 0;
4975 int type;
4976 int chan;
4977
4978 type = board->caldac[0];
4979 if (type == caldac_none)
4980 return;
4981 n_bits = caldacs[type].n_bits;
4982 for (i = 0; i < 3; i++) {
4983 type = board->caldac[i];
4984 if (type == caldac_none)
4985 break;
4986 if (caldacs[type].n_bits != n_bits)
4987 diffbits = 1;
4988 n_chans += caldacs[type].n_chans;
4989 }
4990 n_dacs = i;
4991 s->n_chan = n_chans;
4992
4993 if (diffbits) {
4994 unsigned int *maxdata_list;
4995
4996 if (n_chans > MAX_N_CALDACS) {
4997 printk("BUG! MAX_N_CALDACS too small\n");
4998 }
4999 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5000 chan = 0;
5001 for (i = 0; i < n_dacs; i++) {
5002 type = board->caldac[i];
5003 for (j = 0; j < caldacs[type].n_chans; j++) {
5004 maxdata_list[chan] =
5005 (1 << caldacs[type].n_bits) - 1;
5006 chan++;
5007 }
5008 }
5009
5010 for (chan = 0; chan < s->n_chan; chan++)
5011 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5012 } else {
5013 type = board->caldac[0];
5014 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5015
5016 for (chan = 0; chan < s->n_chan; chan++)
5017 ni_write_caldac(dev, i, s->maxdata / 2);
5018 }
5019 }
5020
5021 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5022 {
5023 const struct ni_board_struct *board = comedi_board(dev);
5024 struct ni_private *devpriv = dev->private;
5025 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5026 int i;
5027 int type;
5028
5029 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5030 if (devpriv->caldacs[addr] == val)
5031 return;
5032 devpriv->caldacs[addr] = val;
5033
5034 for (i = 0; i < 3; i++) {
5035 type = board->caldac[i];
5036 if (type == caldac_none)
5037 break;
5038 if (addr < caldacs[type].n_chans) {
5039 bits = caldacs[type].packbits(addr, val, &bitstring);
5040 loadbit = SerDacLd(i);
5041 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5042 break;
5043 }
5044 addr -= caldacs[type].n_chans;
5045 }
5046
5047 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5048 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5049 udelay(1);
5050 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5051 udelay(1);
5052 }
5053 ni_writeb(loadbit, Serial_Command);
5054 udelay(1);
5055 ni_writeb(0, Serial_Command);
5056 }
5057
5058 static int pack_mb88341(int addr, int val, int *bitstring)
5059 {
5060 /*
5061 Fujitsu MB 88341
5062 Note that address bits are reversed. Thanks to
5063 Ingo Keen for noticing this.
5064
5065 Note also that the 88341 expects address values from
5066 1-12, whereas we use channel numbers 0-11. The NI
5067 docs use 1-12, also, so be careful here.
5068 */
5069 addr++;
5070 *bitstring = ((addr & 0x1) << 11) |
5071 ((addr & 0x2) << 9) |
5072 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5073 return 12;
5074 }
5075
5076 static int pack_dac8800(int addr, int val, int *bitstring)
5077 {
5078 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5079 return 11;
5080 }
5081
5082 static int pack_dac8043(int addr, int val, int *bitstring)
5083 {
5084 *bitstring = val & 0xfff;
5085 return 12;
5086 }
5087
5088 static int pack_ad8522(int addr, int val, int *bitstring)
5089 {
5090 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5091 return 16;
5092 }
5093
5094 static int pack_ad8804(int addr, int val, int *bitstring)
5095 {
5096 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5097 return 12;
5098 }
5099
5100 static int pack_ad8842(int addr, int val, int *bitstring)
5101 {
5102 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5103 return 12;
5104 }
5105
5106 #if 0
5107 /*
5108 * Read the GPCTs current value.
5109 */
5110 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5111 {
5112 unsigned int hi1, hi2, lo;
5113
5114 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5115 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5116 G_Command_Register(chan));
5117
5118 devpriv->gpct_command[chan] |= G_Save_Trace;
5119 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5120 G_Command_Register(chan));
5121
5122 /* This procedure is used because the two registers cannot
5123 * be read atomically. */
5124 do {
5125 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5126 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5127 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5128 } while (hi1 != hi2);
5129
5130 return (hi1 << 16) | lo;
5131 }
5132
5133 static void GPCT_Reset(struct comedi_device *dev, int chan)
5134 {
5135 int temp_ack_reg = 0;
5136
5137 /* printk("GPCT_Reset..."); */
5138 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5139
5140 switch (chan) {
5141 case 0:
5142 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5143 ni_set_bits(dev, Interrupt_A_Enable_Register,
5144 G0_TC_Interrupt_Enable, 0);
5145 ni_set_bits(dev, Interrupt_A_Enable_Register,
5146 G0_Gate_Interrupt_Enable, 0);
5147 temp_ack_reg |= G0_Gate_Error_Confirm;
5148 temp_ack_reg |= G0_TC_Error_Confirm;
5149 temp_ack_reg |= G0_TC_Interrupt_Ack;
5150 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5151 devpriv->stc_writew(dev, temp_ack_reg,
5152 Interrupt_A_Ack_Register);
5153
5154 /* problem...this interferes with the other ctr... */
5155 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5156 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5157 Analog_Trigger_Etc_Register);
5158 break;
5159 case 1:
5160 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5161 ni_set_bits(dev, Interrupt_B_Enable_Register,
5162 G1_TC_Interrupt_Enable, 0);
5163 ni_set_bits(dev, Interrupt_B_Enable_Register,
5164 G0_Gate_Interrupt_Enable, 0);
5165 temp_ack_reg |= G1_Gate_Error_Confirm;
5166 temp_ack_reg |= G1_TC_Error_Confirm;
5167 temp_ack_reg |= G1_TC_Interrupt_Ack;
5168 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5169 devpriv->stc_writew(dev, temp_ack_reg,
5170 Interrupt_B_Ack_Register);
5171
5172 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5173 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5174 Analog_Trigger_Etc_Register);
5175 break;
5176 }
5177
5178 devpriv->gpct_mode[chan] = 0;
5179 devpriv->gpct_input_select[chan] = 0;
5180 devpriv->gpct_command[chan] = 0;
5181
5182 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5183
5184 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5185 G_Mode_Register(chan));
5186 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5187 G_Input_Select_Register(chan));
5188 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5189
5190 /* printk("exit GPCT_Reset\n"); */
5191 }
5192
5193 #endif
5194
5195 static int ni_gpct_insn_config(struct comedi_device *dev,
5196 struct comedi_subdevice *s,
5197 struct comedi_insn *insn, unsigned int *data)
5198 {
5199 struct ni_gpct *counter = s->private;
5200 return ni_tio_insn_config(counter, insn, data);
5201 }
5202
5203 static int ni_gpct_insn_read(struct comedi_device *dev,
5204 struct comedi_subdevice *s,
5205 struct comedi_insn *insn, unsigned int *data)
5206 {
5207 struct ni_gpct *counter = s->private;
5208 return ni_tio_rinsn(counter, insn, data);
5209 }
5210
5211 static int ni_gpct_insn_write(struct comedi_device *dev,
5212 struct comedi_subdevice *s,
5213 struct comedi_insn *insn, unsigned int *data)
5214 {
5215 struct ni_gpct *counter = s->private;
5216 return ni_tio_winsn(counter, insn, data);
5217 }
5218
5219 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5220 {
5221 int retval;
5222 #ifdef PCIDMA
5223 struct ni_gpct *counter = s->private;
5224 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5225
5226 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5227 COMEDI_INPUT);
5228 if (retval) {
5229 comedi_error(dev,
5230 "no dma channel available for use by counter");
5231 return retval;
5232 }
5233 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5234 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5235 retval = ni_tio_cmd(counter, s->async);
5236 #else
5237 retval = -ENOTSUPP;
5238 #endif
5239 return retval;
5240 }
5241
5242 static int ni_gpct_cmdtest(struct comedi_device *dev,
5243 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5244 {
5245 #ifdef PCIDMA
5246 struct ni_gpct *counter = s->private;
5247
5248 return ni_tio_cmdtest(counter, cmd);
5249 #else
5250 return -ENOTSUPP;
5251 #endif
5252 }
5253
5254 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5255 {
5256 #ifdef PCIDMA
5257 struct ni_gpct *counter = s->private;
5258 int retval;
5259
5260 retval = ni_tio_cancel(counter);
5261 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5262 ni_release_gpct_mite_channel(dev, counter->counter_index);
5263 return retval;
5264 #else
5265 return 0;
5266 #endif
5267 }
5268
5269 /*
5270 *
5271 * Programmable Function Inputs
5272 *
5273 */
5274
5275 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5276 unsigned source)
5277 {
5278 struct ni_private *devpriv = dev->private;
5279 unsigned pfi_reg_index;
5280 unsigned array_offset;
5281
5282 if ((source & 0x1f) != source)
5283 return -EINVAL;
5284 pfi_reg_index = 1 + chan / 3;
5285 array_offset = pfi_reg_index - 1;
5286 devpriv->pfi_output_select_reg[array_offset] &=
5287 ~MSeries_PFI_Output_Select_Mask(chan);
5288 devpriv->pfi_output_select_reg[array_offset] |=
5289 MSeries_PFI_Output_Select_Bits(chan, source);
5290 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5291 M_Offset_PFI_Output_Select(pfi_reg_index));
5292 return 2;
5293 }
5294
5295 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5296 unsigned source)
5297 {
5298 /* pre-m-series boards have fixed signals on pfi pins */
5299 if (source != ni_old_get_pfi_routing(dev, chan))
5300 return -EINVAL;
5301 return 2;
5302 }
5303
5304 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5305 unsigned source)
5306 {
5307 const struct ni_board_struct *board = comedi_board(dev);
5308
5309 if (board->reg_type & ni_reg_m_series_mask)
5310 return ni_m_series_set_pfi_routing(dev, chan, source);
5311 else
5312 return ni_old_set_pfi_routing(dev, chan, source);
5313 }
5314
5315 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5316 unsigned chan)
5317 {
5318 struct ni_private *devpriv = dev->private;
5319 const unsigned array_offset = chan / 3;
5320
5321 return MSeries_PFI_Output_Select_Source(chan,
5322 devpriv->
5323 pfi_output_select_reg
5324 [array_offset]);
5325 }
5326
5327 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5328 {
5329 /* pre-m-series boards have fixed signals on pfi pins */
5330 switch (chan) {
5331 case 0:
5332 return NI_PFI_OUTPUT_AI_START1;
5333 break;
5334 case 1:
5335 return NI_PFI_OUTPUT_AI_START2;
5336 break;
5337 case 2:
5338 return NI_PFI_OUTPUT_AI_CONVERT;
5339 break;
5340 case 3:
5341 return NI_PFI_OUTPUT_G_SRC1;
5342 break;
5343 case 4:
5344 return NI_PFI_OUTPUT_G_GATE1;
5345 break;
5346 case 5:
5347 return NI_PFI_OUTPUT_AO_UPDATE_N;
5348 break;
5349 case 6:
5350 return NI_PFI_OUTPUT_AO_START1;
5351 break;
5352 case 7:
5353 return NI_PFI_OUTPUT_AI_START_PULSE;
5354 break;
5355 case 8:
5356 return NI_PFI_OUTPUT_G_SRC0;
5357 break;
5358 case 9:
5359 return NI_PFI_OUTPUT_G_GATE0;
5360 break;
5361 default:
5362 printk("%s: bug, unhandled case in switch.\n", __func__);
5363 break;
5364 }
5365 return 0;
5366 }
5367
5368 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5369 {
5370 const struct ni_board_struct *board = comedi_board(dev);
5371
5372 if (board->reg_type & ni_reg_m_series_mask)
5373 return ni_m_series_get_pfi_routing(dev, chan);
5374 else
5375 return ni_old_get_pfi_routing(dev, chan);
5376 }
5377
5378 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5379 enum ni_pfi_filter_select filter)
5380 {
5381 const struct ni_board_struct *board = comedi_board(dev);
5382 struct ni_private *devpriv __maybe_unused = dev->private;
5383 unsigned bits;
5384
5385 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5386 return -ENOTSUPP;
5387 }
5388 bits = ni_readl(M_Offset_PFI_Filter);
5389 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5390 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5391 ni_writel(bits, M_Offset_PFI_Filter);
5392 return 0;
5393 }
5394
5395 static int ni_pfi_insn_bits(struct comedi_device *dev,
5396 struct comedi_subdevice *s,
5397 struct comedi_insn *insn, unsigned int *data)
5398 {
5399 const struct ni_board_struct *board = comedi_board(dev);
5400 struct ni_private *devpriv __maybe_unused = dev->private;
5401
5402 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5403 return -ENOTSUPP;
5404 }
5405 if (data[0]) {
5406 s->state &= ~data[0];
5407 s->state |= (data[0] & data[1]);
5408 ni_writew(s->state, M_Offset_PFI_DO);
5409 }
5410 data[1] = ni_readw(M_Offset_PFI_DI);
5411 return insn->n;
5412 }
5413
5414 static int ni_pfi_insn_config(struct comedi_device *dev,
5415 struct comedi_subdevice *s,
5416 struct comedi_insn *insn, unsigned int *data)
5417 {
5418 struct ni_private *devpriv = dev->private;
5419 unsigned int chan;
5420
5421 if (insn->n < 1)
5422 return -EINVAL;
5423
5424 chan = CR_CHAN(insn->chanspec);
5425
5426 switch (data[0]) {
5427 case COMEDI_OUTPUT:
5428 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5429 break;
5430 case COMEDI_INPUT:
5431 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5432 break;
5433 case INSN_CONFIG_DIO_QUERY:
5434 data[1] =
5435 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5436 COMEDI_OUTPUT : COMEDI_INPUT;
5437 return 0;
5438 break;
5439 case INSN_CONFIG_SET_ROUTING:
5440 return ni_set_pfi_routing(dev, chan, data[1]);
5441 break;
5442 case INSN_CONFIG_GET_ROUTING:
5443 data[1] = ni_get_pfi_routing(dev, chan);
5444 break;
5445 case INSN_CONFIG_FILTER:
5446 return ni_config_filter(dev, chan, data[1]);
5447 break;
5448 default:
5449 return -EINVAL;
5450 }
5451 return 0;
5452 }
5453
5454 /*
5455 *
5456 * NI RTSI Bus Functions
5457 *
5458 */
5459 static void ni_rtsi_init(struct comedi_device *dev)
5460 {
5461 const struct ni_board_struct *board = comedi_board(dev);
5462 struct ni_private *devpriv = dev->private;
5463
5464 /* Initialises the RTSI bus signal switch to a default state */
5465
5466 /* Set clock mode to internal */
5467 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5468 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5469 printk("ni_set_master_clock failed, bug?");
5470 }
5471 /* default internal lines routing to RTSI bus lines */
5472 devpriv->rtsi_trig_a_output_reg =
5473 RTSI_Trig_Output_Bits(0,
5474 NI_RTSI_OUTPUT_ADR_START1) |
5475 RTSI_Trig_Output_Bits(1,
5476 NI_RTSI_OUTPUT_ADR_START2) |
5477 RTSI_Trig_Output_Bits(2,
5478 NI_RTSI_OUTPUT_SCLKG) |
5479 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5480 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5481 RTSI_Trig_A_Output_Register);
5482 devpriv->rtsi_trig_b_output_reg =
5483 RTSI_Trig_Output_Bits(4,
5484 NI_RTSI_OUTPUT_DA_START1) |
5485 RTSI_Trig_Output_Bits(5,
5486 NI_RTSI_OUTPUT_G_SRC0) |
5487 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5488 if (board->reg_type & ni_reg_m_series_mask)
5489 devpriv->rtsi_trig_b_output_reg |=
5490 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5491 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5492 RTSI_Trig_B_Output_Register);
5493
5494 /*
5495 * Sets the source and direction of the 4 on board lines
5496 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5497 */
5498 }
5499
5500 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5501 struct comedi_subdevice *s,
5502 struct comedi_insn *insn, unsigned int *data)
5503 {
5504 data[1] = 0;
5505
5506 return insn->n;
5507 }
5508
5509 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5510 * given an arbitrary frequency input clock */
5511 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5512 unsigned *freq_divider,
5513 unsigned *freq_multiplier,
5514 unsigned *actual_period_ns)
5515 {
5516 unsigned div;
5517 unsigned best_div = 1;
5518 static const unsigned max_div = 0x10;
5519 unsigned mult;
5520 unsigned best_mult = 1;
5521 static const unsigned max_mult = 0x100;
5522 static const unsigned pico_per_nano = 1000;
5523
5524 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5525 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5526 * 20 MHz for most timing clocks */
5527 static const unsigned target_picosec = 12500;
5528 static const unsigned fudge_factor_80_to_20Mhz = 4;
5529 int best_period_picosec = 0;
5530 for (div = 1; div <= max_div; ++div) {
5531 for (mult = 1; mult <= max_mult; ++mult) {
5532 unsigned new_period_ps =
5533 (reference_picosec * div) / mult;
5534 if (abs(new_period_ps - target_picosec) <
5535 abs(best_period_picosec - target_picosec)) {
5536 best_period_picosec = new_period_ps;
5537 best_div = div;
5538 best_mult = mult;
5539 }
5540 }
5541 }
5542 if (best_period_picosec == 0) {
5543 printk("%s: bug, failed to find pll parameters\n", __func__);
5544 return -EIO;
5545 }
5546 *freq_divider = best_div;
5547 *freq_multiplier = best_mult;
5548 *actual_period_ns =
5549 (best_period_picosec * fudge_factor_80_to_20Mhz +
5550 (pico_per_nano / 2)) / pico_per_nano;
5551 return 0;
5552 }
5553
5554 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5555 {
5556 const struct ni_board_struct *board = comedi_board(dev);
5557
5558 if (board->reg_type & ni_reg_m_series_mask)
5559 return 8;
5560 else
5561 return 7;
5562 }
5563
5564 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5565 unsigned source, unsigned period_ns)
5566 {
5567 struct ni_private *devpriv = dev->private;
5568 static const unsigned min_period_ns = 50;
5569 static const unsigned max_period_ns = 1000;
5570 static const unsigned timeout = 1000;
5571 unsigned pll_control_bits;
5572 unsigned freq_divider;
5573 unsigned freq_multiplier;
5574 unsigned i;
5575 int retval;
5576
5577 if (source == NI_MIO_PLL_PXI10_CLOCK)
5578 period_ns = 100;
5579 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5580 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5581 printk
5582 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5583 "for the phased-lock loop.\n", __func__,
5584 min_period_ns, max_period_ns);
5585 return -EINVAL;
5586 }
5587 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5588 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5589 RTSI_Trig_Direction_Register);
5590 pll_control_bits =
5591 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5592 devpriv->clock_and_fout2 |=
5593 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5594 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5595 switch (source) {
5596 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5597 devpriv->clock_and_fout2 |=
5598 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5599 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5600 &freq_multiplier,
5601 &devpriv->clock_ns);
5602 if (retval < 0)
5603 return retval;
5604 break;
5605 case NI_MIO_PLL_PXI10_CLOCK:
5606 /* pxi clock is 10MHz */
5607 devpriv->clock_and_fout2 |=
5608 MSeries_PLL_In_Source_Select_PXI_Clock10;
5609 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5610 &freq_multiplier,
5611 &devpriv->clock_ns);
5612 if (retval < 0)
5613 return retval;
5614 break;
5615 default:
5616 {
5617 unsigned rtsi_channel;
5618 static const unsigned max_rtsi_channel = 7;
5619 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5620 ++rtsi_channel) {
5621 if (source ==
5622 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5623 devpriv->clock_and_fout2 |=
5624 MSeries_PLL_In_Source_Select_RTSI_Bits
5625 (rtsi_channel);
5626 break;
5627 }
5628 }
5629 if (rtsi_channel > max_rtsi_channel)
5630 return -EINVAL;
5631 retval = ni_mseries_get_pll_parameters(period_ns,
5632 &freq_divider,
5633 &freq_multiplier,
5634 &devpriv->
5635 clock_ns);
5636 if (retval < 0)
5637 return retval;
5638 }
5639 break;
5640 }
5641 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5642 pll_control_bits |=
5643 MSeries_PLL_Divisor_Bits(freq_divider) |
5644 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5645
5646 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5647 * freq_divider, freq_multiplier, pll_control_bits); */
5648 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5649 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5650 devpriv->clock_source = source;
5651 /* it seems to typically take a few hundred microseconds for PLL to lock */
5652 for (i = 0; i < timeout; ++i) {
5653 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5654 break;
5655 }
5656 udelay(1);
5657 }
5658 if (i == timeout) {
5659 printk
5660 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5661 __func__, source, period_ns);
5662 return -ETIMEDOUT;
5663 }
5664 return 3;
5665 }
5666
5667 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5668 unsigned period_ns)
5669 {
5670 const struct ni_board_struct *board = comedi_board(dev);
5671 struct ni_private *devpriv = dev->private;
5672
5673 if (source == NI_MIO_INTERNAL_CLOCK) {
5674 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5675 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5676 RTSI_Trig_Direction_Register);
5677 devpriv->clock_ns = TIMEBASE_1_NS;
5678 if (board->reg_type & ni_reg_m_series_mask) {
5679 devpriv->clock_and_fout2 &=
5680 ~(MSeries_Timebase1_Select_Bit |
5681 MSeries_Timebase3_Select_Bit);
5682 ni_writew(devpriv->clock_and_fout2,
5683 M_Offset_Clock_and_Fout2);
5684 ni_writew(0, M_Offset_PLL_Control);
5685 }
5686 devpriv->clock_source = source;
5687 } else {
5688 if (board->reg_type & ni_reg_m_series_mask) {
5689 return ni_mseries_set_pll_master_clock(dev, source,
5690 period_ns);
5691 } else {
5692 if (source == NI_MIO_RTSI_CLOCK) {
5693 devpriv->rtsi_trig_direction_reg |=
5694 Use_RTSI_Clock_Bit;
5695 devpriv->stc_writew(dev,
5696 devpriv->
5697 rtsi_trig_direction_reg,
5698 RTSI_Trig_Direction_Register);
5699 if (period_ns == 0) {
5700 printk
5701 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5702 __func__);
5703 return -EINVAL;
5704 } else {
5705 devpriv->clock_ns = period_ns;
5706 }
5707 devpriv->clock_source = source;
5708 } else
5709 return -EINVAL;
5710 }
5711 }
5712 return 3;
5713 }
5714
5715 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5716 unsigned source)
5717 {
5718 const struct ni_board_struct *board = comedi_board(dev);
5719
5720 if (chan >= num_configurable_rtsi_channels(dev)) {
5721 if (chan == old_RTSI_clock_channel) {
5722 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5723 return 1;
5724 else {
5725 printk
5726 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5727 __func__, chan, old_RTSI_clock_channel);
5728 return 0;
5729 }
5730 }
5731 return 0;
5732 }
5733 switch (source) {
5734 case NI_RTSI_OUTPUT_ADR_START1:
5735 case NI_RTSI_OUTPUT_ADR_START2:
5736 case NI_RTSI_OUTPUT_SCLKG:
5737 case NI_RTSI_OUTPUT_DACUPDN:
5738 case NI_RTSI_OUTPUT_DA_START1:
5739 case NI_RTSI_OUTPUT_G_SRC0:
5740 case NI_RTSI_OUTPUT_G_GATE0:
5741 case NI_RTSI_OUTPUT_RGOUT0:
5742 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5743 return 1;
5744 break;
5745 case NI_RTSI_OUTPUT_RTSI_OSC:
5746 if (board->reg_type & ni_reg_m_series_mask)
5747 return 1;
5748 else
5749 return 0;
5750 break;
5751 default:
5752 return 0;
5753 break;
5754 }
5755 }
5756
5757 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5758 unsigned source)
5759 {
5760 struct ni_private *devpriv = dev->private;
5761
5762 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5763 return -EINVAL;
5764 if (chan < 4) {
5765 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5766 devpriv->rtsi_trig_a_output_reg |=
5767 RTSI_Trig_Output_Bits(chan, source);
5768 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5769 RTSI_Trig_A_Output_Register);
5770 } else if (chan < 8) {
5771 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5772 devpriv->rtsi_trig_b_output_reg |=
5773 RTSI_Trig_Output_Bits(chan, source);
5774 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5775 RTSI_Trig_B_Output_Register);
5776 }
5777 return 2;
5778 }
5779
5780 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5781 {
5782 struct ni_private *devpriv = dev->private;
5783
5784 if (chan < 4) {
5785 return RTSI_Trig_Output_Source(chan,
5786 devpriv->rtsi_trig_a_output_reg);
5787 } else if (chan < num_configurable_rtsi_channels(dev)) {
5788 return RTSI_Trig_Output_Source(chan,
5789 devpriv->rtsi_trig_b_output_reg);
5790 } else {
5791 if (chan == old_RTSI_clock_channel)
5792 return NI_RTSI_OUTPUT_RTSI_OSC;
5793 printk("%s: bug! should never get here?\n", __func__);
5794 return 0;
5795 }
5796 }
5797
5798 static int ni_rtsi_insn_config(struct comedi_device *dev,
5799 struct comedi_subdevice *s,
5800 struct comedi_insn *insn, unsigned int *data)
5801 {
5802 const struct ni_board_struct *board = comedi_board(dev);
5803 struct ni_private *devpriv = dev->private;
5804 unsigned int chan = CR_CHAN(insn->chanspec);
5805
5806 switch (data[0]) {
5807 case INSN_CONFIG_DIO_OUTPUT:
5808 if (chan < num_configurable_rtsi_channels(dev)) {
5809 devpriv->rtsi_trig_direction_reg |=
5810 RTSI_Output_Bit(chan,
5811 (board->reg_type & ni_reg_m_series_mask) != 0);
5812 } else if (chan == old_RTSI_clock_channel) {
5813 devpriv->rtsi_trig_direction_reg |=
5814 Drive_RTSI_Clock_Bit;
5815 }
5816 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5817 RTSI_Trig_Direction_Register);
5818 break;
5819 case INSN_CONFIG_DIO_INPUT:
5820 if (chan < num_configurable_rtsi_channels(dev)) {
5821 devpriv->rtsi_trig_direction_reg &=
5822 ~RTSI_Output_Bit(chan,
5823 (board->reg_type & ni_reg_m_series_mask) != 0);
5824 } else if (chan == old_RTSI_clock_channel) {
5825 devpriv->rtsi_trig_direction_reg &=
5826 ~Drive_RTSI_Clock_Bit;
5827 }
5828 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5829 RTSI_Trig_Direction_Register);
5830 break;
5831 case INSN_CONFIG_DIO_QUERY:
5832 if (chan < num_configurable_rtsi_channels(dev)) {
5833 data[1] =
5834 (devpriv->rtsi_trig_direction_reg &
5835 RTSI_Output_Bit(chan,
5836 (board->reg_type & ni_reg_m_series_mask) != 0))
5837 ? INSN_CONFIG_DIO_OUTPUT
5838 : INSN_CONFIG_DIO_INPUT;
5839 } else if (chan == old_RTSI_clock_channel) {
5840 data[1] =
5841 (devpriv->rtsi_trig_direction_reg &
5842 Drive_RTSI_Clock_Bit)
5843 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5844 }
5845 return 2;
5846 break;
5847 case INSN_CONFIG_SET_CLOCK_SRC:
5848 return ni_set_master_clock(dev, data[1], data[2]);
5849 break;
5850 case INSN_CONFIG_GET_CLOCK_SRC:
5851 data[1] = devpriv->clock_source;
5852 data[2] = devpriv->clock_ns;
5853 return 3;
5854 break;
5855 case INSN_CONFIG_SET_ROUTING:
5856 return ni_set_rtsi_routing(dev, chan, data[1]);
5857 break;
5858 case INSN_CONFIG_GET_ROUTING:
5859 data[1] = ni_get_rtsi_routing(dev, chan);
5860 return 2;
5861 break;
5862 default:
5863 return -EINVAL;
5864 break;
5865 }
5866 return 1;
5867 }
5868
5869 static int cs5529_wait_for_idle(struct comedi_device *dev)
5870 {
5871 unsigned short status;
5872 const int timeout = HZ;
5873 int i;
5874
5875 for (i = 0; i < timeout; i++) {
5876 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5877 if ((status & CSS_ADC_BUSY) == 0) {
5878 break;
5879 }
5880 set_current_state(TASK_INTERRUPTIBLE);
5881 if (schedule_timeout(1)) {
5882 return -EIO;
5883 }
5884 }
5885 /* printk("looped %i times waiting for idle\n", i); */
5886 if (i == timeout) {
5887 printk("%s: %s: timeout\n", __FILE__, __func__);
5888 return -ETIME;
5889 }
5890 return 0;
5891 }
5892
5893 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5894 {
5895 static const int timeout = 100;
5896 int i;
5897
5898 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5899 /* give time for command to start being serially clocked into cs5529.
5900 * this insures that the CSS_ADC_BUSY bit will get properly
5901 * set before we exit this function.
5902 */
5903 for (i = 0; i < timeout; i++) {
5904 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5905 break;
5906 udelay(1);
5907 }
5908 /* printk("looped %i times writing command to cs5529\n", i); */
5909 if (i == timeout) {
5910 comedi_error(dev, "possible problem - never saw adc go busy?");
5911 }
5912 }
5913
5914 /* write to cs5529 register */
5915 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5916 unsigned int reg_select_bits)
5917 {
5918 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5919 CAL_ADC_Config_Data_High_Word_67xx);
5920 ni_ao_win_outw(dev, (value & 0xffff),
5921 CAL_ADC_Config_Data_Low_Word_67xx);
5922 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5923 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5924 if (cs5529_wait_for_idle(dev))
5925 comedi_error(dev, "time or signal in cs5529_config_write()");
5926 }
5927
5928 #ifdef NI_CS5529_DEBUG
5929 /* read from cs5529 register */
5930 static unsigned int cs5529_config_read(struct comedi_device *dev,
5931 unsigned int reg_select_bits)
5932 {
5933 unsigned int value;
5934
5935 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5936 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5937 if (cs5529_wait_for_idle(dev))
5938 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5939 value = (ni_ao_win_inw(dev,
5940 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5941 0xff0000;
5942 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5943 return value;
5944 }
5945 #endif
5946
5947 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5948 {
5949 int retval;
5950 unsigned short status;
5951
5952 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5953 retval = cs5529_wait_for_idle(dev);
5954 if (retval) {
5955 comedi_error(dev,
5956 "timeout or signal in cs5529_do_conversion()");
5957 return -ETIME;
5958 }
5959 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5960 if (status & CSS_OSC_DETECT) {
5961 printk
5962 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5963 return -EIO;
5964 }
5965 if (status & CSS_OVERRANGE) {
5966 printk
5967 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5968 }
5969 if (data) {
5970 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5971 /* cs5529 returns 16 bit signed data in bipolar mode */
5972 *data ^= (1 << 15);
5973 }
5974 return 0;
5975 }
5976
5977 static int cs5529_ai_insn_read(struct comedi_device *dev,
5978 struct comedi_subdevice *s,
5979 struct comedi_insn *insn, unsigned int *data)
5980 {
5981 int n, retval;
5982 unsigned short sample;
5983 unsigned int channel_select;
5984 const unsigned int INTERNAL_REF = 0x1000;
5985
5986 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5987 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5988 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5989 if (insn->chanspec & CR_ALT_SOURCE)
5990 channel_select = INTERNAL_REF;
5991 else
5992 channel_select = CR_CHAN(insn->chanspec);
5993 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5994
5995 for (n = 0; n < insn->n; n++) {
5996 retval = cs5529_do_conversion(dev, &sample);
5997 if (retval < 0)
5998 return retval;
5999 data[n] = sample;
6000 }
6001 return insn->n;
6002 }
6003
6004 static int init_cs5529(struct comedi_device *dev)
6005 {
6006 unsigned int config_bits =
6007 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6008
6009 #if 1
6010 /* do self-calibration */
6011 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6012 CSCMD_CONFIG_REGISTER);
6013 /* need to force a conversion for calibration to run */
6014 cs5529_do_conversion(dev, NULL);
6015 #else
6016 /* force gain calibration to 1 */
6017 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6018 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6019 CSCMD_CONFIG_REGISTER);
6020 if (cs5529_wait_for_idle(dev))
6021 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6022 #endif
6023 #ifdef NI_CS5529_DEBUG
6024 printk("config: 0x%x\n", cs5529_config_read(dev,
6025 CSCMD_CONFIG_REGISTER));
6026 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6027 printk("offset: 0x%x\n", cs5529_config_read(dev,
6028 CSCMD_OFFSET_REGISTER));
6029 #endif
6030 return 0;
6031 }
kernel source for telekom puls (alcatel/mediatek)