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Merge tag 'mxs-fixes-3.10' of git://git.linaro.org/people/shawnguo/linux-2.6 into...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / comedi / drivers / ni_mio_common.c
1 /*
2 comedi/drivers/ni_mio_common.c
3 Hardware driver for DAQ-STC based boards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23 */
24
25 /*
26 This file is meant to be included by another file, e.g.,
27 ni_atmio.c or ni_pcimio.c.
28
29 Interrupt support originally added by Truxton Fulton
30 <trux@truxton.com>
31
32 References (from ftp://ftp.natinst.com/support/manuals):
33
34 340747b.pdf AT-MIO E series Register Level Programmer Manual
35 341079b.pdf PCI E Series RLPM
36 340934b.pdf DAQ-STC reference manual
37 67xx and 611x registers (from ftp://ftp.ni.com/support/daq/mhddk/documentation/)
38 release_ni611x.pdf
39 release_ni67xx.pdf
40 Other possibly relevant info:
41
42 320517c.pdf User manual (obsolete)
43 320517f.pdf User manual (new)
44 320889a.pdf delete
45 320906c.pdf maximum signal ratings
46 321066a.pdf about 16x
47 321791a.pdf discontinuation of at-mio-16e-10 rev. c
48 321808a.pdf about at-mio-16e-10 rev P
49 321837a.pdf discontinuation of at-mio-16de-10 rev d
50 321838a.pdf about at-mio-16de-10 rev N
51
52 ISSUES:
53
54 - the interrupt routine needs to be cleaned up
55
56 2006-02-07: S-Series PCI-6143: Support has been added but is not
57 fully tested as yet. Terry Barnaby, BEAM Ltd.
58 */
59
60 /* #define DEBUG_INTERRUPT */
61 /* #define DEBUG_STATUS_A */
62 /* #define DEBUG_STATUS_B */
63
64 #include <linux/interrupt.h>
65 #include <linux/sched.h>
66 #include "8255.h"
67 #include "mite.h"
68 #include "comedi_fc.h"
69
70 #ifndef MDPRINTK
71 #define MDPRINTK(format, args...)
72 #endif
73
74 /* A timeout count */
75 #define NI_TIMEOUT 1000
76 static const unsigned old_RTSI_clock_channel = 7;
77
78 /* Note: this table must match the ai_gain_* definitions */
79 static const short ni_gainlkup[][16] = {
80 [ai_gain_16] = {0, 1, 2, 3, 4, 5, 6, 7,
81 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
82 [ai_gain_8] = {1, 2, 4, 7, 0x101, 0x102, 0x104, 0x107},
83 [ai_gain_14] = {1, 2, 3, 4, 5, 6, 7,
84 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107},
85 [ai_gain_4] = {0, 1, 4, 7},
86 [ai_gain_611x] = {0x00a, 0x00b, 0x001, 0x002,
87 0x003, 0x004, 0x005, 0x006},
88 [ai_gain_622x] = {0, 1, 4, 5},
89 [ai_gain_628x] = {1, 2, 3, 4, 5, 6, 7},
90 [ai_gain_6143] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
91 };
92
93 static const struct comedi_lrange range_ni_E_ai = { 16, {
94 RANGE(-10, 10),
95 RANGE(-5, 5),
96 RANGE(-2.5, 2.5),
97 RANGE(-1, 1),
98 RANGE(-0.5, 0.5),
99 RANGE(-0.25, 0.25),
100 RANGE(-0.1, 0.1),
101 RANGE(-0.05, 0.05),
102 RANGE(0, 20),
103 RANGE(0, 10),
104 RANGE(0, 5),
105 RANGE(0, 2),
106 RANGE(0, 1),
107 RANGE(0, 0.5),
108 RANGE(0, 0.2),
109 RANGE(0, 0.1),
110 }
111 };
112
113 static const struct comedi_lrange range_ni_E_ai_limited = { 8, {
114 RANGE(-10, 10),
115 RANGE(-5, 5),
116 RANGE(-1, 1),
117 RANGE(-0.1,
118 0.1),
119 RANGE(0, 10),
120 RANGE(0, 5),
121 RANGE(0, 1),
122 RANGE(0, 0.1),
123 }
124 };
125
126 static const struct comedi_lrange range_ni_E_ai_limited14 = { 14, {
127 RANGE(-10,
128 10),
129 RANGE(-5, 5),
130 RANGE(-2, 2),
131 RANGE(-1, 1),
132 RANGE(-0.5,
133 0.5),
134 RANGE(-0.2,
135 0.2),
136 RANGE(-0.1,
137 0.1),
138 RANGE(0, 10),
139 RANGE(0, 5),
140 RANGE(0, 2),
141 RANGE(0, 1),
142 RANGE(0,
143 0.5),
144 RANGE(0,
145 0.2),
146 RANGE(0,
147 0.1),
148 }
149 };
150
151 static const struct comedi_lrange range_ni_E_ai_bipolar4 = { 4, {
152 RANGE(-10, 10),
153 RANGE(-5, 5),
154 RANGE(-0.5,
155 0.5),
156 RANGE(-0.05,
157 0.05),
158 }
159 };
160
161 static const struct comedi_lrange range_ni_E_ai_611x = { 8, {
162 RANGE(-50, 50),
163 RANGE(-20, 20),
164 RANGE(-10, 10),
165 RANGE(-5, 5),
166 RANGE(-2, 2),
167 RANGE(-1, 1),
168 RANGE(-0.5, 0.5),
169 RANGE(-0.2, 0.2),
170 }
171 };
172
173 static const struct comedi_lrange range_ni_M_ai_622x = { 4, {
174 RANGE(-10, 10),
175 RANGE(-5, 5),
176 RANGE(-1, 1),
177 RANGE(-0.2, 0.2),
178 }
179 };
180
181 static const struct comedi_lrange range_ni_M_ai_628x = { 7, {
182 RANGE(-10, 10),
183 RANGE(-5, 5),
184 RANGE(-2, 2),
185 RANGE(-1, 1),
186 RANGE(-0.5, 0.5),
187 RANGE(-0.2, 0.2),
188 RANGE(-0.1, 0.1),
189 }
190 };
191
192 static const struct comedi_lrange range_ni_E_ao_ext = { 4, {
193 RANGE(-10, 10),
194 RANGE(0, 10),
195 RANGE_ext(-1, 1),
196 RANGE_ext(0, 1),
197 }
198 };
199
200 static const struct comedi_lrange *const ni_range_lkup[] = {
201 [ai_gain_16] = &range_ni_E_ai,
202 [ai_gain_8] = &range_ni_E_ai_limited,
203 [ai_gain_14] = &range_ni_E_ai_limited14,
204 [ai_gain_4] = &range_ni_E_ai_bipolar4,
205 [ai_gain_611x] = &range_ni_E_ai_611x,
206 [ai_gain_622x] = &range_ni_M_ai_622x,
207 [ai_gain_628x] = &range_ni_M_ai_628x,
208 [ai_gain_6143] = &range_bipolar5
209 };
210
211 static int ni_dio_insn_config(struct comedi_device *dev,
212 struct comedi_subdevice *s,
213 struct comedi_insn *insn, unsigned int *data);
214 static int ni_dio_insn_bits(struct comedi_device *dev,
215 struct comedi_subdevice *s,
216 struct comedi_insn *insn, unsigned int *data);
217 static int ni_cdio_cmdtest(struct comedi_device *dev,
218 struct comedi_subdevice *s, struct comedi_cmd *cmd);
219 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
220 static int ni_cdio_cancel(struct comedi_device *dev,
221 struct comedi_subdevice *s);
222 static void handle_cdio_interrupt(struct comedi_device *dev);
223 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
224 unsigned int trignum);
225
226 static int ni_serial_insn_config(struct comedi_device *dev,
227 struct comedi_subdevice *s,
228 struct comedi_insn *insn, unsigned int *data);
229 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
230 struct comedi_subdevice *s,
231 unsigned char data_out,
232 unsigned char *data_in);
233 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 unsigned char data_out,
236 unsigned char *data_in);
237
238 static int ni_calib_insn_read(struct comedi_device *dev,
239 struct comedi_subdevice *s,
240 struct comedi_insn *insn, unsigned int *data);
241 static int ni_calib_insn_write(struct comedi_device *dev,
242 struct comedi_subdevice *s,
243 struct comedi_insn *insn, unsigned int *data);
244
245 static int ni_eeprom_insn_read(struct comedi_device *dev,
246 struct comedi_subdevice *s,
247 struct comedi_insn *insn, unsigned int *data);
248 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
249 struct comedi_subdevice *s,
250 struct comedi_insn *insn,
251 unsigned int *data);
252
253 static int ni_pfi_insn_bits(struct comedi_device *dev,
254 struct comedi_subdevice *s,
255 struct comedi_insn *insn, unsigned int *data);
256 static int ni_pfi_insn_config(struct comedi_device *dev,
257 struct comedi_subdevice *s,
258 struct comedi_insn *insn, unsigned int *data);
259 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev,
260 unsigned chan);
261
262 static void ni_rtsi_init(struct comedi_device *dev);
263 static int ni_rtsi_insn_bits(struct comedi_device *dev,
264 struct comedi_subdevice *s,
265 struct comedi_insn *insn, unsigned int *data);
266 static int ni_rtsi_insn_config(struct comedi_device *dev,
267 struct comedi_subdevice *s,
268 struct comedi_insn *insn, unsigned int *data);
269
270 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s);
271 static int ni_read_eeprom(struct comedi_device *dev, int addr);
272
273 #ifdef DEBUG_STATUS_A
274 static void ni_mio_print_status_a(int status);
275 #else
276 #define ni_mio_print_status_a(a)
277 #endif
278 #ifdef DEBUG_STATUS_B
279 static void ni_mio_print_status_b(int status);
280 #else
281 #define ni_mio_print_status_b(a)
282 #endif
283
284 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s);
285 #ifndef PCIDMA
286 static void ni_handle_fifo_half_full(struct comedi_device *dev);
287 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
288 struct comedi_subdevice *s);
289 #endif
290 static void ni_handle_fifo_dregs(struct comedi_device *dev);
291 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
292 unsigned int trignum);
293 static void ni_load_channelgain_list(struct comedi_device *dev,
294 unsigned int n_chan, unsigned int *list);
295 static void shutdown_ai_command(struct comedi_device *dev);
296
297 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
298 unsigned int trignum);
299
300 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s);
301
302 static int ni_8255_callback(int dir, int port, int data, unsigned long arg);
303
304 static int ni_gpct_insn_write(struct comedi_device *dev,
305 struct comedi_subdevice *s,
306 struct comedi_insn *insn, unsigned int *data);
307 static int ni_gpct_insn_read(struct comedi_device *dev,
308 struct comedi_subdevice *s,
309 struct comedi_insn *insn, unsigned int *data);
310 static int ni_gpct_insn_config(struct comedi_device *dev,
311 struct comedi_subdevice *s,
312 struct comedi_insn *insn, unsigned int *data);
313 #ifdef PCIDMA
314 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
315 static int ni_gpct_cmdtest(struct comedi_device *dev,
316 struct comedi_subdevice *s, struct comedi_cmd *cmd);
317 #endif
318 static int ni_gpct_cancel(struct comedi_device *dev,
319 struct comedi_subdevice *s);
320 static void handle_gpct_interrupt(struct comedi_device *dev,
321 unsigned short counter_index);
322
323 static int init_cs5529(struct comedi_device *dev);
324 static int cs5529_do_conversion(struct comedi_device *dev,
325 unsigned short *data);
326 static int cs5529_ai_insn_read(struct comedi_device *dev,
327 struct comedi_subdevice *s,
328 struct comedi_insn *insn, unsigned int *data);
329 #ifdef NI_CS5529_DEBUG
330 static unsigned int cs5529_config_read(struct comedi_device *dev,
331 unsigned int reg_select_bits);
332 #endif
333 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
334 unsigned int reg_select_bits);
335
336 static int ni_m_series_pwm_config(struct comedi_device *dev,
337 struct comedi_subdevice *s,
338 struct comedi_insn *insn, unsigned int *data);
339 static int ni_6143_pwm_config(struct comedi_device *dev,
340 struct comedi_subdevice *s,
341 struct comedi_insn *insn, unsigned int *data);
342
343 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
344 unsigned period_ns);
345 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status);
346 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status);
347
348 enum aimodes {
349 AIMODE_NONE = 0,
350 AIMODE_HALF_FULL = 1,
351 AIMODE_SCAN = 2,
352 AIMODE_SAMPLE = 3,
353 };
354
355 enum ni_common_subdevices {
356 NI_AI_SUBDEV,
357 NI_AO_SUBDEV,
358 NI_DIO_SUBDEV,
359 NI_8255_DIO_SUBDEV,
360 NI_UNUSED_SUBDEV,
361 NI_CALIBRATION_SUBDEV,
362 NI_EEPROM_SUBDEV,
363 NI_PFI_DIO_SUBDEV,
364 NI_CS5529_CALIBRATION_SUBDEV,
365 NI_SERIAL_SUBDEV,
366 NI_RTSI_SUBDEV,
367 NI_GPCT0_SUBDEV,
368 NI_GPCT1_SUBDEV,
369 NI_FREQ_OUT_SUBDEV,
370 NI_NUM_SUBDEVICES
371 };
372 static inline unsigned NI_GPCT_SUBDEV(unsigned counter_index)
373 {
374 switch (counter_index) {
375 case 0:
376 return NI_GPCT0_SUBDEV;
377 break;
378 case 1:
379 return NI_GPCT1_SUBDEV;
380 break;
381 default:
382 break;
383 }
384 BUG();
385 return NI_GPCT0_SUBDEV;
386 }
387
388 enum timebase_nanoseconds {
389 TIMEBASE_1_NS = 50,
390 TIMEBASE_2_NS = 10000
391 };
392
393 #define SERIAL_DISABLED 0
394 #define SERIAL_600NS 600
395 #define SERIAL_1_2US 1200
396 #define SERIAL_10US 10000
397
398 static const int num_adc_stages_611x = 3;
399
400 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
401 unsigned ai_mite_status);
402 static void handle_b_interrupt(struct comedi_device *dev, unsigned short status,
403 unsigned ao_mite_status);
404 static void get_last_sample_611x(struct comedi_device *dev);
405 static void get_last_sample_6143(struct comedi_device *dev);
406
407 static inline void ni_set_bitfield(struct comedi_device *dev, int reg,
408 unsigned bit_mask, unsigned bit_values)
409 {
410 struct ni_private *devpriv = dev->private;
411 unsigned long flags;
412
413 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
414 switch (reg) {
415 case Interrupt_A_Enable_Register:
416 devpriv->int_a_enable_reg &= ~bit_mask;
417 devpriv->int_a_enable_reg |= bit_values & bit_mask;
418 devpriv->stc_writew(dev, devpriv->int_a_enable_reg,
419 Interrupt_A_Enable_Register);
420 break;
421 case Interrupt_B_Enable_Register:
422 devpriv->int_b_enable_reg &= ~bit_mask;
423 devpriv->int_b_enable_reg |= bit_values & bit_mask;
424 devpriv->stc_writew(dev, devpriv->int_b_enable_reg,
425 Interrupt_B_Enable_Register);
426 break;
427 case IO_Bidirection_Pin_Register:
428 devpriv->io_bidirection_pin_reg &= ~bit_mask;
429 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask;
430 devpriv->stc_writew(dev, devpriv->io_bidirection_pin_reg,
431 IO_Bidirection_Pin_Register);
432 break;
433 case AI_AO_Select:
434 devpriv->ai_ao_select_reg &= ~bit_mask;
435 devpriv->ai_ao_select_reg |= bit_values & bit_mask;
436 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
437 break;
438 case G0_G1_Select:
439 devpriv->g0_g1_select_reg &= ~bit_mask;
440 devpriv->g0_g1_select_reg |= bit_values & bit_mask;
441 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
442 break;
443 default:
444 printk("Warning %s() called with invalid register\n", __func__);
445 printk("reg is %d\n", reg);
446 break;
447 }
448 mmiowb();
449 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
450 }
451
452 #ifdef PCIDMA
453 static int ni_ai_drain_dma(struct comedi_device *dev);
454
455 /* DMA channel setup */
456
457 /* negative channel means no channel */
458 static inline void ni_set_ai_dma_channel(struct comedi_device *dev, int channel)
459 {
460 unsigned bitfield;
461
462 if (channel >= 0) {
463 bitfield =
464 (ni_stc_dma_channel_select_bitfield(channel) <<
465 AI_DMA_Select_Shift) & AI_DMA_Select_Mask;
466 } else {
467 bitfield = 0;
468 }
469 ni_set_bitfield(dev, AI_AO_Select, AI_DMA_Select_Mask, bitfield);
470 }
471
472 /* negative channel means no channel */
473 static inline void ni_set_ao_dma_channel(struct comedi_device *dev, int channel)
474 {
475 unsigned bitfield;
476
477 if (channel >= 0) {
478 bitfield =
479 (ni_stc_dma_channel_select_bitfield(channel) <<
480 AO_DMA_Select_Shift) & AO_DMA_Select_Mask;
481 } else {
482 bitfield = 0;
483 }
484 ni_set_bitfield(dev, AI_AO_Select, AO_DMA_Select_Mask, bitfield);
485 }
486
487 /* negative mite_channel means no channel */
488 static inline void ni_set_gpct_dma_channel(struct comedi_device *dev,
489 unsigned gpct_index,
490 int mite_channel)
491 {
492 unsigned bitfield;
493
494 if (mite_channel >= 0) {
495 bitfield = GPCT_DMA_Select_Bits(gpct_index, mite_channel);
496 } else {
497 bitfield = 0;
498 }
499 ni_set_bitfield(dev, G0_G1_Select, GPCT_DMA_Select_Mask(gpct_index),
500 bitfield);
501 }
502
503 /* negative mite_channel means no channel */
504 static inline void ni_set_cdo_dma_channel(struct comedi_device *dev,
505 int mite_channel)
506 {
507 struct ni_private *devpriv = dev->private;
508 unsigned long flags;
509
510 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags);
511 devpriv->cdio_dma_select_reg &= ~CDO_DMA_Select_Mask;
512 if (mite_channel >= 0) {
513 /*XXX just guessing ni_stc_dma_channel_select_bitfield() returns the right bits,
514 under the assumption the cdio dma selection works just like ai/ao/gpct.
515 Definitely works for dma channels 0 and 1. */
516 devpriv->cdio_dma_select_reg |=
517 (ni_stc_dma_channel_select_bitfield(mite_channel) <<
518 CDO_DMA_Select_Shift) & CDO_DMA_Select_Mask;
519 }
520 ni_writeb(devpriv->cdio_dma_select_reg, M_Offset_CDIO_DMA_Select);
521 mmiowb();
522 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags);
523 }
524
525 static int ni_request_ai_mite_channel(struct comedi_device *dev)
526 {
527 struct ni_private *devpriv = dev->private;
528 unsigned long flags;
529
530 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
531 BUG_ON(devpriv->ai_mite_chan);
532 devpriv->ai_mite_chan =
533 mite_request_channel(devpriv->mite, devpriv->ai_mite_ring);
534 if (devpriv->ai_mite_chan == NULL) {
535 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
536 comedi_error(dev,
537 "failed to reserve mite dma channel for analog input.");
538 return -EBUSY;
539 }
540 devpriv->ai_mite_chan->dir = COMEDI_INPUT;
541 ni_set_ai_dma_channel(dev, devpriv->ai_mite_chan->channel);
542 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
543 return 0;
544 }
545
546 static int ni_request_ao_mite_channel(struct comedi_device *dev)
547 {
548 struct ni_private *devpriv = dev->private;
549 unsigned long flags;
550
551 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
552 BUG_ON(devpriv->ao_mite_chan);
553 devpriv->ao_mite_chan =
554 mite_request_channel(devpriv->mite, devpriv->ao_mite_ring);
555 if (devpriv->ao_mite_chan == NULL) {
556 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
557 comedi_error(dev,
558 "failed to reserve mite dma channel for analog outut.");
559 return -EBUSY;
560 }
561 devpriv->ao_mite_chan->dir = COMEDI_OUTPUT;
562 ni_set_ao_dma_channel(dev, devpriv->ao_mite_chan->channel);
563 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
564 return 0;
565 }
566
567 static int ni_request_gpct_mite_channel(struct comedi_device *dev,
568 unsigned gpct_index,
569 enum comedi_io_direction direction)
570 {
571 struct ni_private *devpriv = dev->private;
572 unsigned long flags;
573 struct mite_channel *mite_chan;
574
575 BUG_ON(gpct_index >= NUM_GPCT);
576 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
577 BUG_ON(devpriv->counter_dev->counters[gpct_index].mite_chan);
578 mite_chan =
579 mite_request_channel(devpriv->mite,
580 devpriv->gpct_mite_ring[gpct_index]);
581 if (mite_chan == NULL) {
582 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
583 comedi_error(dev,
584 "failed to reserve mite dma channel for counter.");
585 return -EBUSY;
586 }
587 mite_chan->dir = direction;
588 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index],
589 mite_chan);
590 ni_set_gpct_dma_channel(dev, gpct_index, mite_chan->channel);
591 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
592 return 0;
593 }
594
595 #endif /* PCIDMA */
596
597 static int ni_request_cdo_mite_channel(struct comedi_device *dev)
598 {
599 #ifdef PCIDMA
600 struct ni_private *devpriv = dev->private;
601 unsigned long flags;
602
603 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
604 BUG_ON(devpriv->cdo_mite_chan);
605 devpriv->cdo_mite_chan =
606 mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring);
607 if (devpriv->cdo_mite_chan == NULL) {
608 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
609 comedi_error(dev,
610 "failed to reserve mite dma channel for correlated digital outut.");
611 return -EBUSY;
612 }
613 devpriv->cdo_mite_chan->dir = COMEDI_OUTPUT;
614 ni_set_cdo_dma_channel(dev, devpriv->cdo_mite_chan->channel);
615 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
616 #endif /* PCIDMA */
617 return 0;
618 }
619
620 static void ni_release_ai_mite_channel(struct comedi_device *dev)
621 {
622 #ifdef PCIDMA
623 struct ni_private *devpriv = dev->private;
624 unsigned long flags;
625
626 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
627 if (devpriv->ai_mite_chan) {
628 ni_set_ai_dma_channel(dev, -1);
629 mite_release_channel(devpriv->ai_mite_chan);
630 devpriv->ai_mite_chan = NULL;
631 }
632 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
633 #endif /* PCIDMA */
634 }
635
636 static void ni_release_ao_mite_channel(struct comedi_device *dev)
637 {
638 #ifdef PCIDMA
639 struct ni_private *devpriv = dev->private;
640 unsigned long flags;
641
642 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
643 if (devpriv->ao_mite_chan) {
644 ni_set_ao_dma_channel(dev, -1);
645 mite_release_channel(devpriv->ao_mite_chan);
646 devpriv->ao_mite_chan = NULL;
647 }
648 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
649 #endif /* PCIDMA */
650 }
651
652 #ifdef PCIDMA
653 static void ni_release_gpct_mite_channel(struct comedi_device *dev,
654 unsigned gpct_index)
655 {
656 struct ni_private *devpriv = dev->private;
657 unsigned long flags;
658
659 BUG_ON(gpct_index >= NUM_GPCT);
660 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
661 if (devpriv->counter_dev->counters[gpct_index].mite_chan) {
662 struct mite_channel *mite_chan =
663 devpriv->counter_dev->counters[gpct_index].mite_chan;
664
665 ni_set_gpct_dma_channel(dev, gpct_index, -1);
666 ni_tio_set_mite_channel(&devpriv->
667 counter_dev->counters[gpct_index],
668 NULL);
669 mite_release_channel(mite_chan);
670 }
671 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
672 }
673 #endif /* PCIDMA */
674
675 static void ni_release_cdo_mite_channel(struct comedi_device *dev)
676 {
677 #ifdef PCIDMA
678 struct ni_private *devpriv = dev->private;
679 unsigned long flags;
680
681 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
682 if (devpriv->cdo_mite_chan) {
683 ni_set_cdo_dma_channel(dev, -1);
684 mite_release_channel(devpriv->cdo_mite_chan);
685 devpriv->cdo_mite_chan = NULL;
686 }
687 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
688 #endif /* PCIDMA */
689 }
690
691 /* e-series boards use the second irq signals to generate dma requests for their counters */
692 #ifdef PCIDMA
693 static void ni_e_series_enable_second_irq(struct comedi_device *dev,
694 unsigned gpct_index, short enable)
695 {
696 const struct ni_board_struct *board = comedi_board(dev);
697 struct ni_private *devpriv = dev->private;
698
699 if (board->reg_type & ni_reg_m_series_mask)
700 return;
701 switch (gpct_index) {
702 case 0:
703 if (enable) {
704 devpriv->stc_writew(dev, G0_Gate_Second_Irq_Enable,
705 Second_IRQ_A_Enable_Register);
706 } else {
707 devpriv->stc_writew(dev, 0,
708 Second_IRQ_A_Enable_Register);
709 }
710 break;
711 case 1:
712 if (enable) {
713 devpriv->stc_writew(dev, G1_Gate_Second_Irq_Enable,
714 Second_IRQ_B_Enable_Register);
715 } else {
716 devpriv->stc_writew(dev, 0,
717 Second_IRQ_B_Enable_Register);
718 }
719 break;
720 default:
721 BUG();
722 break;
723 }
724 }
725 #endif /* PCIDMA */
726
727 static void ni_clear_ai_fifo(struct comedi_device *dev)
728 {
729 const struct ni_board_struct *board = comedi_board(dev);
730 struct ni_private *devpriv = dev->private;
731
732 if (board->reg_type == ni_reg_6143) {
733 /* Flush the 6143 data FIFO */
734 ni_writel(0x10, AIFIFO_Control_6143); /* Flush fifo */
735 ni_writel(0x00, AIFIFO_Control_6143); /* Flush fifo */
736 while (ni_readl(AIFIFO_Status_6143) & 0x10) ; /* Wait for complete */
737 } else {
738 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
739 if (board->reg_type == ni_reg_625x) {
740 ni_writeb(0, M_Offset_Static_AI_Control(0));
741 ni_writeb(1, M_Offset_Static_AI_Control(0));
742 #if 0
743 /* the NI example code does 3 convert pulses for 625x boards,
744 but that appears to be wrong in practice. */
745 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
746 AI_Command_1_Register);
747 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
748 AI_Command_1_Register);
749 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
750 AI_Command_1_Register);
751 #endif
752 }
753 }
754 }
755
756 static void win_out2(struct comedi_device *dev, uint32_t data, int reg)
757 {
758 struct ni_private *devpriv = dev->private;
759
760 devpriv->stc_writew(dev, data >> 16, reg);
761 devpriv->stc_writew(dev, data & 0xffff, reg + 1);
762 }
763
764 static uint32_t win_in2(struct comedi_device *dev, int reg)
765 {
766 struct ni_private *devpriv = dev->private;
767 uint32_t bits;
768
769 bits = devpriv->stc_readw(dev, reg) << 16;
770 bits |= devpriv->stc_readw(dev, reg + 1);
771 return bits;
772 }
773
774 #define ao_win_out(data, addr) ni_ao_win_outw(dev, data, addr)
775 static inline void ni_ao_win_outw(struct comedi_device *dev, uint16_t data,
776 int addr)
777 {
778 struct ni_private *devpriv = dev->private;
779 unsigned long flags;
780
781 spin_lock_irqsave(&devpriv->window_lock, flags);
782 ni_writew(addr, AO_Window_Address_611x);
783 ni_writew(data, AO_Window_Data_611x);
784 spin_unlock_irqrestore(&devpriv->window_lock, flags);
785 }
786
787 static inline void ni_ao_win_outl(struct comedi_device *dev, uint32_t data,
788 int addr)
789 {
790 struct ni_private *devpriv = dev->private;
791 unsigned long flags;
792
793 spin_lock_irqsave(&devpriv->window_lock, flags);
794 ni_writew(addr, AO_Window_Address_611x);
795 ni_writel(data, AO_Window_Data_611x);
796 spin_unlock_irqrestore(&devpriv->window_lock, flags);
797 }
798
799 static inline unsigned short ni_ao_win_inw(struct comedi_device *dev, int addr)
800 {
801 struct ni_private *devpriv = dev->private;
802 unsigned long flags;
803 unsigned short data;
804
805 spin_lock_irqsave(&devpriv->window_lock, flags);
806 ni_writew(addr, AO_Window_Address_611x);
807 data = ni_readw(AO_Window_Data_611x);
808 spin_unlock_irqrestore(&devpriv->window_lock, flags);
809 return data;
810 }
811
812 /* ni_set_bits( ) allows different parts of the ni_mio_common driver to
813 * share registers (such as Interrupt_A_Register) without interfering with
814 * each other.
815 *
816 * NOTE: the switch/case statements are optimized out for a constant argument
817 * so this is actually quite fast--- If you must wrap another function around this
818 * make it inline to avoid a large speed penalty.
819 *
820 * value should only be 1 or 0.
821 */
822 static inline void ni_set_bits(struct comedi_device *dev, int reg,
823 unsigned bits, unsigned value)
824 {
825 unsigned bit_values;
826
827 if (value)
828 bit_values = bits;
829 else
830 bit_values = 0;
831 ni_set_bitfield(dev, reg, bits, bit_values);
832 }
833
834 static irqreturn_t ni_E_interrupt(int irq, void *d)
835 {
836 struct comedi_device *dev = d;
837 struct ni_private *devpriv = dev->private;
838 unsigned short a_status;
839 unsigned short b_status;
840 unsigned int ai_mite_status = 0;
841 unsigned int ao_mite_status = 0;
842 unsigned long flags;
843 #ifdef PCIDMA
844 struct mite_struct *mite = devpriv->mite;
845 #endif
846
847 if (!dev->attached)
848 return IRQ_NONE;
849 smp_mb(); /* make sure dev->attached is checked before handler does anything else. */
850
851 /* lock to avoid race with comedi_poll */
852 spin_lock_irqsave(&dev->spinlock, flags);
853 a_status = devpriv->stc_readw(dev, AI_Status_1_Register);
854 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
855 #ifdef PCIDMA
856 if (mite) {
857 unsigned long flags_too;
858
859 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too);
860 if (devpriv->ai_mite_chan) {
861 ai_mite_status = mite_get_status(devpriv->ai_mite_chan);
862 if (ai_mite_status & CHSR_LINKC)
863 writel(CHOR_CLRLC,
864 devpriv->mite->mite_io_addr +
865 MITE_CHOR(devpriv->
866 ai_mite_chan->channel));
867 }
868 if (devpriv->ao_mite_chan) {
869 ao_mite_status = mite_get_status(devpriv->ao_mite_chan);
870 if (ao_mite_status & CHSR_LINKC)
871 writel(CHOR_CLRLC,
872 mite->mite_io_addr +
873 MITE_CHOR(devpriv->
874 ao_mite_chan->channel));
875 }
876 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too);
877 }
878 #endif
879 ack_a_interrupt(dev, a_status);
880 ack_b_interrupt(dev, b_status);
881 if ((a_status & Interrupt_A_St) || (ai_mite_status & CHSR_INT))
882 handle_a_interrupt(dev, a_status, ai_mite_status);
883 if ((b_status & Interrupt_B_St) || (ao_mite_status & CHSR_INT))
884 handle_b_interrupt(dev, b_status, ao_mite_status);
885 handle_gpct_interrupt(dev, 0);
886 handle_gpct_interrupt(dev, 1);
887 handle_cdio_interrupt(dev);
888
889 spin_unlock_irqrestore(&dev->spinlock, flags);
890 return IRQ_HANDLED;
891 }
892
893 #ifdef PCIDMA
894 static void ni_sync_ai_dma(struct comedi_device *dev)
895 {
896 struct ni_private *devpriv = dev->private;
897 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
898 unsigned long flags;
899
900 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
901 if (devpriv->ai_mite_chan)
902 mite_sync_input_dma(devpriv->ai_mite_chan, s->async);
903 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
904 }
905
906 static void mite_handle_b_linkc(struct mite_struct *mite,
907 struct comedi_device *dev)
908 {
909 struct ni_private *devpriv = dev->private;
910 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
911 unsigned long flags;
912
913 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
914 if (devpriv->ao_mite_chan) {
915 mite_sync_output_dma(devpriv->ao_mite_chan, s->async);
916 }
917 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
918 }
919
920 static int ni_ao_wait_for_dma_load(struct comedi_device *dev)
921 {
922 struct ni_private *devpriv = dev->private;
923 static const int timeout = 10000;
924 int i;
925 for (i = 0; i < timeout; i++) {
926 unsigned short b_status;
927
928 b_status = devpriv->stc_readw(dev, AO_Status_1_Register);
929 if (b_status & AO_FIFO_Half_Full_St)
930 break;
931 /* if we poll too often, the pci bus activity seems
932 to slow the dma transfer down */
933 udelay(10);
934 }
935 if (i == timeout) {
936 comedi_error(dev, "timed out waiting for dma load");
937 return -EPIPE;
938 }
939 return 0;
940 }
941
942 #endif /* PCIDMA */
943 static void ni_handle_eos(struct comedi_device *dev, struct comedi_subdevice *s)
944 {
945 struct ni_private *devpriv = dev->private;
946
947 if (devpriv->aimode == AIMODE_SCAN) {
948 #ifdef PCIDMA
949 static const int timeout = 10;
950 int i;
951
952 for (i = 0; i < timeout; i++) {
953 ni_sync_ai_dma(dev);
954 if ((s->async->events & COMEDI_CB_EOS))
955 break;
956 udelay(1);
957 }
958 #else
959 ni_handle_fifo_dregs(dev);
960 s->async->events |= COMEDI_CB_EOS;
961 #endif
962 }
963 /* handle special case of single scan using AI_End_On_End_Of_Scan */
964 if ((devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
965 shutdown_ai_command(dev);
966 }
967 }
968
969 static void shutdown_ai_command(struct comedi_device *dev)
970 {
971 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
972
973 #ifdef PCIDMA
974 ni_ai_drain_dma(dev);
975 #endif
976 ni_handle_fifo_dregs(dev);
977 get_last_sample_611x(dev);
978 get_last_sample_6143(dev);
979
980 s->async->events |= COMEDI_CB_EOA;
981 }
982
983 static void ni_event(struct comedi_device *dev, struct comedi_subdevice *s)
984 {
985 if (s->
986 async->events & (COMEDI_CB_ERROR | COMEDI_CB_OVERFLOW |
987 COMEDI_CB_EOA)) {
988 switch (s->index) {
989 case NI_AI_SUBDEV:
990 ni_ai_reset(dev, s);
991 break;
992 case NI_AO_SUBDEV:
993 ni_ao_reset(dev, s);
994 break;
995 case NI_GPCT0_SUBDEV:
996 case NI_GPCT1_SUBDEV:
997 ni_gpct_cancel(dev, s);
998 break;
999 case NI_DIO_SUBDEV:
1000 ni_cdio_cancel(dev, s);
1001 break;
1002 default:
1003 break;
1004 }
1005 }
1006 comedi_event(dev, s);
1007 }
1008
1009 static void handle_gpct_interrupt(struct comedi_device *dev,
1010 unsigned short counter_index)
1011 {
1012 #ifdef PCIDMA
1013 struct ni_private *devpriv = dev->private;
1014 struct comedi_subdevice *s;
1015
1016 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)];
1017
1018 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index],
1019 s);
1020 if (s->async->events)
1021 ni_event(dev, s);
1022 #endif
1023 }
1024
1025 static void ack_a_interrupt(struct comedi_device *dev, unsigned short a_status)
1026 {
1027 struct ni_private *devpriv = dev->private;
1028 unsigned short ack = 0;
1029
1030 if (a_status & AI_SC_TC_St) {
1031 ack |= AI_SC_TC_Interrupt_Ack;
1032 }
1033 if (a_status & AI_START1_St) {
1034 ack |= AI_START1_Interrupt_Ack;
1035 }
1036 if (a_status & AI_START_St) {
1037 ack |= AI_START_Interrupt_Ack;
1038 }
1039 if (a_status & AI_STOP_St) {
1040 /* not sure why we used to ack the START here also, instead of doing it independently. Frank Hess 2007-07-06 */
1041 ack |= AI_STOP_Interrupt_Ack /*| AI_START_Interrupt_Ack */ ;
1042 }
1043 if (ack)
1044 devpriv->stc_writew(dev, ack, Interrupt_A_Ack_Register);
1045 }
1046
1047 static void handle_a_interrupt(struct comedi_device *dev, unsigned short status,
1048 unsigned ai_mite_status)
1049 {
1050 struct ni_private *devpriv = dev->private;
1051 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1052
1053 /* 67xx boards don't have ai subdevice, but their gpct0 might generate an a interrupt */
1054 if (s->type == COMEDI_SUBD_UNUSED)
1055 return;
1056
1057 #ifdef DEBUG_INTERRUPT
1058 printk
1059 ("ni_mio_common: interrupt: a_status=%04x ai_mite_status=%08x\n",
1060 status, ai_mite_status);
1061 ni_mio_print_status_a(status);
1062 #endif
1063 #ifdef PCIDMA
1064 if (ai_mite_status & CHSR_LINKC) {
1065 ni_sync_ai_dma(dev);
1066 }
1067
1068 if (ai_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1069 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1070 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1071 printk
1072 ("unknown mite interrupt, ack! (ai_mite_status=%08x)\n",
1073 ai_mite_status);
1074 /* mite_print_chsr(ai_mite_status); */
1075 s->async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1076 /* disable_irq(dev->irq); */
1077 }
1078 #endif
1079
1080 /* test for all uncommon interrupt events at the same time */
1081 if (status & (AI_Overrun_St | AI_Overflow_St | AI_SC_TC_Error_St |
1082 AI_SC_TC_St | AI_START1_St)) {
1083 if (status == 0xffff) {
1084 printk
1085 ("ni_mio_common: a_status=0xffff. Card removed?\n");
1086 /* we probably aren't even running a command now,
1087 * so it's a good idea to be careful. */
1088 if (comedi_is_subdevice_running(s)) {
1089 s->async->events |=
1090 COMEDI_CB_ERROR | COMEDI_CB_EOA;
1091 ni_event(dev, s);
1092 }
1093 return;
1094 }
1095 if (status & (AI_Overrun_St | AI_Overflow_St |
1096 AI_SC_TC_Error_St)) {
1097 printk("ni_mio_common: ai error a_status=%04x\n",
1098 status);
1099 ni_mio_print_status_a(status);
1100
1101 shutdown_ai_command(dev);
1102
1103 s->async->events |= COMEDI_CB_ERROR;
1104 if (status & (AI_Overrun_St | AI_Overflow_St))
1105 s->async->events |= COMEDI_CB_OVERFLOW;
1106
1107 ni_event(dev, s);
1108
1109 return;
1110 }
1111 if (status & AI_SC_TC_St) {
1112 #ifdef DEBUG_INTERRUPT
1113 printk("ni_mio_common: SC_TC interrupt\n");
1114 #endif
1115 if (!devpriv->ai_continuous) {
1116 shutdown_ai_command(dev);
1117 }
1118 }
1119 }
1120 #ifndef PCIDMA
1121 if (status & AI_FIFO_Half_Full_St) {
1122 int i;
1123 static const int timeout = 10;
1124 /* pcmcia cards (at least 6036) seem to stop producing interrupts if we
1125 *fail to get the fifo less than half full, so loop to be sure.*/
1126 for (i = 0; i < timeout; ++i) {
1127 ni_handle_fifo_half_full(dev);
1128 if ((devpriv->stc_readw(dev,
1129 AI_Status_1_Register) &
1130 AI_FIFO_Half_Full_St) == 0)
1131 break;
1132 }
1133 }
1134 #endif /* !PCIDMA */
1135
1136 if ((status & AI_STOP_St)) {
1137 ni_handle_eos(dev, s);
1138 }
1139
1140 ni_event(dev, s);
1141
1142 #ifdef DEBUG_INTERRUPT
1143 status = devpriv->stc_readw(dev, AI_Status_1_Register);
1144 if (status & Interrupt_A_St) {
1145 printk
1146 ("handle_a_interrupt: didn't clear interrupt? status=0x%x\n",
1147 status);
1148 }
1149 #endif
1150 }
1151
1152 static void ack_b_interrupt(struct comedi_device *dev, unsigned short b_status)
1153 {
1154 struct ni_private *devpriv = dev->private;
1155 unsigned short ack = 0;
1156
1157 if (b_status & AO_BC_TC_St) {
1158 ack |= AO_BC_TC_Interrupt_Ack;
1159 }
1160 if (b_status & AO_Overrun_St) {
1161 ack |= AO_Error_Interrupt_Ack;
1162 }
1163 if (b_status & AO_START_St) {
1164 ack |= AO_START_Interrupt_Ack;
1165 }
1166 if (b_status & AO_START1_St) {
1167 ack |= AO_START1_Interrupt_Ack;
1168 }
1169 if (b_status & AO_UC_TC_St) {
1170 ack |= AO_UC_TC_Interrupt_Ack;
1171 }
1172 if (b_status & AO_UI2_TC_St) {
1173 ack |= AO_UI2_TC_Interrupt_Ack;
1174 }
1175 if (b_status & AO_UPDATE_St) {
1176 ack |= AO_UPDATE_Interrupt_Ack;
1177 }
1178 if (ack)
1179 devpriv->stc_writew(dev, ack, Interrupt_B_Ack_Register);
1180 }
1181
1182 static void handle_b_interrupt(struct comedi_device *dev,
1183 unsigned short b_status, unsigned ao_mite_status)
1184 {
1185 struct ni_private *devpriv = dev->private;
1186 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1187 /* unsigned short ack=0; */
1188
1189 #ifdef DEBUG_INTERRUPT
1190 printk("ni_mio_common: interrupt: b_status=%04x m1_status=%08x\n",
1191 b_status, ao_mite_status);
1192 ni_mio_print_status_b(b_status);
1193 #endif
1194
1195 #ifdef PCIDMA
1196 /* Currently, mite.c requires us to handle LINKC */
1197 if (ao_mite_status & CHSR_LINKC) {
1198 mite_handle_b_linkc(devpriv->mite, dev);
1199 }
1200
1201 if (ao_mite_status & ~(CHSR_INT | CHSR_LINKC | CHSR_DONE | CHSR_MRDY |
1202 CHSR_DRDY | CHSR_DRQ1 | CHSR_DRQ0 | CHSR_ERROR |
1203 CHSR_SABORT | CHSR_XFERR | CHSR_LxERR_mask)) {
1204 printk
1205 ("unknown mite interrupt, ack! (ao_mite_status=%08x)\n",
1206 ao_mite_status);
1207 /* mite_print_chsr(ao_mite_status); */
1208 s->async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
1209 }
1210 #endif
1211
1212 if (b_status == 0xffff)
1213 return;
1214 if (b_status & AO_Overrun_St) {
1215 printk
1216 ("ni_mio_common: AO FIFO underrun status=0x%04x status2=0x%04x\n",
1217 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1218 s->async->events |= COMEDI_CB_OVERFLOW;
1219 }
1220
1221 if (b_status & AO_BC_TC_St) {
1222 MDPRINTK
1223 ("ni_mio_common: AO BC_TC status=0x%04x status2=0x%04x\n",
1224 b_status, devpriv->stc_readw(dev, AO_Status_2_Register));
1225 s->async->events |= COMEDI_CB_EOA;
1226 }
1227 #ifndef PCIDMA
1228 if (b_status & AO_FIFO_Request_St) {
1229 int ret;
1230
1231 ret = ni_ao_fifo_half_empty(dev, s);
1232 if (!ret) {
1233 printk("ni_mio_common: AO buffer underrun\n");
1234 ni_set_bits(dev, Interrupt_B_Enable_Register,
1235 AO_FIFO_Interrupt_Enable |
1236 AO_Error_Interrupt_Enable, 0);
1237 s->async->events |= COMEDI_CB_OVERFLOW;
1238 }
1239 }
1240 #endif
1241
1242 ni_event(dev, s);
1243 }
1244
1245 #ifdef DEBUG_STATUS_A
1246 static const char *const status_a_strings[] = {
1247 "passthru0", "fifo", "G0_gate", "G0_TC",
1248 "stop", "start", "sc_tc", "start1",
1249 "start2", "sc_tc_error", "overflow", "overrun",
1250 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_a"
1251 };
1252
1253 static void ni_mio_print_status_a(int status)
1254 {
1255 int i;
1256
1257 printk("A status:");
1258 for (i = 15; i >= 0; i--) {
1259 if (status & (1 << i)) {
1260 printk(" %s", status_a_strings[i]);
1261 }
1262 }
1263 printk("\n");
1264 }
1265 #endif
1266
1267 #ifdef DEBUG_STATUS_B
1268 static const char *const status_b_strings[] = {
1269 "passthru1", "fifo", "G1_gate", "G1_TC",
1270 "UI2_TC", "UPDATE", "UC_TC", "BC_TC",
1271 "start1", "overrun", "start", "bc_tc_error",
1272 "fifo_empty", "fifo_half_full", "fifo_full", "interrupt_b"
1273 };
1274
1275 static void ni_mio_print_status_b(int status)
1276 {
1277 int i;
1278
1279 printk("B status:");
1280 for (i = 15; i >= 0; i--) {
1281 if (status & (1 << i)) {
1282 printk(" %s", status_b_strings[i]);
1283 }
1284 }
1285 printk("\n");
1286 }
1287 #endif
1288
1289 #ifndef PCIDMA
1290
1291 static void ni_ao_fifo_load(struct comedi_device *dev,
1292 struct comedi_subdevice *s, int n)
1293 {
1294 const struct ni_board_struct *board = comedi_board(dev);
1295 struct comedi_async *async = s->async;
1296 struct comedi_cmd *cmd = &async->cmd;
1297 int chan;
1298 int i;
1299 short d;
1300 u32 packed_data;
1301 int range;
1302 int err = 1;
1303
1304 chan = async->cur_chan;
1305 for (i = 0; i < n; i++) {
1306 err &= comedi_buf_get(async, &d);
1307 if (err == 0)
1308 break;
1309
1310 range = CR_RANGE(cmd->chanlist[chan]);
1311
1312 if (board->reg_type & ni_reg_6xxx_mask) {
1313 packed_data = d & 0xffff;
1314 /* 6711 only has 16 bit wide ao fifo */
1315 if (board->reg_type != ni_reg_6711) {
1316 err &= comedi_buf_get(async, &d);
1317 if (err == 0)
1318 break;
1319 chan++;
1320 i++;
1321 packed_data |= (d << 16) & 0xffff0000;
1322 }
1323 ni_writel(packed_data, DAC_FIFO_Data_611x);
1324 } else {
1325 ni_writew(d, DAC_FIFO_Data);
1326 }
1327 chan++;
1328 chan %= cmd->chanlist_len;
1329 }
1330 async->cur_chan = chan;
1331 if (err == 0) {
1332 async->events |= COMEDI_CB_OVERFLOW;
1333 }
1334 }
1335
1336 /*
1337 * There's a small problem if the FIFO gets really low and we
1338 * don't have the data to fill it. Basically, if after we fill
1339 * the FIFO with all the data available, the FIFO is _still_
1340 * less than half full, we never clear the interrupt. If the
1341 * IRQ is in edge mode, we never get another interrupt, because
1342 * this one wasn't cleared. If in level mode, we get flooded
1343 * with interrupts that we can't fulfill, because nothing ever
1344 * gets put into the buffer.
1345 *
1346 * This kind of situation is recoverable, but it is easier to
1347 * just pretend we had a FIFO underrun, since there is a good
1348 * chance it will happen anyway. This is _not_ the case for
1349 * RT code, as RT code might purposely be running close to the
1350 * metal. Needs to be fixed eventually.
1351 */
1352 static int ni_ao_fifo_half_empty(struct comedi_device *dev,
1353 struct comedi_subdevice *s)
1354 {
1355 const struct ni_board_struct *board = comedi_board(dev);
1356 int n;
1357
1358 n = comedi_buf_read_n_available(s->async);
1359 if (n == 0) {
1360 s->async->events |= COMEDI_CB_OVERFLOW;
1361 return 0;
1362 }
1363
1364 n /= sizeof(short);
1365 if (n > board->ao_fifo_depth / 2)
1366 n = board->ao_fifo_depth / 2;
1367
1368 ni_ao_fifo_load(dev, s, n);
1369
1370 s->async->events |= COMEDI_CB_BLOCK;
1371
1372 return 1;
1373 }
1374
1375 static int ni_ao_prep_fifo(struct comedi_device *dev,
1376 struct comedi_subdevice *s)
1377 {
1378 const struct ni_board_struct *board = comedi_board(dev);
1379 struct ni_private *devpriv = dev->private;
1380 int n;
1381
1382 /* reset fifo */
1383 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
1384 if (board->reg_type & ni_reg_6xxx_mask)
1385 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
1386
1387 /* load some data */
1388 n = comedi_buf_read_n_available(s->async);
1389 if (n == 0)
1390 return 0;
1391
1392 n /= sizeof(short);
1393 if (n > board->ao_fifo_depth)
1394 n = board->ao_fifo_depth;
1395
1396 ni_ao_fifo_load(dev, s, n);
1397
1398 return n;
1399 }
1400
1401 static void ni_ai_fifo_read(struct comedi_device *dev,
1402 struct comedi_subdevice *s, int n)
1403 {
1404 const struct ni_board_struct *board = comedi_board(dev);
1405 struct ni_private *devpriv = dev->private;
1406 struct comedi_async *async = s->async;
1407 int i;
1408
1409 if (board->reg_type == ni_reg_611x) {
1410 short data[2];
1411 u32 dl;
1412
1413 for (i = 0; i < n / 2; i++) {
1414 dl = ni_readl(ADC_FIFO_Data_611x);
1415 /* This may get the hi/lo data in the wrong order */
1416 data[0] = (dl >> 16) & 0xffff;
1417 data[1] = dl & 0xffff;
1418 cfc_write_array_to_buffer(s, data, sizeof(data));
1419 }
1420 /* Check if there's a single sample stuck in the FIFO */
1421 if (n % 2) {
1422 dl = ni_readl(ADC_FIFO_Data_611x);
1423 data[0] = dl & 0xffff;
1424 cfc_write_to_buffer(s, data[0]);
1425 }
1426 } else if (board->reg_type == ni_reg_6143) {
1427 short data[2];
1428 u32 dl;
1429
1430 /* This just reads the FIFO assuming the data is present, no checks on the FIFO status are performed */
1431 for (i = 0; i < n / 2; i++) {
1432 dl = ni_readl(AIFIFO_Data_6143);
1433
1434 data[0] = (dl >> 16) & 0xffff;
1435 data[1] = dl & 0xffff;
1436 cfc_write_array_to_buffer(s, data, sizeof(data));
1437 }
1438 if (n % 2) {
1439 /* Assume there is a single sample stuck in the FIFO */
1440 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1441 dl = ni_readl(AIFIFO_Data_6143);
1442 data[0] = (dl >> 16) & 0xffff;
1443 cfc_write_to_buffer(s, data[0]);
1444 }
1445 } else {
1446 if (n > sizeof(devpriv->ai_fifo_buffer) /
1447 sizeof(devpriv->ai_fifo_buffer[0])) {
1448 comedi_error(dev, "bug! ai_fifo_buffer too small");
1449 async->events |= COMEDI_CB_ERROR;
1450 return;
1451 }
1452 for (i = 0; i < n; i++) {
1453 devpriv->ai_fifo_buffer[i] =
1454 ni_readw(ADC_FIFO_Data_Register);
1455 }
1456 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1457 n *
1458 sizeof(devpriv->ai_fifo_buffer[0]));
1459 }
1460 }
1461
1462 static void ni_handle_fifo_half_full(struct comedi_device *dev)
1463 {
1464 const struct ni_board_struct *board = comedi_board(dev);
1465 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1466 int n;
1467
1468 n = board->ai_fifo_depth / 2;
1469
1470 ni_ai_fifo_read(dev, s, n);
1471 }
1472 #endif
1473
1474 #ifdef PCIDMA
1475 static int ni_ai_drain_dma(struct comedi_device *dev)
1476 {
1477 struct ni_private *devpriv = dev->private;
1478 int i;
1479 static const int timeout = 10000;
1480 unsigned long flags;
1481 int retval = 0;
1482
1483 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1484 if (devpriv->ai_mite_chan) {
1485 for (i = 0; i < timeout; i++) {
1486 if ((devpriv->stc_readw(dev,
1487 AI_Status_1_Register) &
1488 AI_FIFO_Empty_St)
1489 && mite_bytes_in_transit(devpriv->ai_mite_chan) ==
1490 0)
1491 break;
1492 udelay(5);
1493 }
1494 if (i == timeout) {
1495 printk("ni_mio_common: wait for dma drain timed out\n");
1496 printk
1497 ("mite_bytes_in_transit=%i, AI_Status1_Register=0x%x\n",
1498 mite_bytes_in_transit(devpriv->ai_mite_chan),
1499 devpriv->stc_readw(dev, AI_Status_1_Register));
1500 retval = -1;
1501 }
1502 }
1503 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1504
1505 ni_sync_ai_dma(dev);
1506
1507 return retval;
1508 }
1509 #endif
1510 /*
1511 Empties the AI fifo
1512 */
1513 static void ni_handle_fifo_dregs(struct comedi_device *dev)
1514 {
1515 const struct ni_board_struct *board = comedi_board(dev);
1516 struct ni_private *devpriv = dev->private;
1517 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1518 short data[2];
1519 u32 dl;
1520 short fifo_empty;
1521 int i;
1522
1523 if (board->reg_type == ni_reg_611x) {
1524 while ((devpriv->stc_readw(dev,
1525 AI_Status_1_Register) &
1526 AI_FIFO_Empty_St) == 0) {
1527 dl = ni_readl(ADC_FIFO_Data_611x);
1528
1529 /* This may get the hi/lo data in the wrong order */
1530 data[0] = (dl >> 16);
1531 data[1] = (dl & 0xffff);
1532 cfc_write_array_to_buffer(s, data, sizeof(data));
1533 }
1534 } else if (board->reg_type == ni_reg_6143) {
1535 i = 0;
1536 while (ni_readl(AIFIFO_Status_6143) & 0x04) {
1537 dl = ni_readl(AIFIFO_Data_6143);
1538
1539 /* This may get the hi/lo data in the wrong order */
1540 data[0] = (dl >> 16);
1541 data[1] = (dl & 0xffff);
1542 cfc_write_array_to_buffer(s, data, sizeof(data));
1543 i += 2;
1544 }
1545 /* Check if stranded sample is present */
1546 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1547 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1548 dl = ni_readl(AIFIFO_Data_6143);
1549 data[0] = (dl >> 16) & 0xffff;
1550 cfc_write_to_buffer(s, data[0]);
1551 }
1552
1553 } else {
1554 fifo_empty =
1555 devpriv->stc_readw(dev,
1556 AI_Status_1_Register) & AI_FIFO_Empty_St;
1557 while (fifo_empty == 0) {
1558 for (i = 0;
1559 i <
1560 sizeof(devpriv->ai_fifo_buffer) /
1561 sizeof(devpriv->ai_fifo_buffer[0]); i++) {
1562 fifo_empty =
1563 devpriv->stc_readw(dev,
1564 AI_Status_1_Register) &
1565 AI_FIFO_Empty_St;
1566 if (fifo_empty)
1567 break;
1568 devpriv->ai_fifo_buffer[i] =
1569 ni_readw(ADC_FIFO_Data_Register);
1570 }
1571 cfc_write_array_to_buffer(s, devpriv->ai_fifo_buffer,
1572 i *
1573 sizeof(devpriv->
1574 ai_fifo_buffer[0]));
1575 }
1576 }
1577 }
1578
1579 static void get_last_sample_611x(struct comedi_device *dev)
1580 {
1581 const struct ni_board_struct *board = comedi_board(dev);
1582 struct ni_private *devpriv __maybe_unused = dev->private;
1583 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1584 short data;
1585 u32 dl;
1586
1587 if (board->reg_type != ni_reg_611x)
1588 return;
1589
1590 /* Check if there's a single sample stuck in the FIFO */
1591 if (ni_readb(XXX_Status) & 0x80) {
1592 dl = ni_readl(ADC_FIFO_Data_611x);
1593 data = (dl & 0xffff);
1594 cfc_write_to_buffer(s, data);
1595 }
1596 }
1597
1598 static void get_last_sample_6143(struct comedi_device *dev)
1599 {
1600 const struct ni_board_struct *board = comedi_board(dev);
1601 struct ni_private *devpriv __maybe_unused = dev->private;
1602 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1603 short data;
1604 u32 dl;
1605
1606 if (board->reg_type != ni_reg_6143)
1607 return;
1608
1609 /* Check if there's a single sample stuck in the FIFO */
1610 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1611 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1612 dl = ni_readl(AIFIFO_Data_6143);
1613
1614 /* This may get the hi/lo data in the wrong order */
1615 data = (dl >> 16) & 0xffff;
1616 cfc_write_to_buffer(s, data);
1617 }
1618 }
1619
1620 static void ni_ai_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1621 void *data, unsigned int num_bytes,
1622 unsigned int chan_index)
1623 {
1624 struct ni_private *devpriv = dev->private;
1625 struct comedi_async *async = s->async;
1626 unsigned int i;
1627 unsigned int length = num_bytes / bytes_per_sample(s);
1628 short *array = data;
1629 unsigned int *larray = data;
1630
1631 for (i = 0; i < length; i++) {
1632 #ifdef PCIDMA
1633 if (s->subdev_flags & SDF_LSAMPL)
1634 larray[i] = le32_to_cpu(larray[i]);
1635 else
1636 array[i] = le16_to_cpu(array[i]);
1637 #endif
1638 if (s->subdev_flags & SDF_LSAMPL)
1639 larray[i] += devpriv->ai_offset[chan_index];
1640 else
1641 array[i] += devpriv->ai_offset[chan_index];
1642 chan_index++;
1643 chan_index %= async->cmd.chanlist_len;
1644 }
1645 }
1646
1647 #ifdef PCIDMA
1648
1649 static int ni_ai_setup_MITE_dma(struct comedi_device *dev)
1650 {
1651 const struct ni_board_struct *board = comedi_board(dev);
1652 struct ni_private *devpriv = dev->private;
1653 struct comedi_subdevice *s = &dev->subdevices[NI_AI_SUBDEV];
1654 int retval;
1655 unsigned long flags;
1656
1657 retval = ni_request_ai_mite_channel(dev);
1658 if (retval)
1659 return retval;
1660 /* printk("comedi_debug: using mite channel %i for ai.\n", devpriv->ai_mite_chan->channel); */
1661
1662 /* write alloc the entire buffer */
1663 comedi_buf_write_alloc(s->async, s->async->prealloc_bufsz);
1664
1665 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1666 if (devpriv->ai_mite_chan == NULL) {
1667 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1668 return -EIO;
1669 }
1670
1671 switch (board->reg_type) {
1672 case ni_reg_611x:
1673 case ni_reg_6143:
1674 mite_prep_dma(devpriv->ai_mite_chan, 32, 16);
1675 break;
1676 case ni_reg_628x:
1677 mite_prep_dma(devpriv->ai_mite_chan, 32, 32);
1678 break;
1679 default:
1680 mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
1681 break;
1682 }
1683 /*start the MITE */
1684 mite_dma_arm(devpriv->ai_mite_chan);
1685 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1686
1687 return 0;
1688 }
1689
1690 static int ni_ao_setup_MITE_dma(struct comedi_device *dev)
1691 {
1692 const struct ni_board_struct *board = comedi_board(dev);
1693 struct ni_private *devpriv = dev->private;
1694 struct comedi_subdevice *s = &dev->subdevices[NI_AO_SUBDEV];
1695 int retval;
1696 unsigned long flags;
1697
1698 retval = ni_request_ao_mite_channel(dev);
1699 if (retval)
1700 return retval;
1701
1702 /* read alloc the entire buffer */
1703 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
1704
1705 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
1706 if (devpriv->ao_mite_chan) {
1707 if (board->reg_type & (ni_reg_611x | ni_reg_6713)) {
1708 mite_prep_dma(devpriv->ao_mite_chan, 32, 32);
1709 } else {
1710 /* doing 32 instead of 16 bit wide transfers from memory
1711 makes the mite do 32 bit pci transfers, doubling pci bandwidth. */
1712 mite_prep_dma(devpriv->ao_mite_chan, 16, 32);
1713 }
1714 mite_dma_arm(devpriv->ao_mite_chan);
1715 } else
1716 retval = -EIO;
1717 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
1718
1719 return retval;
1720 }
1721
1722 #endif /* PCIDMA */
1723
1724 /*
1725 used for both cancel ioctl and board initialization
1726
1727 this is pretty harsh for a cancel, but it works...
1728 */
1729
1730 static int ni_ai_reset(struct comedi_device *dev, struct comedi_subdevice *s)
1731 {
1732 const struct ni_board_struct *board = comedi_board(dev);
1733 struct ni_private *devpriv = dev->private;
1734
1735 ni_release_ai_mite_channel(dev);
1736 /* ai configuration */
1737 devpriv->stc_writew(dev, AI_Configuration_Start | AI_Reset,
1738 Joint_Reset_Register);
1739
1740 ni_set_bits(dev, Interrupt_A_Enable_Register,
1741 AI_SC_TC_Interrupt_Enable | AI_START1_Interrupt_Enable |
1742 AI_START2_Interrupt_Enable | AI_START_Interrupt_Enable |
1743 AI_STOP_Interrupt_Enable | AI_Error_Interrupt_Enable |
1744 AI_FIFO_Interrupt_Enable, 0);
1745
1746 ni_clear_ai_fifo(dev);
1747
1748 if (board->reg_type != ni_reg_6143)
1749 ni_writeb(0, Misc_Command);
1750
1751 devpriv->stc_writew(dev, AI_Disarm, AI_Command_1_Register); /* reset pulses */
1752 devpriv->stc_writew(dev,
1753 AI_Start_Stop | AI_Mode_1_Reserved
1754 /*| AI_Trigger_Once */ ,
1755 AI_Mode_1_Register);
1756 devpriv->stc_writew(dev, 0x0000, AI_Mode_2_Register);
1757 /* generate FIFO interrupts on non-empty */
1758 devpriv->stc_writew(dev, (0 << 6) | 0x0000, AI_Mode_3_Register);
1759 if (board->reg_type == ni_reg_611x) {
1760 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1761 AI_SOC_Polarity |
1762 AI_LOCALMUX_CLK_Pulse_Width,
1763 AI_Personal_Register);
1764 devpriv->stc_writew(dev,
1765 AI_SCAN_IN_PROG_Output_Select(3) |
1766 AI_EXTMUX_CLK_Output_Select(0) |
1767 AI_LOCALMUX_CLK_Output_Select(2) |
1768 AI_SC_TC_Output_Select(3) |
1769 AI_CONVERT_Output_Select
1770 (AI_CONVERT_Output_Enable_High),
1771 AI_Output_Control_Register);
1772 } else if (board->reg_type == ni_reg_6143) {
1773 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1774 AI_SOC_Polarity |
1775 AI_LOCALMUX_CLK_Pulse_Width,
1776 AI_Personal_Register);
1777 devpriv->stc_writew(dev,
1778 AI_SCAN_IN_PROG_Output_Select(3) |
1779 AI_EXTMUX_CLK_Output_Select(0) |
1780 AI_LOCALMUX_CLK_Output_Select(2) |
1781 AI_SC_TC_Output_Select(3) |
1782 AI_CONVERT_Output_Select
1783 (AI_CONVERT_Output_Enable_Low),
1784 AI_Output_Control_Register);
1785 } else {
1786 unsigned ai_output_control_bits;
1787 devpriv->stc_writew(dev, AI_SHIFTIN_Pulse_Width |
1788 AI_SOC_Polarity |
1789 AI_CONVERT_Pulse_Width |
1790 AI_LOCALMUX_CLK_Pulse_Width,
1791 AI_Personal_Register);
1792 ai_output_control_bits =
1793 AI_SCAN_IN_PROG_Output_Select(3) |
1794 AI_EXTMUX_CLK_Output_Select(0) |
1795 AI_LOCALMUX_CLK_Output_Select(2) |
1796 AI_SC_TC_Output_Select(3);
1797 if (board->reg_type == ni_reg_622x)
1798 ai_output_control_bits |=
1799 AI_CONVERT_Output_Select
1800 (AI_CONVERT_Output_Enable_High);
1801 else
1802 ai_output_control_bits |=
1803 AI_CONVERT_Output_Select
1804 (AI_CONVERT_Output_Enable_Low);
1805 devpriv->stc_writew(dev, ai_output_control_bits,
1806 AI_Output_Control_Register);
1807 }
1808 /* the following registers should not be changed, because there
1809 * are no backup registers in devpriv. If you want to change
1810 * any of these, add a backup register and other appropriate code:
1811 * AI_Mode_1_Register
1812 * AI_Mode_3_Register
1813 * AI_Personal_Register
1814 * AI_Output_Control_Register
1815 */
1816 devpriv->stc_writew(dev, AI_SC_TC_Error_Confirm | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack, Interrupt_A_Ack_Register); /* clear interrupts */
1817
1818 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
1819
1820 return 0;
1821 }
1822
1823 static int ni_ai_poll(struct comedi_device *dev, struct comedi_subdevice *s)
1824 {
1825 unsigned long flags;
1826 int count;
1827
1828 /* lock to avoid race with interrupt handler */
1829 spin_lock_irqsave(&dev->spinlock, flags);
1830 #ifndef PCIDMA
1831 ni_handle_fifo_dregs(dev);
1832 #else
1833 ni_sync_ai_dma(dev);
1834 #endif
1835 count = s->async->buf_write_count - s->async->buf_read_count;
1836 spin_unlock_irqrestore(&dev->spinlock, flags);
1837
1838 return count;
1839 }
1840
1841 static int ni_ai_insn_read(struct comedi_device *dev,
1842 struct comedi_subdevice *s, struct comedi_insn *insn,
1843 unsigned int *data)
1844 {
1845 const struct ni_board_struct *board = comedi_board(dev);
1846 struct ni_private *devpriv = dev->private;
1847 int i, n;
1848 const unsigned int mask = (1 << board->adbits) - 1;
1849 unsigned signbits;
1850 unsigned short d;
1851 unsigned long dl;
1852
1853 ni_load_channelgain_list(dev, 1, &insn->chanspec);
1854
1855 ni_clear_ai_fifo(dev);
1856
1857 signbits = devpriv->ai_offset[0];
1858 if (board->reg_type == ni_reg_611x) {
1859 for (n = 0; n < num_adc_stages_611x; n++) {
1860 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1861 AI_Command_1_Register);
1862 udelay(1);
1863 }
1864 for (n = 0; n < insn->n; n++) {
1865 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1866 AI_Command_1_Register);
1867 /* The 611x has screwy 32-bit FIFOs. */
1868 d = 0;
1869 for (i = 0; i < NI_TIMEOUT; i++) {
1870 if (ni_readb(XXX_Status) & 0x80) {
1871 d = (ni_readl(ADC_FIFO_Data_611x) >> 16)
1872 & 0xffff;
1873 break;
1874 }
1875 if (!(devpriv->stc_readw(dev,
1876 AI_Status_1_Register) &
1877 AI_FIFO_Empty_St)) {
1878 d = ni_readl(ADC_FIFO_Data_611x) &
1879 0xffff;
1880 break;
1881 }
1882 }
1883 if (i == NI_TIMEOUT) {
1884 printk
1885 ("ni_mio_common: timeout in 611x ni_ai_insn_read\n");
1886 return -ETIME;
1887 }
1888 d += signbits;
1889 data[n] = d;
1890 }
1891 } else if (board->reg_type == ni_reg_6143) {
1892 for (n = 0; n < insn->n; n++) {
1893 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1894 AI_Command_1_Register);
1895
1896 /* The 6143 has 32-bit FIFOs. You need to strobe a bit to move a single 16bit stranded sample into the FIFO */
1897 dl = 0;
1898 for (i = 0; i < NI_TIMEOUT; i++) {
1899 if (ni_readl(AIFIFO_Status_6143) & 0x01) {
1900 ni_writel(0x01, AIFIFO_Control_6143); /* Get stranded sample into FIFO */
1901 dl = ni_readl(AIFIFO_Data_6143);
1902 break;
1903 }
1904 }
1905 if (i == NI_TIMEOUT) {
1906 printk
1907 ("ni_mio_common: timeout in 6143 ni_ai_insn_read\n");
1908 return -ETIME;
1909 }
1910 data[n] = (((dl >> 16) & 0xFFFF) + signbits) & 0xFFFF;
1911 }
1912 } else {
1913 for (n = 0; n < insn->n; n++) {
1914 devpriv->stc_writew(dev, AI_CONVERT_Pulse,
1915 AI_Command_1_Register);
1916 for (i = 0; i < NI_TIMEOUT; i++) {
1917 if (!(devpriv->stc_readw(dev,
1918 AI_Status_1_Register) &
1919 AI_FIFO_Empty_St))
1920 break;
1921 }
1922 if (i == NI_TIMEOUT) {
1923 printk
1924 ("ni_mio_common: timeout in ni_ai_insn_read\n");
1925 return -ETIME;
1926 }
1927 if (board->reg_type & ni_reg_m_series_mask) {
1928 data[n] =
1929 ni_readl(M_Offset_AI_FIFO_Data) & mask;
1930 } else {
1931 d = ni_readw(ADC_FIFO_Data_Register);
1932 d += signbits; /* subtle: needs to be short addition */
1933 data[n] = d;
1934 }
1935 }
1936 }
1937 return insn->n;
1938 }
1939
1940 static void ni_prime_channelgain_list(struct comedi_device *dev)
1941 {
1942 struct ni_private *devpriv = dev->private;
1943 int i;
1944
1945 devpriv->stc_writew(dev, AI_CONVERT_Pulse, AI_Command_1_Register);
1946 for (i = 0; i < NI_TIMEOUT; ++i) {
1947 if (!(devpriv->stc_readw(dev,
1948 AI_Status_1_Register) &
1949 AI_FIFO_Empty_St)) {
1950 devpriv->stc_writew(dev, 1, ADC_FIFO_Clear);
1951 return;
1952 }
1953 udelay(1);
1954 }
1955 printk("ni_mio_common: timeout loading channel/gain list\n");
1956 }
1957
1958 static void ni_m_series_load_channelgain_list(struct comedi_device *dev,
1959 unsigned int n_chan,
1960 unsigned int *list)
1961 {
1962 const struct ni_board_struct *board = comedi_board(dev);
1963 struct ni_private *devpriv = dev->private;
1964 unsigned int chan, range, aref;
1965 unsigned int i;
1966 unsigned offset;
1967 unsigned int dither;
1968 unsigned range_code;
1969
1970 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
1971
1972 /* offset = 1 << (board->adbits - 1); */
1973 if ((list[0] & CR_ALT_SOURCE)) {
1974 unsigned bypass_bits;
1975 chan = CR_CHAN(list[0]);
1976 range = CR_RANGE(list[0]);
1977 range_code = ni_gainlkup[board->gainlkup][range];
1978 dither = ((list[0] & CR_ALT_FILTER) != 0);
1979 bypass_bits = MSeries_AI_Bypass_Config_FIFO_Bit;
1980 bypass_bits |= chan;
1981 bypass_bits |=
1982 (devpriv->ai_calib_source) &
1983 (MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
1984 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
1985 MSeries_AI_Bypass_Mode_Mux_Mask |
1986 MSeries_AO_Bypass_AO_Cal_Sel_Mask);
1987 bypass_bits |= MSeries_AI_Bypass_Gain_Bits(range_code);
1988 if (dither)
1989 bypass_bits |= MSeries_AI_Bypass_Dither_Bit;
1990 /* don't use 2's complement encoding */
1991 bypass_bits |= MSeries_AI_Bypass_Polarity_Bit;
1992 ni_writel(bypass_bits, M_Offset_AI_Config_FIFO_Bypass);
1993 } else {
1994 ni_writel(0, M_Offset_AI_Config_FIFO_Bypass);
1995 }
1996 offset = 0;
1997 for (i = 0; i < n_chan; i++) {
1998 unsigned config_bits = 0;
1999 chan = CR_CHAN(list[i]);
2000 aref = CR_AREF(list[i]);
2001 range = CR_RANGE(list[i]);
2002 dither = ((list[i] & CR_ALT_FILTER) != 0);
2003
2004 range_code = ni_gainlkup[board->gainlkup][range];
2005 devpriv->ai_offset[i] = offset;
2006 switch (aref) {
2007 case AREF_DIFF:
2008 config_bits |=
2009 MSeries_AI_Config_Channel_Type_Differential_Bits;
2010 break;
2011 case AREF_COMMON:
2012 config_bits |=
2013 MSeries_AI_Config_Channel_Type_Common_Ref_Bits;
2014 break;
2015 case AREF_GROUND:
2016 config_bits |=
2017 MSeries_AI_Config_Channel_Type_Ground_Ref_Bits;
2018 break;
2019 case AREF_OTHER:
2020 break;
2021 }
2022 config_bits |= MSeries_AI_Config_Channel_Bits(chan);
2023 config_bits |=
2024 MSeries_AI_Config_Bank_Bits(board->reg_type, chan);
2025 config_bits |= MSeries_AI_Config_Gain_Bits(range_code);
2026 if (i == n_chan - 1)
2027 config_bits |= MSeries_AI_Config_Last_Channel_Bit;
2028 if (dither)
2029 config_bits |= MSeries_AI_Config_Dither_Bit;
2030 /* don't use 2's complement encoding */
2031 config_bits |= MSeries_AI_Config_Polarity_Bit;
2032 ni_writew(config_bits, M_Offset_AI_Config_FIFO_Data);
2033 }
2034 ni_prime_channelgain_list(dev);
2035 }
2036
2037 /*
2038 * Notes on the 6110 and 6111:
2039 * These boards a slightly different than the rest of the series, since
2040 * they have multiple A/D converters.
2041 * From the driver side, the configuration memory is a
2042 * little different.
2043 * Configuration Memory Low:
2044 * bits 15-9: same
2045 * bit 8: unipolar/bipolar (should be 0 for bipolar)
2046 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
2047 * 1001 gain=0.1 (+/- 50)
2048 * 1010 0.2
2049 * 1011 0.1
2050 * 0001 1
2051 * 0010 2
2052 * 0011 5
2053 * 0100 10
2054 * 0101 20
2055 * 0110 50
2056 * Configuration Memory High:
2057 * bits 12-14: Channel Type
2058 * 001 for differential
2059 * 000 for calibration
2060 * bit 11: coupling (this is not currently handled)
2061 * 1 AC coupling
2062 * 0 DC coupling
2063 * bits 0-2: channel
2064 * valid channels are 0-3
2065 */
2066 static void ni_load_channelgain_list(struct comedi_device *dev,
2067 unsigned int n_chan, unsigned int *list)
2068 {
2069 const struct ni_board_struct *board = comedi_board(dev);
2070 struct ni_private *devpriv = dev->private;
2071 unsigned int chan, range, aref;
2072 unsigned int i;
2073 unsigned int hi, lo;
2074 unsigned offset;
2075 unsigned int dither;
2076
2077 if (board->reg_type & ni_reg_m_series_mask) {
2078 ni_m_series_load_channelgain_list(dev, n_chan, list);
2079 return;
2080 }
2081 if (n_chan == 1 && (board->reg_type != ni_reg_611x)
2082 && (board->reg_type != ni_reg_6143)) {
2083 if (devpriv->changain_state
2084 && devpriv->changain_spec == list[0]) {
2085 /* ready to go. */
2086 return;
2087 }
2088 devpriv->changain_state = 1;
2089 devpriv->changain_spec = list[0];
2090 } else {
2091 devpriv->changain_state = 0;
2092 }
2093
2094 devpriv->stc_writew(dev, 1, Configuration_Memory_Clear);
2095
2096 /* Set up Calibration mode if required */
2097 if (board->reg_type == ni_reg_6143) {
2098 if ((list[0] & CR_ALT_SOURCE)
2099 && !devpriv->ai_calib_source_enabled) {
2100 /* Strobe Relay enable bit */
2101 ni_writew(devpriv->ai_calib_source |
2102 Calibration_Channel_6143_RelayOn,
2103 Calibration_Channel_6143);
2104 ni_writew(devpriv->ai_calib_source,
2105 Calibration_Channel_6143);
2106 devpriv->ai_calib_source_enabled = 1;
2107 msleep_interruptible(100); /* Allow relays to change */
2108 } else if (!(list[0] & CR_ALT_SOURCE)
2109 && devpriv->ai_calib_source_enabled) {
2110 /* Strobe Relay disable bit */
2111 ni_writew(devpriv->ai_calib_source |
2112 Calibration_Channel_6143_RelayOff,
2113 Calibration_Channel_6143);
2114 ni_writew(devpriv->ai_calib_source,
2115 Calibration_Channel_6143);
2116 devpriv->ai_calib_source_enabled = 0;
2117 msleep_interruptible(100); /* Allow relays to change */
2118 }
2119 }
2120
2121 offset = 1 << (board->adbits - 1);
2122 for (i = 0; i < n_chan; i++) {
2123 if ((board->reg_type != ni_reg_6143)
2124 && (list[i] & CR_ALT_SOURCE)) {
2125 chan = devpriv->ai_calib_source;
2126 } else {
2127 chan = CR_CHAN(list[i]);
2128 }
2129 aref = CR_AREF(list[i]);
2130 range = CR_RANGE(list[i]);
2131 dither = ((list[i] & CR_ALT_FILTER) != 0);
2132
2133 /* fix the external/internal range differences */
2134 range = ni_gainlkup[board->gainlkup][range];
2135 if (board->reg_type == ni_reg_611x)
2136 devpriv->ai_offset[i] = offset;
2137 else
2138 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset;
2139
2140 hi = 0;
2141 if ((list[i] & CR_ALT_SOURCE)) {
2142 if (board->reg_type == ni_reg_611x)
2143 ni_writew(CR_CHAN(list[i]) & 0x0003,
2144 Calibration_Channel_Select_611x);
2145 } else {
2146 if (board->reg_type == ni_reg_611x)
2147 aref = AREF_DIFF;
2148 else if (board->reg_type == ni_reg_6143)
2149 aref = AREF_OTHER;
2150 switch (aref) {
2151 case AREF_DIFF:
2152 hi |= AI_DIFFERENTIAL;
2153 break;
2154 case AREF_COMMON:
2155 hi |= AI_COMMON;
2156 break;
2157 case AREF_GROUND:
2158 hi |= AI_GROUND;
2159 break;
2160 case AREF_OTHER:
2161 break;
2162 }
2163 }
2164 hi |= AI_CONFIG_CHANNEL(chan);
2165
2166 ni_writew(hi, Configuration_Memory_High);
2167
2168 if (board->reg_type != ni_reg_6143) {
2169 lo = range;
2170 if (i == n_chan - 1)
2171 lo |= AI_LAST_CHANNEL;
2172 if (dither)
2173 lo |= AI_DITHER;
2174
2175 ni_writew(lo, Configuration_Memory_Low);
2176 }
2177 }
2178
2179 /* prime the channel/gain list */
2180 if ((board->reg_type != ni_reg_611x)
2181 && (board->reg_type != ni_reg_6143)) {
2182 ni_prime_channelgain_list(dev);
2183 }
2184 }
2185
2186 static int ni_ns_to_timer(const struct comedi_device *dev, unsigned nanosec,
2187 int round_mode)
2188 {
2189 struct ni_private *devpriv = dev->private;
2190 int divider;
2191
2192 switch (round_mode) {
2193 case TRIG_ROUND_NEAREST:
2194 default:
2195 divider = (nanosec + devpriv->clock_ns / 2) / devpriv->clock_ns;
2196 break;
2197 case TRIG_ROUND_DOWN:
2198 divider = (nanosec) / devpriv->clock_ns;
2199 break;
2200 case TRIG_ROUND_UP:
2201 divider = (nanosec + devpriv->clock_ns - 1) / devpriv->clock_ns;
2202 break;
2203 }
2204 return divider - 1;
2205 }
2206
2207 static unsigned ni_timer_to_ns(const struct comedi_device *dev, int timer)
2208 {
2209 struct ni_private *devpriv = dev->private;
2210
2211 return devpriv->clock_ns * (timer + 1);
2212 }
2213
2214 static unsigned ni_min_ai_scan_period_ns(struct comedi_device *dev,
2215 unsigned num_channels)
2216 {
2217 const struct ni_board_struct *board = comedi_board(dev);
2218
2219 switch (board->reg_type) {
2220 case ni_reg_611x:
2221 case ni_reg_6143:
2222 /* simultaneously-sampled inputs */
2223 return board->ai_speed;
2224 break;
2225 default:
2226 /* multiplexed inputs */
2227 break;
2228 }
2229 return board->ai_speed * num_channels;
2230 }
2231
2232 static int ni_ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2233 struct comedi_cmd *cmd)
2234 {
2235 const struct ni_board_struct *board = comedi_board(dev);
2236 struct ni_private *devpriv = dev->private;
2237 int err = 0;
2238 int tmp;
2239 unsigned int sources;
2240
2241 /* Step 1 : check if triggers are trivially valid */
2242
2243 if ((cmd->flags & CMDF_WRITE))
2244 cmd->flags &= ~CMDF_WRITE;
2245
2246 err |= cfc_check_trigger_src(&cmd->start_src,
2247 TRIG_NOW | TRIG_INT | TRIG_EXT);
2248 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
2249 TRIG_TIMER | TRIG_EXT);
2250
2251 sources = TRIG_TIMER | TRIG_EXT;
2252 if (board->reg_type == ni_reg_611x ||
2253 board->reg_type == ni_reg_6143)
2254 sources |= TRIG_NOW;
2255 err |= cfc_check_trigger_src(&cmd->convert_src, sources);
2256
2257 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2258 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2259
2260 if (err)
2261 return 1;
2262
2263 /* Step 2a : make sure trigger sources are unique */
2264
2265 err |= cfc_check_trigger_is_unique(cmd->start_src);
2266 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2267 err |= cfc_check_trigger_is_unique(cmd->convert_src);
2268 err |= cfc_check_trigger_is_unique(cmd->stop_src);
2269
2270 /* Step 2b : and mutually compatible */
2271
2272 if (err)
2273 return 2;
2274
2275 /* Step 3: check if arguments are trivially valid */
2276
2277 if (cmd->start_src == TRIG_EXT) {
2278 /* external trigger */
2279 unsigned int tmp = CR_CHAN(cmd->start_arg);
2280
2281 if (tmp > 16)
2282 tmp = 16;
2283 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
2284 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
2285 } else {
2286 /* true for both TRIG_NOW and TRIG_INT */
2287 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2288 }
2289
2290 if (cmd->scan_begin_src == TRIG_TIMER) {
2291 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
2292 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len));
2293 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
2294 devpriv->clock_ns * 0xffffff);
2295 } else if (cmd->scan_begin_src == TRIG_EXT) {
2296 /* external trigger */
2297 unsigned int tmp = CR_CHAN(cmd->scan_begin_arg);
2298
2299 if (tmp > 16)
2300 tmp = 16;
2301 tmp |= (cmd->scan_begin_arg & (CR_INVERT | CR_EDGE));
2302 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, tmp);
2303 } else { /* TRIG_OTHER */
2304 err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
2305 }
2306
2307 if (cmd->convert_src == TRIG_TIMER) {
2308 if ((board->reg_type == ni_reg_611x)
2309 || (board->reg_type == ni_reg_6143)) {
2310 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2311 } else {
2312 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2313 board->ai_speed);
2314 err |= cfc_check_trigger_arg_max(&cmd->convert_arg,
2315 devpriv->clock_ns * 0xffff);
2316 }
2317 } else if (cmd->convert_src == TRIG_EXT) {
2318 /* external trigger */
2319 unsigned int tmp = CR_CHAN(cmd->convert_arg);
2320
2321 if (tmp > 16)
2322 tmp = 16;
2323 tmp |= (cmd->convert_arg & (CR_ALT_FILTER | CR_INVERT));
2324 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, tmp);
2325 } else if (cmd->convert_src == TRIG_NOW) {
2326 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2327 }
2328
2329 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2330
2331 if (cmd->stop_src == TRIG_COUNT) {
2332 unsigned int max_count = 0x01000000;
2333
2334 if (board->reg_type == ni_reg_611x)
2335 max_count -= num_adc_stages_611x;
2336 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, max_count);
2337 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2338 } else {
2339 /* TRIG_NONE */
2340 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2341 }
2342
2343 if (err)
2344 return 3;
2345
2346 /* step 4: fix up any arguments */
2347
2348 if (cmd->scan_begin_src == TRIG_TIMER) {
2349 tmp = cmd->scan_begin_arg;
2350 cmd->scan_begin_arg =
2351 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2352 cmd->scan_begin_arg,
2353 cmd->
2354 flags &
2355 TRIG_ROUND_MASK));
2356 if (tmp != cmd->scan_begin_arg)
2357 err++;
2358 }
2359 if (cmd->convert_src == TRIG_TIMER) {
2360 if ((board->reg_type != ni_reg_611x)
2361 && (board->reg_type != ni_reg_6143)) {
2362 tmp = cmd->convert_arg;
2363 cmd->convert_arg =
2364 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
2365 cmd->convert_arg,
2366 cmd->
2367 flags &
2368 TRIG_ROUND_MASK));
2369 if (tmp != cmd->convert_arg)
2370 err++;
2371 if (cmd->scan_begin_src == TRIG_TIMER &&
2372 cmd->scan_begin_arg <
2373 cmd->convert_arg * cmd->scan_end_arg) {
2374 cmd->scan_begin_arg =
2375 cmd->convert_arg * cmd->scan_end_arg;
2376 err++;
2377 }
2378 }
2379 }
2380
2381 if (err)
2382 return 4;
2383
2384 return 0;
2385 }
2386
2387 static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2388 {
2389 const struct ni_board_struct *board = comedi_board(dev);
2390 struct ni_private *devpriv = dev->private;
2391 const struct comedi_cmd *cmd = &s->async->cmd;
2392 int timer;
2393 int mode1 = 0; /* mode1 is needed for both stop and convert */
2394 int mode2 = 0;
2395 int start_stop_select = 0;
2396 unsigned int stop_count;
2397 int interrupt_a_enable = 0;
2398
2399 MDPRINTK("ni_ai_cmd\n");
2400 if (dev->irq == 0) {
2401 comedi_error(dev, "cannot run command without an irq");
2402 return -EIO;
2403 }
2404 ni_clear_ai_fifo(dev);
2405
2406 ni_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist);
2407
2408 /* start configuration */
2409 devpriv->stc_writew(dev, AI_Configuration_Start, Joint_Reset_Register);
2410
2411 /* disable analog triggering for now, since it
2412 * interferes with the use of pfi0 */
2413 devpriv->an_trig_etc_reg &= ~Analog_Trigger_Enable;
2414 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
2415 Analog_Trigger_Etc_Register);
2416
2417 switch (cmd->start_src) {
2418 case TRIG_INT:
2419 case TRIG_NOW:
2420 devpriv->stc_writew(dev, AI_START2_Select(0) |
2421 AI_START1_Sync | AI_START1_Edge |
2422 AI_START1_Select(0),
2423 AI_Trigger_Select_Register);
2424 break;
2425 case TRIG_EXT:
2426 {
2427 int chan = CR_CHAN(cmd->start_arg);
2428 unsigned int bits = AI_START2_Select(0) |
2429 AI_START1_Sync | AI_START1_Select(chan + 1);
2430
2431 if (cmd->start_arg & CR_INVERT)
2432 bits |= AI_START1_Polarity;
2433 if (cmd->start_arg & CR_EDGE)
2434 bits |= AI_START1_Edge;
2435 devpriv->stc_writew(dev, bits,
2436 AI_Trigger_Select_Register);
2437 break;
2438 }
2439 }
2440
2441 mode2 &= ~AI_Pre_Trigger;
2442 mode2 &= ~AI_SC_Initial_Load_Source;
2443 mode2 &= ~AI_SC_Reload_Mode;
2444 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2445
2446 if (cmd->chanlist_len == 1 || (board->reg_type == ni_reg_611x)
2447 || (board->reg_type == ni_reg_6143)) {
2448 start_stop_select |= AI_STOP_Polarity;
2449 start_stop_select |= AI_STOP_Select(31); /* logic low */
2450 start_stop_select |= AI_STOP_Sync;
2451 } else {
2452 start_stop_select |= AI_STOP_Select(19); /* ai configuration memory */
2453 }
2454 devpriv->stc_writew(dev, start_stop_select,
2455 AI_START_STOP_Select_Register);
2456
2457 devpriv->ai_cmd2 = 0;
2458 switch (cmd->stop_src) {
2459 case TRIG_COUNT:
2460 stop_count = cmd->stop_arg - 1;
2461
2462 if (board->reg_type == ni_reg_611x) {
2463 /* have to take 3 stage adc pipeline into account */
2464 stop_count += num_adc_stages_611x;
2465 }
2466 /* stage number of scans */
2467 devpriv->stc_writel(dev, stop_count, AI_SC_Load_A_Registers);
2468
2469 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Trigger_Once;
2470 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2471 /* load SC (Scan Count) */
2472 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2473
2474 devpriv->ai_continuous = 0;
2475 if (stop_count == 0) {
2476 devpriv->ai_cmd2 |= AI_End_On_End_Of_Scan;
2477 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2478 /* this is required to get the last sample for chanlist_len > 1, not sure why */
2479 if (cmd->chanlist_len > 1)
2480 start_stop_select |=
2481 AI_STOP_Polarity | AI_STOP_Edge;
2482 }
2483 break;
2484 case TRIG_NONE:
2485 /* stage number of scans */
2486 devpriv->stc_writel(dev, 0, AI_SC_Load_A_Registers);
2487
2488 mode1 |= AI_Start_Stop | AI_Mode_1_Reserved | AI_Continuous;
2489 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2490
2491 /* load SC (Scan Count) */
2492 devpriv->stc_writew(dev, AI_SC_Load, AI_Command_1_Register);
2493
2494 devpriv->ai_continuous = 1;
2495
2496 break;
2497 }
2498
2499 switch (cmd->scan_begin_src) {
2500 case TRIG_TIMER:
2501 /*
2502 stop bits for non 611x boards
2503 AI_SI_Special_Trigger_Delay=0
2504 AI_Pre_Trigger=0
2505 AI_START_STOP_Select_Register:
2506 AI_START_Polarity=0 (?) rising edge
2507 AI_START_Edge=1 edge triggered
2508 AI_START_Sync=1 (?)
2509 AI_START_Select=0 SI_TC
2510 AI_STOP_Polarity=0 rising edge
2511 AI_STOP_Edge=0 level
2512 AI_STOP_Sync=1
2513 AI_STOP_Select=19 external pin (configuration mem)
2514 */
2515 start_stop_select |= AI_START_Edge | AI_START_Sync;
2516 devpriv->stc_writew(dev, start_stop_select,
2517 AI_START_STOP_Select_Register);
2518
2519 mode2 |= AI_SI_Reload_Mode(0);
2520 /* AI_SI_Initial_Load_Source=A */
2521 mode2 &= ~AI_SI_Initial_Load_Source;
2522 /* mode2 |= AI_SC_Reload_Mode; */
2523 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2524
2525 /* load SI */
2526 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg,
2527 TRIG_ROUND_NEAREST);
2528 devpriv->stc_writel(dev, timer, AI_SI_Load_A_Registers);
2529 devpriv->stc_writew(dev, AI_SI_Load, AI_Command_1_Register);
2530 break;
2531 case TRIG_EXT:
2532 if (cmd->scan_begin_arg & CR_EDGE)
2533 start_stop_select |= AI_START_Edge;
2534 /* AI_START_Polarity==1 is falling edge */
2535 if (cmd->scan_begin_arg & CR_INVERT)
2536 start_stop_select |= AI_START_Polarity;
2537 if (cmd->scan_begin_src != cmd->convert_src ||
2538 (cmd->scan_begin_arg & ~CR_EDGE) !=
2539 (cmd->convert_arg & ~CR_EDGE))
2540 start_stop_select |= AI_START_Sync;
2541 start_stop_select |=
2542 AI_START_Select(1 + CR_CHAN(cmd->scan_begin_arg));
2543 devpriv->stc_writew(dev, start_stop_select,
2544 AI_START_STOP_Select_Register);
2545 break;
2546 }
2547
2548 switch (cmd->convert_src) {
2549 case TRIG_TIMER:
2550 case TRIG_NOW:
2551 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW)
2552 timer = 1;
2553 else
2554 timer = ni_ns_to_timer(dev, cmd->convert_arg,
2555 TRIG_ROUND_NEAREST);
2556 devpriv->stc_writew(dev, 1, AI_SI2_Load_A_Register); /* 0,0 does not work. */
2557 devpriv->stc_writew(dev, timer, AI_SI2_Load_B_Register);
2558
2559 /* AI_SI2_Reload_Mode = alternate */
2560 /* AI_SI2_Initial_Load_Source = A */
2561 mode2 &= ~AI_SI2_Initial_Load_Source;
2562 mode2 |= AI_SI2_Reload_Mode;
2563 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2564
2565 /* AI_SI2_Load */
2566 devpriv->stc_writew(dev, AI_SI2_Load, AI_Command_1_Register);
2567
2568 mode2 |= AI_SI2_Reload_Mode; /* alternate */
2569 mode2 |= AI_SI2_Initial_Load_Source; /* B */
2570
2571 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2572 break;
2573 case TRIG_EXT:
2574 mode1 |= AI_CONVERT_Source_Select(1 + cmd->convert_arg);
2575 if ((cmd->convert_arg & CR_INVERT) == 0)
2576 mode1 |= AI_CONVERT_Source_Polarity;
2577 devpriv->stc_writew(dev, mode1, AI_Mode_1_Register);
2578
2579 mode2 |= AI_Start_Stop_Gate_Enable | AI_SC_Gate_Enable;
2580 devpriv->stc_writew(dev, mode2, AI_Mode_2_Register);
2581
2582 break;
2583 }
2584
2585 if (dev->irq) {
2586
2587 /* interrupt on FIFO, errors, SC_TC */
2588 interrupt_a_enable |= AI_Error_Interrupt_Enable |
2589 AI_SC_TC_Interrupt_Enable;
2590
2591 #ifndef PCIDMA
2592 interrupt_a_enable |= AI_FIFO_Interrupt_Enable;
2593 #endif
2594
2595 if (cmd->flags & TRIG_WAKE_EOS
2596 || (devpriv->ai_cmd2 & AI_End_On_End_Of_Scan)) {
2597 /* wake on end-of-scan */
2598 devpriv->aimode = AIMODE_SCAN;
2599 } else {
2600 devpriv->aimode = AIMODE_HALF_FULL;
2601 }
2602
2603 switch (devpriv->aimode) {
2604 case AIMODE_HALF_FULL:
2605 /*generate FIFO interrupts and DMA requests on half-full */
2606 #ifdef PCIDMA
2607 devpriv->stc_writew(dev, AI_FIFO_Mode_HF_to_E,
2608 AI_Mode_3_Register);
2609 #else
2610 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2611 AI_Mode_3_Register);
2612 #endif
2613 break;
2614 case AIMODE_SAMPLE:
2615 /*generate FIFO interrupts on non-empty */
2616 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2617 AI_Mode_3_Register);
2618 break;
2619 case AIMODE_SCAN:
2620 #ifdef PCIDMA
2621 devpriv->stc_writew(dev, AI_FIFO_Mode_NE,
2622 AI_Mode_3_Register);
2623 #else
2624 devpriv->stc_writew(dev, AI_FIFO_Mode_HF,
2625 AI_Mode_3_Register);
2626 #endif
2627 interrupt_a_enable |= AI_STOP_Interrupt_Enable;
2628 break;
2629 default:
2630 break;
2631 }
2632
2633 devpriv->stc_writew(dev, AI_Error_Interrupt_Ack | AI_STOP_Interrupt_Ack | AI_START_Interrupt_Ack | AI_START2_Interrupt_Ack | AI_START1_Interrupt_Ack | AI_SC_TC_Interrupt_Ack | AI_SC_TC_Error_Confirm, Interrupt_A_Ack_Register); /* clear interrupts */
2634
2635 ni_set_bits(dev, Interrupt_A_Enable_Register,
2636 interrupt_a_enable, 1);
2637
2638 MDPRINTK("Interrupt_A_Enable_Register = 0x%04x\n",
2639 devpriv->int_a_enable_reg);
2640 } else {
2641 /* interrupt on nothing */
2642 ni_set_bits(dev, Interrupt_A_Enable_Register, ~0, 0);
2643
2644 /* XXX start polling if necessary */
2645 MDPRINTK("interrupting on nothing\n");
2646 }
2647
2648 /* end configuration */
2649 devpriv->stc_writew(dev, AI_Configuration_End, Joint_Reset_Register);
2650
2651 switch (cmd->scan_begin_src) {
2652 case TRIG_TIMER:
2653 devpriv->stc_writew(dev,
2654 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2655 AI_SC_Arm, AI_Command_1_Register);
2656 break;
2657 case TRIG_EXT:
2658 /* XXX AI_SI_Arm? */
2659 devpriv->stc_writew(dev,
2660 AI_SI2_Arm | AI_SI_Arm | AI_DIV_Arm |
2661 AI_SC_Arm, AI_Command_1_Register);
2662 break;
2663 }
2664
2665 #ifdef PCIDMA
2666 {
2667 int retval = ni_ai_setup_MITE_dma(dev);
2668 if (retval)
2669 return retval;
2670 }
2671 /* mite_dump_regs(devpriv->mite); */
2672 #endif
2673
2674 switch (cmd->start_src) {
2675 case TRIG_NOW:
2676 /* AI_START1_Pulse */
2677 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2678 AI_Command_2_Register);
2679 s->async->inttrig = NULL;
2680 break;
2681 case TRIG_EXT:
2682 s->async->inttrig = NULL;
2683 break;
2684 case TRIG_INT:
2685 s->async->inttrig = &ni_ai_inttrig;
2686 break;
2687 }
2688
2689 MDPRINTK("exit ni_ai_cmd\n");
2690
2691 return 0;
2692 }
2693
2694 static int ni_ai_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
2695 unsigned int trignum)
2696 {
2697 struct ni_private *devpriv = dev->private;
2698
2699 if (trignum != 0)
2700 return -EINVAL;
2701
2702 devpriv->stc_writew(dev, AI_START1_Pulse | devpriv->ai_cmd2,
2703 AI_Command_2_Register);
2704 s->async->inttrig = NULL;
2705
2706 return 1;
2707 }
2708
2709 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2710 struct comedi_subdevice *s,
2711 struct comedi_insn *insn,
2712 unsigned int *data);
2713
2714 static int ni_ai_insn_config(struct comedi_device *dev,
2715 struct comedi_subdevice *s,
2716 struct comedi_insn *insn, unsigned int *data)
2717 {
2718 const struct ni_board_struct *board = comedi_board(dev);
2719 struct ni_private *devpriv = dev->private;
2720
2721 if (insn->n < 1)
2722 return -EINVAL;
2723
2724 switch (data[0]) {
2725 case INSN_CONFIG_ANALOG_TRIG:
2726 return ni_ai_config_analog_trig(dev, s, insn, data);
2727 case INSN_CONFIG_ALT_SOURCE:
2728 if (board->reg_type & ni_reg_m_series_mask) {
2729 if (data[1] & ~(MSeries_AI_Bypass_Cal_Sel_Pos_Mask |
2730 MSeries_AI_Bypass_Cal_Sel_Neg_Mask |
2731 MSeries_AI_Bypass_Mode_Mux_Mask |
2732 MSeries_AO_Bypass_AO_Cal_Sel_Mask)) {
2733 return -EINVAL;
2734 }
2735 devpriv->ai_calib_source = data[1];
2736 } else if (board->reg_type == ni_reg_6143) {
2737 unsigned int calib_source;
2738
2739 calib_source = data[1] & 0xf;
2740
2741 if (calib_source > 0xF)
2742 return -EINVAL;
2743
2744 devpriv->ai_calib_source = calib_source;
2745 ni_writew(calib_source, Calibration_Channel_6143);
2746 } else {
2747 unsigned int calib_source;
2748 unsigned int calib_source_adjust;
2749
2750 calib_source = data[1] & 0xf;
2751 calib_source_adjust = (data[1] >> 4) & 0xff;
2752
2753 if (calib_source >= 8)
2754 return -EINVAL;
2755 devpriv->ai_calib_source = calib_source;
2756 if (board->reg_type == ni_reg_611x) {
2757 ni_writeb(calib_source_adjust,
2758 Cal_Gain_Select_611x);
2759 }
2760 }
2761 return 2;
2762 default:
2763 break;
2764 }
2765
2766 return -EINVAL;
2767 }
2768
2769 static int ni_ai_config_analog_trig(struct comedi_device *dev,
2770 struct comedi_subdevice *s,
2771 struct comedi_insn *insn,
2772 unsigned int *data)
2773 {
2774 const struct ni_board_struct *board = comedi_board(dev);
2775 struct ni_private *devpriv = dev->private;
2776 unsigned int a, b, modebits;
2777 int err = 0;
2778
2779 /* data[1] is flags
2780 * data[2] is analog line
2781 * data[3] is set level
2782 * data[4] is reset level */
2783 if (!board->has_analog_trig)
2784 return -EINVAL;
2785 if ((data[1] & 0xffff0000) != COMEDI_EV_SCAN_BEGIN) {
2786 data[1] &= (COMEDI_EV_SCAN_BEGIN | 0xffff);
2787 err++;
2788 }
2789 if (data[2] >= board->n_adchan) {
2790 data[2] = board->n_adchan - 1;
2791 err++;
2792 }
2793 if (data[3] > 255) { /* a */
2794 data[3] = 255;
2795 err++;
2796 }
2797 if (data[4] > 255) { /* b */
2798 data[4] = 255;
2799 err++;
2800 }
2801 /*
2802 * 00 ignore
2803 * 01 set
2804 * 10 reset
2805 *
2806 * modes:
2807 * 1 level: +b- +a-
2808 * high mode 00 00 01 10
2809 * low mode 00 00 10 01
2810 * 2 level: (a<b)
2811 * hysteresis low mode 10 00 00 01
2812 * hysteresis high mode 01 00 00 10
2813 * middle mode 10 01 01 10
2814 */
2815
2816 a = data[3];
2817 b = data[4];
2818 modebits = data[1] & 0xff;
2819 if (modebits & 0xf0) {
2820 /* two level mode */
2821 if (b < a) {
2822 /* swap order */
2823 a = data[4];
2824 b = data[3];
2825 modebits =
2826 ((data[1] & 0xf) << 4) | ((data[1] & 0xf0) >> 4);
2827 }
2828 devpriv->atrig_low = a;
2829 devpriv->atrig_high = b;
2830 switch (modebits) {
2831 case 0x81: /* low hysteresis mode */
2832 devpriv->atrig_mode = 6;
2833 break;
2834 case 0x42: /* high hysteresis mode */
2835 devpriv->atrig_mode = 3;
2836 break;
2837 case 0x96: /* middle window mode */
2838 devpriv->atrig_mode = 2;
2839 break;
2840 default:
2841 data[1] &= ~0xff;
2842 err++;
2843 }
2844 } else {
2845 /* one level mode */
2846 if (b != 0) {
2847 data[4] = 0;
2848 err++;
2849 }
2850 switch (modebits) {
2851 case 0x06: /* high window mode */
2852 devpriv->atrig_high = a;
2853 devpriv->atrig_mode = 0;
2854 break;
2855 case 0x09: /* low window mode */
2856 devpriv->atrig_low = a;
2857 devpriv->atrig_mode = 1;
2858 break;
2859 default:
2860 data[1] &= ~0xff;
2861 err++;
2862 }
2863 }
2864 if (err)
2865 return -EAGAIN;
2866 return 5;
2867 }
2868
2869 /* munge data from unsigned to 2's complement for analog output bipolar modes */
2870 static void ni_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
2871 void *data, unsigned int num_bytes,
2872 unsigned int chan_index)
2873 {
2874 const struct ni_board_struct *board = comedi_board(dev);
2875 struct comedi_async *async = s->async;
2876 unsigned int range;
2877 unsigned int i;
2878 unsigned int offset;
2879 unsigned int length = num_bytes / sizeof(short);
2880 short *array = data;
2881
2882 offset = 1 << (board->aobits - 1);
2883 for (i = 0; i < length; i++) {
2884 range = CR_RANGE(async->cmd.chanlist[chan_index]);
2885 if (board->ao_unipolar == 0 || (range & 1) == 0)
2886 array[i] -= offset;
2887 #ifdef PCIDMA
2888 array[i] = cpu_to_le16(array[i]);
2889 #endif
2890 chan_index++;
2891 chan_index %= async->cmd.chanlist_len;
2892 }
2893 }
2894
2895 static int ni_m_series_ao_config_chanlist(struct comedi_device *dev,
2896 struct comedi_subdevice *s,
2897 unsigned int chanspec[],
2898 unsigned int n_chans, int timed)
2899 {
2900 const struct ni_board_struct *board = comedi_board(dev);
2901 struct ni_private *devpriv = dev->private;
2902 unsigned int range;
2903 unsigned int chan;
2904 unsigned int conf;
2905 int i;
2906 int invert = 0;
2907
2908 if (timed) {
2909 for (i = 0; i < board->n_aochan; ++i) {
2910 devpriv->ao_conf[i] &= ~MSeries_AO_Update_Timed_Bit;
2911 ni_writeb(devpriv->ao_conf[i],
2912 M_Offset_AO_Config_Bank(i));
2913 ni_writeb(0xf, M_Offset_AO_Waveform_Order(i));
2914 }
2915 }
2916 for (i = 0; i < n_chans; i++) {
2917 const struct comedi_krange *krange;
2918 chan = CR_CHAN(chanspec[i]);
2919 range = CR_RANGE(chanspec[i]);
2920 krange = s->range_table->range + range;
2921 invert = 0;
2922 conf = 0;
2923 switch (krange->max - krange->min) {
2924 case 20000000:
2925 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2926 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2927 break;
2928 case 10000000:
2929 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2930 ni_writeb(0, M_Offset_AO_Reference_Attenuation(chan));
2931 break;
2932 case 4000000:
2933 conf |= MSeries_AO_DAC_Reference_10V_Internal_Bits;
2934 ni_writeb(MSeries_Attenuate_x5_Bit,
2935 M_Offset_AO_Reference_Attenuation(chan));
2936 break;
2937 case 2000000:
2938 conf |= MSeries_AO_DAC_Reference_5V_Internal_Bits;
2939 ni_writeb(MSeries_Attenuate_x5_Bit,
2940 M_Offset_AO_Reference_Attenuation(chan));
2941 break;
2942 default:
2943 printk("%s: bug! unhandled ao reference voltage\n",
2944 __func__);
2945 break;
2946 }
2947 switch (krange->max + krange->min) {
2948 case 0:
2949 conf |= MSeries_AO_DAC_Offset_0V_Bits;
2950 break;
2951 case 10000000:
2952 conf |= MSeries_AO_DAC_Offset_5V_Bits;
2953 break;
2954 default:
2955 printk("%s: bug! unhandled ao offset voltage\n",
2956 __func__);
2957 break;
2958 }
2959 if (timed)
2960 conf |= MSeries_AO_Update_Timed_Bit;
2961 ni_writeb(conf, M_Offset_AO_Config_Bank(chan));
2962 devpriv->ao_conf[chan] = conf;
2963 ni_writeb(i, M_Offset_AO_Waveform_Order(chan));
2964 }
2965 return invert;
2966 }
2967
2968 static int ni_old_ao_config_chanlist(struct comedi_device *dev,
2969 struct comedi_subdevice *s,
2970 unsigned int chanspec[],
2971 unsigned int n_chans)
2972 {
2973 const struct ni_board_struct *board = comedi_board(dev);
2974 struct ni_private *devpriv = dev->private;
2975 unsigned int range;
2976 unsigned int chan;
2977 unsigned int conf;
2978 int i;
2979 int invert = 0;
2980
2981 for (i = 0; i < n_chans; i++) {
2982 chan = CR_CHAN(chanspec[i]);
2983 range = CR_RANGE(chanspec[i]);
2984 conf = AO_Channel(chan);
2985
2986 if (board->ao_unipolar) {
2987 if ((range & 1) == 0) {
2988 conf |= AO_Bipolar;
2989 invert = (1 << (board->aobits - 1));
2990 } else {
2991 invert = 0;
2992 }
2993 if (range & 2)
2994 conf |= AO_Ext_Ref;
2995 } else {
2996 conf |= AO_Bipolar;
2997 invert = (1 << (board->aobits - 1));
2998 }
2999
3000 /* not all boards can deglitch, but this shouldn't hurt */
3001 if (chanspec[i] & CR_DEGLITCH)
3002 conf |= AO_Deglitch;
3003
3004 /* analog reference */
3005 /* AREF_OTHER connects AO ground to AI ground, i think */
3006 conf |= (CR_AREF(chanspec[i]) ==
3007 AREF_OTHER) ? AO_Ground_Ref : 0;
3008
3009 ni_writew(conf, AO_Configuration);
3010 devpriv->ao_conf[chan] = conf;
3011 }
3012 return invert;
3013 }
3014
3015 static int ni_ao_config_chanlist(struct comedi_device *dev,
3016 struct comedi_subdevice *s,
3017 unsigned int chanspec[], unsigned int n_chans,
3018 int timed)
3019 {
3020 const struct ni_board_struct *board = comedi_board(dev);
3021
3022 if (board->reg_type & ni_reg_m_series_mask)
3023 return ni_m_series_ao_config_chanlist(dev, s, chanspec, n_chans,
3024 timed);
3025 else
3026 return ni_old_ao_config_chanlist(dev, s, chanspec, n_chans);
3027 }
3028
3029 static int ni_ao_insn_read(struct comedi_device *dev,
3030 struct comedi_subdevice *s, struct comedi_insn *insn,
3031 unsigned int *data)
3032 {
3033 struct ni_private *devpriv = dev->private;
3034
3035 data[0] = devpriv->ao[CR_CHAN(insn->chanspec)];
3036
3037 return 1;
3038 }
3039
3040 static int ni_ao_insn_write(struct comedi_device *dev,
3041 struct comedi_subdevice *s,
3042 struct comedi_insn *insn, unsigned int *data)
3043 {
3044 const struct ni_board_struct *board = comedi_board(dev);
3045 struct ni_private *devpriv = dev->private;
3046 unsigned int chan = CR_CHAN(insn->chanspec);
3047 unsigned int invert;
3048
3049 invert = ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3050
3051 devpriv->ao[chan] = data[0];
3052
3053 if (board->reg_type & ni_reg_m_series_mask) {
3054 ni_writew(data[0], M_Offset_DAC_Direct_Data(chan));
3055 } else
3056 ni_writew(data[0] ^ invert,
3057 (chan) ? DAC1_Direct_Data : DAC0_Direct_Data);
3058
3059 return 1;
3060 }
3061
3062 static int ni_ao_insn_write_671x(struct comedi_device *dev,
3063 struct comedi_subdevice *s,
3064 struct comedi_insn *insn, unsigned int *data)
3065 {
3066 const struct ni_board_struct *board = comedi_board(dev);
3067 struct ni_private *devpriv = dev->private;
3068 unsigned int chan = CR_CHAN(insn->chanspec);
3069 unsigned int invert;
3070
3071 ao_win_out(1 << chan, AO_Immediate_671x);
3072 invert = 1 << (board->aobits - 1);
3073
3074 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0);
3075
3076 devpriv->ao[chan] = data[0];
3077 ao_win_out(data[0] ^ invert, DACx_Direct_Data_671x(chan));
3078
3079 return 1;
3080 }
3081
3082 static int ni_ao_insn_config(struct comedi_device *dev,
3083 struct comedi_subdevice *s,
3084 struct comedi_insn *insn, unsigned int *data)
3085 {
3086 const struct ni_board_struct *board = comedi_board(dev);
3087 struct ni_private *devpriv = dev->private;
3088
3089 switch (data[0]) {
3090 case INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE:
3091 switch (data[1]) {
3092 case COMEDI_OUTPUT:
3093 data[2] = 1 + board->ao_fifo_depth * sizeof(short);
3094 if (devpriv->mite)
3095 data[2] += devpriv->mite->fifo_size;
3096 break;
3097 case COMEDI_INPUT:
3098 data[2] = 0;
3099 break;
3100 default:
3101 return -EINVAL;
3102 break;
3103 }
3104 return 0;
3105 default:
3106 break;
3107 }
3108
3109 return -EINVAL;
3110 }
3111
3112 static int ni_ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3113 unsigned int trignum)
3114 {
3115 const struct ni_board_struct *board __maybe_unused = comedi_board(dev);
3116 struct ni_private *devpriv = dev->private;
3117 int ret;
3118 int interrupt_b_bits;
3119 int i;
3120 static const int timeout = 1000;
3121
3122 if (trignum != 0)
3123 return -EINVAL;
3124
3125 /* Null trig at beginning prevent ao start trigger from executing more than
3126 once per command (and doing things like trying to allocate the ao dma channel
3127 multiple times) */
3128 s->async->inttrig = NULL;
3129
3130 ni_set_bits(dev, Interrupt_B_Enable_Register,
3131 AO_FIFO_Interrupt_Enable | AO_Error_Interrupt_Enable, 0);
3132 interrupt_b_bits = AO_Error_Interrupt_Enable;
3133 #ifdef PCIDMA
3134 devpriv->stc_writew(dev, 1, DAC_FIFO_Clear);
3135 if (board->reg_type & ni_reg_6xxx_mask)
3136 ni_ao_win_outl(dev, 0x6, AO_FIFO_Offset_Load_611x);
3137 ret = ni_ao_setup_MITE_dma(dev);
3138 if (ret)
3139 return ret;
3140 ret = ni_ao_wait_for_dma_load(dev);
3141 if (ret < 0)
3142 return ret;
3143 #else
3144 ret = ni_ao_prep_fifo(dev, s);
3145 if (ret == 0)
3146 return -EPIPE;
3147
3148 interrupt_b_bits |= AO_FIFO_Interrupt_Enable;
3149 #endif
3150
3151 devpriv->stc_writew(dev, devpriv->ao_mode3 | AO_Not_An_UPDATE,
3152 AO_Mode_3_Register);
3153 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3154 /* wait for DACs to be loaded */
3155 for (i = 0; i < timeout; i++) {
3156 udelay(1);
3157 if ((devpriv->stc_readw(dev,
3158 Joint_Status_2_Register) &
3159 AO_TMRDACWRs_In_Progress_St) == 0)
3160 break;
3161 }
3162 if (i == timeout) {
3163 comedi_error(dev,
3164 "timed out waiting for AO_TMRDACWRs_In_Progress_St to clear");
3165 return -EIO;
3166 }
3167 /* stc manual says we are need to clear error interrupt after AO_TMRDACWRs_In_Progress_St clears */
3168 devpriv->stc_writew(dev, AO_Error_Interrupt_Ack,
3169 Interrupt_B_Ack_Register);
3170
3171 ni_set_bits(dev, Interrupt_B_Enable_Register, interrupt_b_bits, 1);
3172
3173 devpriv->stc_writew(dev,
3174 devpriv->ao_cmd1 | AO_UI_Arm | AO_UC_Arm | AO_BC_Arm
3175 | AO_DAC1_Update_Mode | AO_DAC0_Update_Mode,
3176 AO_Command_1_Register);
3177
3178 devpriv->stc_writew(dev, devpriv->ao_cmd2 | AO_START1_Pulse,
3179 AO_Command_2_Register);
3180
3181 return 0;
3182 }
3183
3184 static int ni_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3185 {
3186 const struct ni_board_struct *board = comedi_board(dev);
3187 struct ni_private *devpriv = dev->private;
3188 const struct comedi_cmd *cmd = &s->async->cmd;
3189 int bits;
3190 int i;
3191 unsigned trigvar;
3192
3193 if (dev->irq == 0) {
3194 comedi_error(dev, "cannot run command without an irq");
3195 return -EIO;
3196 }
3197
3198 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3199
3200 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3201
3202 if (board->reg_type & ni_reg_6xxx_mask) {
3203 ao_win_out(CLEAR_WG, AO_Misc_611x);
3204
3205 bits = 0;
3206 for (i = 0; i < cmd->chanlist_len; i++) {
3207 int chan;
3208
3209 chan = CR_CHAN(cmd->chanlist[i]);
3210 bits |= 1 << chan;
3211 ao_win_out(chan, AO_Waveform_Generation_611x);
3212 }
3213 ao_win_out(bits, AO_Timed_611x);
3214 }
3215
3216 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1);
3217
3218 if (cmd->stop_src == TRIG_NONE) {
3219 devpriv->ao_mode1 |= AO_Continuous;
3220 devpriv->ao_mode1 &= ~AO_Trigger_Once;
3221 } else {
3222 devpriv->ao_mode1 &= ~AO_Continuous;
3223 devpriv->ao_mode1 |= AO_Trigger_Once;
3224 }
3225 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3226 switch (cmd->start_src) {
3227 case TRIG_INT:
3228 case TRIG_NOW:
3229 devpriv->ao_trigger_select &=
3230 ~(AO_START1_Polarity | AO_START1_Select(-1));
3231 devpriv->ao_trigger_select |= AO_START1_Edge | AO_START1_Sync;
3232 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3233 AO_Trigger_Select_Register);
3234 break;
3235 case TRIG_EXT:
3236 devpriv->ao_trigger_select =
3237 AO_START1_Select(CR_CHAN(cmd->start_arg) + 1);
3238 if (cmd->start_arg & CR_INVERT)
3239 devpriv->ao_trigger_select |= AO_START1_Polarity; /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */
3240 if (cmd->start_arg & CR_EDGE)
3241 devpriv->ao_trigger_select |= AO_START1_Edge; /* 0=edge detection disabled, 1=enabled */
3242 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3243 AO_Trigger_Select_Register);
3244 break;
3245 default:
3246 BUG();
3247 break;
3248 }
3249 devpriv->ao_mode3 &= ~AO_Trigger_Length;
3250 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3251
3252 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3253 devpriv->ao_mode2 &= ~AO_BC_Initial_Load_Source;
3254 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3255 if (cmd->stop_src == TRIG_NONE) {
3256 devpriv->stc_writel(dev, 0xffffff, AO_BC_Load_A_Register);
3257 } else {
3258 devpriv->stc_writel(dev, 0, AO_BC_Load_A_Register);
3259 }
3260 devpriv->stc_writew(dev, AO_BC_Load, AO_Command_1_Register);
3261 devpriv->ao_mode2 &= ~AO_UC_Initial_Load_Source;
3262 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3263 switch (cmd->stop_src) {
3264 case TRIG_COUNT:
3265 if (board->reg_type & ni_reg_m_series_mask) {
3266 /* this is how the NI example code does it for m-series boards, verified correct with 6259 */
3267 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3268 AO_UC_Load_A_Register);
3269 devpriv->stc_writew(dev, AO_UC_Load,
3270 AO_Command_1_Register);
3271 } else {
3272 devpriv->stc_writel(dev, cmd->stop_arg,
3273 AO_UC_Load_A_Register);
3274 devpriv->stc_writew(dev, AO_UC_Load,
3275 AO_Command_1_Register);
3276 devpriv->stc_writel(dev, cmd->stop_arg - 1,
3277 AO_UC_Load_A_Register);
3278 }
3279 break;
3280 case TRIG_NONE:
3281 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3282 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3283 devpriv->stc_writel(dev, 0xffffff, AO_UC_Load_A_Register);
3284 break;
3285 default:
3286 devpriv->stc_writel(dev, 0, AO_UC_Load_A_Register);
3287 devpriv->stc_writew(dev, AO_UC_Load, AO_Command_1_Register);
3288 devpriv->stc_writel(dev, cmd->stop_arg, AO_UC_Load_A_Register);
3289 }
3290
3291 devpriv->ao_mode1 &=
3292 ~(AO_UI_Source_Select(0x1f) | AO_UI_Source_Polarity |
3293 AO_UPDATE_Source_Select(0x1f) | AO_UPDATE_Source_Polarity);
3294 switch (cmd->scan_begin_src) {
3295 case TRIG_TIMER:
3296 devpriv->ao_cmd2 &= ~AO_BC_Gate_Enable;
3297 trigvar =
3298 ni_ns_to_timer(dev, cmd->scan_begin_arg,
3299 TRIG_ROUND_NEAREST);
3300 devpriv->stc_writel(dev, 1, AO_UI_Load_A_Register);
3301 devpriv->stc_writew(dev, AO_UI_Load, AO_Command_1_Register);
3302 devpriv->stc_writel(dev, trigvar, AO_UI_Load_A_Register);
3303 break;
3304 case TRIG_EXT:
3305 devpriv->ao_mode1 |=
3306 AO_UPDATE_Source_Select(cmd->scan_begin_arg);
3307 if (cmd->scan_begin_arg & CR_INVERT)
3308 devpriv->ao_mode1 |= AO_UPDATE_Source_Polarity;
3309 devpriv->ao_cmd2 |= AO_BC_Gate_Enable;
3310 break;
3311 default:
3312 BUG();
3313 break;
3314 }
3315 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3316 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3317 devpriv->ao_mode2 &=
3318 ~(AO_UI_Reload_Mode(3) | AO_UI_Initial_Load_Source);
3319 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3320
3321 if (cmd->scan_end_arg > 1) {
3322 devpriv->ao_mode1 |= AO_Multiple_Channels;
3323 devpriv->stc_writew(dev,
3324 AO_Number_Of_Channels(cmd->scan_end_arg -
3325 1) |
3326 AO_UPDATE_Output_Select
3327 (AO_Update_Output_High_Z),
3328 AO_Output_Control_Register);
3329 } else {
3330 unsigned bits;
3331 devpriv->ao_mode1 &= ~AO_Multiple_Channels;
3332 bits = AO_UPDATE_Output_Select(AO_Update_Output_High_Z);
3333 if (board->reg_type &
3334 (ni_reg_m_series_mask | ni_reg_6xxx_mask)) {
3335 bits |= AO_Number_Of_Channels(0);
3336 } else {
3337 bits |=
3338 AO_Number_Of_Channels(CR_CHAN(cmd->chanlist[0]));
3339 }
3340 devpriv->stc_writew(dev, bits, AO_Output_Control_Register);
3341 }
3342 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3343
3344 devpriv->stc_writew(dev, AO_DAC0_Update_Mode | AO_DAC1_Update_Mode,
3345 AO_Command_1_Register);
3346
3347 devpriv->ao_mode3 |= AO_Stop_On_Overrun_Error;
3348 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3349
3350 devpriv->ao_mode2 &= ~AO_FIFO_Mode_Mask;
3351 #ifdef PCIDMA
3352 devpriv->ao_mode2 |= AO_FIFO_Mode_HF_to_F;
3353 #else
3354 devpriv->ao_mode2 |= AO_FIFO_Mode_HF;
3355 #endif
3356 devpriv->ao_mode2 &= ~AO_FIFO_Retransmit_Enable;
3357 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3358
3359 bits = AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3360 AO_TMRDACWR_Pulse_Width;
3361 if (board->ao_fifo_depth)
3362 bits |= AO_FIFO_Enable;
3363 else
3364 bits |= AO_DMA_PIO_Control;
3365 #if 0
3366 /* F Hess: windows driver does not set AO_Number_Of_DAC_Packages bit for 6281,
3367 verified with bus analyzer. */
3368 if (board->reg_type & ni_reg_m_series_mask)
3369 bits |= AO_Number_Of_DAC_Packages;
3370 #endif
3371 devpriv->stc_writew(dev, bits, AO_Personal_Register);
3372 /* enable sending of ao dma requests */
3373 devpriv->stc_writew(dev, AO_AOFREQ_Enable, AO_Start_Select_Register);
3374
3375 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3376
3377 if (cmd->stop_src == TRIG_COUNT) {
3378 devpriv->stc_writew(dev, AO_BC_TC_Interrupt_Ack,
3379 Interrupt_B_Ack_Register);
3380 ni_set_bits(dev, Interrupt_B_Enable_Register,
3381 AO_BC_TC_Interrupt_Enable, 1);
3382 }
3383
3384 s->async->inttrig = &ni_ao_inttrig;
3385
3386 return 0;
3387 }
3388
3389 static int ni_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3390 struct comedi_cmd *cmd)
3391 {
3392 const struct ni_board_struct *board = comedi_board(dev);
3393 struct ni_private *devpriv = dev->private;
3394 int err = 0;
3395 int tmp;
3396
3397 /* Step 1 : check if triggers are trivially valid */
3398
3399 if ((cmd->flags & CMDF_WRITE) == 0)
3400 cmd->flags |= CMDF_WRITE;
3401
3402 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3403 err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3404 TRIG_TIMER | TRIG_EXT);
3405 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3406 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3407 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
3408
3409 if (err)
3410 return 1;
3411
3412 /* Step 2a : make sure trigger sources are unique */
3413
3414 err |= cfc_check_trigger_is_unique(cmd->start_src);
3415 err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3416 err |= cfc_check_trigger_is_unique(cmd->stop_src);
3417
3418 /* Step 2b : and mutually compatible */
3419
3420 if (err)
3421 return 2;
3422
3423 /* Step 3: check if arguments are trivially valid */
3424
3425 if (cmd->start_src == TRIG_EXT) {
3426 /* external trigger */
3427 unsigned int tmp = CR_CHAN(cmd->start_arg);
3428
3429 if (tmp > 18)
3430 tmp = 18;
3431 tmp |= (cmd->start_arg & (CR_INVERT | CR_EDGE));
3432 err |= cfc_check_trigger_arg_is(&cmd->start_arg, tmp);
3433 } else {
3434 /* true for both TRIG_NOW and TRIG_INT */
3435 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3436 }
3437
3438 if (cmd->scan_begin_src == TRIG_TIMER) {
3439 err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3440 board->ao_speed);
3441 err |= cfc_check_trigger_arg_max(&cmd->scan_begin_arg,
3442 devpriv->clock_ns * 0xffffff);
3443 }
3444
3445 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3446 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3447
3448 if (cmd->stop_src == TRIG_COUNT)
3449 err |= cfc_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff);
3450 else /* TRIG_NONE */
3451 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3452
3453 if (err)
3454 return 3;
3455
3456 /* step 4: fix up any arguments */
3457 if (cmd->scan_begin_src == TRIG_TIMER) {
3458 tmp = cmd->scan_begin_arg;
3459 cmd->scan_begin_arg =
3460 ni_timer_to_ns(dev, ni_ns_to_timer(dev,
3461 cmd->scan_begin_arg,
3462 cmd->
3463 flags &
3464 TRIG_ROUND_MASK));
3465 if (tmp != cmd->scan_begin_arg)
3466 err++;
3467 }
3468 if (err)
3469 return 4;
3470
3471 /* step 5: fix up chanlist */
3472
3473 if (err)
3474 return 5;
3475
3476 return 0;
3477 }
3478
3479 static int ni_ao_reset(struct comedi_device *dev, struct comedi_subdevice *s)
3480 {
3481 const struct ni_board_struct *board = comedi_board(dev);
3482 struct ni_private *devpriv = dev->private;
3483
3484 /* devpriv->ao0p=0x0000; */
3485 /* ni_writew(devpriv->ao0p,AO_Configuration); */
3486
3487 /* devpriv->ao1p=AO_Channel(1); */
3488 /* ni_writew(devpriv->ao1p,AO_Configuration); */
3489
3490 ni_release_ao_mite_channel(dev);
3491
3492 devpriv->stc_writew(dev, AO_Configuration_Start, Joint_Reset_Register);
3493 devpriv->stc_writew(dev, AO_Disarm, AO_Command_1_Register);
3494 ni_set_bits(dev, Interrupt_B_Enable_Register, ~0, 0);
3495 devpriv->stc_writew(dev, AO_BC_Source_Select, AO_Personal_Register);
3496 devpriv->stc_writew(dev, 0x3f98, Interrupt_B_Ack_Register);
3497 devpriv->stc_writew(dev, AO_BC_Source_Select | AO_UPDATE_Pulse_Width |
3498 AO_TMRDACWR_Pulse_Width, AO_Personal_Register);
3499 devpriv->stc_writew(dev, 0, AO_Output_Control_Register);
3500 devpriv->stc_writew(dev, 0, AO_Start_Select_Register);
3501 devpriv->ao_cmd1 = 0;
3502 devpriv->stc_writew(dev, devpriv->ao_cmd1, AO_Command_1_Register);
3503 devpriv->ao_cmd2 = 0;
3504 devpriv->stc_writew(dev, devpriv->ao_cmd2, AO_Command_2_Register);
3505 devpriv->ao_mode1 = 0;
3506 devpriv->stc_writew(dev, devpriv->ao_mode1, AO_Mode_1_Register);
3507 devpriv->ao_mode2 = 0;
3508 devpriv->stc_writew(dev, devpriv->ao_mode2, AO_Mode_2_Register);
3509 if (board->reg_type & ni_reg_m_series_mask)
3510 devpriv->ao_mode3 = AO_Last_Gate_Disable;
3511 else
3512 devpriv->ao_mode3 = 0;
3513 devpriv->stc_writew(dev, devpriv->ao_mode3, AO_Mode_3_Register);
3514 devpriv->ao_trigger_select = 0;
3515 devpriv->stc_writew(dev, devpriv->ao_trigger_select,
3516 AO_Trigger_Select_Register);
3517 if (board->reg_type & ni_reg_6xxx_mask) {
3518 unsigned immediate_bits = 0;
3519 unsigned i;
3520 for (i = 0; i < s->n_chan; ++i) {
3521 immediate_bits |= 1 << i;
3522 }
3523 ao_win_out(immediate_bits, AO_Immediate_671x);
3524 ao_win_out(CLEAR_WG, AO_Misc_611x);
3525 }
3526 devpriv->stc_writew(dev, AO_Configuration_End, Joint_Reset_Register);
3527
3528 return 0;
3529 }
3530
3531 /* digital io */
3532
3533 static int ni_dio_insn_config(struct comedi_device *dev,
3534 struct comedi_subdevice *s,
3535 struct comedi_insn *insn, unsigned int *data)
3536 {
3537 struct ni_private *devpriv = dev->private;
3538
3539 #ifdef DEBUG_DIO
3540 printk("ni_dio_insn_config() chan=%d io=%d\n",
3541 CR_CHAN(insn->chanspec), data[0]);
3542 #endif
3543 switch (data[0]) {
3544 case INSN_CONFIG_DIO_OUTPUT:
3545 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3546 break;
3547 case INSN_CONFIG_DIO_INPUT:
3548 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3549 break;
3550 case INSN_CONFIG_DIO_QUERY:
3551 data[1] =
3552 (s->
3553 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3554 COMEDI_INPUT;
3555 return insn->n;
3556 break;
3557 default:
3558 return -EINVAL;
3559 }
3560
3561 devpriv->dio_control &= ~DIO_Pins_Dir_Mask;
3562 devpriv->dio_control |= DIO_Pins_Dir(s->io_bits);
3563 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3564
3565 return 1;
3566 }
3567
3568 static int ni_dio_insn_bits(struct comedi_device *dev,
3569 struct comedi_subdevice *s,
3570 struct comedi_insn *insn, unsigned int *data)
3571 {
3572 struct ni_private *devpriv = dev->private;
3573
3574 #ifdef DEBUG_DIO
3575 printk("ni_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0], data[1]);
3576 #endif
3577
3578 if (data[0]) {
3579 /* Perform check to make sure we're not using the
3580 serial part of the dio */
3581 if ((data[0] & (DIO_SDIN | DIO_SDOUT))
3582 && devpriv->serial_interval_ns)
3583 return -EBUSY;
3584
3585 s->state &= ~data[0];
3586 s->state |= (data[0] & data[1]);
3587 devpriv->dio_output &= ~DIO_Parallel_Data_Mask;
3588 devpriv->dio_output |= DIO_Parallel_Data_Out(s->state);
3589 devpriv->stc_writew(dev, devpriv->dio_output,
3590 DIO_Output_Register);
3591 }
3592 data[1] = devpriv->stc_readw(dev, DIO_Parallel_Input_Register);
3593
3594 return insn->n;
3595 }
3596
3597 static int ni_m_series_dio_insn_config(struct comedi_device *dev,
3598 struct comedi_subdevice *s,
3599 struct comedi_insn *insn,
3600 unsigned int *data)
3601 {
3602 struct ni_private *devpriv __maybe_unused = dev->private;
3603
3604 #ifdef DEBUG_DIO
3605 printk("ni_m_series_dio_insn_config() chan=%d io=%d\n",
3606 CR_CHAN(insn->chanspec), data[0]);
3607 #endif
3608 switch (data[0]) {
3609 case INSN_CONFIG_DIO_OUTPUT:
3610 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
3611 break;
3612 case INSN_CONFIG_DIO_INPUT:
3613 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
3614 break;
3615 case INSN_CONFIG_DIO_QUERY:
3616 data[1] =
3617 (s->
3618 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
3619 COMEDI_INPUT;
3620 return insn->n;
3621 break;
3622 default:
3623 return -EINVAL;
3624 }
3625
3626 ni_writel(s->io_bits, M_Offset_DIO_Direction);
3627
3628 return 1;
3629 }
3630
3631 static int ni_m_series_dio_insn_bits(struct comedi_device *dev,
3632 struct comedi_subdevice *s,
3633 struct comedi_insn *insn,
3634 unsigned int *data)
3635 {
3636 struct ni_private *devpriv __maybe_unused = dev->private;
3637
3638 #ifdef DEBUG_DIO
3639 printk("ni_m_series_dio_insn_bits() mask=0x%x bits=0x%x\n", data[0],
3640 data[1]);
3641 #endif
3642
3643 if (data[0]) {
3644 s->state &= ~data[0];
3645 s->state |= (data[0] & data[1]);
3646 ni_writel(s->state, M_Offset_Static_Digital_Output);
3647 }
3648 data[1] = ni_readl(M_Offset_Static_Digital_Input);
3649
3650 return insn->n;
3651 }
3652
3653 static int ni_cdio_cmdtest(struct comedi_device *dev,
3654 struct comedi_subdevice *s, struct comedi_cmd *cmd)
3655 {
3656 int err = 0;
3657 int tmp;
3658 unsigned i;
3659
3660 /* Step 1 : check if triggers are trivially valid */
3661
3662 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT);
3663 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
3664 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3665 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3666 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3667
3668 if (err)
3669 return 1;
3670
3671 /* Step 2a : make sure trigger sources are unique */
3672 /* Step 2b : and mutually compatible */
3673
3674 if (err)
3675 return 2;
3676
3677 /* Step 3: check if arguments are trivially valid */
3678
3679 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3680
3681 tmp = cmd->scan_begin_arg;
3682 tmp &= CR_PACK_FLAGS(CDO_Sample_Source_Select_Mask, 0, 0, CR_INVERT);
3683 if (tmp != cmd->scan_begin_arg)
3684 err |= -EINVAL;
3685
3686 err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
3687 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3688 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
3689
3690 if (err)
3691 return 3;
3692
3693 /* step 4: fix up any arguments */
3694
3695 if (err)
3696 return 4;
3697
3698 /* step 5: check chanlist */
3699
3700 for (i = 0; i < cmd->chanlist_len; ++i) {
3701 if (cmd->chanlist[i] != i)
3702 err = 1;
3703 }
3704
3705 if (err)
3706 return 5;
3707
3708 return 0;
3709 }
3710
3711 static int ni_cdio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3712 {
3713 struct ni_private *devpriv __maybe_unused = dev->private;
3714 const struct comedi_cmd *cmd = &s->async->cmd;
3715 unsigned cdo_mode_bits = CDO_FIFO_Mode_Bit | CDO_Halt_On_Error_Bit;
3716 int retval;
3717
3718 ni_writel(CDO_Reset_Bit, M_Offset_CDIO_Command);
3719 switch (cmd->scan_begin_src) {
3720 case TRIG_EXT:
3721 cdo_mode_bits |=
3722 CR_CHAN(cmd->scan_begin_arg) &
3723 CDO_Sample_Source_Select_Mask;
3724 break;
3725 default:
3726 BUG();
3727 break;
3728 }
3729 if (cmd->scan_begin_arg & CR_INVERT)
3730 cdo_mode_bits |= CDO_Polarity_Bit;
3731 ni_writel(cdo_mode_bits, M_Offset_CDO_Mode);
3732 if (s->io_bits) {
3733 ni_writel(s->state, M_Offset_CDO_FIFO_Data);
3734 ni_writel(CDO_SW_Update_Bit, M_Offset_CDIO_Command);
3735 ni_writel(s->io_bits, M_Offset_CDO_Mask_Enable);
3736 } else {
3737 comedi_error(dev,
3738 "attempted to run digital output command with no lines configured as outputs");
3739 return -EIO;
3740 }
3741 retval = ni_request_cdo_mite_channel(dev);
3742 if (retval < 0) {
3743 return retval;
3744 }
3745 s->async->inttrig = &ni_cdo_inttrig;
3746 return 0;
3747 }
3748
3749 static int ni_cdo_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3750 unsigned int trignum)
3751 {
3752 #ifdef PCIDMA
3753 struct ni_private *devpriv = dev->private;
3754 unsigned long flags;
3755 #endif
3756 int retval = 0;
3757 unsigned i;
3758 const unsigned timeout = 1000;
3759
3760 s->async->inttrig = NULL;
3761
3762 /* read alloc the entire buffer */
3763 comedi_buf_read_alloc(s->async, s->async->prealloc_bufsz);
3764
3765 #ifdef PCIDMA
3766 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3767 if (devpriv->cdo_mite_chan) {
3768 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32);
3769 mite_dma_arm(devpriv->cdo_mite_chan);
3770 } else {
3771 comedi_error(dev, "BUG: no cdo mite channel?");
3772 retval = -EIO;
3773 }
3774 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3775 if (retval < 0)
3776 return retval;
3777 #endif
3778 /*
3779 * XXX not sure what interrupt C group does
3780 * ni_writeb(Interrupt_Group_C_Enable_Bit,
3781 * M_Offset_Interrupt_C_Enable); wait for dma to fill output fifo
3782 */
3783 for (i = 0; i < timeout; ++i) {
3784 if (ni_readl(M_Offset_CDIO_Status) & CDO_FIFO_Full_Bit)
3785 break;
3786 udelay(10);
3787 }
3788 if (i == timeout) {
3789 comedi_error(dev, "dma failed to fill cdo fifo!");
3790 ni_cdio_cancel(dev, s);
3791 return -EIO;
3792 }
3793 ni_writel(CDO_Arm_Bit | CDO_Error_Interrupt_Enable_Set_Bit |
3794 CDO_Empty_FIFO_Interrupt_Enable_Set_Bit,
3795 M_Offset_CDIO_Command);
3796 return retval;
3797 }
3798
3799 static int ni_cdio_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3800 {
3801 struct ni_private *devpriv __maybe_unused = dev->private;
3802
3803 ni_writel(CDO_Disarm_Bit | CDO_Error_Interrupt_Enable_Clear_Bit |
3804 CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit |
3805 CDO_FIFO_Request_Interrupt_Enable_Clear_Bit,
3806 M_Offset_CDIO_Command);
3807 /*
3808 * XXX not sure what interrupt C group does ni_writeb(0,
3809 * M_Offset_Interrupt_C_Enable);
3810 */
3811 ni_writel(0, M_Offset_CDO_Mask_Enable);
3812 ni_release_cdo_mite_channel(dev);
3813 return 0;
3814 }
3815
3816 static void handle_cdio_interrupt(struct comedi_device *dev)
3817 {
3818 const struct ni_board_struct *board = comedi_board(dev);
3819 struct ni_private *devpriv __maybe_unused = dev->private;
3820 unsigned cdio_status;
3821 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV];
3822 #ifdef PCIDMA
3823 unsigned long flags;
3824 #endif
3825
3826 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
3827 return;
3828 }
3829 #ifdef PCIDMA
3830 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
3831 if (devpriv->cdo_mite_chan) {
3832 unsigned cdo_mite_status =
3833 mite_get_status(devpriv->cdo_mite_chan);
3834 if (cdo_mite_status & CHSR_LINKC) {
3835 writel(CHOR_CLRLC,
3836 devpriv->mite->mite_io_addr +
3837 MITE_CHOR(devpriv->cdo_mite_chan->channel));
3838 }
3839 mite_sync_output_dma(devpriv->cdo_mite_chan, s->async);
3840 }
3841 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
3842 #endif
3843
3844 cdio_status = ni_readl(M_Offset_CDIO_Status);
3845 if (cdio_status & (CDO_Overrun_Bit | CDO_Underflow_Bit)) {
3846 /* printk("cdio error: statux=0x%x\n", cdio_status); */
3847 ni_writel(CDO_Error_Interrupt_Confirm_Bit, M_Offset_CDIO_Command); /* XXX just guessing this is needed and does something useful */
3848 s->async->events |= COMEDI_CB_OVERFLOW;
3849 }
3850 if (cdio_status & CDO_FIFO_Empty_Bit) {
3851 /* printk("cdio fifo empty\n"); */
3852 ni_writel(CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit,
3853 M_Offset_CDIO_Command);
3854 /* s->async->events |= COMEDI_CB_EOA; */
3855 }
3856 ni_event(dev, s);
3857 }
3858
3859 static int ni_serial_insn_config(struct comedi_device *dev,
3860 struct comedi_subdevice *s,
3861 struct comedi_insn *insn, unsigned int *data)
3862 {
3863 struct ni_private *devpriv = dev->private;
3864 int err = insn->n;
3865 unsigned char byte_out, byte_in = 0;
3866
3867 if (insn->n != 2)
3868 return -EINVAL;
3869
3870 switch (data[0]) {
3871 case INSN_CONFIG_SERIAL_CLOCK:
3872
3873 #ifdef DEBUG_DIO
3874 printk("SPI serial clock Config cd\n", data[1]);
3875 #endif
3876 devpriv->serial_hw_mode = 1;
3877 devpriv->dio_control |= DIO_HW_Serial_Enable;
3878
3879 if (data[1] == SERIAL_DISABLED) {
3880 devpriv->serial_hw_mode = 0;
3881 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3882 DIO_Software_Serial_Control);
3883 data[1] = SERIAL_DISABLED;
3884 devpriv->serial_interval_ns = data[1];
3885 } else if (data[1] <= SERIAL_600NS) {
3886 /* Warning: this clock speed is too fast to reliably
3887 control SCXI. */
3888 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3889 devpriv->clock_and_fout |= Slow_Internal_Timebase;
3890 devpriv->clock_and_fout &= ~DIO_Serial_Out_Divide_By_2;
3891 data[1] = SERIAL_600NS;
3892 devpriv->serial_interval_ns = data[1];
3893 } else if (data[1] <= SERIAL_1_2US) {
3894 devpriv->dio_control &= ~DIO_HW_Serial_Timebase;
3895 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3896 DIO_Serial_Out_Divide_By_2;
3897 data[1] = SERIAL_1_2US;
3898 devpriv->serial_interval_ns = data[1];
3899 } else if (data[1] <= SERIAL_10US) {
3900 devpriv->dio_control |= DIO_HW_Serial_Timebase;
3901 devpriv->clock_and_fout |= Slow_Internal_Timebase |
3902 DIO_Serial_Out_Divide_By_2;
3903 /* Note: DIO_Serial_Out_Divide_By_2 only affects
3904 600ns/1.2us. If you turn divide_by_2 off with the
3905 slow clock, you will still get 10us, except then
3906 all your delays are wrong. */
3907 data[1] = SERIAL_10US;
3908 devpriv->serial_interval_ns = data[1];
3909 } else {
3910 devpriv->dio_control &= ~(DIO_HW_Serial_Enable |
3911 DIO_Software_Serial_Control);
3912 devpriv->serial_hw_mode = 0;
3913 data[1] = (data[1] / 1000) * 1000;
3914 devpriv->serial_interval_ns = data[1];
3915 }
3916
3917 devpriv->stc_writew(dev, devpriv->dio_control,
3918 DIO_Control_Register);
3919 devpriv->stc_writew(dev, devpriv->clock_and_fout,
3920 Clock_and_FOUT_Register);
3921 return 1;
3922
3923 break;
3924
3925 case INSN_CONFIG_BIDIRECTIONAL_DATA:
3926
3927 if (devpriv->serial_interval_ns == 0) {
3928 return -EINVAL;
3929 }
3930
3931 byte_out = data[1] & 0xFF;
3932
3933 if (devpriv->serial_hw_mode) {
3934 err = ni_serial_hw_readwrite8(dev, s, byte_out,
3935 &byte_in);
3936 } else if (devpriv->serial_interval_ns > 0) {
3937 err = ni_serial_sw_readwrite8(dev, s, byte_out,
3938 &byte_in);
3939 } else {
3940 printk("ni_serial_insn_config: serial disabled!\n");
3941 return -EINVAL;
3942 }
3943 if (err < 0)
3944 return err;
3945 data[1] = byte_in & 0xFF;
3946 return insn->n;
3947
3948 break;
3949 default:
3950 return -EINVAL;
3951 }
3952
3953 }
3954
3955 static int ni_serial_hw_readwrite8(struct comedi_device *dev,
3956 struct comedi_subdevice *s,
3957 unsigned char data_out,
3958 unsigned char *data_in)
3959 {
3960 struct ni_private *devpriv = dev->private;
3961 unsigned int status1;
3962 int err = 0, count = 20;
3963
3964 #ifdef DEBUG_DIO
3965 printk("ni_serial_hw_readwrite8: outputting 0x%x\n", data_out);
3966 #endif
3967
3968 devpriv->dio_output &= ~DIO_Serial_Data_Mask;
3969 devpriv->dio_output |= DIO_Serial_Data_Out(data_out);
3970 devpriv->stc_writew(dev, devpriv->dio_output, DIO_Output_Register);
3971
3972 status1 = devpriv->stc_readw(dev, Joint_Status_1_Register);
3973 if (status1 & DIO_Serial_IO_In_Progress_St) {
3974 err = -EBUSY;
3975 goto Error;
3976 }
3977
3978 devpriv->dio_control |= DIO_HW_Serial_Start;
3979 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
3980 devpriv->dio_control &= ~DIO_HW_Serial_Start;
3981
3982 /* Wait until STC says we're done, but don't loop infinitely. */
3983 while ((status1 =
3984 devpriv->stc_readw(dev,
3985 Joint_Status_1_Register)) &
3986 DIO_Serial_IO_In_Progress_St) {
3987 /* Delay one bit per loop */
3988 udelay((devpriv->serial_interval_ns + 999) / 1000);
3989 if (--count < 0) {
3990 printk
3991 ("ni_serial_hw_readwrite8: SPI serial I/O didn't finish in time!\n");
3992 err = -ETIME;
3993 goto Error;
3994 }
3995 }
3996
3997 /* Delay for last bit. This delay is absolutely necessary, because
3998 DIO_Serial_IO_In_Progress_St goes high one bit too early. */
3999 udelay((devpriv->serial_interval_ns + 999) / 1000);
4000
4001 if (data_in != NULL) {
4002 *data_in = devpriv->stc_readw(dev, DIO_Serial_Input_Register);
4003 #ifdef DEBUG_DIO
4004 printk("ni_serial_hw_readwrite8: inputted 0x%x\n", *data_in);
4005 #endif
4006 }
4007
4008 Error:
4009 devpriv->stc_writew(dev, devpriv->dio_control, DIO_Control_Register);
4010
4011 return err;
4012 }
4013
4014 static int ni_serial_sw_readwrite8(struct comedi_device *dev,
4015 struct comedi_subdevice *s,
4016 unsigned char data_out,
4017 unsigned char *data_in)
4018 {
4019 struct ni_private *devpriv = dev->private;
4020 unsigned char mask, input = 0;
4021
4022 #ifdef DEBUG_DIO
4023 printk("ni_serial_sw_readwrite8: outputting 0x%x\n", data_out);
4024 #endif
4025
4026 /* Wait for one bit before transfer */
4027 udelay((devpriv->serial_interval_ns + 999) / 1000);
4028
4029 for (mask = 0x80; mask; mask >>= 1) {
4030 /* Output current bit; note that we cannot touch s->state
4031 because it is a per-subdevice field, and serial is
4032 a separate subdevice from DIO. */
4033 devpriv->dio_output &= ~DIO_SDOUT;
4034 if (data_out & mask) {
4035 devpriv->dio_output |= DIO_SDOUT;
4036 }
4037 devpriv->stc_writew(dev, devpriv->dio_output,
4038 DIO_Output_Register);
4039
4040 /* Assert SDCLK (active low, inverted), wait for half of
4041 the delay, deassert SDCLK, and wait for the other half. */
4042 devpriv->dio_control |= DIO_Software_Serial_Control;
4043 devpriv->stc_writew(dev, devpriv->dio_control,
4044 DIO_Control_Register);
4045
4046 udelay((devpriv->serial_interval_ns + 999) / 2000);
4047
4048 devpriv->dio_control &= ~DIO_Software_Serial_Control;
4049 devpriv->stc_writew(dev, devpriv->dio_control,
4050 DIO_Control_Register);
4051
4052 udelay((devpriv->serial_interval_ns + 999) / 2000);
4053
4054 /* Input current bit */
4055 if (devpriv->stc_readw(dev,
4056 DIO_Parallel_Input_Register) & DIO_SDIN)
4057 {
4058 /* printk("DIO_P_I_R: 0x%x\n", devpriv->stc_readw(dev, DIO_Parallel_Input_Register)); */
4059 input |= mask;
4060 }
4061 }
4062 #ifdef DEBUG_DIO
4063 printk("ni_serial_sw_readwrite8: inputted 0x%x\n", input);
4064 #endif
4065 if (data_in)
4066 *data_in = input;
4067
4068 return 0;
4069 }
4070
4071 static void mio_common_detach(struct comedi_device *dev)
4072 {
4073 struct ni_private *devpriv = dev->private;
4074
4075 if (devpriv) {
4076 if (devpriv->counter_dev) {
4077 ni_gpct_device_destroy(devpriv->counter_dev);
4078 }
4079 }
4080 comedi_spriv_free(dev, NI_8255_DIO_SUBDEV);
4081 }
4082
4083 static void init_ao_67xx(struct comedi_device *dev, struct comedi_subdevice *s)
4084 {
4085 int i;
4086
4087 for (i = 0; i < s->n_chan; i++) {
4088 ni_ao_win_outw(dev, AO_Channel(i) | 0x0,
4089 AO_Configuration_2_67xx);
4090 }
4091 ao_win_out(0x0, AO_Later_Single_Point_Updates);
4092 }
4093
4094 static unsigned ni_gpct_to_stc_register(enum ni_gpct_register reg)
4095 {
4096 unsigned stc_register;
4097 switch (reg) {
4098 case NITIO_G0_Autoincrement_Reg:
4099 stc_register = G_Autoincrement_Register(0);
4100 break;
4101 case NITIO_G1_Autoincrement_Reg:
4102 stc_register = G_Autoincrement_Register(1);
4103 break;
4104 case NITIO_G0_Command_Reg:
4105 stc_register = G_Command_Register(0);
4106 break;
4107 case NITIO_G1_Command_Reg:
4108 stc_register = G_Command_Register(1);
4109 break;
4110 case NITIO_G0_HW_Save_Reg:
4111 stc_register = G_HW_Save_Register(0);
4112 break;
4113 case NITIO_G1_HW_Save_Reg:
4114 stc_register = G_HW_Save_Register(1);
4115 break;
4116 case NITIO_G0_SW_Save_Reg:
4117 stc_register = G_Save_Register(0);
4118 break;
4119 case NITIO_G1_SW_Save_Reg:
4120 stc_register = G_Save_Register(1);
4121 break;
4122 case NITIO_G0_Mode_Reg:
4123 stc_register = G_Mode_Register(0);
4124 break;
4125 case NITIO_G1_Mode_Reg:
4126 stc_register = G_Mode_Register(1);
4127 break;
4128 case NITIO_G0_LoadA_Reg:
4129 stc_register = G_Load_A_Register(0);
4130 break;
4131 case NITIO_G1_LoadA_Reg:
4132 stc_register = G_Load_A_Register(1);
4133 break;
4134 case NITIO_G0_LoadB_Reg:
4135 stc_register = G_Load_B_Register(0);
4136 break;
4137 case NITIO_G1_LoadB_Reg:
4138 stc_register = G_Load_B_Register(1);
4139 break;
4140 case NITIO_G0_Input_Select_Reg:
4141 stc_register = G_Input_Select_Register(0);
4142 break;
4143 case NITIO_G1_Input_Select_Reg:
4144 stc_register = G_Input_Select_Register(1);
4145 break;
4146 case NITIO_G01_Status_Reg:
4147 stc_register = G_Status_Register;
4148 break;
4149 case NITIO_G01_Joint_Reset_Reg:
4150 stc_register = Joint_Reset_Register;
4151 break;
4152 case NITIO_G01_Joint_Status1_Reg:
4153 stc_register = Joint_Status_1_Register;
4154 break;
4155 case NITIO_G01_Joint_Status2_Reg:
4156 stc_register = Joint_Status_2_Register;
4157 break;
4158 case NITIO_G0_Interrupt_Acknowledge_Reg:
4159 stc_register = Interrupt_A_Ack_Register;
4160 break;
4161 case NITIO_G1_Interrupt_Acknowledge_Reg:
4162 stc_register = Interrupt_B_Ack_Register;
4163 break;
4164 case NITIO_G0_Status_Reg:
4165 stc_register = AI_Status_1_Register;
4166 break;
4167 case NITIO_G1_Status_Reg:
4168 stc_register = AO_Status_1_Register;
4169 break;
4170 case NITIO_G0_Interrupt_Enable_Reg:
4171 stc_register = Interrupt_A_Enable_Register;
4172 break;
4173 case NITIO_G1_Interrupt_Enable_Reg:
4174 stc_register = Interrupt_B_Enable_Register;
4175 break;
4176 default:
4177 printk("%s: unhandled register 0x%x in switch.\n",
4178 __func__, reg);
4179 BUG();
4180 return 0;
4181 break;
4182 }
4183 return stc_register;
4184 }
4185
4186 static void ni_gpct_write_register(struct ni_gpct *counter, unsigned bits,
4187 enum ni_gpct_register reg)
4188 {
4189 struct comedi_device *dev = counter->counter_dev->dev;
4190 struct ni_private *devpriv = dev->private;
4191 unsigned stc_register;
4192 /* bits in the join reset register which are relevant to counters */
4193 static const unsigned gpct_joint_reset_mask = G0_Reset | G1_Reset;
4194 static const unsigned gpct_interrupt_a_enable_mask =
4195 G0_Gate_Interrupt_Enable | G0_TC_Interrupt_Enable;
4196 static const unsigned gpct_interrupt_b_enable_mask =
4197 G1_Gate_Interrupt_Enable | G1_TC_Interrupt_Enable;
4198
4199 switch (reg) {
4200 /* m-series-only registers */
4201 case NITIO_G0_Counting_Mode_Reg:
4202 ni_writew(bits, M_Offset_G0_Counting_Mode);
4203 break;
4204 case NITIO_G1_Counting_Mode_Reg:
4205 ni_writew(bits, M_Offset_G1_Counting_Mode);
4206 break;
4207 case NITIO_G0_Second_Gate_Reg:
4208 ni_writew(bits, M_Offset_G0_Second_Gate);
4209 break;
4210 case NITIO_G1_Second_Gate_Reg:
4211 ni_writew(bits, M_Offset_G1_Second_Gate);
4212 break;
4213 case NITIO_G0_DMA_Config_Reg:
4214 ni_writew(bits, M_Offset_G0_DMA_Config);
4215 break;
4216 case NITIO_G1_DMA_Config_Reg:
4217 ni_writew(bits, M_Offset_G1_DMA_Config);
4218 break;
4219 case NITIO_G0_ABZ_Reg:
4220 ni_writew(bits, M_Offset_G0_MSeries_ABZ);
4221 break;
4222 case NITIO_G1_ABZ_Reg:
4223 ni_writew(bits, M_Offset_G1_MSeries_ABZ);
4224 break;
4225
4226 /* 32 bit registers */
4227 case NITIO_G0_LoadA_Reg:
4228 case NITIO_G1_LoadA_Reg:
4229 case NITIO_G0_LoadB_Reg:
4230 case NITIO_G1_LoadB_Reg:
4231 stc_register = ni_gpct_to_stc_register(reg);
4232 devpriv->stc_writel(dev, bits, stc_register);
4233 break;
4234
4235 /* 16 bit registers */
4236 case NITIO_G0_Interrupt_Enable_Reg:
4237 BUG_ON(bits & ~gpct_interrupt_a_enable_mask);
4238 ni_set_bitfield(dev, Interrupt_A_Enable_Register,
4239 gpct_interrupt_a_enable_mask, bits);
4240 break;
4241 case NITIO_G1_Interrupt_Enable_Reg:
4242 BUG_ON(bits & ~gpct_interrupt_b_enable_mask);
4243 ni_set_bitfield(dev, Interrupt_B_Enable_Register,
4244 gpct_interrupt_b_enable_mask, bits);
4245 break;
4246 case NITIO_G01_Joint_Reset_Reg:
4247 BUG_ON(bits & ~gpct_joint_reset_mask);
4248 /* fall-through */
4249 default:
4250 stc_register = ni_gpct_to_stc_register(reg);
4251 devpriv->stc_writew(dev, bits, stc_register);
4252 }
4253 }
4254
4255 static unsigned ni_gpct_read_register(struct ni_gpct *counter,
4256 enum ni_gpct_register reg)
4257 {
4258 struct comedi_device *dev = counter->counter_dev->dev;
4259 struct ni_private *devpriv = dev->private;
4260 unsigned stc_register;
4261
4262 switch (reg) {
4263 /* m-series only registers */
4264 case NITIO_G0_DMA_Status_Reg:
4265 return ni_readw(M_Offset_G0_DMA_Status);
4266 break;
4267 case NITIO_G1_DMA_Status_Reg:
4268 return ni_readw(M_Offset_G1_DMA_Status);
4269 break;
4270
4271 /* 32 bit registers */
4272 case NITIO_G0_HW_Save_Reg:
4273 case NITIO_G1_HW_Save_Reg:
4274 case NITIO_G0_SW_Save_Reg:
4275 case NITIO_G1_SW_Save_Reg:
4276 stc_register = ni_gpct_to_stc_register(reg);
4277 return devpriv->stc_readl(dev, stc_register);
4278 break;
4279
4280 /* 16 bit registers */
4281 default:
4282 stc_register = ni_gpct_to_stc_register(reg);
4283 return devpriv->stc_readw(dev, stc_register);
4284 break;
4285 }
4286 return 0;
4287 }
4288
4289 static int ni_freq_out_insn_read(struct comedi_device *dev,
4290 struct comedi_subdevice *s,
4291 struct comedi_insn *insn, unsigned int *data)
4292 {
4293 struct ni_private *devpriv = dev->private;
4294
4295 data[0] = devpriv->clock_and_fout & FOUT_Divider_mask;
4296 return 1;
4297 }
4298
4299 static int ni_freq_out_insn_write(struct comedi_device *dev,
4300 struct comedi_subdevice *s,
4301 struct comedi_insn *insn, unsigned int *data)
4302 {
4303 struct ni_private *devpriv = dev->private;
4304
4305 devpriv->clock_and_fout &= ~FOUT_Enable;
4306 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4307 Clock_and_FOUT_Register);
4308 devpriv->clock_and_fout &= ~FOUT_Divider_mask;
4309 devpriv->clock_and_fout |= FOUT_Divider(data[0]);
4310 devpriv->clock_and_fout |= FOUT_Enable;
4311 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4312 Clock_and_FOUT_Register);
4313 return insn->n;
4314 }
4315
4316 static int ni_set_freq_out_clock(struct comedi_device *dev,
4317 unsigned int clock_source)
4318 {
4319 struct ni_private *devpriv = dev->private;
4320
4321 switch (clock_source) {
4322 case NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC:
4323 devpriv->clock_and_fout &= ~FOUT_Timebase_Select;
4324 break;
4325 case NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC:
4326 devpriv->clock_and_fout |= FOUT_Timebase_Select;
4327 break;
4328 default:
4329 return -EINVAL;
4330 }
4331 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4332 Clock_and_FOUT_Register);
4333 return 3;
4334 }
4335
4336 static void ni_get_freq_out_clock(struct comedi_device *dev,
4337 unsigned int *clock_source,
4338 unsigned int *clock_period_ns)
4339 {
4340 struct ni_private *devpriv = dev->private;
4341
4342 if (devpriv->clock_and_fout & FOUT_Timebase_Select) {
4343 *clock_source = NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC;
4344 *clock_period_ns = TIMEBASE_2_NS;
4345 } else {
4346 *clock_source = NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC;
4347 *clock_period_ns = TIMEBASE_1_NS * 2;
4348 }
4349 }
4350
4351 static int ni_freq_out_insn_config(struct comedi_device *dev,
4352 struct comedi_subdevice *s,
4353 struct comedi_insn *insn, unsigned int *data)
4354 {
4355 switch (data[0]) {
4356 case INSN_CONFIG_SET_CLOCK_SRC:
4357 return ni_set_freq_out_clock(dev, data[1]);
4358 break;
4359 case INSN_CONFIG_GET_CLOCK_SRC:
4360 ni_get_freq_out_clock(dev, &data[1], &data[2]);
4361 return 3;
4362 default:
4363 break;
4364 }
4365 return -EINVAL;
4366 }
4367
4368 static int ni_alloc_private(struct comedi_device *dev)
4369 {
4370 struct ni_private *devpriv;
4371
4372 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
4373 if (!devpriv)
4374 return -ENOMEM;
4375 dev->private = devpriv;
4376
4377 spin_lock_init(&devpriv->window_lock);
4378 spin_lock_init(&devpriv->soft_reg_copy_lock);
4379 spin_lock_init(&devpriv->mite_channel_lock);
4380
4381 return 0;
4382 };
4383
4384 static int ni_E_init(struct comedi_device *dev)
4385 {
4386 const struct ni_board_struct *board = comedi_board(dev);
4387 struct ni_private *devpriv = dev->private;
4388 struct comedi_subdevice *s;
4389 unsigned j;
4390 enum ni_gpct_variant counter_variant;
4391 int ret;
4392
4393 if (board->n_aochan > MAX_N_AO_CHAN) {
4394 printk("bug! n_aochan > MAX_N_AO_CHAN\n");
4395 return -EINVAL;
4396 }
4397
4398 ret = comedi_alloc_subdevices(dev, NI_NUM_SUBDEVICES);
4399 if (ret)
4400 return ret;
4401
4402 /* analog input subdevice */
4403
4404 s = &dev->subdevices[NI_AI_SUBDEV];
4405 dev->read_subdev = s;
4406 if (board->n_adchan) {
4407 s->type = COMEDI_SUBD_AI;
4408 s->subdev_flags =
4409 SDF_READABLE | SDF_DIFF | SDF_DITHER | SDF_CMD_READ;
4410 if (board->reg_type != ni_reg_611x)
4411 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER;
4412 if (board->adbits > 16)
4413 s->subdev_flags |= SDF_LSAMPL;
4414 if (board->reg_type & ni_reg_m_series_mask)
4415 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4416 s->n_chan = board->n_adchan;
4417 s->len_chanlist = 512;
4418 s->maxdata = (1 << board->adbits) - 1;
4419 s->range_table = ni_range_lkup[board->gainlkup];
4420 s->insn_read = &ni_ai_insn_read;
4421 s->insn_config = &ni_ai_insn_config;
4422 s->do_cmdtest = &ni_ai_cmdtest;
4423 s->do_cmd = &ni_ai_cmd;
4424 s->cancel = &ni_ai_reset;
4425 s->poll = &ni_ai_poll;
4426 s->munge = &ni_ai_munge;
4427 #ifdef PCIDMA
4428 s->async_dma_dir = DMA_FROM_DEVICE;
4429 #endif
4430 } else {
4431 s->type = COMEDI_SUBD_UNUSED;
4432 }
4433
4434 /* analog output subdevice */
4435
4436 s = &dev->subdevices[NI_AO_SUBDEV];
4437 if (board->n_aochan) {
4438 s->type = COMEDI_SUBD_AO;
4439 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND;
4440 if (board->reg_type & ni_reg_m_series_mask)
4441 s->subdev_flags |= SDF_SOFT_CALIBRATED;
4442 s->n_chan = board->n_aochan;
4443 s->maxdata = (1 << board->aobits) - 1;
4444 s->range_table = board->ao_range_table;
4445 s->insn_read = &ni_ao_insn_read;
4446 if (board->reg_type & ni_reg_6xxx_mask) {
4447 s->insn_write = &ni_ao_insn_write_671x;
4448 } else {
4449 s->insn_write = &ni_ao_insn_write;
4450 }
4451 s->insn_config = &ni_ao_insn_config;
4452 #ifdef PCIDMA
4453 if (board->n_aochan) {
4454 s->async_dma_dir = DMA_TO_DEVICE;
4455 #else
4456 if (board->ao_fifo_depth) {
4457 #endif
4458 dev->write_subdev = s;
4459 s->subdev_flags |= SDF_CMD_WRITE;
4460 s->do_cmd = &ni_ao_cmd;
4461 s->do_cmdtest = &ni_ao_cmdtest;
4462 s->len_chanlist = board->n_aochan;
4463 if ((board->reg_type & ni_reg_m_series_mask) == 0)
4464 s->munge = ni_ao_munge;
4465 }
4466 s->cancel = &ni_ao_reset;
4467 } else {
4468 s->type = COMEDI_SUBD_UNUSED;
4469 }
4470 if ((board->reg_type & ni_reg_67xx_mask))
4471 init_ao_67xx(dev, s);
4472
4473 /* digital i/o subdevice */
4474
4475 s = &dev->subdevices[NI_DIO_SUBDEV];
4476 s->type = COMEDI_SUBD_DIO;
4477 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
4478 s->maxdata = 1;
4479 s->io_bits = 0; /* all bits input */
4480 s->range_table = &range_digital;
4481 s->n_chan = board->num_p0_dio_channels;
4482 if (board->reg_type & ni_reg_m_series_mask) {
4483 s->subdev_flags |=
4484 SDF_LSAMPL | SDF_CMD_WRITE /* | SDF_CMD_READ */ ;
4485 s->insn_bits = &ni_m_series_dio_insn_bits;
4486 s->insn_config = &ni_m_series_dio_insn_config;
4487 s->do_cmd = &ni_cdio_cmd;
4488 s->do_cmdtest = &ni_cdio_cmdtest;
4489 s->cancel = &ni_cdio_cancel;
4490 s->async_dma_dir = DMA_BIDIRECTIONAL;
4491 s->len_chanlist = s->n_chan;
4492
4493 ni_writel(CDO_Reset_Bit | CDI_Reset_Bit, M_Offset_CDIO_Command);
4494 ni_writel(s->io_bits, M_Offset_DIO_Direction);
4495 } else {
4496 s->insn_bits = &ni_dio_insn_bits;
4497 s->insn_config = &ni_dio_insn_config;
4498 devpriv->dio_control = DIO_Pins_Dir(s->io_bits);
4499 ni_writew(devpriv->dio_control, DIO_Control_Register);
4500 }
4501
4502 /* 8255 device */
4503 s = &dev->subdevices[NI_8255_DIO_SUBDEV];
4504 if (board->has_8255) {
4505 subdev_8255_init(dev, s, ni_8255_callback, (unsigned long)dev);
4506 } else {
4507 s->type = COMEDI_SUBD_UNUSED;
4508 }
4509
4510 /* formerly general purpose counter/timer device, but no longer used */
4511 s = &dev->subdevices[NI_UNUSED_SUBDEV];
4512 s->type = COMEDI_SUBD_UNUSED;
4513
4514 /* calibration subdevice -- ai and ao */
4515 s = &dev->subdevices[NI_CALIBRATION_SUBDEV];
4516 s->type = COMEDI_SUBD_CALIB;
4517 if (board->reg_type & ni_reg_m_series_mask) {
4518 /* internal PWM analog output used for AI nonlinearity calibration */
4519 s->subdev_flags = SDF_INTERNAL;
4520 s->insn_config = &ni_m_series_pwm_config;
4521 s->n_chan = 1;
4522 s->maxdata = 0;
4523 ni_writel(0x0, M_Offset_Cal_PWM);
4524 } else if (board->reg_type == ni_reg_6143) {
4525 /* internal PWM analog output used for AI nonlinearity calibration */
4526 s->subdev_flags = SDF_INTERNAL;
4527 s->insn_config = &ni_6143_pwm_config;
4528 s->n_chan = 1;
4529 s->maxdata = 0;
4530 } else {
4531 s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
4532 s->insn_read = &ni_calib_insn_read;
4533 s->insn_write = &ni_calib_insn_write;
4534 caldac_setup(dev, s);
4535 }
4536
4537 /* EEPROM */
4538 s = &dev->subdevices[NI_EEPROM_SUBDEV];
4539 s->type = COMEDI_SUBD_MEMORY;
4540 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
4541 s->maxdata = 0xff;
4542 if (board->reg_type & ni_reg_m_series_mask) {
4543 s->n_chan = M_SERIES_EEPROM_SIZE;
4544 s->insn_read = &ni_m_series_eeprom_insn_read;
4545 } else {
4546 s->n_chan = 512;
4547 s->insn_read = &ni_eeprom_insn_read;
4548 }
4549
4550 /* PFI */
4551 s = &dev->subdevices[NI_PFI_DIO_SUBDEV];
4552 s->type = COMEDI_SUBD_DIO;
4553 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4554 if (board->reg_type & ni_reg_m_series_mask) {
4555 unsigned i;
4556 s->n_chan = 16;
4557 ni_writew(s->state, M_Offset_PFI_DO);
4558 for (i = 0; i < NUM_PFI_OUTPUT_SELECT_REGS; ++i) {
4559 ni_writew(devpriv->pfi_output_select_reg[i],
4560 M_Offset_PFI_Output_Select(i + 1));
4561 }
4562 } else {
4563 s->n_chan = 10;
4564 }
4565 s->maxdata = 1;
4566 if (board->reg_type & ni_reg_m_series_mask) {
4567 s->insn_bits = &ni_pfi_insn_bits;
4568 }
4569 s->insn_config = &ni_pfi_insn_config;
4570 ni_set_bits(dev, IO_Bidirection_Pin_Register, ~0, 0);
4571
4572 /* cs5529 calibration adc */
4573 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV];
4574 if (board->reg_type & ni_reg_67xx_mask) {
4575 s->type = COMEDI_SUBD_AI;
4576 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL;
4577 /* one channel for each analog output channel */
4578 s->n_chan = board->n_aochan;
4579 s->maxdata = (1 << 16) - 1;
4580 s->range_table = &range_unknown; /* XXX */
4581 s->insn_read = cs5529_ai_insn_read;
4582 s->insn_config = NULL;
4583 init_cs5529(dev);
4584 } else {
4585 s->type = COMEDI_SUBD_UNUSED;
4586 }
4587
4588 /* Serial */
4589 s = &dev->subdevices[NI_SERIAL_SUBDEV];
4590 s->type = COMEDI_SUBD_SERIAL;
4591 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4592 s->n_chan = 1;
4593 s->maxdata = 0xff;
4594 s->insn_config = ni_serial_insn_config;
4595 devpriv->serial_interval_ns = 0;
4596 devpriv->serial_hw_mode = 0;
4597
4598 /* RTSI */
4599 s = &dev->subdevices[NI_RTSI_SUBDEV];
4600 s->type = COMEDI_SUBD_DIO;
4601 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
4602 s->n_chan = 8;
4603 s->maxdata = 1;
4604 s->insn_bits = ni_rtsi_insn_bits;
4605 s->insn_config = ni_rtsi_insn_config;
4606 ni_rtsi_init(dev);
4607
4608 if (board->reg_type & ni_reg_m_series_mask) {
4609 counter_variant = ni_gpct_variant_m_series;
4610 } else {
4611 counter_variant = ni_gpct_variant_e_series;
4612 }
4613 devpriv->counter_dev = ni_gpct_device_construct(dev,
4614 &ni_gpct_write_register,
4615 &ni_gpct_read_register,
4616 counter_variant,
4617 NUM_GPCT);
4618 /* General purpose counters */
4619 for (j = 0; j < NUM_GPCT; ++j) {
4620 s = &dev->subdevices[NI_GPCT_SUBDEV(j)];
4621 s->type = COMEDI_SUBD_COUNTER;
4622 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL;
4623 s->n_chan = 3;
4624 if (board->reg_type & ni_reg_m_series_mask)
4625 s->maxdata = 0xffffffff;
4626 else
4627 s->maxdata = 0xffffff;
4628 s->insn_read = &ni_gpct_insn_read;
4629 s->insn_write = &ni_gpct_insn_write;
4630 s->insn_config = &ni_gpct_insn_config;
4631 #ifdef PCIDMA
4632 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */;
4633 s->do_cmd = &ni_gpct_cmd;
4634 s->len_chanlist = 1;
4635 s->do_cmdtest = &ni_gpct_cmdtest;
4636 s->cancel = &ni_gpct_cancel;
4637 s->async_dma_dir = DMA_BIDIRECTIONAL;
4638 #endif
4639 s->private = &devpriv->counter_dev->counters[j];
4640
4641 devpriv->counter_dev->counters[j].chip_index = 0;
4642 devpriv->counter_dev->counters[j].counter_index = j;
4643 ni_tio_init_counter(&devpriv->counter_dev->counters[j]);
4644 }
4645
4646 /* Frequency output */
4647 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV];
4648 s->type = COMEDI_SUBD_COUNTER;
4649 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
4650 s->n_chan = 1;
4651 s->maxdata = 0xf;
4652 s->insn_read = &ni_freq_out_insn_read;
4653 s->insn_write = &ni_freq_out_insn_write;
4654 s->insn_config = &ni_freq_out_insn_config;
4655
4656 /* ai configuration */
4657 s = &dev->subdevices[NI_AI_SUBDEV];
4658 ni_ai_reset(dev, s);
4659 if ((board->reg_type & ni_reg_6xxx_mask) == 0) {
4660 /* BEAM is this needed for PCI-6143 ?? */
4661 devpriv->clock_and_fout =
4662 Slow_Internal_Time_Divide_By_2 |
4663 Slow_Internal_Timebase |
4664 Clock_To_Board_Divide_By_2 |
4665 Clock_To_Board |
4666 AI_Output_Divide_By_2 | AO_Output_Divide_By_2;
4667 } else {
4668 devpriv->clock_and_fout =
4669 Slow_Internal_Time_Divide_By_2 |
4670 Slow_Internal_Timebase |
4671 Clock_To_Board_Divide_By_2 | Clock_To_Board;
4672 }
4673 devpriv->stc_writew(dev, devpriv->clock_and_fout,
4674 Clock_and_FOUT_Register);
4675
4676 /* analog output configuration */
4677 s = &dev->subdevices[NI_AO_SUBDEV];
4678 ni_ao_reset(dev, s);
4679
4680 if (dev->irq) {
4681 devpriv->stc_writew(dev,
4682 (IRQ_POLARITY ? Interrupt_Output_Polarity :
4683 0) | (Interrupt_Output_On_3_Pins & 0) |
4684 Interrupt_A_Enable | Interrupt_B_Enable |
4685 Interrupt_A_Output_Select(interrupt_pin
4686 (dev->irq)) |
4687 Interrupt_B_Output_Select(interrupt_pin
4688 (dev->irq)),
4689 Interrupt_Control_Register);
4690 }
4691
4692 /* DMA setup */
4693 ni_writeb(devpriv->ai_ao_select_reg, AI_AO_Select);
4694 ni_writeb(devpriv->g0_g1_select_reg, G0_G1_Select);
4695
4696 if (board->reg_type & ni_reg_6xxx_mask) {
4697 ni_writeb(0, Magic_611x);
4698 } else if (board->reg_type & ni_reg_m_series_mask) {
4699 int channel;
4700 for (channel = 0; channel < board->n_aochan; ++channel) {
4701 ni_writeb(0xf, M_Offset_AO_Waveform_Order(channel));
4702 ni_writeb(0x0,
4703 M_Offset_AO_Reference_Attenuation(channel));
4704 }
4705 ni_writeb(0x0, M_Offset_AO_Calibration);
4706 }
4707
4708 printk("\n");
4709 return 0;
4710 }
4711
4712 static int ni_8255_callback(int dir, int port, int data, unsigned long arg)
4713 {
4714 struct comedi_device *dev = (struct comedi_device *)arg;
4715 struct ni_private *devpriv __maybe_unused = dev->private;
4716
4717 if (dir) {
4718 ni_writeb(data, Port_A + 2 * port);
4719 return 0;
4720 } else {
4721 return ni_readb(Port_A + 2 * port);
4722 }
4723 }
4724
4725 /*
4726 presents the EEPROM as a subdevice
4727 */
4728
4729 static int ni_eeprom_insn_read(struct comedi_device *dev,
4730 struct comedi_subdevice *s,
4731 struct comedi_insn *insn, unsigned int *data)
4732 {
4733 data[0] = ni_read_eeprom(dev, CR_CHAN(insn->chanspec));
4734
4735 return 1;
4736 }
4737
4738 /*
4739 reads bytes out of eeprom
4740 */
4741
4742 static int ni_read_eeprom(struct comedi_device *dev, int addr)
4743 {
4744 struct ni_private *devpriv __maybe_unused = dev->private;
4745 int bit;
4746 int bitstring;
4747
4748 bitstring = 0x0300 | ((addr & 0x100) << 3) | (addr & 0xff);
4749 ni_writeb(0x04, Serial_Command);
4750 for (bit = 0x8000; bit; bit >>= 1) {
4751 ni_writeb(0x04 | ((bit & bitstring) ? 0x02 : 0),
4752 Serial_Command);
4753 ni_writeb(0x05 | ((bit & bitstring) ? 0x02 : 0),
4754 Serial_Command);
4755 }
4756 bitstring = 0;
4757 for (bit = 0x80; bit; bit >>= 1) {
4758 ni_writeb(0x04, Serial_Command);
4759 ni_writeb(0x05, Serial_Command);
4760 bitstring |= ((ni_readb(XXX_Status) & PROMOUT) ? bit : 0);
4761 }
4762 ni_writeb(0x00, Serial_Command);
4763
4764 return bitstring;
4765 }
4766
4767 static int ni_m_series_eeprom_insn_read(struct comedi_device *dev,
4768 struct comedi_subdevice *s,
4769 struct comedi_insn *insn,
4770 unsigned int *data)
4771 {
4772 struct ni_private *devpriv = dev->private;
4773
4774 data[0] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)];
4775
4776 return 1;
4777 }
4778
4779 static int ni_get_pwm_config(struct comedi_device *dev, unsigned int *data)
4780 {
4781 struct ni_private *devpriv = dev->private;
4782
4783 data[1] = devpriv->pwm_up_count * devpriv->clock_ns;
4784 data[2] = devpriv->pwm_down_count * devpriv->clock_ns;
4785 return 3;
4786 }
4787
4788 static int ni_m_series_pwm_config(struct comedi_device *dev,
4789 struct comedi_subdevice *s,
4790 struct comedi_insn *insn, unsigned int *data)
4791 {
4792 struct ni_private *devpriv = dev->private;
4793 unsigned up_count, down_count;
4794
4795 switch (data[0]) {
4796 case INSN_CONFIG_PWM_OUTPUT:
4797 switch (data[1]) {
4798 case TRIG_ROUND_NEAREST:
4799 up_count =
4800 (data[2] +
4801 devpriv->clock_ns / 2) / devpriv->clock_ns;
4802 break;
4803 case TRIG_ROUND_DOWN:
4804 up_count = data[2] / devpriv->clock_ns;
4805 break;
4806 case TRIG_ROUND_UP:
4807 up_count =
4808 (data[2] + devpriv->clock_ns -
4809 1) / devpriv->clock_ns;
4810 break;
4811 default:
4812 return -EINVAL;
4813 break;
4814 }
4815 switch (data[3]) {
4816 case TRIG_ROUND_NEAREST:
4817 down_count =
4818 (data[4] +
4819 devpriv->clock_ns / 2) / devpriv->clock_ns;
4820 break;
4821 case TRIG_ROUND_DOWN:
4822 down_count = data[4] / devpriv->clock_ns;
4823 break;
4824 case TRIG_ROUND_UP:
4825 down_count =
4826 (data[4] + devpriv->clock_ns -
4827 1) / devpriv->clock_ns;
4828 break;
4829 default:
4830 return -EINVAL;
4831 break;
4832 }
4833 if (up_count * devpriv->clock_ns != data[2] ||
4834 down_count * devpriv->clock_ns != data[4]) {
4835 data[2] = up_count * devpriv->clock_ns;
4836 data[4] = down_count * devpriv->clock_ns;
4837 return -EAGAIN;
4838 }
4839 ni_writel(MSeries_Cal_PWM_High_Time_Bits(up_count) |
4840 MSeries_Cal_PWM_Low_Time_Bits(down_count),
4841 M_Offset_Cal_PWM);
4842 devpriv->pwm_up_count = up_count;
4843 devpriv->pwm_down_count = down_count;
4844 return 5;
4845 break;
4846 case INSN_CONFIG_GET_PWM_OUTPUT:
4847 return ni_get_pwm_config(dev, data);
4848 break;
4849 default:
4850 return -EINVAL;
4851 break;
4852 }
4853 return 0;
4854 }
4855
4856 static int ni_6143_pwm_config(struct comedi_device *dev,
4857 struct comedi_subdevice *s,
4858 struct comedi_insn *insn, unsigned int *data)
4859 {
4860 struct ni_private *devpriv = dev->private;
4861 unsigned up_count, down_count;
4862
4863 switch (data[0]) {
4864 case INSN_CONFIG_PWM_OUTPUT:
4865 switch (data[1]) {
4866 case TRIG_ROUND_NEAREST:
4867 up_count =
4868 (data[2] +
4869 devpriv->clock_ns / 2) / devpriv->clock_ns;
4870 break;
4871 case TRIG_ROUND_DOWN:
4872 up_count = data[2] / devpriv->clock_ns;
4873 break;
4874 case TRIG_ROUND_UP:
4875 up_count =
4876 (data[2] + devpriv->clock_ns -
4877 1) / devpriv->clock_ns;
4878 break;
4879 default:
4880 return -EINVAL;
4881 break;
4882 }
4883 switch (data[3]) {
4884 case TRIG_ROUND_NEAREST:
4885 down_count =
4886 (data[4] +
4887 devpriv->clock_ns / 2) / devpriv->clock_ns;
4888 break;
4889 case TRIG_ROUND_DOWN:
4890 down_count = data[4] / devpriv->clock_ns;
4891 break;
4892 case TRIG_ROUND_UP:
4893 down_count =
4894 (data[4] + devpriv->clock_ns -
4895 1) / devpriv->clock_ns;
4896 break;
4897 default:
4898 return -EINVAL;
4899 break;
4900 }
4901 if (up_count * devpriv->clock_ns != data[2] ||
4902 down_count * devpriv->clock_ns != data[4]) {
4903 data[2] = up_count * devpriv->clock_ns;
4904 data[4] = down_count * devpriv->clock_ns;
4905 return -EAGAIN;
4906 }
4907 ni_writel(up_count, Calibration_HighTime_6143);
4908 devpriv->pwm_up_count = up_count;
4909 ni_writel(down_count, Calibration_LowTime_6143);
4910 devpriv->pwm_down_count = down_count;
4911 return 5;
4912 break;
4913 case INSN_CONFIG_GET_PWM_OUTPUT:
4914 return ni_get_pwm_config(dev, data);
4915 default:
4916 return -EINVAL;
4917 break;
4918 }
4919 return 0;
4920 }
4921
4922 static void ni_write_caldac(struct comedi_device *dev, int addr, int val);
4923 /*
4924 calibration subdevice
4925 */
4926 static int ni_calib_insn_write(struct comedi_device *dev,
4927 struct comedi_subdevice *s,
4928 struct comedi_insn *insn, unsigned int *data)
4929 {
4930 ni_write_caldac(dev, CR_CHAN(insn->chanspec), data[0]);
4931
4932 return 1;
4933 }
4934
4935 static int ni_calib_insn_read(struct comedi_device *dev,
4936 struct comedi_subdevice *s,
4937 struct comedi_insn *insn, unsigned int *data)
4938 {
4939 struct ni_private *devpriv = dev->private;
4940
4941 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)];
4942
4943 return 1;
4944 }
4945
4946 static int pack_mb88341(int addr, int val, int *bitstring);
4947 static int pack_dac8800(int addr, int val, int *bitstring);
4948 static int pack_dac8043(int addr, int val, int *bitstring);
4949 static int pack_ad8522(int addr, int val, int *bitstring);
4950 static int pack_ad8804(int addr, int val, int *bitstring);
4951 static int pack_ad8842(int addr, int val, int *bitstring);
4952
4953 struct caldac_struct {
4954 int n_chans;
4955 int n_bits;
4956 int (*packbits) (int, int, int *);
4957 };
4958
4959 static struct caldac_struct caldacs[] = {
4960 [mb88341] = {12, 8, pack_mb88341},
4961 [dac8800] = {8, 8, pack_dac8800},
4962 [dac8043] = {1, 12, pack_dac8043},
4963 [ad8522] = {2, 12, pack_ad8522},
4964 [ad8804] = {12, 8, pack_ad8804},
4965 [ad8842] = {8, 8, pack_ad8842},
4966 [ad8804_debug] = {16, 8, pack_ad8804},
4967 };
4968
4969 static void caldac_setup(struct comedi_device *dev, struct comedi_subdevice *s)
4970 {
4971 const struct ni_board_struct *board = comedi_board(dev);
4972 struct ni_private *devpriv = dev->private;
4973 int i, j;
4974 int n_dacs;
4975 int n_chans = 0;
4976 int n_bits;
4977 int diffbits = 0;
4978 int type;
4979 int chan;
4980
4981 type = board->caldac[0];
4982 if (type == caldac_none)
4983 return;
4984 n_bits = caldacs[type].n_bits;
4985 for (i = 0; i < 3; i++) {
4986 type = board->caldac[i];
4987 if (type == caldac_none)
4988 break;
4989 if (caldacs[type].n_bits != n_bits)
4990 diffbits = 1;
4991 n_chans += caldacs[type].n_chans;
4992 }
4993 n_dacs = i;
4994 s->n_chan = n_chans;
4995
4996 if (diffbits) {
4997 unsigned int *maxdata_list;
4998
4999 if (n_chans > MAX_N_CALDACS) {
5000 printk("BUG! MAX_N_CALDACS too small\n");
5001 }
5002 s->maxdata_list = maxdata_list = devpriv->caldac_maxdata_list;
5003 chan = 0;
5004 for (i = 0; i < n_dacs; i++) {
5005 type = board->caldac[i];
5006 for (j = 0; j < caldacs[type].n_chans; j++) {
5007 maxdata_list[chan] =
5008 (1 << caldacs[type].n_bits) - 1;
5009 chan++;
5010 }
5011 }
5012
5013 for (chan = 0; chan < s->n_chan; chan++)
5014 ni_write_caldac(dev, i, s->maxdata_list[i] / 2);
5015 } else {
5016 type = board->caldac[0];
5017 s->maxdata = (1 << caldacs[type].n_bits) - 1;
5018
5019 for (chan = 0; chan < s->n_chan; chan++)
5020 ni_write_caldac(dev, i, s->maxdata / 2);
5021 }
5022 }
5023
5024 static void ni_write_caldac(struct comedi_device *dev, int addr, int val)
5025 {
5026 const struct ni_board_struct *board = comedi_board(dev);
5027 struct ni_private *devpriv = dev->private;
5028 unsigned int loadbit = 0, bits = 0, bit, bitstring = 0;
5029 int i;
5030 int type;
5031
5032 /* printk("ni_write_caldac: chan=%d val=%d\n",addr,val); */
5033 if (devpriv->caldacs[addr] == val)
5034 return;
5035 devpriv->caldacs[addr] = val;
5036
5037 for (i = 0; i < 3; i++) {
5038 type = board->caldac[i];
5039 if (type == caldac_none)
5040 break;
5041 if (addr < caldacs[type].n_chans) {
5042 bits = caldacs[type].packbits(addr, val, &bitstring);
5043 loadbit = SerDacLd(i);
5044 /* printk("caldac: using i=%d addr=%d %x\n",i,addr,bitstring); */
5045 break;
5046 }
5047 addr -= caldacs[type].n_chans;
5048 }
5049
5050 for (bit = 1 << (bits - 1); bit; bit >>= 1) {
5051 ni_writeb(((bit & bitstring) ? 0x02 : 0), Serial_Command);
5052 udelay(1);
5053 ni_writeb(1 | ((bit & bitstring) ? 0x02 : 0), Serial_Command);
5054 udelay(1);
5055 }
5056 ni_writeb(loadbit, Serial_Command);
5057 udelay(1);
5058 ni_writeb(0, Serial_Command);
5059 }
5060
5061 static int pack_mb88341(int addr, int val, int *bitstring)
5062 {
5063 /*
5064 Fujitsu MB 88341
5065 Note that address bits are reversed. Thanks to
5066 Ingo Keen for noticing this.
5067
5068 Note also that the 88341 expects address values from
5069 1-12, whereas we use channel numbers 0-11. The NI
5070 docs use 1-12, also, so be careful here.
5071 */
5072 addr++;
5073 *bitstring = ((addr & 0x1) << 11) |
5074 ((addr & 0x2) << 9) |
5075 ((addr & 0x4) << 7) | ((addr & 0x8) << 5) | (val & 0xff);
5076 return 12;
5077 }
5078
5079 static int pack_dac8800(int addr, int val, int *bitstring)
5080 {
5081 *bitstring = ((addr & 0x7) << 8) | (val & 0xff);
5082 return 11;
5083 }
5084
5085 static int pack_dac8043(int addr, int val, int *bitstring)
5086 {
5087 *bitstring = val & 0xfff;
5088 return 12;
5089 }
5090
5091 static int pack_ad8522(int addr, int val, int *bitstring)
5092 {
5093 *bitstring = (val & 0xfff) | (addr ? 0xc000 : 0xa000);
5094 return 16;
5095 }
5096
5097 static int pack_ad8804(int addr, int val, int *bitstring)
5098 {
5099 *bitstring = ((addr & 0xf) << 8) | (val & 0xff);
5100 return 12;
5101 }
5102
5103 static int pack_ad8842(int addr, int val, int *bitstring)
5104 {
5105 *bitstring = ((addr + 1) << 8) | (val & 0xff);
5106 return 12;
5107 }
5108
5109 #if 0
5110 /*
5111 * Read the GPCTs current value.
5112 */
5113 static int GPCT_G_Watch(struct comedi_device *dev, int chan)
5114 {
5115 unsigned int hi1, hi2, lo;
5116
5117 devpriv->gpct_command[chan] &= ~G_Save_Trace;
5118 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5119 G_Command_Register(chan));
5120
5121 devpriv->gpct_command[chan] |= G_Save_Trace;
5122 devpriv->stc_writew(dev, devpriv->gpct_command[chan],
5123 G_Command_Register(chan));
5124
5125 /* This procedure is used because the two registers cannot
5126 * be read atomically. */
5127 do {
5128 hi1 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5129 lo = devpriv->stc_readw(dev, G_Save_Register_Low(chan));
5130 hi2 = devpriv->stc_readw(dev, G_Save_Register_High(chan));
5131 } while (hi1 != hi2);
5132
5133 return (hi1 << 16) | lo;
5134 }
5135
5136 static void GPCT_Reset(struct comedi_device *dev, int chan)
5137 {
5138 int temp_ack_reg = 0;
5139
5140 /* printk("GPCT_Reset..."); */
5141 devpriv->gpct_cur_operation[chan] = GPCT_RESET;
5142
5143 switch (chan) {
5144 case 0:
5145 devpriv->stc_writew(dev, G0_Reset, Joint_Reset_Register);
5146 ni_set_bits(dev, Interrupt_A_Enable_Register,
5147 G0_TC_Interrupt_Enable, 0);
5148 ni_set_bits(dev, Interrupt_A_Enable_Register,
5149 G0_Gate_Interrupt_Enable, 0);
5150 temp_ack_reg |= G0_Gate_Error_Confirm;
5151 temp_ack_reg |= G0_TC_Error_Confirm;
5152 temp_ack_reg |= G0_TC_Interrupt_Ack;
5153 temp_ack_reg |= G0_Gate_Interrupt_Ack;
5154 devpriv->stc_writew(dev, temp_ack_reg,
5155 Interrupt_A_Ack_Register);
5156
5157 /* problem...this interferes with the other ctr... */
5158 devpriv->an_trig_etc_reg |= GPFO_0_Output_Enable;
5159 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5160 Analog_Trigger_Etc_Register);
5161 break;
5162 case 1:
5163 devpriv->stc_writew(dev, G1_Reset, Joint_Reset_Register);
5164 ni_set_bits(dev, Interrupt_B_Enable_Register,
5165 G1_TC_Interrupt_Enable, 0);
5166 ni_set_bits(dev, Interrupt_B_Enable_Register,
5167 G0_Gate_Interrupt_Enable, 0);
5168 temp_ack_reg |= G1_Gate_Error_Confirm;
5169 temp_ack_reg |= G1_TC_Error_Confirm;
5170 temp_ack_reg |= G1_TC_Interrupt_Ack;
5171 temp_ack_reg |= G1_Gate_Interrupt_Ack;
5172 devpriv->stc_writew(dev, temp_ack_reg,
5173 Interrupt_B_Ack_Register);
5174
5175 devpriv->an_trig_etc_reg |= GPFO_1_Output_Enable;
5176 devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
5177 Analog_Trigger_Etc_Register);
5178 break;
5179 }
5180
5181 devpriv->gpct_mode[chan] = 0;
5182 devpriv->gpct_input_select[chan] = 0;
5183 devpriv->gpct_command[chan] = 0;
5184
5185 devpriv->gpct_command[chan] |= G_Synchronized_Gate;
5186
5187 devpriv->stc_writew(dev, devpriv->gpct_mode[chan],
5188 G_Mode_Register(chan));
5189 devpriv->stc_writew(dev, devpriv->gpct_input_select[chan],
5190 G_Input_Select_Register(chan));
5191 devpriv->stc_writew(dev, 0, G_Autoincrement_Register(chan));
5192
5193 /* printk("exit GPCT_Reset\n"); */
5194 }
5195
5196 #endif
5197
5198 static int ni_gpct_insn_config(struct comedi_device *dev,
5199 struct comedi_subdevice *s,
5200 struct comedi_insn *insn, unsigned int *data)
5201 {
5202 struct ni_gpct *counter = s->private;
5203 return ni_tio_insn_config(counter, insn, data);
5204 }
5205
5206 static int ni_gpct_insn_read(struct comedi_device *dev,
5207 struct comedi_subdevice *s,
5208 struct comedi_insn *insn, unsigned int *data)
5209 {
5210 struct ni_gpct *counter = s->private;
5211 return ni_tio_rinsn(counter, insn, data);
5212 }
5213
5214 static int ni_gpct_insn_write(struct comedi_device *dev,
5215 struct comedi_subdevice *s,
5216 struct comedi_insn *insn, unsigned int *data)
5217 {
5218 struct ni_gpct *counter = s->private;
5219 return ni_tio_winsn(counter, insn, data);
5220 }
5221
5222 #ifdef PCIDMA
5223 static int ni_gpct_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
5224 {
5225 int retval;
5226 struct ni_gpct *counter = s->private;
5227 /* const struct comedi_cmd *cmd = &s->async->cmd; */
5228
5229 retval = ni_request_gpct_mite_channel(dev, counter->counter_index,
5230 COMEDI_INPUT);
5231 if (retval) {
5232 comedi_error(dev,
5233 "no dma channel available for use by counter");
5234 return retval;
5235 }
5236 ni_tio_acknowledge_and_confirm(counter, NULL, NULL, NULL, NULL);
5237 ni_e_series_enable_second_irq(dev, counter->counter_index, 1);
5238 retval = ni_tio_cmd(counter, s->async);
5239 return retval;
5240 }
5241 #endif
5242
5243 #ifdef PCIDMA
5244 static int ni_gpct_cmdtest(struct comedi_device *dev,
5245 struct comedi_subdevice *s, struct comedi_cmd *cmd)
5246 {
5247 struct ni_gpct *counter = s->private;
5248
5249 return ni_tio_cmdtest(counter, cmd);
5250 return -ENOTSUPP;
5251 }
5252 #endif
5253
5254 static int ni_gpct_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
5255 {
5256 #ifdef PCIDMA
5257 struct ni_gpct *counter = s->private;
5258 int retval;
5259
5260 retval = ni_tio_cancel(counter);
5261 ni_e_series_enable_second_irq(dev, counter->counter_index, 0);
5262 ni_release_gpct_mite_channel(dev, counter->counter_index);
5263 return retval;
5264 #else
5265 return 0;
5266 #endif
5267 }
5268
5269 /*
5270 *
5271 * Programmable Function Inputs
5272 *
5273 */
5274
5275 static int ni_m_series_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5276 unsigned source)
5277 {
5278 struct ni_private *devpriv = dev->private;
5279 unsigned pfi_reg_index;
5280 unsigned array_offset;
5281
5282 if ((source & 0x1f) != source)
5283 return -EINVAL;
5284 pfi_reg_index = 1 + chan / 3;
5285 array_offset = pfi_reg_index - 1;
5286 devpriv->pfi_output_select_reg[array_offset] &=
5287 ~MSeries_PFI_Output_Select_Mask(chan);
5288 devpriv->pfi_output_select_reg[array_offset] |=
5289 MSeries_PFI_Output_Select_Bits(chan, source);
5290 ni_writew(devpriv->pfi_output_select_reg[array_offset],
5291 M_Offset_PFI_Output_Select(pfi_reg_index));
5292 return 2;
5293 }
5294
5295 static int ni_old_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5296 unsigned source)
5297 {
5298 /* pre-m-series boards have fixed signals on pfi pins */
5299 if (source != ni_old_get_pfi_routing(dev, chan))
5300 return -EINVAL;
5301 return 2;
5302 }
5303
5304 static int ni_set_pfi_routing(struct comedi_device *dev, unsigned chan,
5305 unsigned source)
5306 {
5307 const struct ni_board_struct *board = comedi_board(dev);
5308
5309 if (board->reg_type & ni_reg_m_series_mask)
5310 return ni_m_series_set_pfi_routing(dev, chan, source);
5311 else
5312 return ni_old_set_pfi_routing(dev, chan, source);
5313 }
5314
5315 static unsigned ni_m_series_get_pfi_routing(struct comedi_device *dev,
5316 unsigned chan)
5317 {
5318 struct ni_private *devpriv = dev->private;
5319 const unsigned array_offset = chan / 3;
5320
5321 return MSeries_PFI_Output_Select_Source(chan,
5322 devpriv->
5323 pfi_output_select_reg
5324 [array_offset]);
5325 }
5326
5327 static unsigned ni_old_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5328 {
5329 /* pre-m-series boards have fixed signals on pfi pins */
5330 switch (chan) {
5331 case 0:
5332 return NI_PFI_OUTPUT_AI_START1;
5333 break;
5334 case 1:
5335 return NI_PFI_OUTPUT_AI_START2;
5336 break;
5337 case 2:
5338 return NI_PFI_OUTPUT_AI_CONVERT;
5339 break;
5340 case 3:
5341 return NI_PFI_OUTPUT_G_SRC1;
5342 break;
5343 case 4:
5344 return NI_PFI_OUTPUT_G_GATE1;
5345 break;
5346 case 5:
5347 return NI_PFI_OUTPUT_AO_UPDATE_N;
5348 break;
5349 case 6:
5350 return NI_PFI_OUTPUT_AO_START1;
5351 break;
5352 case 7:
5353 return NI_PFI_OUTPUT_AI_START_PULSE;
5354 break;
5355 case 8:
5356 return NI_PFI_OUTPUT_G_SRC0;
5357 break;
5358 case 9:
5359 return NI_PFI_OUTPUT_G_GATE0;
5360 break;
5361 default:
5362 printk("%s: bug, unhandled case in switch.\n", __func__);
5363 break;
5364 }
5365 return 0;
5366 }
5367
5368 static unsigned ni_get_pfi_routing(struct comedi_device *dev, unsigned chan)
5369 {
5370 const struct ni_board_struct *board = comedi_board(dev);
5371
5372 if (board->reg_type & ni_reg_m_series_mask)
5373 return ni_m_series_get_pfi_routing(dev, chan);
5374 else
5375 return ni_old_get_pfi_routing(dev, chan);
5376 }
5377
5378 static int ni_config_filter(struct comedi_device *dev, unsigned pfi_channel,
5379 enum ni_pfi_filter_select filter)
5380 {
5381 const struct ni_board_struct *board = comedi_board(dev);
5382 struct ni_private *devpriv __maybe_unused = dev->private;
5383 unsigned bits;
5384
5385 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5386 return -ENOTSUPP;
5387 }
5388 bits = ni_readl(M_Offset_PFI_Filter);
5389 bits &= ~MSeries_PFI_Filter_Select_Mask(pfi_channel);
5390 bits |= MSeries_PFI_Filter_Select_Bits(pfi_channel, filter);
5391 ni_writel(bits, M_Offset_PFI_Filter);
5392 return 0;
5393 }
5394
5395 static int ni_pfi_insn_bits(struct comedi_device *dev,
5396 struct comedi_subdevice *s,
5397 struct comedi_insn *insn, unsigned int *data)
5398 {
5399 const struct ni_board_struct *board = comedi_board(dev);
5400 struct ni_private *devpriv __maybe_unused = dev->private;
5401
5402 if ((board->reg_type & ni_reg_m_series_mask) == 0) {
5403 return -ENOTSUPP;
5404 }
5405 if (data[0]) {
5406 s->state &= ~data[0];
5407 s->state |= (data[0] & data[1]);
5408 ni_writew(s->state, M_Offset_PFI_DO);
5409 }
5410 data[1] = ni_readw(M_Offset_PFI_DI);
5411 return insn->n;
5412 }
5413
5414 static int ni_pfi_insn_config(struct comedi_device *dev,
5415 struct comedi_subdevice *s,
5416 struct comedi_insn *insn, unsigned int *data)
5417 {
5418 struct ni_private *devpriv = dev->private;
5419 unsigned int chan;
5420
5421 if (insn->n < 1)
5422 return -EINVAL;
5423
5424 chan = CR_CHAN(insn->chanspec);
5425
5426 switch (data[0]) {
5427 case COMEDI_OUTPUT:
5428 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 1);
5429 break;
5430 case COMEDI_INPUT:
5431 ni_set_bits(dev, IO_Bidirection_Pin_Register, 1 << chan, 0);
5432 break;
5433 case INSN_CONFIG_DIO_QUERY:
5434 data[1] =
5435 (devpriv->io_bidirection_pin_reg & (1 << chan)) ?
5436 COMEDI_OUTPUT : COMEDI_INPUT;
5437 return 0;
5438 break;
5439 case INSN_CONFIG_SET_ROUTING:
5440 return ni_set_pfi_routing(dev, chan, data[1]);
5441 break;
5442 case INSN_CONFIG_GET_ROUTING:
5443 data[1] = ni_get_pfi_routing(dev, chan);
5444 break;
5445 case INSN_CONFIG_FILTER:
5446 return ni_config_filter(dev, chan, data[1]);
5447 break;
5448 default:
5449 return -EINVAL;
5450 }
5451 return 0;
5452 }
5453
5454 /*
5455 *
5456 * NI RTSI Bus Functions
5457 *
5458 */
5459 static void ni_rtsi_init(struct comedi_device *dev)
5460 {
5461 const struct ni_board_struct *board = comedi_board(dev);
5462 struct ni_private *devpriv = dev->private;
5463
5464 /* Initialises the RTSI bus signal switch to a default state */
5465
5466 /* Set clock mode to internal */
5467 devpriv->clock_and_fout2 = MSeries_RTSI_10MHz_Bit;
5468 if (ni_set_master_clock(dev, NI_MIO_INTERNAL_CLOCK, 0) < 0) {
5469 printk("ni_set_master_clock failed, bug?");
5470 }
5471 /* default internal lines routing to RTSI bus lines */
5472 devpriv->rtsi_trig_a_output_reg =
5473 RTSI_Trig_Output_Bits(0,
5474 NI_RTSI_OUTPUT_ADR_START1) |
5475 RTSI_Trig_Output_Bits(1,
5476 NI_RTSI_OUTPUT_ADR_START2) |
5477 RTSI_Trig_Output_Bits(2,
5478 NI_RTSI_OUTPUT_SCLKG) |
5479 RTSI_Trig_Output_Bits(3, NI_RTSI_OUTPUT_DACUPDN);
5480 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5481 RTSI_Trig_A_Output_Register);
5482 devpriv->rtsi_trig_b_output_reg =
5483 RTSI_Trig_Output_Bits(4,
5484 NI_RTSI_OUTPUT_DA_START1) |
5485 RTSI_Trig_Output_Bits(5,
5486 NI_RTSI_OUTPUT_G_SRC0) |
5487 RTSI_Trig_Output_Bits(6, NI_RTSI_OUTPUT_G_GATE0);
5488 if (board->reg_type & ni_reg_m_series_mask)
5489 devpriv->rtsi_trig_b_output_reg |=
5490 RTSI_Trig_Output_Bits(7, NI_RTSI_OUTPUT_RTSI_OSC);
5491 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5492 RTSI_Trig_B_Output_Register);
5493
5494 /*
5495 * Sets the source and direction of the 4 on board lines
5496 * devpriv->stc_writew(dev, 0x0000, RTSI_Board_Register);
5497 */
5498 }
5499
5500 static int ni_rtsi_insn_bits(struct comedi_device *dev,
5501 struct comedi_subdevice *s,
5502 struct comedi_insn *insn, unsigned int *data)
5503 {
5504 data[1] = 0;
5505
5506 return insn->n;
5507 }
5508
5509 /* Find best multiplier/divider to try and get the PLL running at 80 MHz
5510 * given an arbitrary frequency input clock */
5511 static int ni_mseries_get_pll_parameters(unsigned reference_period_ns,
5512 unsigned *freq_divider,
5513 unsigned *freq_multiplier,
5514 unsigned *actual_period_ns)
5515 {
5516 unsigned div;
5517 unsigned best_div = 1;
5518 static const unsigned max_div = 0x10;
5519 unsigned mult;
5520 unsigned best_mult = 1;
5521 static const unsigned max_mult = 0x100;
5522 static const unsigned pico_per_nano = 1000;
5523
5524 const unsigned reference_picosec = reference_period_ns * pico_per_nano;
5525 /* m-series wants the phased-locked loop to output 80MHz, which is divided by 4 to
5526 * 20 MHz for most timing clocks */
5527 static const unsigned target_picosec = 12500;
5528 static const unsigned fudge_factor_80_to_20Mhz = 4;
5529 int best_period_picosec = 0;
5530 for (div = 1; div <= max_div; ++div) {
5531 for (mult = 1; mult <= max_mult; ++mult) {
5532 unsigned new_period_ps =
5533 (reference_picosec * div) / mult;
5534 if (abs(new_period_ps - target_picosec) <
5535 abs(best_period_picosec - target_picosec)) {
5536 best_period_picosec = new_period_ps;
5537 best_div = div;
5538 best_mult = mult;
5539 }
5540 }
5541 }
5542 if (best_period_picosec == 0) {
5543 printk("%s: bug, failed to find pll parameters\n", __func__);
5544 return -EIO;
5545 }
5546 *freq_divider = best_div;
5547 *freq_multiplier = best_mult;
5548 *actual_period_ns =
5549 (best_period_picosec * fudge_factor_80_to_20Mhz +
5550 (pico_per_nano / 2)) / pico_per_nano;
5551 return 0;
5552 }
5553
5554 static inline unsigned num_configurable_rtsi_channels(struct comedi_device *dev)
5555 {
5556 const struct ni_board_struct *board = comedi_board(dev);
5557
5558 if (board->reg_type & ni_reg_m_series_mask)
5559 return 8;
5560 else
5561 return 7;
5562 }
5563
5564 static int ni_mseries_set_pll_master_clock(struct comedi_device *dev,
5565 unsigned source, unsigned period_ns)
5566 {
5567 struct ni_private *devpriv = dev->private;
5568 static const unsigned min_period_ns = 50;
5569 static const unsigned max_period_ns = 1000;
5570 static const unsigned timeout = 1000;
5571 unsigned pll_control_bits;
5572 unsigned freq_divider;
5573 unsigned freq_multiplier;
5574 unsigned i;
5575 int retval;
5576
5577 if (source == NI_MIO_PLL_PXI10_CLOCK)
5578 period_ns = 100;
5579 /* these limits are somewhat arbitrary, but NI advertises 1 to 20MHz range so we'll use that */
5580 if (period_ns < min_period_ns || period_ns > max_period_ns) {
5581 printk
5582 ("%s: you must specify an input clock frequency between %i and %i nanosec "
5583 "for the phased-lock loop.\n", __func__,
5584 min_period_ns, max_period_ns);
5585 return -EINVAL;
5586 }
5587 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5588 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5589 RTSI_Trig_Direction_Register);
5590 pll_control_bits =
5591 MSeries_PLL_Enable_Bit | MSeries_PLL_VCO_Mode_75_150MHz_Bits;
5592 devpriv->clock_and_fout2 |=
5593 MSeries_Timebase1_Select_Bit | MSeries_Timebase3_Select_Bit;
5594 devpriv->clock_and_fout2 &= ~MSeries_PLL_In_Source_Select_Mask;
5595 switch (source) {
5596 case NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK:
5597 devpriv->clock_and_fout2 |=
5598 MSeries_PLL_In_Source_Select_Star_Trigger_Bits;
5599 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5600 &freq_multiplier,
5601 &devpriv->clock_ns);
5602 if (retval < 0)
5603 return retval;
5604 break;
5605 case NI_MIO_PLL_PXI10_CLOCK:
5606 /* pxi clock is 10MHz */
5607 devpriv->clock_and_fout2 |=
5608 MSeries_PLL_In_Source_Select_PXI_Clock10;
5609 retval = ni_mseries_get_pll_parameters(period_ns, &freq_divider,
5610 &freq_multiplier,
5611 &devpriv->clock_ns);
5612 if (retval < 0)
5613 return retval;
5614 break;
5615 default:
5616 {
5617 unsigned rtsi_channel;
5618 static const unsigned max_rtsi_channel = 7;
5619 for (rtsi_channel = 0; rtsi_channel <= max_rtsi_channel;
5620 ++rtsi_channel) {
5621 if (source ==
5622 NI_MIO_PLL_RTSI_CLOCK(rtsi_channel)) {
5623 devpriv->clock_and_fout2 |=
5624 MSeries_PLL_In_Source_Select_RTSI_Bits
5625 (rtsi_channel);
5626 break;
5627 }
5628 }
5629 if (rtsi_channel > max_rtsi_channel)
5630 return -EINVAL;
5631 retval = ni_mseries_get_pll_parameters(period_ns,
5632 &freq_divider,
5633 &freq_multiplier,
5634 &devpriv->
5635 clock_ns);
5636 if (retval < 0)
5637 return retval;
5638 }
5639 break;
5640 }
5641 ni_writew(devpriv->clock_and_fout2, M_Offset_Clock_and_Fout2);
5642 pll_control_bits |=
5643 MSeries_PLL_Divisor_Bits(freq_divider) |
5644 MSeries_PLL_Multiplier_Bits(freq_multiplier);
5645
5646 /* printk("using divider=%i, multiplier=%i for PLL. pll_control_bits = 0x%x\n",
5647 * freq_divider, freq_multiplier, pll_control_bits); */
5648 /* printk("clock_ns=%d\n", devpriv->clock_ns); */
5649 ni_writew(pll_control_bits, M_Offset_PLL_Control);
5650 devpriv->clock_source = source;
5651 /* it seems to typically take a few hundred microseconds for PLL to lock */
5652 for (i = 0; i < timeout; ++i) {
5653 if (ni_readw(M_Offset_PLL_Status) & MSeries_PLL_Locked_Bit) {
5654 break;
5655 }
5656 udelay(1);
5657 }
5658 if (i == timeout) {
5659 printk
5660 ("%s: timed out waiting for PLL to lock to reference clock source %i with period %i ns.\n",
5661 __func__, source, period_ns);
5662 return -ETIMEDOUT;
5663 }
5664 return 3;
5665 }
5666
5667 static int ni_set_master_clock(struct comedi_device *dev, unsigned source,
5668 unsigned period_ns)
5669 {
5670 const struct ni_board_struct *board = comedi_board(dev);
5671 struct ni_private *devpriv = dev->private;
5672
5673 if (source == NI_MIO_INTERNAL_CLOCK) {
5674 devpriv->rtsi_trig_direction_reg &= ~Use_RTSI_Clock_Bit;
5675 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5676 RTSI_Trig_Direction_Register);
5677 devpriv->clock_ns = TIMEBASE_1_NS;
5678 if (board->reg_type & ni_reg_m_series_mask) {
5679 devpriv->clock_and_fout2 &=
5680 ~(MSeries_Timebase1_Select_Bit |
5681 MSeries_Timebase3_Select_Bit);
5682 ni_writew(devpriv->clock_and_fout2,
5683 M_Offset_Clock_and_Fout2);
5684 ni_writew(0, M_Offset_PLL_Control);
5685 }
5686 devpriv->clock_source = source;
5687 } else {
5688 if (board->reg_type & ni_reg_m_series_mask) {
5689 return ni_mseries_set_pll_master_clock(dev, source,
5690 period_ns);
5691 } else {
5692 if (source == NI_MIO_RTSI_CLOCK) {
5693 devpriv->rtsi_trig_direction_reg |=
5694 Use_RTSI_Clock_Bit;
5695 devpriv->stc_writew(dev,
5696 devpriv->
5697 rtsi_trig_direction_reg,
5698 RTSI_Trig_Direction_Register);
5699 if (period_ns == 0) {
5700 printk
5701 ("%s: we don't handle an unspecified clock period correctly yet, returning error.\n",
5702 __func__);
5703 return -EINVAL;
5704 } else {
5705 devpriv->clock_ns = period_ns;
5706 }
5707 devpriv->clock_source = source;
5708 } else
5709 return -EINVAL;
5710 }
5711 }
5712 return 3;
5713 }
5714
5715 static int ni_valid_rtsi_output_source(struct comedi_device *dev, unsigned chan,
5716 unsigned source)
5717 {
5718 const struct ni_board_struct *board = comedi_board(dev);
5719
5720 if (chan >= num_configurable_rtsi_channels(dev)) {
5721 if (chan == old_RTSI_clock_channel) {
5722 if (source == NI_RTSI_OUTPUT_RTSI_OSC)
5723 return 1;
5724 else {
5725 printk
5726 ("%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards.\n",
5727 __func__, chan, old_RTSI_clock_channel);
5728 return 0;
5729 }
5730 }
5731 return 0;
5732 }
5733 switch (source) {
5734 case NI_RTSI_OUTPUT_ADR_START1:
5735 case NI_RTSI_OUTPUT_ADR_START2:
5736 case NI_RTSI_OUTPUT_SCLKG:
5737 case NI_RTSI_OUTPUT_DACUPDN:
5738 case NI_RTSI_OUTPUT_DA_START1:
5739 case NI_RTSI_OUTPUT_G_SRC0:
5740 case NI_RTSI_OUTPUT_G_GATE0:
5741 case NI_RTSI_OUTPUT_RGOUT0:
5742 case NI_RTSI_OUTPUT_RTSI_BRD_0:
5743 return 1;
5744 break;
5745 case NI_RTSI_OUTPUT_RTSI_OSC:
5746 if (board->reg_type & ni_reg_m_series_mask)
5747 return 1;
5748 else
5749 return 0;
5750 break;
5751 default:
5752 return 0;
5753 break;
5754 }
5755 }
5756
5757 static int ni_set_rtsi_routing(struct comedi_device *dev, unsigned chan,
5758 unsigned source)
5759 {
5760 struct ni_private *devpriv = dev->private;
5761
5762 if (ni_valid_rtsi_output_source(dev, chan, source) == 0)
5763 return -EINVAL;
5764 if (chan < 4) {
5765 devpriv->rtsi_trig_a_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5766 devpriv->rtsi_trig_a_output_reg |=
5767 RTSI_Trig_Output_Bits(chan, source);
5768 devpriv->stc_writew(dev, devpriv->rtsi_trig_a_output_reg,
5769 RTSI_Trig_A_Output_Register);
5770 } else if (chan < 8) {
5771 devpriv->rtsi_trig_b_output_reg &= ~RTSI_Trig_Output_Mask(chan);
5772 devpriv->rtsi_trig_b_output_reg |=
5773 RTSI_Trig_Output_Bits(chan, source);
5774 devpriv->stc_writew(dev, devpriv->rtsi_trig_b_output_reg,
5775 RTSI_Trig_B_Output_Register);
5776 }
5777 return 2;
5778 }
5779
5780 static unsigned ni_get_rtsi_routing(struct comedi_device *dev, unsigned chan)
5781 {
5782 struct ni_private *devpriv = dev->private;
5783
5784 if (chan < 4) {
5785 return RTSI_Trig_Output_Source(chan,
5786 devpriv->rtsi_trig_a_output_reg);
5787 } else if (chan < num_configurable_rtsi_channels(dev)) {
5788 return RTSI_Trig_Output_Source(chan,
5789 devpriv->rtsi_trig_b_output_reg);
5790 } else {
5791 if (chan == old_RTSI_clock_channel)
5792 return NI_RTSI_OUTPUT_RTSI_OSC;
5793 printk("%s: bug! should never get here?\n", __func__);
5794 return 0;
5795 }
5796 }
5797
5798 static int ni_rtsi_insn_config(struct comedi_device *dev,
5799 struct comedi_subdevice *s,
5800 struct comedi_insn *insn, unsigned int *data)
5801 {
5802 const struct ni_board_struct *board = comedi_board(dev);
5803 struct ni_private *devpriv = dev->private;
5804 unsigned int chan = CR_CHAN(insn->chanspec);
5805
5806 switch (data[0]) {
5807 case INSN_CONFIG_DIO_OUTPUT:
5808 if (chan < num_configurable_rtsi_channels(dev)) {
5809 devpriv->rtsi_trig_direction_reg |=
5810 RTSI_Output_Bit(chan,
5811 (board->reg_type & ni_reg_m_series_mask) != 0);
5812 } else if (chan == old_RTSI_clock_channel) {
5813 devpriv->rtsi_trig_direction_reg |=
5814 Drive_RTSI_Clock_Bit;
5815 }
5816 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5817 RTSI_Trig_Direction_Register);
5818 break;
5819 case INSN_CONFIG_DIO_INPUT:
5820 if (chan < num_configurable_rtsi_channels(dev)) {
5821 devpriv->rtsi_trig_direction_reg &=
5822 ~RTSI_Output_Bit(chan,
5823 (board->reg_type & ni_reg_m_series_mask) != 0);
5824 } else if (chan == old_RTSI_clock_channel) {
5825 devpriv->rtsi_trig_direction_reg &=
5826 ~Drive_RTSI_Clock_Bit;
5827 }
5828 devpriv->stc_writew(dev, devpriv->rtsi_trig_direction_reg,
5829 RTSI_Trig_Direction_Register);
5830 break;
5831 case INSN_CONFIG_DIO_QUERY:
5832 if (chan < num_configurable_rtsi_channels(dev)) {
5833 data[1] =
5834 (devpriv->rtsi_trig_direction_reg &
5835 RTSI_Output_Bit(chan,
5836 (board->reg_type & ni_reg_m_series_mask) != 0))
5837 ? INSN_CONFIG_DIO_OUTPUT
5838 : INSN_CONFIG_DIO_INPUT;
5839 } else if (chan == old_RTSI_clock_channel) {
5840 data[1] =
5841 (devpriv->rtsi_trig_direction_reg &
5842 Drive_RTSI_Clock_Bit)
5843 ? INSN_CONFIG_DIO_OUTPUT : INSN_CONFIG_DIO_INPUT;
5844 }
5845 return 2;
5846 break;
5847 case INSN_CONFIG_SET_CLOCK_SRC:
5848 return ni_set_master_clock(dev, data[1], data[2]);
5849 break;
5850 case INSN_CONFIG_GET_CLOCK_SRC:
5851 data[1] = devpriv->clock_source;
5852 data[2] = devpriv->clock_ns;
5853 return 3;
5854 break;
5855 case INSN_CONFIG_SET_ROUTING:
5856 return ni_set_rtsi_routing(dev, chan, data[1]);
5857 break;
5858 case INSN_CONFIG_GET_ROUTING:
5859 data[1] = ni_get_rtsi_routing(dev, chan);
5860 return 2;
5861 break;
5862 default:
5863 return -EINVAL;
5864 break;
5865 }
5866 return 1;
5867 }
5868
5869 static int cs5529_wait_for_idle(struct comedi_device *dev)
5870 {
5871 unsigned short status;
5872 const int timeout = HZ;
5873 int i;
5874
5875 for (i = 0; i < timeout; i++) {
5876 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5877 if ((status & CSS_ADC_BUSY) == 0) {
5878 break;
5879 }
5880 set_current_state(TASK_INTERRUPTIBLE);
5881 if (schedule_timeout(1)) {
5882 return -EIO;
5883 }
5884 }
5885 /* printk("looped %i times waiting for idle\n", i); */
5886 if (i == timeout) {
5887 printk("%s: %s: timeout\n", __FILE__, __func__);
5888 return -ETIME;
5889 }
5890 return 0;
5891 }
5892
5893 static void cs5529_command(struct comedi_device *dev, unsigned short value)
5894 {
5895 static const int timeout = 100;
5896 int i;
5897
5898 ni_ao_win_outw(dev, value, CAL_ADC_Command_67xx);
5899 /* give time for command to start being serially clocked into cs5529.
5900 * this insures that the CSS_ADC_BUSY bit will get properly
5901 * set before we exit this function.
5902 */
5903 for (i = 0; i < timeout; i++) {
5904 if ((ni_ao_win_inw(dev, CAL_ADC_Status_67xx) & CSS_ADC_BUSY))
5905 break;
5906 udelay(1);
5907 }
5908 /* printk("looped %i times writing command to cs5529\n", i); */
5909 if (i == timeout) {
5910 comedi_error(dev, "possible problem - never saw adc go busy?");
5911 }
5912 }
5913
5914 /* write to cs5529 register */
5915 static void cs5529_config_write(struct comedi_device *dev, unsigned int value,
5916 unsigned int reg_select_bits)
5917 {
5918 ni_ao_win_outw(dev, ((value >> 16) & 0xff),
5919 CAL_ADC_Config_Data_High_Word_67xx);
5920 ni_ao_win_outw(dev, (value & 0xffff),
5921 CAL_ADC_Config_Data_Low_Word_67xx);
5922 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5923 cs5529_command(dev, CSCMD_COMMAND | reg_select_bits);
5924 if (cs5529_wait_for_idle(dev))
5925 comedi_error(dev, "time or signal in cs5529_config_write()");
5926 }
5927
5928 #ifdef NI_CS5529_DEBUG
5929 /* read from cs5529 register */
5930 static unsigned int cs5529_config_read(struct comedi_device *dev,
5931 unsigned int reg_select_bits)
5932 {
5933 unsigned int value;
5934
5935 reg_select_bits &= CSCMD_REGISTER_SELECT_MASK;
5936 cs5529_command(dev, CSCMD_COMMAND | CSCMD_READ | reg_select_bits);
5937 if (cs5529_wait_for_idle(dev))
5938 comedi_error(dev, "timeout or signal in cs5529_config_read()");
5939 value = (ni_ao_win_inw(dev,
5940 CAL_ADC_Config_Data_High_Word_67xx) << 16) &
5941 0xff0000;
5942 value |= ni_ao_win_inw(dev, CAL_ADC_Config_Data_Low_Word_67xx) & 0xffff;
5943 return value;
5944 }
5945 #endif
5946
5947 static int cs5529_do_conversion(struct comedi_device *dev, unsigned short *data)
5948 {
5949 int retval;
5950 unsigned short status;
5951
5952 cs5529_command(dev, CSCMD_COMMAND | CSCMD_SINGLE_CONVERSION);
5953 retval = cs5529_wait_for_idle(dev);
5954 if (retval) {
5955 comedi_error(dev,
5956 "timeout or signal in cs5529_do_conversion()");
5957 return -ETIME;
5958 }
5959 status = ni_ao_win_inw(dev, CAL_ADC_Status_67xx);
5960 if (status & CSS_OSC_DETECT) {
5961 printk
5962 ("ni_mio_common: cs5529 conversion error, status CSS_OSC_DETECT\n");
5963 return -EIO;
5964 }
5965 if (status & CSS_OVERRANGE) {
5966 printk
5967 ("ni_mio_common: cs5529 conversion error, overrange (ignoring)\n");
5968 }
5969 if (data) {
5970 *data = ni_ao_win_inw(dev, CAL_ADC_Data_67xx);
5971 /* cs5529 returns 16 bit signed data in bipolar mode */
5972 *data ^= (1 << 15);
5973 }
5974 return 0;
5975 }
5976
5977 static int cs5529_ai_insn_read(struct comedi_device *dev,
5978 struct comedi_subdevice *s,
5979 struct comedi_insn *insn, unsigned int *data)
5980 {
5981 int n, retval;
5982 unsigned short sample;
5983 unsigned int channel_select;
5984 const unsigned int INTERNAL_REF = 0x1000;
5985
5986 /* Set calibration adc source. Docs lie, reference select bits 8 to 11
5987 * do nothing. bit 12 seems to chooses internal reference voltage, bit
5988 * 13 causes the adc input to go overrange (maybe reads external reference?) */
5989 if (insn->chanspec & CR_ALT_SOURCE)
5990 channel_select = INTERNAL_REF;
5991 else
5992 channel_select = CR_CHAN(insn->chanspec);
5993 ni_ao_win_outw(dev, channel_select, AO_Calibration_Channel_Select_67xx);
5994
5995 for (n = 0; n < insn->n; n++) {
5996 retval = cs5529_do_conversion(dev, &sample);
5997 if (retval < 0)
5998 return retval;
5999 data[n] = sample;
6000 }
6001 return insn->n;
6002 }
6003
6004 static int init_cs5529(struct comedi_device *dev)
6005 {
6006 unsigned int config_bits =
6007 CSCFG_PORT_MODE | CSCFG_WORD_RATE_2180_CYCLES;
6008
6009 #if 1
6010 /* do self-calibration */
6011 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET_GAIN,
6012 CSCMD_CONFIG_REGISTER);
6013 /* need to force a conversion for calibration to run */
6014 cs5529_do_conversion(dev, NULL);
6015 #else
6016 /* force gain calibration to 1 */
6017 cs5529_config_write(dev, 0x400000, CSCMD_GAIN_REGISTER);
6018 cs5529_config_write(dev, config_bits | CSCFG_SELF_CAL_OFFSET,
6019 CSCMD_CONFIG_REGISTER);
6020 if (cs5529_wait_for_idle(dev))
6021 comedi_error(dev, "timeout or signal in init_cs5529()\n");
6022 #endif
6023 #ifdef NI_CS5529_DEBUG
6024 printk("config: 0x%x\n", cs5529_config_read(dev,
6025 CSCMD_CONFIG_REGISTER));
6026 printk("gain: 0x%x\n", cs5529_config_read(dev, CSCMD_GAIN_REGISTER));
6027 printk("offset: 0x%x\n", cs5529_config_read(dev,
6028 CSCMD_OFFSET_REGISTER));
6029 #endif
6030 return 0;
6031 }
kernel source for telekom puls (alcatel/mediatek)