drivers/spi/spi-sirf.c

   1 /*
   2  * SPI bus driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/bitops.h>
  17 #include <linux/err.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/spi_bitbang.h>
  22 #include <linux/pinctrl/consumer.h>
  23
  24 #define DRIVER_NAME "sirfsoc_spi"
  25
  26 #define SIRFSOC_SPI_CTRL                0x0000
  27 #define SIRFSOC_SPI_CMD                 0x0004
  28 #define SIRFSOC_SPI_TX_RX_EN            0x0008
  29 #define SIRFSOC_SPI_INT_EN              0x000C
  30 #define SIRFSOC_SPI_INT_STATUS          0x0010
  31 #define SIRFSOC_SPI_TX_DMA_IO_CTRL      0x0100
  32 #define SIRFSOC_SPI_TX_DMA_IO_LEN       0x0104
  33 #define SIRFSOC_SPI_TXFIFO_CTRL         0x0108
  34 #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK    0x010C
  35 #define SIRFSOC_SPI_TXFIFO_OP           0x0110
  36 #define SIRFSOC_SPI_TXFIFO_STATUS       0x0114
  37 #define SIRFSOC_SPI_TXFIFO_DATA         0x0118
  38 #define SIRFSOC_SPI_RX_DMA_IO_CTRL      0x0120
  39 #define SIRFSOC_SPI_RX_DMA_IO_LEN       0x0124
  40 #define SIRFSOC_SPI_RXFIFO_CTRL         0x0128
  41 #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK    0x012C
  42 #define SIRFSOC_SPI_RXFIFO_OP           0x0130
  43 #define SIRFSOC_SPI_RXFIFO_STATUS       0x0134
  44 #define SIRFSOC_SPI_RXFIFO_DATA         0x0138
  45 #define SIRFSOC_SPI_DUMMY_DELAY_CTL     0x0144
  46
  47 /* SPI CTRL register defines */
  48 #define SIRFSOC_SPI_SLV_MODE            BIT(16)
  49 #define SIRFSOC_SPI_CMD_MODE            BIT(17)
  50 #define SIRFSOC_SPI_CS_IO_OUT           BIT(18)
  51 #define SIRFSOC_SPI_CS_IO_MODE          BIT(19)
  52 #define SIRFSOC_SPI_CLK_IDLE_STAT       BIT(20)
  53 #define SIRFSOC_SPI_CS_IDLE_STAT        BIT(21)
  54 #define SIRFSOC_SPI_TRAN_MSB            BIT(22)
  55 #define SIRFSOC_SPI_DRV_POS_EDGE        BIT(23)
  56 #define SIRFSOC_SPI_CS_HOLD_TIME        BIT(24)
  57 #define SIRFSOC_SPI_CLK_SAMPLE_MODE     BIT(25)
  58 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8   (0 << 26)
  59 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12  (1 << 26)
  60 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16  (2 << 26)
  61 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32  (3 << 26)
  62 #define SIRFSOC_SPI_CMD_BYTE_NUM(x)             ((x & 3) << 28)
  63 #define SIRFSOC_SPI_ENA_AUTO_CLR                BIT(30)
  64 #define SIRFSOC_SPI_MUL_DAT_MODE                BIT(31)
  65
  66 /* Interrupt Enable */
  67 #define SIRFSOC_SPI_RX_DONE_INT_EN              BIT(0)
  68 #define SIRFSOC_SPI_TX_DONE_INT_EN              BIT(1)
  69 #define SIRFSOC_SPI_RX_OFLOW_INT_EN             BIT(2)
  70 #define SIRFSOC_SPI_TX_UFLOW_INT_EN             BIT(3)
  71 #define SIRFSOC_SPI_RX_IO_DMA_INT_EN    BIT(4)
  72 #define SIRFSOC_SPI_TX_IO_DMA_INT_EN    BIT(5)
  73 #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN  BIT(6)
  74 #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
  75 #define SIRFSOC_SPI_RXFIFO_THD_INT_EN   BIT(8)
  76 #define SIRFSOC_SPI_TXFIFO_THD_INT_EN   BIT(9)
  77 #define SIRFSOC_SPI_FRM_END_INT_EN      BIT(10)
  78
  79 #define SIRFSOC_SPI_INT_MASK_ALL                0x1FFF
  80
  81 /* Interrupt status */
  82 #define SIRFSOC_SPI_RX_DONE             BIT(0)
  83 #define SIRFSOC_SPI_TX_DONE             BIT(1)
  84 #define SIRFSOC_SPI_RX_OFLOW            BIT(2)
  85 #define SIRFSOC_SPI_TX_UFLOW            BIT(3)
  86 #define SIRFSOC_SPI_RX_FIFO_FULL        BIT(6)
  87 #define SIRFSOC_SPI_TXFIFO_EMPTY        BIT(7)
  88 #define SIRFSOC_SPI_RXFIFO_THD_REACH    BIT(8)
  89 #define SIRFSOC_SPI_TXFIFO_THD_REACH    BIT(9)
  90 #define SIRFSOC_SPI_FRM_END             BIT(10)
  91
  92 /* TX RX enable */
  93 #define SIRFSOC_SPI_RX_EN               BIT(0)
  94 #define SIRFSOC_SPI_TX_EN               BIT(1)
  95 #define SIRFSOC_SPI_CMD_TX_EN           BIT(2)
  96
  97 #define SIRFSOC_SPI_IO_MODE_SEL         BIT(0)
  98 #define SIRFSOC_SPI_RX_DMA_FLUSH        BIT(2)
  99
 100 /* FIFO OPs */
 101 #define SIRFSOC_SPI_FIFO_RESET          BIT(0)
 102 #define SIRFSOC_SPI_FIFO_START          BIT(1)
 103
 104 /* FIFO CTRL */
 105 #define SIRFSOC_SPI_FIFO_WIDTH_BYTE     (0 << 0)
 106 #define SIRFSOC_SPI_FIFO_WIDTH_WORD     (1 << 0)
 107 #define SIRFSOC_SPI_FIFO_WIDTH_DWORD    (2 << 0)
 108
 109 /* FIFO Status */
 110 #define SIRFSOC_SPI_FIFO_LEVEL_MASK     0xFF
 111 #define SIRFSOC_SPI_FIFO_FULL           BIT(8)
 112 #define SIRFSOC_SPI_FIFO_EMPTY          BIT(9)
 113
 114 /* 256 bytes rx/tx FIFO */
 115 #define SIRFSOC_SPI_FIFO_SIZE           256
 116 #define SIRFSOC_SPI_DAT_FRM_LEN_MAX     (64 * 1024)
 117
 118 #define SIRFSOC_SPI_FIFO_SC(x)          ((x) & 0x3F)
 119 #define SIRFSOC_SPI_FIFO_LC(x)          (((x) & 0x3F) << 10)
 120 #define SIRFSOC_SPI_FIFO_HC(x)          (((x) & 0x3F) << 20)
 121 #define SIRFSOC_SPI_FIFO_THD(x)         (((x) & 0xFF) << 2)
 122
 123 struct sirfsoc_spi {
 124         struct spi_bitbang bitbang;
 125         struct completion done;
 126
 127         void __iomem *base;
 128         u32 ctrl_freq;  /* SPI controller clock speed */
 129         struct clk *clk;
 130         struct pinctrl *p;
 131
 132         /* rx & tx bufs from the spi_transfer */
 133         const void *tx;
 134         void *rx;
 135
 136         /* place received word into rx buffer */
 137         void (*rx_word) (struct sirfsoc_spi *);
 138         /* get word from tx buffer for sending */
 139         void (*tx_word) (struct sirfsoc_spi *);
 140
 141         /* number of words left to be tranmitted/received */
 142         unsigned int left_tx_cnt;
 143         unsigned int left_rx_cnt;
 144
 145         /* tasklet to push tx msg into FIFO */
 146         struct tasklet_struct tasklet_tx;
 147
 148         int chipselect[0];
 149 };
 150
 151 static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
 152 {
 153         u32 data;
 154         u8 *rx = sspi->rx;
 155
 156         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 157
 158         if (rx) {
 159                 *rx++ = (u8) data;
 160                 sspi->rx = rx;
 161         }
 162
 163         sspi->left_rx_cnt--;
 164 }
 165
 166 static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
 167 {
 168         u32 data = 0;
 169         const u8 *tx = sspi->tx;
 170
 171         if (tx) {
 172                 data = *tx++;
 173                 sspi->tx = tx;
 174         }
 175
 176         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 177         sspi->left_tx_cnt--;
 178 }
 179
 180 static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
 181 {
 182         u32 data;
 183         u16 *rx = sspi->rx;
 184
 185         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 186
 187         if (rx) {
 188                 *rx++ = (u16) data;
 189                 sspi->rx = rx;
 190         }
 191
 192         sspi->left_rx_cnt--;
 193 }
 194
 195 static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
 196 {
 197         u32 data = 0;
 198         const u16 *tx = sspi->tx;
 199
 200         if (tx) {
 201                 data = *tx++;
 202                 sspi->tx = tx;
 203         }
 204
 205         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 206         sspi->left_tx_cnt--;
 207 }
 208
 209 static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
 210 {
 211         u32 data;
 212         u32 *rx = sspi->rx;
 213
 214         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 215
 216         if (rx) {
 217                 *rx++ = (u32) data;
 218                 sspi->rx = rx;
 219         }
 220
 221         sspi->left_rx_cnt--;
 222
 223 }
 224
 225 static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
 226 {
 227         u32 data = 0;
 228         const u32 *tx = sspi->tx;
 229
 230         if (tx) {
 231                 data = *tx++;
 232                 sspi->tx = tx;
 233         }
 234
 235         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 236         sspi->left_tx_cnt--;
 237 }
 238
 239 static void spi_sirfsoc_tasklet_tx(unsigned long arg)
 240 {
 241         struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg;
 242
 243         /* Fill Tx FIFO while there are left words to be transmitted */
 244         while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) &
 245                         SIRFSOC_SPI_FIFO_FULL)) &&
 246                         sspi->left_tx_cnt)
 247                 sspi->tx_word(sspi);
 248 }
 249
 250 static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 251 {
 252         struct sirfsoc_spi *sspi = dev_id;
 253         u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
 254
 255         writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
 256
 257         /* Error Conditions */
 258         if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
 259                         spi_stat & SIRFSOC_SPI_TX_UFLOW) {
 260                 complete(&sspi->done);
 261                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 262         }
 263
 264         if (spi_stat & SIRFSOC_SPI_FRM_END) {
 265                 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
 266                                 & SIRFSOC_SPI_FIFO_EMPTY)) &&
 267                                 sspi->left_rx_cnt)
 268                         sspi->rx_word(sspi);
 269
 270                 /* Received all words */
 271                 if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
 272                         complete(&sspi->done);
 273                         writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 274                 }
 275         }
 276
 277         if (spi_stat & SIRFSOC_SPI_RXFIFO_THD_REACH ||
 278                 spi_stat & SIRFSOC_SPI_TXFIFO_THD_REACH ||
 279                 spi_stat & SIRFSOC_SPI_RX_FIFO_FULL ||
 280                 spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
 281                 tasklet_schedule(&sspi->tasklet_tx);
 282
 283         return IRQ_HANDLED;
 284 }
 285
 286 static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
 287 {
 288         struct sirfsoc_spi *sspi;
 289         int timeout = t->len * 10;
 290         sspi = spi_master_get_devdata(spi->master);
 291
 292         sspi->tx = t->tx_buf;
 293         sspi->rx = t->rx_buf;
 294         sspi->left_tx_cnt = sspi->left_rx_cnt = t->len;
 295         INIT_COMPLETION(sspi->done);
 296
 297         writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
 298
 299         if (t->len == 1) {
 300                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 301                         SIRFSOC_SPI_ENA_AUTO_CLR,
 302                         sspi->base + SIRFSOC_SPI_CTRL);
 303                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 304                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 305         } else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
 306                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 307                                 SIRFSOC_SPI_MUL_DAT_MODE |
 308                                 SIRFSOC_SPI_ENA_AUTO_CLR,
 309                         sspi->base + SIRFSOC_SPI_CTRL);
 310                 writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 311                 writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 312         } else {
 313                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
 314                         sspi->base + SIRFSOC_SPI_CTRL);
 315                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 316                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 317         }
 318
 319         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 320         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 321         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 322         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 323
 324         /* Send the first word to trigger the whole tx/rx process */
 325         sspi->tx_word(sspi);
 326
 327         writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
 328                 SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
 329                 SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
 330                 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
 331         writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 332
 333         if (wait_for_completion_timeout(&sspi->done, timeout) == 0)
 334                 dev_err(&spi->dev, "transfer timeout\n");
 335
 336         /* TX, RX FIFO stop */
 337         writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 338         writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 339         writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 340         writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
 341
 342         return t->len - sspi->left_rx_cnt;
 343 }
 344
 345 static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
 346 {
 347         struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
 348
 349         if (sspi->chipselect[spi->chip_select] == 0) {
 350                 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
 351                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 352                 switch (value) {
 353                 case BITBANG_CS_ACTIVE:
 354                         if (spi->mode & SPI_CS_HIGH)
 355                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 356                         else
 357                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 358                         break;
 359                 case BITBANG_CS_INACTIVE:
 360                         if (spi->mode & SPI_CS_HIGH)
 361                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 362                         else
 363                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 364                         break;
 365                 }
 366                 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 367         } else {
 368                 int gpio = sspi->chipselect[spi->chip_select];
 369                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 370         }
 371 }
 372
 373 static int
 374 spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 375 {
 376         struct sirfsoc_spi *sspi;
 377         u8 bits_per_word = 0;
 378         int hz = 0;
 379         u32 regval;
 380         u32 txfifo_ctrl, rxfifo_ctrl;
 381         u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
 382
 383         sspi = spi_master_get_devdata(spi->master);
 384
 385         bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
 386         hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
 387
 388         /* Enable IO mode for RX, TX */
 389         writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 390         writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 391         regval = (sspi->ctrl_freq / (2 * hz)) - 1;
 392
 393         if (regval > 0xFFFF || regval < 0) {
 394                 dev_err(&spi->dev, "Speed %d not supported\n", hz);
 395                 return -EINVAL;
 396         }
 397
 398         switch (bits_per_word) {
 399         case 8:
 400                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
 401                 sspi->rx_word = spi_sirfsoc_rx_word_u8;
 402                 sspi->tx_word = spi_sirfsoc_tx_word_u8;
 403                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 404                                         SIRFSOC_SPI_FIFO_WIDTH_BYTE;
 405                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 406                                         SIRFSOC_SPI_FIFO_WIDTH_BYTE;
 407                 break;
 408         case 12:
 409         case 16:
 410                 regval |= (bits_per_word ==  12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
 411                         SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
 412                 sspi->rx_word = spi_sirfsoc_rx_word_u16;
 413                 sspi->tx_word = spi_sirfsoc_tx_word_u16;
 414                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 415                                         SIRFSOC_SPI_FIFO_WIDTH_WORD;
 416                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 417                                         SIRFSOC_SPI_FIFO_WIDTH_WORD;
 418                 break;
 419         case 32:
 420                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
 421                 sspi->rx_word = spi_sirfsoc_rx_word_u32;
 422                 sspi->tx_word = spi_sirfsoc_tx_word_u32;
 423                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 424                                         SIRFSOC_SPI_FIFO_WIDTH_DWORD;
 425                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 426                                         SIRFSOC_SPI_FIFO_WIDTH_DWORD;
 427                 break;
 428         default:
 429                 dev_err(&spi->dev, "Bits per word %d not supported\n",
 430                        bits_per_word);
 431                 return -EINVAL;
 432         }
 433
 434         if (!(spi->mode & SPI_CS_HIGH))
 435                 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
 436         if (!(spi->mode & SPI_LSB_FIRST))
 437                 regval |= SIRFSOC_SPI_TRAN_MSB;
 438         if (spi->mode & SPI_CPOL)
 439                 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
 440
 441         /*
 442          * Data should be driven at least 1/2 cycle before the fetch edge to make
 443          * sure that data gets stable at the fetch edge.
 444          */
 445         if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
 446             (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
 447                 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
 448         else
 449                 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
 450
 451         writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
 452                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 453                         SIRFSOC_SPI_FIFO_HC(2),
 454                 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
 455         writel(SIRFSOC_SPI_FIFO_SC(2) |
 456                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 457                         SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
 458                 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
 459         writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
 460         writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
 461
 462         writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 463         return 0;
 464 }
 465
 466 static int spi_sirfsoc_setup(struct spi_device *spi)
 467 {
 468         struct sirfsoc_spi *sspi;
 469
 470         if (!spi->max_speed_hz)
 471                 return -EINVAL;
 472
 473         sspi = spi_master_get_devdata(spi->master);
 474
 475         if (!spi->bits_per_word)
 476                 spi->bits_per_word = 8;
 477
 478         return spi_sirfsoc_setup_transfer(spi, NULL);
 479 }
 480
 481 static int spi_sirfsoc_probe(struct platform_device *pdev)
 482 {
 483         struct sirfsoc_spi *sspi;
 484         struct spi_master *master;
 485         struct resource *mem_res;
 486         int num_cs, cs_gpio, irq;
 487         int i;
 488         int ret;
 489
 490         ret = of_property_read_u32(pdev->dev.of_node,
 491                         "sirf,spi-num-chipselects", &num_cs);
 492         if (ret < 0) {
 493                 dev_err(&pdev->dev, "Unable to get chip select number\n");
 494                 goto err_cs;
 495         }
 496
 497         master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
 498         if (!master) {
 499                 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
 500                 return -ENOMEM;
 501         }
 502         platform_set_drvdata(pdev, master);
 503         sspi = spi_master_get_devdata(master);
 504
 505         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 506         if (!mem_res) {
 507                 dev_err(&pdev->dev, "Unable to get IO resource\n");
 508                 ret = -ENODEV;
 509                 goto free_master;
 510         }
 511         master->num_chipselect = num_cs;
 512
 513         for (i = 0; i < master->num_chipselect; i++) {
 514                 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
 515                 if (cs_gpio < 0) {
 516                         dev_err(&pdev->dev, "can't get cs gpio from DT\n");
 517                         ret = -ENODEV;
 518                         goto free_master;
 519                 }
 520
 521                 sspi->chipselect[i] = cs_gpio;
 522                 if (cs_gpio == 0)
 523                         continue; /* use cs from spi controller */
 524
 525                 ret = gpio_request(cs_gpio, DRIVER_NAME);
 526                 if (ret) {
 527                         while (i > 0) {
 528                                 i--;
 529                                 if (sspi->chipselect[i] > 0)
 530                                         gpio_free(sspi->chipselect[i]);
 531                         }
 532                         dev_err(&pdev->dev, "fail to request cs gpios\n");
 533                         goto free_master;
 534                 }
 535         }
 536
 537         sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
 538         if (IS_ERR(sspi->base)) {
 539                 ret = PTR_ERR(sspi->base);
 540                 goto free_master;
 541         }
 542
 543         irq = platform_get_irq(pdev, 0);
 544         if (irq < 0) {
 545                 ret = -ENXIO;
 546                 goto free_master;
 547         }
 548         ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
 549                                 DRIVER_NAME, sspi);
 550         if (ret)
 551                 goto free_master;
 552
 553         sspi->bitbang.master = spi_master_get(master);
 554         sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
 555         sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
 556         sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
 557         sspi->bitbang.master->setup = spi_sirfsoc_setup;
 558         master->bus_num = pdev->id;
 559         sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
 560
 561         sspi->p = pinctrl_get_select_default(&pdev->dev);
 562         ret = IS_ERR(sspi->p);
 563         if (ret)
 564                 goto free_master;
 565
 566         sspi->clk = clk_get(&pdev->dev, NULL);
 567         if (IS_ERR(sspi->clk)) {
 568                 ret = -EINVAL;
 569                 goto free_pin;
 570         }
 571         clk_prepare_enable(sspi->clk);
 572         sspi->ctrl_freq = clk_get_rate(sspi->clk);
 573
 574         init_completion(&sspi->done);
 575
 576         tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx,
 577                      (unsigned long)sspi);
 578
 579         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 580         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 581         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 582         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 583         /* We are not using dummy delay between command and data */
 584         writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
 585
 586         ret = spi_bitbang_start(&sspi->bitbang);
 587         if (ret)
 588                 goto free_clk;
 589
 590         dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
 591
 592         return 0;
 593
 594 free_clk:
 595         clk_disable_unprepare(sspi->clk);
 596         clk_put(sspi->clk);
 597 free_pin:
 598         pinctrl_put(sspi->p);
 599 free_master:
 600         spi_master_put(master);
 601 err_cs:
 602         return ret;
 603 }
 604
 605 static int  spi_sirfsoc_remove(struct platform_device *pdev)
 606 {
 607         struct spi_master *master;
 608         struct sirfsoc_spi *sspi;
 609         int i;
 610
 611         master = platform_get_drvdata(pdev);
 612         sspi = spi_master_get_devdata(master);
 613
 614         spi_bitbang_stop(&sspi->bitbang);
 615         for (i = 0; i < master->num_chipselect; i++) {
 616                 if (sspi->chipselect[i] > 0)
 617                         gpio_free(sspi->chipselect[i]);
 618         }
 619         clk_disable_unprepare(sspi->clk);
 620         clk_put(sspi->clk);
 621         pinctrl_put(sspi->p);
 622         spi_master_put(master);
 623         return 0;
 624 }
 625
 626 #ifdef CONFIG_PM
 627 static int spi_sirfsoc_suspend(struct device *dev)
 628 {
 629         struct platform_device *pdev = to_platform_device(dev);
 630         struct spi_master *master = platform_get_drvdata(pdev);
 631         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 632
 633         clk_disable(sspi->clk);
 634         return 0;
 635 }
 636
 637 static int spi_sirfsoc_resume(struct device *dev)
 638 {
 639         struct platform_device *pdev = to_platform_device(dev);
 640         struct spi_master *master = platform_get_drvdata(pdev);
 641         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 642
 643         clk_enable(sspi->clk);
 644         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 645         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 646         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 647         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 648
 649         return 0;
 650 }
 651
 652 static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
 653         .suspend = spi_sirfsoc_suspend,
 654         .resume = spi_sirfsoc_resume,
 655 };
 656 #endif
 657
 658 static const struct of_device_id spi_sirfsoc_of_match[] = {
 659         { .compatible = "sirf,prima2-spi", },
 660         { .compatible = "sirf,marco-spi", },
 661         {}
 662 };
 663 MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
 664
 665 static struct platform_driver spi_sirfsoc_driver = {
 666         .driver = {
 667                 .name = DRIVER_NAME,
 668                 .owner = THIS_MODULE,
 669 #ifdef CONFIG_PM
 670                 .pm     = &spi_sirfsoc_pm_ops,
 671 #endif
 672                 .of_match_table = spi_sirfsoc_of_match,
 673         },
 674         .probe = spi_sirfsoc_probe,
 675         .remove = spi_sirfsoc_remove,
 676 };
 677 module_platform_driver(spi_sirfsoc_driver);
 678
 679 MODULE_DESCRIPTION("SiRF SoC SPI master driver");
 680 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
 681                 "Barry Song <Baohua.Song@csr.com>");
 682 MODULE_LICENSE("GPL v2");