2 * OMAP2 McSPI controller driver
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
40 #include <linux/of_device.h>
42 #include <linux/spi/spi.h>
44 #include <linux/platform_data/spi-omap2-mcspi.h>
46 #define OMAP2_MCSPI_MAX_FREQ 48000000
47 #define SPI_AUTOSUSPEND_TIMEOUT 2000
49 #define OMAP2_MCSPI_REVISION 0x00
50 #define OMAP2_MCSPI_SYSSTATUS 0x14
51 #define OMAP2_MCSPI_IRQSTATUS 0x18
52 #define OMAP2_MCSPI_IRQENABLE 0x1c
53 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
54 #define OMAP2_MCSPI_SYST 0x24
55 #define OMAP2_MCSPI_MODULCTRL 0x28
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
64 /* per-register bitmasks: */
66 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
67 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
68 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
70 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
71 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
72 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
73 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
74 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
75 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
76 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
77 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
78 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
79 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
80 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
81 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
82 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
83 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
84 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
87 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
88 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
90 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
92 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
94 /* We have 2 DMA channels per CS, one for RX and one for TX */
95 struct omap2_mcspi_dma
{
96 struct dma_chan
*dma_tx
;
97 struct dma_chan
*dma_rx
;
102 struct completion dma_tx_completion
;
103 struct completion dma_rx_completion
;
106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
107 * cache operations; better heuristics consider wordsize and bitrate.
109 #define DMA_MIN_BYTES 160
113 * Used for context save and restore, structure members to be updated whenever
114 * corresponding registers are modified.
116 struct omap2_mcspi_regs
{
123 struct spi_master
*master
;
124 /* Virtual base address of the controller */
127 /* SPI1 has 4 channels, while SPI2 has 2 */
128 struct omap2_mcspi_dma
*dma_channels
;
130 struct omap2_mcspi_regs ctx
;
133 struct omap2_mcspi_cs
{
137 struct list_head node
;
138 /* Context save and restore shadow register */
142 #define MOD_REG_BIT(val, mask, set) do { \
149 static inline void mcspi_write_reg(struct spi_master
*master
,
152 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
154 __raw_writel(val
, mcspi
->base
+ idx
);
157 static inline u32
mcspi_read_reg(struct spi_master
*master
, int idx
)
159 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
161 return __raw_readl(mcspi
->base
+ idx
);
164 static inline void mcspi_write_cs_reg(const struct spi_device
*spi
,
167 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
169 __raw_writel(val
, cs
->base
+ idx
);
172 static inline u32
mcspi_read_cs_reg(const struct spi_device
*spi
, int idx
)
174 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
176 return __raw_readl(cs
->base
+ idx
);
179 static inline u32
mcspi_cached_chconf0(const struct spi_device
*spi
)
181 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
186 static inline void mcspi_write_chconf0(const struct spi_device
*spi
, u32 val
)
188 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
191 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
, val
);
192 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCONF0
);
195 static void omap2_mcspi_set_dma_req(const struct spi_device
*spi
,
196 int is_read
, int enable
)
200 l
= mcspi_cached_chconf0(spi
);
202 if (is_read
) /* 1 is read, 0 write */
203 rw
= OMAP2_MCSPI_CHCONF_DMAR
;
205 rw
= OMAP2_MCSPI_CHCONF_DMAW
;
207 MOD_REG_BIT(l
, rw
, enable
);
208 mcspi_write_chconf0(spi
, l
);
211 static void omap2_mcspi_set_enable(const struct spi_device
*spi
, int enable
)
215 l
= enable
? OMAP2_MCSPI_CHCTRL_EN
: 0;
216 mcspi_write_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
, l
);
217 /* Flash post-writes */
218 mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHCTRL0
);
221 static void omap2_mcspi_force_cs(struct spi_device
*spi
, int cs_active
)
225 l
= mcspi_cached_chconf0(spi
);
226 MOD_REG_BIT(l
, OMAP2_MCSPI_CHCONF_FORCE
, cs_active
);
227 mcspi_write_chconf0(spi
, l
);
230 static void omap2_mcspi_set_master_mode(struct spi_master
*master
)
232 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
233 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
237 * Setup when switching from (reset default) slave mode
238 * to single-channel master mode
240 l
= mcspi_read_reg(master
, OMAP2_MCSPI_MODULCTRL
);
241 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_STEST
, 0);
242 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_MS
, 0);
243 MOD_REG_BIT(l
, OMAP2_MCSPI_MODULCTRL_SINGLE
, 1);
244 mcspi_write_reg(master
, OMAP2_MCSPI_MODULCTRL
, l
);
249 static void omap2_mcspi_restore_ctx(struct omap2_mcspi
*mcspi
)
251 struct spi_master
*spi_cntrl
= mcspi
->master
;
252 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
253 struct omap2_mcspi_cs
*cs
;
255 /* McSPI: context restore */
256 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_MODULCTRL
, ctx
->modulctrl
);
257 mcspi_write_reg(spi_cntrl
, OMAP2_MCSPI_WAKEUPENABLE
, ctx
->wakeupenable
);
259 list_for_each_entry(cs
, &ctx
->cs
, node
)
260 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
262 static void omap2_mcspi_disable_clocks(struct omap2_mcspi
*mcspi
)
264 pm_runtime_mark_last_busy(mcspi
->dev
);
265 pm_runtime_put_autosuspend(mcspi
->dev
);
268 static int omap2_mcspi_enable_clocks(struct omap2_mcspi
*mcspi
)
270 return pm_runtime_get_sync(mcspi
->dev
);
273 static int omap2_prepare_transfer(struct spi_master
*master
)
275 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
277 pm_runtime_get_sync(mcspi
->dev
);
281 static int omap2_unprepare_transfer(struct spi_master
*master
)
283 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
285 pm_runtime_mark_last_busy(mcspi
->dev
);
286 pm_runtime_put_autosuspend(mcspi
->dev
);
290 static int mcspi_wait_for_reg_bit(void __iomem
*reg
, unsigned long bit
)
292 unsigned long timeout
;
294 timeout
= jiffies
+ msecs_to_jiffies(1000);
295 while (!(__raw_readl(reg
) & bit
)) {
296 if (time_after(jiffies
, timeout
))
303 static void omap2_mcspi_rx_callback(void *data
)
305 struct spi_device
*spi
= data
;
306 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
307 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
309 complete(&mcspi_dma
->dma_rx_completion
);
311 /* We must disable the DMA RX request */
312 omap2_mcspi_set_dma_req(spi
, 1, 0);
315 static void omap2_mcspi_tx_callback(void *data
)
317 struct spi_device
*spi
= data
;
318 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
319 struct omap2_mcspi_dma
*mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
321 complete(&mcspi_dma
->dma_tx_completion
);
323 /* We must disable the DMA TX request */
324 omap2_mcspi_set_dma_req(spi
, 0, 0);
328 omap2_mcspi_txrx_dma(struct spi_device
*spi
, struct spi_transfer
*xfer
)
330 struct omap2_mcspi
*mcspi
;
331 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
332 struct omap2_mcspi_dma
*mcspi_dma
;
334 int word_len
, element_count
;
339 void __iomem
*chstat_reg
;
340 struct dma_slave_config cfg
;
341 enum dma_slave_buswidth width
;
344 mcspi
= spi_master_get_devdata(spi
->master
);
345 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
346 l
= mcspi_cached_chconf0(spi
);
348 chstat_reg
= cs
->base
+ OMAP2_MCSPI_CHSTAT0
;
350 if (cs
->word_len
<= 8) {
351 width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
353 } else if (cs
->word_len
<= 16) {
354 width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
357 width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
361 memset(&cfg
, 0, sizeof(cfg
));
362 cfg
.src_addr
= cs
->phys
+ OMAP2_MCSPI_RX0
;
363 cfg
.dst_addr
= cs
->phys
+ OMAP2_MCSPI_TX0
;
364 cfg
.src_addr_width
= width
;
365 cfg
.dst_addr_width
= width
;
366 cfg
.src_maxburst
= 1;
367 cfg
.dst_maxburst
= 1;
369 if (xfer
->tx_buf
&& mcspi_dma
->dma_tx
) {
370 struct dma_async_tx_descriptor
*tx
;
371 struct scatterlist sg
;
373 dmaengine_slave_config(mcspi_dma
->dma_tx
, &cfg
);
375 sg_init_table(&sg
, 1);
376 sg_dma_address(&sg
) = xfer
->tx_dma
;
377 sg_dma_len(&sg
) = xfer
->len
;
379 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_tx
, &sg
, 1,
380 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
382 tx
->callback
= omap2_mcspi_tx_callback
;
383 tx
->callback_param
= spi
;
384 dmaengine_submit(tx
);
386 /* FIXME: fall back to PIO? */
390 if (xfer
->rx_buf
&& mcspi_dma
->dma_rx
) {
391 struct dma_async_tx_descriptor
*tx
;
392 struct scatterlist sg
;
393 size_t len
= xfer
->len
- es
;
395 dmaengine_slave_config(mcspi_dma
->dma_rx
, &cfg
);
397 if (l
& OMAP2_MCSPI_CHCONF_TURBO
)
400 sg_init_table(&sg
, 1);
401 sg_dma_address(&sg
) = xfer
->rx_dma
;
402 sg_dma_len(&sg
) = len
;
404 tx
= dmaengine_prep_slave_sg(mcspi_dma
->dma_rx
, &sg
, 1,
405 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
407 tx
->callback
= omap2_mcspi_rx_callback
;
408 tx
->callback_param
= spi
;
409 dmaengine_submit(tx
);
411 /* FIXME: fall back to PIO? */
416 word_len
= cs
->word_len
;
422 element_count
= count
;
423 } else if (word_len
<= 16) {
424 element_count
= count
>> 1;
425 } else /* word_len <= 32 */ {
426 element_count
= count
>> 2;
430 dma_async_issue_pending(mcspi_dma
->dma_tx
);
431 omap2_mcspi_set_dma_req(spi
, 0, 1);
435 dma_async_issue_pending(mcspi_dma
->dma_rx
);
436 omap2_mcspi_set_dma_req(spi
, 1, 1);
440 wait_for_completion(&mcspi_dma
->dma_tx_completion
);
441 dma_unmap_single(mcspi
->dev
, xfer
->tx_dma
, count
,
444 /* for TX_ONLY mode, be sure all words have shifted out */
446 if (mcspi_wait_for_reg_bit(chstat_reg
,
447 OMAP2_MCSPI_CHSTAT_TXS
) < 0)
448 dev_err(&spi
->dev
, "TXS timed out\n");
449 else if (mcspi_wait_for_reg_bit(chstat_reg
,
450 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
451 dev_err(&spi
->dev
, "EOT timed out\n");
456 wait_for_completion(&mcspi_dma
->dma_rx_completion
);
457 dma_unmap_single(mcspi
->dev
, xfer
->rx_dma
, count
,
459 omap2_mcspi_set_enable(spi
, 0);
461 elements
= element_count
- 1;
463 if (l
& OMAP2_MCSPI_CHCONF_TURBO
) {
466 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
467 & OMAP2_MCSPI_CHSTAT_RXS
)) {
470 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
472 ((u8
*)xfer
->rx_buf
)[elements
++] = w
;
473 else if (word_len
<= 16)
474 ((u16
*)xfer
->rx_buf
)[elements
++] = w
;
475 else /* word_len <= 32 */
476 ((u32
*)xfer
->rx_buf
)[elements
++] = w
;
479 "DMA RX penultimate word empty");
480 count
-= (word_len
<= 8) ? 2 :
481 (word_len
<= 16) ? 4 :
482 /* word_len <= 32 */ 8;
483 omap2_mcspi_set_enable(spi
, 1);
488 if (likely(mcspi_read_cs_reg(spi
, OMAP2_MCSPI_CHSTAT0
)
489 & OMAP2_MCSPI_CHSTAT_RXS
)) {
492 w
= mcspi_read_cs_reg(spi
, OMAP2_MCSPI_RX0
);
494 ((u8
*)xfer
->rx_buf
)[elements
] = w
;
495 else if (word_len
<= 16)
496 ((u16
*)xfer
->rx_buf
)[elements
] = w
;
497 else /* word_len <= 32 */
498 ((u32
*)xfer
->rx_buf
)[elements
] = w
;
500 dev_err(&spi
->dev
, "DMA RX last word empty");
501 count
-= (word_len
<= 8) ? 1 :
502 (word_len
<= 16) ? 2 :
503 /* word_len <= 32 */ 4;
505 omap2_mcspi_set_enable(spi
, 1);
511 omap2_mcspi_txrx_pio(struct spi_device
*spi
, struct spi_transfer
*xfer
)
513 struct omap2_mcspi
*mcspi
;
514 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
515 unsigned int count
, c
;
517 void __iomem
*base
= cs
->base
;
518 void __iomem
*tx_reg
;
519 void __iomem
*rx_reg
;
520 void __iomem
*chstat_reg
;
523 mcspi
= spi_master_get_devdata(spi
->master
);
526 word_len
= cs
->word_len
;
528 l
= mcspi_cached_chconf0(spi
);
530 /* We store the pre-calculated register addresses on stack to speed
531 * up the transfer loop. */
532 tx_reg
= base
+ OMAP2_MCSPI_TX0
;
533 rx_reg
= base
+ OMAP2_MCSPI_RX0
;
534 chstat_reg
= base
+ OMAP2_MCSPI_CHSTAT0
;
536 if (c
< (word_len
>>3))
549 if (mcspi_wait_for_reg_bit(chstat_reg
,
550 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
551 dev_err(&spi
->dev
, "TXS timed out\n");
554 dev_vdbg(&spi
->dev
, "write-%d %02x\n",
556 __raw_writel(*tx
++, tx_reg
);
559 if (mcspi_wait_for_reg_bit(chstat_reg
,
560 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
561 dev_err(&spi
->dev
, "RXS timed out\n");
565 if (c
== 1 && tx
== NULL
&&
566 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
567 omap2_mcspi_set_enable(spi
, 0);
568 *rx
++ = __raw_readl(rx_reg
);
569 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
570 word_len
, *(rx
- 1));
571 if (mcspi_wait_for_reg_bit(chstat_reg
,
572 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
578 } else if (c
== 0 && tx
== NULL
) {
579 omap2_mcspi_set_enable(spi
, 0);
582 *rx
++ = __raw_readl(rx_reg
);
583 dev_vdbg(&spi
->dev
, "read-%d %02x\n",
584 word_len
, *(rx
- 1));
587 } else if (word_len
<= 16) {
596 if (mcspi_wait_for_reg_bit(chstat_reg
,
597 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
598 dev_err(&spi
->dev
, "TXS timed out\n");
601 dev_vdbg(&spi
->dev
, "write-%d %04x\n",
603 __raw_writel(*tx
++, tx_reg
);
606 if (mcspi_wait_for_reg_bit(chstat_reg
,
607 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
608 dev_err(&spi
->dev
, "RXS timed out\n");
612 if (c
== 2 && tx
== NULL
&&
613 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
614 omap2_mcspi_set_enable(spi
, 0);
615 *rx
++ = __raw_readl(rx_reg
);
616 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
617 word_len
, *(rx
- 1));
618 if (mcspi_wait_for_reg_bit(chstat_reg
,
619 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
625 } else if (c
== 0 && tx
== NULL
) {
626 omap2_mcspi_set_enable(spi
, 0);
629 *rx
++ = __raw_readl(rx_reg
);
630 dev_vdbg(&spi
->dev
, "read-%d %04x\n",
631 word_len
, *(rx
- 1));
634 } else if (word_len
<= 32) {
643 if (mcspi_wait_for_reg_bit(chstat_reg
,
644 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
645 dev_err(&spi
->dev
, "TXS timed out\n");
648 dev_vdbg(&spi
->dev
, "write-%d %08x\n",
650 __raw_writel(*tx
++, tx_reg
);
653 if (mcspi_wait_for_reg_bit(chstat_reg
,
654 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
655 dev_err(&spi
->dev
, "RXS timed out\n");
659 if (c
== 4 && tx
== NULL
&&
660 (l
& OMAP2_MCSPI_CHCONF_TURBO
)) {
661 omap2_mcspi_set_enable(spi
, 0);
662 *rx
++ = __raw_readl(rx_reg
);
663 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
664 word_len
, *(rx
- 1));
665 if (mcspi_wait_for_reg_bit(chstat_reg
,
666 OMAP2_MCSPI_CHSTAT_RXS
) < 0) {
672 } else if (c
== 0 && tx
== NULL
) {
673 omap2_mcspi_set_enable(spi
, 0);
676 *rx
++ = __raw_readl(rx_reg
);
677 dev_vdbg(&spi
->dev
, "read-%d %08x\n",
678 word_len
, *(rx
- 1));
683 /* for TX_ONLY mode, be sure all words have shifted out */
684 if (xfer
->rx_buf
== NULL
) {
685 if (mcspi_wait_for_reg_bit(chstat_reg
,
686 OMAP2_MCSPI_CHSTAT_TXS
) < 0) {
687 dev_err(&spi
->dev
, "TXS timed out\n");
688 } else if (mcspi_wait_for_reg_bit(chstat_reg
,
689 OMAP2_MCSPI_CHSTAT_EOT
) < 0)
690 dev_err(&spi
->dev
, "EOT timed out\n");
692 /* disable chan to purge rx datas received in TX_ONLY transfer,
693 * otherwise these rx datas will affect the direct following
696 omap2_mcspi_set_enable(spi
, 0);
699 omap2_mcspi_set_enable(spi
, 1);
703 static u32
omap2_mcspi_calc_divisor(u32 speed_hz
)
707 for (div
= 0; div
< 15; div
++)
708 if (speed_hz
>= (OMAP2_MCSPI_MAX_FREQ
>> div
))
714 /* called only when no transfer is active to this device */
715 static int omap2_mcspi_setup_transfer(struct spi_device
*spi
,
716 struct spi_transfer
*t
)
718 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
719 struct omap2_mcspi
*mcspi
;
720 struct spi_master
*spi_cntrl
;
722 u8 word_len
= spi
->bits_per_word
;
723 u32 speed_hz
= spi
->max_speed_hz
;
725 mcspi
= spi_master_get_devdata(spi
->master
);
726 spi_cntrl
= mcspi
->master
;
728 if (t
!= NULL
&& t
->bits_per_word
)
729 word_len
= t
->bits_per_word
;
731 cs
->word_len
= word_len
;
733 if (t
&& t
->speed_hz
)
734 speed_hz
= t
->speed_hz
;
736 speed_hz
= min_t(u32
, speed_hz
, OMAP2_MCSPI_MAX_FREQ
);
737 div
= omap2_mcspi_calc_divisor(speed_hz
);
739 l
= mcspi_cached_chconf0(spi
);
741 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
742 * REVISIT: this controller could support SPI_3WIRE mode.
744 l
&= ~(OMAP2_MCSPI_CHCONF_IS
|OMAP2_MCSPI_CHCONF_DPE1
);
745 l
|= OMAP2_MCSPI_CHCONF_DPE0
;
748 l
&= ~OMAP2_MCSPI_CHCONF_WL_MASK
;
749 l
|= (word_len
- 1) << 7;
751 /* set chipselect polarity; manage with FORCE */
752 if (!(spi
->mode
& SPI_CS_HIGH
))
753 l
|= OMAP2_MCSPI_CHCONF_EPOL
; /* active-low; normal */
755 l
&= ~OMAP2_MCSPI_CHCONF_EPOL
;
757 /* set clock divisor */
758 l
&= ~OMAP2_MCSPI_CHCONF_CLKD_MASK
;
761 /* set SPI mode 0..3 */
762 if (spi
->mode
& SPI_CPOL
)
763 l
|= OMAP2_MCSPI_CHCONF_POL
;
765 l
&= ~OMAP2_MCSPI_CHCONF_POL
;
766 if (spi
->mode
& SPI_CPHA
)
767 l
|= OMAP2_MCSPI_CHCONF_PHA
;
769 l
&= ~OMAP2_MCSPI_CHCONF_PHA
;
771 mcspi_write_chconf0(spi
, l
);
773 dev_dbg(&spi
->dev
, "setup: speed %d, sample %s edge, clk %s\n",
774 OMAP2_MCSPI_MAX_FREQ
>> div
,
775 (spi
->mode
& SPI_CPHA
) ? "trailing" : "leading",
776 (spi
->mode
& SPI_CPOL
) ? "inverted" : "normal");
781 static int omap2_mcspi_request_dma(struct spi_device
*spi
)
783 struct spi_master
*master
= spi
->master
;
784 struct omap2_mcspi
*mcspi
;
785 struct omap2_mcspi_dma
*mcspi_dma
;
789 mcspi
= spi_master_get_devdata(master
);
790 mcspi_dma
= mcspi
->dma_channels
+ spi
->chip_select
;
792 init_completion(&mcspi_dma
->dma_rx_completion
);
793 init_completion(&mcspi_dma
->dma_tx_completion
);
796 dma_cap_set(DMA_SLAVE
, mask
);
797 sig
= mcspi_dma
->dma_rx_sync_dev
;
798 mcspi_dma
->dma_rx
= dma_request_channel(mask
, omap_dma_filter_fn
, &sig
);
799 if (!mcspi_dma
->dma_rx
) {
800 dev_err(&spi
->dev
, "no RX DMA engine channel for McSPI\n");
804 sig
= mcspi_dma
->dma_tx_sync_dev
;
805 mcspi_dma
->dma_tx
= dma_request_channel(mask
, omap_dma_filter_fn
, &sig
);
806 if (!mcspi_dma
->dma_tx
) {
807 dev_err(&spi
->dev
, "no TX DMA engine channel for McSPI\n");
808 dma_release_channel(mcspi_dma
->dma_rx
);
809 mcspi_dma
->dma_rx
= NULL
;
816 static int omap2_mcspi_setup(struct spi_device
*spi
)
819 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(spi
->master
);
820 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
821 struct omap2_mcspi_dma
*mcspi_dma
;
822 struct omap2_mcspi_cs
*cs
= spi
->controller_state
;
824 if (spi
->bits_per_word
< 4 || spi
->bits_per_word
> 32) {
825 dev_dbg(&spi
->dev
, "setup: unsupported %d bit words\n",
830 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
833 cs
= kzalloc(sizeof *cs
, GFP_KERNEL
);
836 cs
->base
= mcspi
->base
+ spi
->chip_select
* 0x14;
837 cs
->phys
= mcspi
->phys
+ spi
->chip_select
* 0x14;
839 spi
->controller_state
= cs
;
840 /* Link this to context save list */
841 list_add_tail(&cs
->node
, &ctx
->cs
);
844 if (!mcspi_dma
->dma_rx
|| !mcspi_dma
->dma_tx
) {
845 ret
= omap2_mcspi_request_dma(spi
);
850 ret
= omap2_mcspi_enable_clocks(mcspi
);
854 ret
= omap2_mcspi_setup_transfer(spi
, NULL
);
855 omap2_mcspi_disable_clocks(mcspi
);
860 static void omap2_mcspi_cleanup(struct spi_device
*spi
)
862 struct omap2_mcspi
*mcspi
;
863 struct omap2_mcspi_dma
*mcspi_dma
;
864 struct omap2_mcspi_cs
*cs
;
866 mcspi
= spi_master_get_devdata(spi
->master
);
868 if (spi
->controller_state
) {
869 /* Unlink controller state from context save list */
870 cs
= spi
->controller_state
;
876 if (spi
->chip_select
< spi
->master
->num_chipselect
) {
877 mcspi_dma
= &mcspi
->dma_channels
[spi
->chip_select
];
879 if (mcspi_dma
->dma_rx
) {
880 dma_release_channel(mcspi_dma
->dma_rx
);
881 mcspi_dma
->dma_rx
= NULL
;
883 if (mcspi_dma
->dma_tx
) {
884 dma_release_channel(mcspi_dma
->dma_tx
);
885 mcspi_dma
->dma_tx
= NULL
;
890 static void omap2_mcspi_work(struct omap2_mcspi
*mcspi
, struct spi_message
*m
)
893 /* We only enable one channel at a time -- the one whose message is
894 * -- although this controller would gladly
895 * arbitrate among multiple channels. This corresponds to "single
896 * channel" master mode. As a side effect, we need to manage the
897 * chipselect with the FORCE bit ... CS != channel enable.
900 struct spi_device
*spi
;
901 struct spi_transfer
*t
= NULL
;
903 struct omap2_mcspi_cs
*cs
;
904 struct omap2_mcspi_device_config
*cd
;
905 int par_override
= 0;
910 cs
= spi
->controller_state
;
911 cd
= spi
->controller_data
;
913 omap2_mcspi_set_enable(spi
, 1);
914 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
915 if (t
->tx_buf
== NULL
&& t
->rx_buf
== NULL
&& t
->len
) {
919 if (par_override
|| t
->speed_hz
|| t
->bits_per_word
) {
921 status
= omap2_mcspi_setup_transfer(spi
, t
);
924 if (!t
->speed_hz
&& !t
->bits_per_word
)
929 omap2_mcspi_force_cs(spi
, 1);
933 chconf
= mcspi_cached_chconf0(spi
);
934 chconf
&= ~OMAP2_MCSPI_CHCONF_TRM_MASK
;
935 chconf
&= ~OMAP2_MCSPI_CHCONF_TURBO
;
937 if (t
->tx_buf
== NULL
)
938 chconf
|= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY
;
939 else if (t
->rx_buf
== NULL
)
940 chconf
|= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY
;
942 if (cd
&& cd
->turbo_mode
&& t
->tx_buf
== NULL
) {
943 /* Turbo mode is for more than one word */
944 if (t
->len
> ((cs
->word_len
+ 7) >> 3))
945 chconf
|= OMAP2_MCSPI_CHCONF_TURBO
;
948 mcspi_write_chconf0(spi
, chconf
);
953 /* RX_ONLY mode needs dummy data in TX reg */
954 if (t
->tx_buf
== NULL
)
955 __raw_writel(0, cs
->base
958 if (m
->is_dma_mapped
|| t
->len
>= DMA_MIN_BYTES
)
959 count
= omap2_mcspi_txrx_dma(spi
, t
);
961 count
= omap2_mcspi_txrx_pio(spi
, t
);
962 m
->actual_length
+= count
;
964 if (count
!= t
->len
) {
971 udelay(t
->delay_usecs
);
973 /* ignore the "leave it on after last xfer" hint */
975 omap2_mcspi_force_cs(spi
, 0);
979 /* Restore defaults if they were overriden */
982 status
= omap2_mcspi_setup_transfer(spi
, NULL
);
986 omap2_mcspi_force_cs(spi
, 0);
988 omap2_mcspi_set_enable(spi
, 0);
994 static int omap2_mcspi_transfer_one_message(struct spi_master
*master
,
995 struct spi_message
*m
)
997 struct omap2_mcspi
*mcspi
;
998 struct spi_transfer
*t
;
1000 mcspi
= spi_master_get_devdata(master
);
1001 m
->actual_length
= 0;
1004 /* reject invalid messages and transfers */
1005 if (list_empty(&m
->transfers
))
1007 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
1008 const void *tx_buf
= t
->tx_buf
;
1009 void *rx_buf
= t
->rx_buf
;
1010 unsigned len
= t
->len
;
1012 if (t
->speed_hz
> OMAP2_MCSPI_MAX_FREQ
1013 || (len
&& !(rx_buf
|| tx_buf
))
1014 || (t
->bits_per_word
&&
1015 ( t
->bits_per_word
< 4
1016 || t
->bits_per_word
> 32))) {
1017 dev_dbg(mcspi
->dev
, "transfer: %d Hz, %d %s%s, %d bpw\n",
1025 if (t
->speed_hz
&& t
->speed_hz
< (OMAP2_MCSPI_MAX_FREQ
>> 15)) {
1026 dev_dbg(mcspi
->dev
, "speed_hz %d below minimum %d Hz\n",
1028 OMAP2_MCSPI_MAX_FREQ
>> 15);
1032 if (m
->is_dma_mapped
|| len
< DMA_MIN_BYTES
)
1035 if (tx_buf
!= NULL
) {
1036 t
->tx_dma
= dma_map_single(mcspi
->dev
, (void *) tx_buf
,
1037 len
, DMA_TO_DEVICE
);
1038 if (dma_mapping_error(mcspi
->dev
, t
->tx_dma
)) {
1039 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1044 if (rx_buf
!= NULL
) {
1045 t
->rx_dma
= dma_map_single(mcspi
->dev
, rx_buf
, t
->len
,
1047 if (dma_mapping_error(mcspi
->dev
, t
->rx_dma
)) {
1048 dev_dbg(mcspi
->dev
, "dma %cX %d bytes error\n",
1051 dma_unmap_single(mcspi
->dev
, t
->tx_dma
,
1052 len
, DMA_TO_DEVICE
);
1058 omap2_mcspi_work(mcspi
, m
);
1059 spi_finalize_current_message(master
);
1063 static int __devinit
omap2_mcspi_master_setup(struct omap2_mcspi
*mcspi
)
1065 struct spi_master
*master
= mcspi
->master
;
1066 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1069 ret
= omap2_mcspi_enable_clocks(mcspi
);
1073 mcspi_write_reg(master
, OMAP2_MCSPI_WAKEUPENABLE
,
1074 OMAP2_MCSPI_WAKEUPENABLE_WKEN
);
1075 ctx
->wakeupenable
= OMAP2_MCSPI_WAKEUPENABLE_WKEN
;
1077 omap2_mcspi_set_master_mode(master
);
1078 omap2_mcspi_disable_clocks(mcspi
);
1082 static int omap_mcspi_runtime_resume(struct device
*dev
)
1084 struct omap2_mcspi
*mcspi
;
1085 struct spi_master
*master
;
1087 master
= dev_get_drvdata(dev
);
1088 mcspi
= spi_master_get_devdata(master
);
1089 omap2_mcspi_restore_ctx(mcspi
);
1094 static struct omap2_mcspi_platform_config omap2_pdata
= {
1098 static struct omap2_mcspi_platform_config omap4_pdata
= {
1099 .regs_offset
= OMAP4_MCSPI_REG_OFFSET
,
1102 static const struct of_device_id omap_mcspi_of_match
[] = {
1104 .compatible
= "ti,omap2-mcspi",
1105 .data
= &omap2_pdata
,
1108 .compatible
= "ti,omap4-mcspi",
1109 .data
= &omap4_pdata
,
1113 MODULE_DEVICE_TABLE(of
, omap_mcspi_of_match
);
1115 static int __devinit
omap2_mcspi_probe(struct platform_device
*pdev
)
1117 struct spi_master
*master
;
1118 struct omap2_mcspi_platform_config
*pdata
;
1119 struct omap2_mcspi
*mcspi
;
1122 u32 regs_offset
= 0;
1123 static int bus_num
= 1;
1124 struct device_node
*node
= pdev
->dev
.of_node
;
1125 const struct of_device_id
*match
;
1127 master
= spi_alloc_master(&pdev
->dev
, sizeof *mcspi
);
1128 if (master
== NULL
) {
1129 dev_dbg(&pdev
->dev
, "master allocation failed\n");
1133 /* the spi->mode bits understood by this driver: */
1134 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
1136 master
->setup
= omap2_mcspi_setup
;
1137 master
->prepare_transfer_hardware
= omap2_prepare_transfer
;
1138 master
->unprepare_transfer_hardware
= omap2_unprepare_transfer
;
1139 master
->transfer_one_message
= omap2_mcspi_transfer_one_message
;
1140 master
->cleanup
= omap2_mcspi_cleanup
;
1141 master
->dev
.of_node
= node
;
1143 match
= of_match_device(omap_mcspi_of_match
, &pdev
->dev
);
1145 u32 num_cs
= 1; /* default number of chipselect */
1146 pdata
= match
->data
;
1148 of_property_read_u32(node
, "ti,spi-num-cs", &num_cs
);
1149 master
->num_chipselect
= num_cs
;
1150 master
->bus_num
= bus_num
++;
1152 pdata
= pdev
->dev
.platform_data
;
1153 master
->num_chipselect
= pdata
->num_cs
;
1155 master
->bus_num
= pdev
->id
;
1157 regs_offset
= pdata
->regs_offset
;
1159 dev_set_drvdata(&pdev
->dev
, master
);
1161 mcspi
= spi_master_get_devdata(master
);
1162 mcspi
->master
= master
;
1164 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1170 r
->start
+= regs_offset
;
1171 r
->end
+= regs_offset
;
1172 mcspi
->phys
= r
->start
;
1174 mcspi
->base
= devm_request_and_ioremap(&pdev
->dev
, r
);
1176 dev_dbg(&pdev
->dev
, "can't ioremap MCSPI\n");
1181 mcspi
->dev
= &pdev
->dev
;
1183 INIT_LIST_HEAD(&mcspi
->ctx
.cs
);
1185 mcspi
->dma_channels
= kcalloc(master
->num_chipselect
,
1186 sizeof(struct omap2_mcspi_dma
),
1189 if (mcspi
->dma_channels
== NULL
)
1192 for (i
= 0; i
< master
->num_chipselect
; i
++) {
1193 char dma_ch_name
[14];
1194 struct resource
*dma_res
;
1196 sprintf(dma_ch_name
, "rx%d", i
);
1197 dma_res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
,
1200 dev_dbg(&pdev
->dev
, "cannot get DMA RX channel\n");
1205 mcspi
->dma_channels
[i
].dma_rx_sync_dev
= dma_res
->start
;
1206 sprintf(dma_ch_name
, "tx%d", i
);
1207 dma_res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
,
1210 dev_dbg(&pdev
->dev
, "cannot get DMA TX channel\n");
1215 mcspi
->dma_channels
[i
].dma_tx_sync_dev
= dma_res
->start
;
1221 pm_runtime_use_autosuspend(&pdev
->dev
);
1222 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
1223 pm_runtime_enable(&pdev
->dev
);
1225 if (status
|| omap2_mcspi_master_setup(mcspi
) < 0)
1228 status
= spi_register_master(master
);
1235 pm_runtime_disable(&pdev
->dev
);
1237 kfree(mcspi
->dma_channels
);
1239 spi_master_put(master
);
1240 platform_set_drvdata(pdev
, NULL
);
1244 static int __devexit
omap2_mcspi_remove(struct platform_device
*pdev
)
1246 struct spi_master
*master
;
1247 struct omap2_mcspi
*mcspi
;
1248 struct omap2_mcspi_dma
*dma_channels
;
1250 master
= dev_get_drvdata(&pdev
->dev
);
1251 mcspi
= spi_master_get_devdata(master
);
1252 dma_channels
= mcspi
->dma_channels
;
1254 omap2_mcspi_disable_clocks(mcspi
);
1255 pm_runtime_disable(&pdev
->dev
);
1257 spi_unregister_master(master
);
1258 kfree(dma_channels
);
1259 platform_set_drvdata(pdev
, NULL
);
1264 /* work with hotplug and coldplug */
1265 MODULE_ALIAS("platform:omap2_mcspi");
1267 #ifdef CONFIG_SUSPEND
1269 * When SPI wake up from off-mode, CS is in activate state. If it was in
1270 * unactive state when driver was suspend, then force it to unactive state at
1273 static int omap2_mcspi_resume(struct device
*dev
)
1275 struct spi_master
*master
= dev_get_drvdata(dev
);
1276 struct omap2_mcspi
*mcspi
= spi_master_get_devdata(master
);
1277 struct omap2_mcspi_regs
*ctx
= &mcspi
->ctx
;
1278 struct omap2_mcspi_cs
*cs
;
1280 omap2_mcspi_enable_clocks(mcspi
);
1281 list_for_each_entry(cs
, &ctx
->cs
, node
) {
1282 if ((cs
->chconf0
& OMAP2_MCSPI_CHCONF_FORCE
) == 0) {
1284 * We need to toggle CS state for OMAP take this
1285 * change in account.
1287 MOD_REG_BIT(cs
->chconf0
, OMAP2_MCSPI_CHCONF_FORCE
, 1);
1288 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1289 MOD_REG_BIT(cs
->chconf0
, OMAP2_MCSPI_CHCONF_FORCE
, 0);
1290 __raw_writel(cs
->chconf0
, cs
->base
+ OMAP2_MCSPI_CHCONF0
);
1293 omap2_mcspi_disable_clocks(mcspi
);
1297 #define omap2_mcspi_resume NULL
1300 static const struct dev_pm_ops omap2_mcspi_pm_ops
= {
1301 .resume
= omap2_mcspi_resume
,
1302 .runtime_resume
= omap_mcspi_runtime_resume
,
1305 static struct platform_driver omap2_mcspi_driver
= {
1307 .name
= "omap2_mcspi",
1308 .owner
= THIS_MODULE
,
1309 .pm
= &omap2_mcspi_pm_ops
,
1310 .of_match_table
= omap_mcspi_of_match
,
1312 .probe
= omap2_mcspi_probe
,
1313 .remove
= __devexit_p(omap2_mcspi_remove
),
1316 module_platform_driver(omap2_mcspi_driver
);
1317 MODULE_LICENSE("GPL");