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spi/omap-mcspi: check condition also after timeout
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-omap2-mcspi.c
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/dmaengine.h>
32 #include <linux/omap-dma.h>
33 #include <linux/platform_device.h>
34 #include <linux/err.h>
35 #include <linux/clk.h>
36 #include <linux/io.h>
37 #include <linux/slab.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/of.h>
40 #include <linux/of_device.h>
41 #include <linux/pinctrl/consumer.h>
42
43 #include <linux/spi/spi.h>
44
45 #include <linux/platform_data/spi-omap2-mcspi.h>
46
47 #define OMAP2_MCSPI_MAX_FREQ 48000000
48 #define SPI_AUTOSUSPEND_TIMEOUT 2000
49
50 #define OMAP2_MCSPI_REVISION 0x00
51 #define OMAP2_MCSPI_SYSSTATUS 0x14
52 #define OMAP2_MCSPI_IRQSTATUS 0x18
53 #define OMAP2_MCSPI_IRQENABLE 0x1c
54 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
55 #define OMAP2_MCSPI_SYST 0x24
56 #define OMAP2_MCSPI_MODULCTRL 0x28
57
58 /* per-channel banks, 0x14 bytes each, first is: */
59 #define OMAP2_MCSPI_CHCONF0 0x2c
60 #define OMAP2_MCSPI_CHSTAT0 0x30
61 #define OMAP2_MCSPI_CHCTRL0 0x34
62 #define OMAP2_MCSPI_TX0 0x38
63 #define OMAP2_MCSPI_RX0 0x3c
64
65 /* per-register bitmasks: */
66
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
70
71 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86
87 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
88 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
89 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
90
91 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
92
93 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
94
95 /* We have 2 DMA channels per CS, one for RX and one for TX */
96 struct omap2_mcspi_dma {
97 struct dma_chan *dma_tx;
98 struct dma_chan *dma_rx;
99
100 int dma_tx_sync_dev;
101 int dma_rx_sync_dev;
102
103 struct completion dma_tx_completion;
104 struct completion dma_rx_completion;
105 };
106
107 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
108 * cache operations; better heuristics consider wordsize and bitrate.
109 */
110 #define DMA_MIN_BYTES 160
111
112
113 /*
114 * Used for context save and restore, structure members to be updated whenever
115 * corresponding registers are modified.
116 */
117 struct omap2_mcspi_regs {
118 u32 modulctrl;
119 u32 wakeupenable;
120 struct list_head cs;
121 };
122
123 struct omap2_mcspi {
124 struct spi_master *master;
125 /* Virtual base address of the controller */
126 void __iomem *base;
127 unsigned long phys;
128 /* SPI1 has 4 channels, while SPI2 has 2 */
129 struct omap2_mcspi_dma *dma_channels;
130 struct device *dev;
131 struct omap2_mcspi_regs ctx;
132 unsigned int pin_dir:1;
133 };
134
135 struct omap2_mcspi_cs {
136 void __iomem *base;
137 unsigned long phys;
138 int word_len;
139 struct list_head node;
140 /* Context save and restore shadow register */
141 u32 chconf0;
142 };
143
144 static inline void mcspi_write_reg(struct spi_master *master,
145 int idx, u32 val)
146 {
147 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
148
149 __raw_writel(val, mcspi->base + idx);
150 }
151
152 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
153 {
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
156 return __raw_readl(mcspi->base + idx);
157 }
158
159 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
160 int idx, u32 val)
161 {
162 struct omap2_mcspi_cs *cs = spi->controller_state;
163
164 __raw_writel(val, cs->base + idx);
165 }
166
167 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
168 {
169 struct omap2_mcspi_cs *cs = spi->controller_state;
170
171 return __raw_readl(cs->base + idx);
172 }
173
174 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
175 {
176 struct omap2_mcspi_cs *cs = spi->controller_state;
177
178 return cs->chconf0;
179 }
180
181 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
182 {
183 struct omap2_mcspi_cs *cs = spi->controller_state;
184
185 cs->chconf0 = val;
186 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
187 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
188 }
189
190 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
191 int is_read, int enable)
192 {
193 u32 l, rw;
194
195 l = mcspi_cached_chconf0(spi);
196
197 if (is_read) /* 1 is read, 0 write */
198 rw = OMAP2_MCSPI_CHCONF_DMAR;
199 else
200 rw = OMAP2_MCSPI_CHCONF_DMAW;
201
202 if (enable)
203 l |= rw;
204 else
205 l &= ~rw;
206
207 mcspi_write_chconf0(spi, l);
208 }
209
210 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
211 {
212 u32 l;
213
214 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
215 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
216 /* Flash post-writes */
217 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
218 }
219
220 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
221 {
222 u32 l;
223
224 l = mcspi_cached_chconf0(spi);
225 if (cs_active)
226 l |= OMAP2_MCSPI_CHCONF_FORCE;
227 else
228 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
229
230 mcspi_write_chconf0(spi, l);
231 }
232
233 static void omap2_mcspi_set_master_mode(struct spi_master *master)
234 {
235 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
236 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
237 u32 l;
238
239 /*
240 * Setup when switching from (reset default) slave mode
241 * to single-channel master mode
242 */
243 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
244 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
245 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
246 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
247
248 ctx->modulctrl = l;
249 }
250
251 static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
252 {
253 struct spi_master *spi_cntrl = mcspi->master;
254 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
255 struct omap2_mcspi_cs *cs;
256
257 /* McSPI: context restore */
258 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
259 mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
260
261 list_for_each_entry(cs, &ctx->cs, node)
262 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
263 }
264
265 static int omap2_prepare_transfer(struct spi_master *master)
266 {
267 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
268
269 pm_runtime_get_sync(mcspi->dev);
270 return 0;
271 }
272
273 static int omap2_unprepare_transfer(struct spi_master *master)
274 {
275 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
276
277 pm_runtime_mark_last_busy(mcspi->dev);
278 pm_runtime_put_autosuspend(mcspi->dev);
279 return 0;
280 }
281
282 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
283 {
284 unsigned long timeout;
285
286 timeout = jiffies + msecs_to_jiffies(1000);
287 while (!(__raw_readl(reg) & bit)) {
288 if (time_after(jiffies, timeout)) {
289 if (!(__raw_readl(reg) & bit))
290 return -ETIMEDOUT;
291 else
292 return 0;
293 }
294 cpu_relax();
295 }
296 return 0;
297 }
298
299 static void omap2_mcspi_rx_callback(void *data)
300 {
301 struct spi_device *spi = data;
302 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
303 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
304
305 /* We must disable the DMA RX request */
306 omap2_mcspi_set_dma_req(spi, 1, 0);
307
308 complete(&mcspi_dma->dma_rx_completion);
309 }
310
311 static void omap2_mcspi_tx_callback(void *data)
312 {
313 struct spi_device *spi = data;
314 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
315 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
316
317 /* We must disable the DMA TX request */
318 omap2_mcspi_set_dma_req(spi, 0, 0);
319
320 complete(&mcspi_dma->dma_tx_completion);
321 }
322
323 static void omap2_mcspi_tx_dma(struct spi_device *spi,
324 struct spi_transfer *xfer,
325 struct dma_slave_config cfg)
326 {
327 struct omap2_mcspi *mcspi;
328 struct omap2_mcspi_dma *mcspi_dma;
329 unsigned int count;
330
331 mcspi = spi_master_get_devdata(spi->master);
332 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
333 count = xfer->len;
334
335 if (mcspi_dma->dma_tx) {
336 struct dma_async_tx_descriptor *tx;
337 struct scatterlist sg;
338
339 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
340
341 sg_init_table(&sg, 1);
342 sg_dma_address(&sg) = xfer->tx_dma;
343 sg_dma_len(&sg) = xfer->len;
344
345 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, &sg, 1,
346 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
347 if (tx) {
348 tx->callback = omap2_mcspi_tx_callback;
349 tx->callback_param = spi;
350 dmaengine_submit(tx);
351 } else {
352 /* FIXME: fall back to PIO? */
353 }
354 }
355 dma_async_issue_pending(mcspi_dma->dma_tx);
356 omap2_mcspi_set_dma_req(spi, 0, 1);
357
358 }
359
360 static unsigned
361 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
362 struct dma_slave_config cfg,
363 unsigned es)
364 {
365 struct omap2_mcspi *mcspi;
366 struct omap2_mcspi_dma *mcspi_dma;
367 unsigned int count;
368 u32 l;
369 int elements = 0;
370 int word_len, element_count;
371 struct omap2_mcspi_cs *cs = spi->controller_state;
372 mcspi = spi_master_get_devdata(spi->master);
373 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
374 count = xfer->len;
375 word_len = cs->word_len;
376 l = mcspi_cached_chconf0(spi);
377
378 if (word_len <= 8)
379 element_count = count;
380 else if (word_len <= 16)
381 element_count = count >> 1;
382 else /* word_len <= 32 */
383 element_count = count >> 2;
384
385 if (mcspi_dma->dma_rx) {
386 struct dma_async_tx_descriptor *tx;
387 struct scatterlist sg;
388 size_t len = xfer->len - es;
389
390 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
391
392 if (l & OMAP2_MCSPI_CHCONF_TURBO)
393 len -= es;
394
395 sg_init_table(&sg, 1);
396 sg_dma_address(&sg) = xfer->rx_dma;
397 sg_dma_len(&sg) = len;
398
399 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx, &sg, 1,
400 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT |
401 DMA_CTRL_ACK);
402 if (tx) {
403 tx->callback = omap2_mcspi_rx_callback;
404 tx->callback_param = spi;
405 dmaengine_submit(tx);
406 } else {
407 /* FIXME: fall back to PIO? */
408 }
409 }
410
411 dma_async_issue_pending(mcspi_dma->dma_rx);
412 omap2_mcspi_set_dma_req(spi, 1, 1);
413
414 wait_for_completion(&mcspi_dma->dma_rx_completion);
415 dma_unmap_single(mcspi->dev, xfer->rx_dma, count,
416 DMA_FROM_DEVICE);
417 omap2_mcspi_set_enable(spi, 0);
418
419 elements = element_count - 1;
420
421 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
422 elements--;
423
424 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
425 & OMAP2_MCSPI_CHSTAT_RXS)) {
426 u32 w;
427
428 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
429 if (word_len <= 8)
430 ((u8 *)xfer->rx_buf)[elements++] = w;
431 else if (word_len <= 16)
432 ((u16 *)xfer->rx_buf)[elements++] = w;
433 else /* word_len <= 32 */
434 ((u32 *)xfer->rx_buf)[elements++] = w;
435 } else {
436 dev_err(&spi->dev, "DMA RX penultimate word empty");
437 count -= (word_len <= 8) ? 2 :
438 (word_len <= 16) ? 4 :
439 /* word_len <= 32 */ 8;
440 omap2_mcspi_set_enable(spi, 1);
441 return count;
442 }
443 }
444 if (likely(mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHSTAT0)
445 & OMAP2_MCSPI_CHSTAT_RXS)) {
446 u32 w;
447
448 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
449 if (word_len <= 8)
450 ((u8 *)xfer->rx_buf)[elements] = w;
451 else if (word_len <= 16)
452 ((u16 *)xfer->rx_buf)[elements] = w;
453 else /* word_len <= 32 */
454 ((u32 *)xfer->rx_buf)[elements] = w;
455 } else {
456 dev_err(&spi->dev, "DMA RX last word empty");
457 count -= (word_len <= 8) ? 1 :
458 (word_len <= 16) ? 2 :
459 /* word_len <= 32 */ 4;
460 }
461 omap2_mcspi_set_enable(spi, 1);
462 return count;
463 }
464
465 static unsigned
466 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
467 {
468 struct omap2_mcspi *mcspi;
469 struct omap2_mcspi_cs *cs = spi->controller_state;
470 struct omap2_mcspi_dma *mcspi_dma;
471 unsigned int count;
472 u32 l;
473 u8 *rx;
474 const u8 *tx;
475 struct dma_slave_config cfg;
476 enum dma_slave_buswidth width;
477 unsigned es;
478 void __iomem *chstat_reg;
479
480 mcspi = spi_master_get_devdata(spi->master);
481 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
482 l = mcspi_cached_chconf0(spi);
483
484
485 if (cs->word_len <= 8) {
486 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
487 es = 1;
488 } else if (cs->word_len <= 16) {
489 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
490 es = 2;
491 } else {
492 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
493 es = 4;
494 }
495
496 memset(&cfg, 0, sizeof(cfg));
497 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
498 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
499 cfg.src_addr_width = width;
500 cfg.dst_addr_width = width;
501 cfg.src_maxburst = 1;
502 cfg.dst_maxburst = 1;
503
504 rx = xfer->rx_buf;
505 tx = xfer->tx_buf;
506
507 count = xfer->len;
508
509 if (tx != NULL)
510 omap2_mcspi_tx_dma(spi, xfer, cfg);
511
512 if (rx != NULL)
513 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
514
515 if (tx != NULL) {
516 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
517 wait_for_completion(&mcspi_dma->dma_tx_completion);
518 dma_unmap_single(mcspi->dev, xfer->tx_dma, xfer->len,
519 DMA_TO_DEVICE);
520
521 /* for TX_ONLY mode, be sure all words have shifted out */
522 if (rx == NULL) {
523 if (mcspi_wait_for_reg_bit(chstat_reg,
524 OMAP2_MCSPI_CHSTAT_TXS) < 0)
525 dev_err(&spi->dev, "TXS timed out\n");
526 else if (mcspi_wait_for_reg_bit(chstat_reg,
527 OMAP2_MCSPI_CHSTAT_EOT) < 0)
528 dev_err(&spi->dev, "EOT timed out\n");
529 }
530 }
531 return count;
532 }
533
534 static unsigned
535 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
536 {
537 struct omap2_mcspi *mcspi;
538 struct omap2_mcspi_cs *cs = spi->controller_state;
539 unsigned int count, c;
540 u32 l;
541 void __iomem *base = cs->base;
542 void __iomem *tx_reg;
543 void __iomem *rx_reg;
544 void __iomem *chstat_reg;
545 int word_len;
546
547 mcspi = spi_master_get_devdata(spi->master);
548 count = xfer->len;
549 c = count;
550 word_len = cs->word_len;
551
552 l = mcspi_cached_chconf0(spi);
553
554 /* We store the pre-calculated register addresses on stack to speed
555 * up the transfer loop. */
556 tx_reg = base + OMAP2_MCSPI_TX0;
557 rx_reg = base + OMAP2_MCSPI_RX0;
558 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
559
560 if (c < (word_len>>3))
561 return 0;
562
563 if (word_len <= 8) {
564 u8 *rx;
565 const u8 *tx;
566
567 rx = xfer->rx_buf;
568 tx = xfer->tx_buf;
569
570 do {
571 c -= 1;
572 if (tx != NULL) {
573 if (mcspi_wait_for_reg_bit(chstat_reg,
574 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
575 dev_err(&spi->dev, "TXS timed out\n");
576 goto out;
577 }
578 dev_vdbg(&spi->dev, "write-%d %02x\n",
579 word_len, *tx);
580 __raw_writel(*tx++, tx_reg);
581 }
582 if (rx != NULL) {
583 if (mcspi_wait_for_reg_bit(chstat_reg,
584 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
585 dev_err(&spi->dev, "RXS timed out\n");
586 goto out;
587 }
588
589 if (c == 1 && tx == NULL &&
590 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
591 omap2_mcspi_set_enable(spi, 0);
592 *rx++ = __raw_readl(rx_reg);
593 dev_vdbg(&spi->dev, "read-%d %02x\n",
594 word_len, *(rx - 1));
595 if (mcspi_wait_for_reg_bit(chstat_reg,
596 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
597 dev_err(&spi->dev,
598 "RXS timed out\n");
599 goto out;
600 }
601 c = 0;
602 } else if (c == 0 && tx == NULL) {
603 omap2_mcspi_set_enable(spi, 0);
604 }
605
606 *rx++ = __raw_readl(rx_reg);
607 dev_vdbg(&spi->dev, "read-%d %02x\n",
608 word_len, *(rx - 1));
609 }
610 } while (c);
611 } else if (word_len <= 16) {
612 u16 *rx;
613 const u16 *tx;
614
615 rx = xfer->rx_buf;
616 tx = xfer->tx_buf;
617 do {
618 c -= 2;
619 if (tx != NULL) {
620 if (mcspi_wait_for_reg_bit(chstat_reg,
621 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
622 dev_err(&spi->dev, "TXS timed out\n");
623 goto out;
624 }
625 dev_vdbg(&spi->dev, "write-%d %04x\n",
626 word_len, *tx);
627 __raw_writel(*tx++, tx_reg);
628 }
629 if (rx != NULL) {
630 if (mcspi_wait_for_reg_bit(chstat_reg,
631 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
632 dev_err(&spi->dev, "RXS timed out\n");
633 goto out;
634 }
635
636 if (c == 2 && tx == NULL &&
637 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
638 omap2_mcspi_set_enable(spi, 0);
639 *rx++ = __raw_readl(rx_reg);
640 dev_vdbg(&spi->dev, "read-%d %04x\n",
641 word_len, *(rx - 1));
642 if (mcspi_wait_for_reg_bit(chstat_reg,
643 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
644 dev_err(&spi->dev,
645 "RXS timed out\n");
646 goto out;
647 }
648 c = 0;
649 } else if (c == 0 && tx == NULL) {
650 omap2_mcspi_set_enable(spi, 0);
651 }
652
653 *rx++ = __raw_readl(rx_reg);
654 dev_vdbg(&spi->dev, "read-%d %04x\n",
655 word_len, *(rx - 1));
656 }
657 } while (c >= 2);
658 } else if (word_len <= 32) {
659 u32 *rx;
660 const u32 *tx;
661
662 rx = xfer->rx_buf;
663 tx = xfer->tx_buf;
664 do {
665 c -= 4;
666 if (tx != NULL) {
667 if (mcspi_wait_for_reg_bit(chstat_reg,
668 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
669 dev_err(&spi->dev, "TXS timed out\n");
670 goto out;
671 }
672 dev_vdbg(&spi->dev, "write-%d %08x\n",
673 word_len, *tx);
674 __raw_writel(*tx++, tx_reg);
675 }
676 if (rx != NULL) {
677 if (mcspi_wait_for_reg_bit(chstat_reg,
678 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
679 dev_err(&spi->dev, "RXS timed out\n");
680 goto out;
681 }
682
683 if (c == 4 && tx == NULL &&
684 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
685 omap2_mcspi_set_enable(spi, 0);
686 *rx++ = __raw_readl(rx_reg);
687 dev_vdbg(&spi->dev, "read-%d %08x\n",
688 word_len, *(rx - 1));
689 if (mcspi_wait_for_reg_bit(chstat_reg,
690 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
691 dev_err(&spi->dev,
692 "RXS timed out\n");
693 goto out;
694 }
695 c = 0;
696 } else if (c == 0 && tx == NULL) {
697 omap2_mcspi_set_enable(spi, 0);
698 }
699
700 *rx++ = __raw_readl(rx_reg);
701 dev_vdbg(&spi->dev, "read-%d %08x\n",
702 word_len, *(rx - 1));
703 }
704 } while (c >= 4);
705 }
706
707 /* for TX_ONLY mode, be sure all words have shifted out */
708 if (xfer->rx_buf == NULL) {
709 if (mcspi_wait_for_reg_bit(chstat_reg,
710 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
711 dev_err(&spi->dev, "TXS timed out\n");
712 } else if (mcspi_wait_for_reg_bit(chstat_reg,
713 OMAP2_MCSPI_CHSTAT_EOT) < 0)
714 dev_err(&spi->dev, "EOT timed out\n");
715
716 /* disable chan to purge rx datas received in TX_ONLY transfer,
717 * otherwise these rx datas will affect the direct following
718 * RX_ONLY transfer.
719 */
720 omap2_mcspi_set_enable(spi, 0);
721 }
722 out:
723 omap2_mcspi_set_enable(spi, 1);
724 return count - c;
725 }
726
727 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
728 {
729 u32 div;
730
731 for (div = 0; div < 15; div++)
732 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
733 return div;
734
735 return 15;
736 }
737
738 /* called only when no transfer is active to this device */
739 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
740 struct spi_transfer *t)
741 {
742 struct omap2_mcspi_cs *cs = spi->controller_state;
743 struct omap2_mcspi *mcspi;
744 struct spi_master *spi_cntrl;
745 u32 l = 0, div = 0;
746 u8 word_len = spi->bits_per_word;
747 u32 speed_hz = spi->max_speed_hz;
748
749 mcspi = spi_master_get_devdata(spi->master);
750 spi_cntrl = mcspi->master;
751
752 if (t != NULL && t->bits_per_word)
753 word_len = t->bits_per_word;
754
755 cs->word_len = word_len;
756
757 if (t && t->speed_hz)
758 speed_hz = t->speed_hz;
759
760 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
761 div = omap2_mcspi_calc_divisor(speed_hz);
762
763 l = mcspi_cached_chconf0(spi);
764
765 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
766 * REVISIT: this controller could support SPI_3WIRE mode.
767 */
768 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
769 l &= ~OMAP2_MCSPI_CHCONF_IS;
770 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
771 l |= OMAP2_MCSPI_CHCONF_DPE0;
772 } else {
773 l |= OMAP2_MCSPI_CHCONF_IS;
774 l |= OMAP2_MCSPI_CHCONF_DPE1;
775 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
776 }
777
778 /* wordlength */
779 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
780 l |= (word_len - 1) << 7;
781
782 /* set chipselect polarity; manage with FORCE */
783 if (!(spi->mode & SPI_CS_HIGH))
784 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
785 else
786 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
787
788 /* set clock divisor */
789 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
790 l |= div << 2;
791
792 /* set SPI mode 0..3 */
793 if (spi->mode & SPI_CPOL)
794 l |= OMAP2_MCSPI_CHCONF_POL;
795 else
796 l &= ~OMAP2_MCSPI_CHCONF_POL;
797 if (spi->mode & SPI_CPHA)
798 l |= OMAP2_MCSPI_CHCONF_PHA;
799 else
800 l &= ~OMAP2_MCSPI_CHCONF_PHA;
801
802 mcspi_write_chconf0(spi, l);
803
804 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
805 OMAP2_MCSPI_MAX_FREQ >> div,
806 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
807 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
808
809 return 0;
810 }
811
812 static int omap2_mcspi_request_dma(struct spi_device *spi)
813 {
814 struct spi_master *master = spi->master;
815 struct omap2_mcspi *mcspi;
816 struct omap2_mcspi_dma *mcspi_dma;
817 dma_cap_mask_t mask;
818 unsigned sig;
819
820 mcspi = spi_master_get_devdata(master);
821 mcspi_dma = mcspi->dma_channels + spi->chip_select;
822
823 init_completion(&mcspi_dma->dma_rx_completion);
824 init_completion(&mcspi_dma->dma_tx_completion);
825
826 dma_cap_zero(mask);
827 dma_cap_set(DMA_SLAVE, mask);
828 sig = mcspi_dma->dma_rx_sync_dev;
829 mcspi_dma->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
830 if (!mcspi_dma->dma_rx) {
831 dev_err(&spi->dev, "no RX DMA engine channel for McSPI\n");
832 return -EAGAIN;
833 }
834
835 sig = mcspi_dma->dma_tx_sync_dev;
836 mcspi_dma->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig);
837 if (!mcspi_dma->dma_tx) {
838 dev_err(&spi->dev, "no TX DMA engine channel for McSPI\n");
839 dma_release_channel(mcspi_dma->dma_rx);
840 mcspi_dma->dma_rx = NULL;
841 return -EAGAIN;
842 }
843
844 return 0;
845 }
846
847 static int omap2_mcspi_setup(struct spi_device *spi)
848 {
849 int ret;
850 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
851 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
852 struct omap2_mcspi_dma *mcspi_dma;
853 struct omap2_mcspi_cs *cs = spi->controller_state;
854
855 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
856 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
857 spi->bits_per_word);
858 return -EINVAL;
859 }
860
861 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
862
863 if (!cs) {
864 cs = kzalloc(sizeof *cs, GFP_KERNEL);
865 if (!cs)
866 return -ENOMEM;
867 cs->base = mcspi->base + spi->chip_select * 0x14;
868 cs->phys = mcspi->phys + spi->chip_select * 0x14;
869 cs->chconf0 = 0;
870 spi->controller_state = cs;
871 /* Link this to context save list */
872 list_add_tail(&cs->node, &ctx->cs);
873 }
874
875 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
876 ret = omap2_mcspi_request_dma(spi);
877 if (ret < 0)
878 return ret;
879 }
880
881 ret = pm_runtime_get_sync(mcspi->dev);
882 if (ret < 0)
883 return ret;
884
885 ret = omap2_mcspi_setup_transfer(spi, NULL);
886 pm_runtime_mark_last_busy(mcspi->dev);
887 pm_runtime_put_autosuspend(mcspi->dev);
888
889 return ret;
890 }
891
892 static void omap2_mcspi_cleanup(struct spi_device *spi)
893 {
894 struct omap2_mcspi *mcspi;
895 struct omap2_mcspi_dma *mcspi_dma;
896 struct omap2_mcspi_cs *cs;
897
898 mcspi = spi_master_get_devdata(spi->master);
899
900 if (spi->controller_state) {
901 /* Unlink controller state from context save list */
902 cs = spi->controller_state;
903 list_del(&cs->node);
904
905 kfree(cs);
906 }
907
908 if (spi->chip_select < spi->master->num_chipselect) {
909 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
910
911 if (mcspi_dma->dma_rx) {
912 dma_release_channel(mcspi_dma->dma_rx);
913 mcspi_dma->dma_rx = NULL;
914 }
915 if (mcspi_dma->dma_tx) {
916 dma_release_channel(mcspi_dma->dma_tx);
917 mcspi_dma->dma_tx = NULL;
918 }
919 }
920 }
921
922 static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
923 {
924
925 /* We only enable one channel at a time -- the one whose message is
926 * -- although this controller would gladly
927 * arbitrate among multiple channels. This corresponds to "single
928 * channel" master mode. As a side effect, we need to manage the
929 * chipselect with the FORCE bit ... CS != channel enable.
930 */
931
932 struct spi_device *spi;
933 struct spi_transfer *t = NULL;
934 struct spi_master *master;
935 int cs_active = 0;
936 struct omap2_mcspi_cs *cs;
937 struct omap2_mcspi_device_config *cd;
938 int par_override = 0;
939 int status = 0;
940 u32 chconf;
941
942 spi = m->spi;
943 master = spi->master;
944 cs = spi->controller_state;
945 cd = spi->controller_data;
946
947 omap2_mcspi_set_enable(spi, 1);
948 list_for_each_entry(t, &m->transfers, transfer_list) {
949 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
950 status = -EINVAL;
951 break;
952 }
953 if (par_override || t->speed_hz || t->bits_per_word) {
954 par_override = 1;
955 status = omap2_mcspi_setup_transfer(spi, t);
956 if (status < 0)
957 break;
958 if (!t->speed_hz && !t->bits_per_word)
959 par_override = 0;
960 }
961 if (cd && cd->cs_per_word) {
962 chconf = mcspi->ctx.modulctrl;
963 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
964 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
965 mcspi->ctx.modulctrl =
966 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
967 }
968
969
970 if (!cs_active) {
971 omap2_mcspi_force_cs(spi, 1);
972 cs_active = 1;
973 }
974
975 chconf = mcspi_cached_chconf0(spi);
976 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
977 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
978
979 if (t->tx_buf == NULL)
980 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
981 else if (t->rx_buf == NULL)
982 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
983
984 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
985 /* Turbo mode is for more than one word */
986 if (t->len > ((cs->word_len + 7) >> 3))
987 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
988 }
989
990 mcspi_write_chconf0(spi, chconf);
991
992 if (t->len) {
993 unsigned count;
994
995 /* RX_ONLY mode needs dummy data in TX reg */
996 if (t->tx_buf == NULL)
997 __raw_writel(0, cs->base
998 + OMAP2_MCSPI_TX0);
999
1000 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
1001 count = omap2_mcspi_txrx_dma(spi, t);
1002 else
1003 count = omap2_mcspi_txrx_pio(spi, t);
1004 m->actual_length += count;
1005
1006 if (count != t->len) {
1007 status = -EIO;
1008 break;
1009 }
1010 }
1011
1012 if (t->delay_usecs)
1013 udelay(t->delay_usecs);
1014
1015 /* ignore the "leave it on after last xfer" hint */
1016 if (t->cs_change) {
1017 omap2_mcspi_force_cs(spi, 0);
1018 cs_active = 0;
1019 }
1020 }
1021 /* Restore defaults if they were overriden */
1022 if (par_override) {
1023 par_override = 0;
1024 status = omap2_mcspi_setup_transfer(spi, NULL);
1025 }
1026
1027 if (cs_active)
1028 omap2_mcspi_force_cs(spi, 0);
1029
1030 if (cd && cd->cs_per_word) {
1031 chconf = mcspi->ctx.modulctrl;
1032 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1033 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1034 mcspi->ctx.modulctrl =
1035 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1036 }
1037
1038 omap2_mcspi_set_enable(spi, 0);
1039
1040 m->status = status;
1041
1042 }
1043
1044 static int omap2_mcspi_transfer_one_message(struct spi_master *master,
1045 struct spi_message *m)
1046 {
1047 struct omap2_mcspi *mcspi;
1048 struct spi_transfer *t;
1049
1050 mcspi = spi_master_get_devdata(master);
1051 m->actual_length = 0;
1052 m->status = 0;
1053
1054 /* reject invalid messages and transfers */
1055 if (list_empty(&m->transfers))
1056 return -EINVAL;
1057 list_for_each_entry(t, &m->transfers, transfer_list) {
1058 const void *tx_buf = t->tx_buf;
1059 void *rx_buf = t->rx_buf;
1060 unsigned len = t->len;
1061
1062 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
1063 || (len && !(rx_buf || tx_buf))
1064 || (t->bits_per_word &&
1065 ( t->bits_per_word < 4
1066 || t->bits_per_word > 32))) {
1067 dev_dbg(mcspi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
1068 t->speed_hz,
1069 len,
1070 tx_buf ? "tx" : "",
1071 rx_buf ? "rx" : "",
1072 t->bits_per_word);
1073 return -EINVAL;
1074 }
1075 if (t->speed_hz && t->speed_hz < (OMAP2_MCSPI_MAX_FREQ >> 15)) {
1076 dev_dbg(mcspi->dev, "speed_hz %d below minimum %d Hz\n",
1077 t->speed_hz,
1078 OMAP2_MCSPI_MAX_FREQ >> 15);
1079 return -EINVAL;
1080 }
1081
1082 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
1083 continue;
1084
1085 if (tx_buf != NULL) {
1086 t->tx_dma = dma_map_single(mcspi->dev, (void *) tx_buf,
1087 len, DMA_TO_DEVICE);
1088 if (dma_mapping_error(mcspi->dev, t->tx_dma)) {
1089 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1090 'T', len);
1091 return -EINVAL;
1092 }
1093 }
1094 if (rx_buf != NULL) {
1095 t->rx_dma = dma_map_single(mcspi->dev, rx_buf, t->len,
1096 DMA_FROM_DEVICE);
1097 if (dma_mapping_error(mcspi->dev, t->rx_dma)) {
1098 dev_dbg(mcspi->dev, "dma %cX %d bytes error\n",
1099 'R', len);
1100 if (tx_buf != NULL)
1101 dma_unmap_single(mcspi->dev, t->tx_dma,
1102 len, DMA_TO_DEVICE);
1103 return -EINVAL;
1104 }
1105 }
1106 }
1107
1108 omap2_mcspi_work(mcspi, m);
1109 spi_finalize_current_message(master);
1110 return 0;
1111 }
1112
1113 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1114 {
1115 struct spi_master *master = mcspi->master;
1116 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1117 int ret = 0;
1118
1119 ret = pm_runtime_get_sync(mcspi->dev);
1120 if (ret < 0)
1121 return ret;
1122
1123 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1124 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1125 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1126
1127 omap2_mcspi_set_master_mode(master);
1128 pm_runtime_mark_last_busy(mcspi->dev);
1129 pm_runtime_put_autosuspend(mcspi->dev);
1130 return 0;
1131 }
1132
1133 static int omap_mcspi_runtime_resume(struct device *dev)
1134 {
1135 struct omap2_mcspi *mcspi;
1136 struct spi_master *master;
1137
1138 master = dev_get_drvdata(dev);
1139 mcspi = spi_master_get_devdata(master);
1140 omap2_mcspi_restore_ctx(mcspi);
1141
1142 return 0;
1143 }
1144
1145 static struct omap2_mcspi_platform_config omap2_pdata = {
1146 .regs_offset = 0,
1147 };
1148
1149 static struct omap2_mcspi_platform_config omap4_pdata = {
1150 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1151 };
1152
1153 static const struct of_device_id omap_mcspi_of_match[] = {
1154 {
1155 .compatible = "ti,omap2-mcspi",
1156 .data = &omap2_pdata,
1157 },
1158 {
1159 .compatible = "ti,omap4-mcspi",
1160 .data = &omap4_pdata,
1161 },
1162 { },
1163 };
1164 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1165
1166 static int omap2_mcspi_probe(struct platform_device *pdev)
1167 {
1168 struct spi_master *master;
1169 const struct omap2_mcspi_platform_config *pdata;
1170 struct omap2_mcspi *mcspi;
1171 struct resource *r;
1172 int status = 0, i;
1173 u32 regs_offset = 0;
1174 static int bus_num = 1;
1175 struct device_node *node = pdev->dev.of_node;
1176 const struct of_device_id *match;
1177 struct pinctrl *pinctrl;
1178
1179 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1180 if (master == NULL) {
1181 dev_dbg(&pdev->dev, "master allocation failed\n");
1182 return -ENOMEM;
1183 }
1184
1185 /* the spi->mode bits understood by this driver: */
1186 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1187
1188 master->setup = omap2_mcspi_setup;
1189 master->prepare_transfer_hardware = omap2_prepare_transfer;
1190 master->unprepare_transfer_hardware = omap2_unprepare_transfer;
1191 master->transfer_one_message = omap2_mcspi_transfer_one_message;
1192 master->cleanup = omap2_mcspi_cleanup;
1193 master->dev.of_node = node;
1194
1195 dev_set_drvdata(&pdev->dev, master);
1196
1197 mcspi = spi_master_get_devdata(master);
1198 mcspi->master = master;
1199
1200 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1201 if (match) {
1202 u32 num_cs = 1; /* default number of chipselect */
1203 pdata = match->data;
1204
1205 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1206 master->num_chipselect = num_cs;
1207 master->bus_num = bus_num++;
1208 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1209 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1210 } else {
1211 pdata = pdev->dev.platform_data;
1212 master->num_chipselect = pdata->num_cs;
1213 if (pdev->id != -1)
1214 master->bus_num = pdev->id;
1215 mcspi->pin_dir = pdata->pin_dir;
1216 }
1217 regs_offset = pdata->regs_offset;
1218
1219 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1220 if (r == NULL) {
1221 status = -ENODEV;
1222 goto free_master;
1223 }
1224
1225 r->start += regs_offset;
1226 r->end += regs_offset;
1227 mcspi->phys = r->start;
1228
1229 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1230 if (IS_ERR(mcspi->base)) {
1231 status = PTR_ERR(mcspi->base);
1232 goto free_master;
1233 }
1234
1235 mcspi->dev = &pdev->dev;
1236
1237 INIT_LIST_HEAD(&mcspi->ctx.cs);
1238
1239 mcspi->dma_channels = kcalloc(master->num_chipselect,
1240 sizeof(struct omap2_mcspi_dma),
1241 GFP_KERNEL);
1242
1243 if (mcspi->dma_channels == NULL)
1244 goto free_master;
1245
1246 for (i = 0; i < master->num_chipselect; i++) {
1247 char dma_ch_name[14];
1248 struct resource *dma_res;
1249
1250 sprintf(dma_ch_name, "rx%d", i);
1251 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1252 dma_ch_name);
1253 if (!dma_res) {
1254 dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
1255 status = -ENODEV;
1256 break;
1257 }
1258
1259 mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
1260 sprintf(dma_ch_name, "tx%d", i);
1261 dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
1262 dma_ch_name);
1263 if (!dma_res) {
1264 dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
1265 status = -ENODEV;
1266 break;
1267 }
1268
1269 mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
1270 }
1271
1272 if (status < 0)
1273 goto dma_chnl_free;
1274
1275 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1276 if (IS_ERR(pinctrl))
1277 dev_warn(&pdev->dev,
1278 "pins are not configured from the driver\n");
1279
1280 pm_runtime_use_autosuspend(&pdev->dev);
1281 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1282 pm_runtime_enable(&pdev->dev);
1283
1284 if (status || omap2_mcspi_master_setup(mcspi) < 0)
1285 goto disable_pm;
1286
1287 status = spi_register_master(master);
1288 if (status < 0)
1289 goto disable_pm;
1290
1291 return status;
1292
1293 disable_pm:
1294 pm_runtime_disable(&pdev->dev);
1295 dma_chnl_free:
1296 kfree(mcspi->dma_channels);
1297 free_master:
1298 spi_master_put(master);
1299 return status;
1300 }
1301
1302 static int omap2_mcspi_remove(struct platform_device *pdev)
1303 {
1304 struct spi_master *master;
1305 struct omap2_mcspi *mcspi;
1306 struct omap2_mcspi_dma *dma_channels;
1307
1308 master = dev_get_drvdata(&pdev->dev);
1309 mcspi = spi_master_get_devdata(master);
1310 dma_channels = mcspi->dma_channels;
1311
1312 pm_runtime_put_sync(mcspi->dev);
1313 pm_runtime_disable(&pdev->dev);
1314
1315 spi_unregister_master(master);
1316 kfree(dma_channels);
1317
1318 return 0;
1319 }
1320
1321 /* work with hotplug and coldplug */
1322 MODULE_ALIAS("platform:omap2_mcspi");
1323
1324 #ifdef CONFIG_SUSPEND
1325 /*
1326 * When SPI wake up from off-mode, CS is in activate state. If it was in
1327 * unactive state when driver was suspend, then force it to unactive state at
1328 * wake up.
1329 */
1330 static int omap2_mcspi_resume(struct device *dev)
1331 {
1332 struct spi_master *master = dev_get_drvdata(dev);
1333 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1334 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1335 struct omap2_mcspi_cs *cs;
1336
1337 pm_runtime_get_sync(mcspi->dev);
1338 list_for_each_entry(cs, &ctx->cs, node) {
1339 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1340 /*
1341 * We need to toggle CS state for OMAP take this
1342 * change in account.
1343 */
1344 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1345 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1346 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1347 __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
1348 }
1349 }
1350 pm_runtime_mark_last_busy(mcspi->dev);
1351 pm_runtime_put_autosuspend(mcspi->dev);
1352 return 0;
1353 }
1354 #else
1355 #define omap2_mcspi_resume NULL
1356 #endif
1357
1358 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1359 .resume = omap2_mcspi_resume,
1360 .runtime_resume = omap_mcspi_runtime_resume,
1361 };
1362
1363 static struct platform_driver omap2_mcspi_driver = {
1364 .driver = {
1365 .name = "omap2_mcspi",
1366 .owner = THIS_MODULE,
1367 .pm = &omap2_mcspi_pm_ops,
1368 .of_match_table = omap_mcspi_of_match,
1369 },
1370 .probe = omap2_mcspi_probe,
1371 .remove = omap2_mcspi_remove,
1372 };
1373
1374 module_platform_driver(omap2_mcspi_driver);
1375 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)