drivers/spi/spi-omap-uwire.c

   1 /*
   2  * MicroWire interface driver for OMAP
   3  *
   4  * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
   5  *
   6  * Ported to 2.6 OMAP uwire interface.
   7  * Copyright (C) 2004 Texas Instruments.
   8  *
   9  * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
  10  *
  11  * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
  12  * Copyright (C) 2006 Nokia
  13  *
  14  * Many updates by Imre Deak <imre.deak@nokia.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * You should have received a copy of the GNU General Public License along
  33  * with this program; if not, write to the Free Software Foundation, Inc.,
  34  * 675 Mass Ave, Cambridge, MA 02139, USA.
  35  */
  36 #include <linux/kernel.h>
  37 #include <linux/init.h>
  38 #include <linux/delay.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/err.h>
  43 #include <linux/clk.h>
  44 #include <linux/slab.h>
  45
  46 #include <linux/spi/spi.h>
  47 #include <linux/spi/spi_bitbang.h>
  48 #include <linux/module.h>
  49
  50 #include <asm/irq.h>
  51 #include <mach/hardware.h>
  52 #include <asm/io.h>
  53 #include <asm/mach-types.h>
  54
  55 #include <mach/mux.h>
  56
  57 #include <mach/omap7xx.h>       /* OMAP7XX_IO_CONF registers */
  58
  59
  60 /* FIXME address is now a platform device resource,
  61  * and irqs should show there too...
  62  */
  63 #define UWIRE_BASE_PHYS         0xFFFB3000
  64
  65 /* uWire Registers: */
  66 #define UWIRE_IO_SIZE 0x20
  67 #define UWIRE_TDR     0x00
  68 #define UWIRE_RDR     0x00
  69 #define UWIRE_CSR     0x01
  70 #define UWIRE_SR1     0x02
  71 #define UWIRE_SR2     0x03
  72 #define UWIRE_SR3     0x04
  73 #define UWIRE_SR4     0x05
  74 #define UWIRE_SR5     0x06
  75
  76 /* CSR bits */
  77 #define RDRB    (1 << 15)
  78 #define CSRB    (1 << 14)
  79 #define START   (1 << 13)
  80 #define CS_CMD  (1 << 12)
  81
  82 /* SR1 or SR2 bits */
  83 #define UWIRE_READ_FALLING_EDGE         0x0001
  84 #define UWIRE_READ_RISING_EDGE          0x0000
  85 #define UWIRE_WRITE_FALLING_EDGE        0x0000
  86 #define UWIRE_WRITE_RISING_EDGE         0x0002
  87 #define UWIRE_CS_ACTIVE_LOW             0x0000
  88 #define UWIRE_CS_ACTIVE_HIGH            0x0004
  89 #define UWIRE_FREQ_DIV_2                0x0000
  90 #define UWIRE_FREQ_DIV_4                0x0008
  91 #define UWIRE_FREQ_DIV_8                0x0010
  92 #define UWIRE_CHK_READY                 0x0020
  93 #define UWIRE_CLK_INVERTED              0x0040
  94
  95
  96 struct uwire_spi {
  97         struct spi_bitbang      bitbang;
  98         struct clk              *ck;
  99 };
 100
 101 struct uwire_state {
 102         unsigned        bits_per_word;
 103         unsigned        div1_idx;
 104 };
 105
 106 /* REVISIT compile time constant for idx_shift? */
 107 /*
 108  * Or, put it in a structure which is used throughout the driver;
 109  * that avoids having to issue two loads for each bit of static data.
 110  */
 111 static unsigned int uwire_idx_shift;
 112 static void __iomem *uwire_base;
 113
 114 static inline void uwire_write_reg(int idx, u16 val)
 115 {
 116         __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
 117 }
 118
 119 static inline u16 uwire_read_reg(int idx)
 120 {
 121         return __raw_readw(uwire_base + (idx << uwire_idx_shift));
 122 }
 123
 124 static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
 125 {
 126         u16     w, val = 0;
 127         int     shift, reg;
 128
 129         if (flags & UWIRE_CLK_INVERTED)
 130                 val ^= 0x03;
 131         val = flags & 0x3f;
 132         if (cs & 1)
 133                 shift = 6;
 134         else
 135                 shift = 0;
 136         if (cs <= 1)
 137                 reg = UWIRE_SR1;
 138         else
 139                 reg = UWIRE_SR2;
 140
 141         w = uwire_read_reg(reg);
 142         w &= ~(0x3f << shift);
 143         w |= val << shift;
 144         uwire_write_reg(reg, w);
 145 }
 146
 147 static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
 148 {
 149         u16 w;
 150         int c = 0;
 151         unsigned long max_jiffies = jiffies + HZ;
 152
 153         for (;;) {
 154                 w = uwire_read_reg(UWIRE_CSR);
 155                 if ((w & mask) == val)
 156                         break;
 157                 if (time_after(jiffies, max_jiffies)) {
 158                         printk(KERN_ERR "%s: timeout. reg=%#06x "
 159                                         "mask=%#06x val=%#06x\n",
 160                                __func__, w, mask, val);
 161                         return -1;
 162                 }
 163                 c++;
 164                 if (might_not_catch && c > 64)
 165                         break;
 166         }
 167         return 0;
 168 }
 169
 170 static void uwire_set_clk1_div(int div1_idx)
 171 {
 172         u16 w;
 173
 174         w = uwire_read_reg(UWIRE_SR3);
 175         w &= ~(0x03 << 1);
 176         w |= div1_idx << 1;
 177         uwire_write_reg(UWIRE_SR3, w);
 178 }
 179
 180 static void uwire_chipselect(struct spi_device *spi, int value)
 181 {
 182         struct  uwire_state *ust = spi->controller_state;
 183         u16     w;
 184         int     old_cs;
 185
 186
 187         BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
 188
 189         w = uwire_read_reg(UWIRE_CSR);
 190         old_cs = (w >> 10) & 0x03;
 191         if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
 192                 /* Deselect this CS, or the previous CS */
 193                 w &= ~CS_CMD;
 194                 uwire_write_reg(UWIRE_CSR, w);
 195         }
 196         /* activate specfied chipselect */
 197         if (value == BITBANG_CS_ACTIVE) {
 198                 uwire_set_clk1_div(ust->div1_idx);
 199                 /* invert clock? */
 200                 if (spi->mode & SPI_CPOL)
 201                         uwire_write_reg(UWIRE_SR4, 1);
 202                 else
 203                         uwire_write_reg(UWIRE_SR4, 0);
 204
 205                 w = spi->chip_select << 10;
 206                 w |= CS_CMD;
 207                 uwire_write_reg(UWIRE_CSR, w);
 208         }
 209 }
 210
 211 static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
 212 {
 213         struct uwire_state *ust = spi->controller_state;
 214         unsigned        len = t->len;
 215         unsigned        bits = ust->bits_per_word;
 216         unsigned        bytes;
 217         u16             val, w;
 218         int             status = 0;
 219
 220         if (!t->tx_buf && !t->rx_buf)
 221                 return 0;
 222
 223         /* Microwire doesn't read and write concurrently */
 224         if (t->tx_buf && t->rx_buf)
 225                 return -EPERM;
 226
 227         w = spi->chip_select << 10;
 228         w |= CS_CMD;
 229
 230         if (t->tx_buf) {
 231                 const u8        *buf = t->tx_buf;
 232
 233                 /* NOTE:  DMA could be used for TX transfers */
 234
 235                 /* write one or two bytes at a time */
 236                 while (len >= 1) {
 237                         /* tx bit 15 is first sent; we byteswap multibyte words
 238                          * (msb-first) on the way out from memory.
 239                          */
 240                         val = *buf++;
 241                         if (bits > 8) {
 242                                 bytes = 2;
 243                                 val |= *buf++ << 8;
 244                         } else
 245                                 bytes = 1;
 246                         val <<= 16 - bits;
 247
 248 #ifdef  VERBOSE
 249                         pr_debug("%s: write-%d =%04x\n",
 250                                         dev_name(&spi->dev), bits, val);
 251 #endif
 252                         if (wait_uwire_csr_flag(CSRB, 0, 0))
 253                                 goto eio;
 254
 255                         uwire_write_reg(UWIRE_TDR, val);
 256
 257                         /* start write */
 258                         val = START | w | (bits << 5);
 259
 260                         uwire_write_reg(UWIRE_CSR, val);
 261                         len -= bytes;
 262
 263                         /* Wait till write actually starts.
 264                          * This is needed with MPU clock 60+ MHz.
 265                          * REVISIT: we may not have time to catch it...
 266                          */
 267                         if (wait_uwire_csr_flag(CSRB, CSRB, 1))
 268                                 goto eio;
 269
 270                         status += bytes;
 271                 }
 272
 273                 /* REVISIT:  save this for later to get more i/o overlap */
 274                 if (wait_uwire_csr_flag(CSRB, 0, 0))
 275                         goto eio;
 276
 277         } else if (t->rx_buf) {
 278                 u8              *buf = t->rx_buf;
 279
 280                 /* read one or two bytes at a time */
 281                 while (len) {
 282                         if (bits > 8) {
 283                                 bytes = 2;
 284                         } else
 285                                 bytes = 1;
 286
 287                         /* start read */
 288                         val = START | w | (bits << 0);
 289                         uwire_write_reg(UWIRE_CSR, val);
 290                         len -= bytes;
 291
 292                         /* Wait till read actually starts */
 293                         (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
 294
 295                         if (wait_uwire_csr_flag(RDRB | CSRB,
 296                                                 RDRB, 0))
 297                                 goto eio;
 298
 299                         /* rx bit 0 is last received; multibyte words will
 300                          * be properly byteswapped on the way to memory.
 301                          */
 302                         val = uwire_read_reg(UWIRE_RDR);
 303                         val &= (1 << bits) - 1;
 304                         *buf++ = (u8) val;
 305                         if (bytes == 2)
 306                                 *buf++ = val >> 8;
 307                         status += bytes;
 308 #ifdef  VERBOSE
 309                         pr_debug("%s: read-%d =%04x\n",
 310                                         dev_name(&spi->dev), bits, val);
 311 #endif
 312
 313                 }
 314         }
 315         return status;
 316 eio:
 317         return -EIO;
 318 }
 319
 320 static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 321 {
 322         struct uwire_state      *ust = spi->controller_state;
 323         struct uwire_spi        *uwire;
 324         unsigned                flags = 0;
 325         unsigned                bits;
 326         unsigned                hz;
 327         unsigned long           rate;
 328         int                     div1_idx;
 329         int                     div1;
 330         int                     div2;
 331         int                     status;
 332
 333         uwire = spi_master_get_devdata(spi->master);
 334
 335         if (spi->chip_select > 3) {
 336                 pr_debug("%s: cs%d?\n", dev_name(&spi->dev), spi->chip_select);
 337                 status = -ENODEV;
 338                 goto done;
 339         }
 340
 341         bits = spi->bits_per_word;
 342         if (t != NULL && t->bits_per_word)
 343                 bits = t->bits_per_word;
 344
 345         if (bits > 16) {
 346                 pr_debug("%s: wordsize %d?\n", dev_name(&spi->dev), bits);
 347                 status = -ENODEV;
 348                 goto done;
 349         }
 350         ust->bits_per_word = bits;
 351
 352         /* mode 0..3, clock inverted separately;
 353          * standard nCS signaling;
 354          * don't treat DI=high as "not ready"
 355          */
 356         if (spi->mode & SPI_CS_HIGH)
 357                 flags |= UWIRE_CS_ACTIVE_HIGH;
 358
 359         if (spi->mode & SPI_CPOL)
 360                 flags |= UWIRE_CLK_INVERTED;
 361
 362         switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
 363         case SPI_MODE_0:
 364         case SPI_MODE_3:
 365                 flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
 366                 break;
 367         case SPI_MODE_1:
 368         case SPI_MODE_2:
 369                 flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
 370                 break;
 371         }
 372
 373         /* assume it's already enabled */
 374         rate = clk_get_rate(uwire->ck);
 375
 376         hz = spi->max_speed_hz;
 377         if (t != NULL && t->speed_hz)
 378                 hz = t->speed_hz;
 379
 380         if (!hz) {
 381                 pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
 382                 status = -EINVAL;
 383                 goto done;
 384         }
 385
 386         /* F_INT = mpu_xor_clk / DIV1 */
 387         for (div1_idx = 0; div1_idx < 4; div1_idx++) {
 388                 switch (div1_idx) {
 389                 case 0:
 390                         div1 = 2;
 391                         break;
 392                 case 1:
 393                         div1 = 4;
 394                         break;
 395                 case 2:
 396                         div1 = 7;
 397                         break;
 398                 default:
 399                 case 3:
 400                         div1 = 10;
 401                         break;
 402                 }
 403                 div2 = (rate / div1 + hz - 1) / hz;
 404                 if (div2 <= 8)
 405                         break;
 406         }
 407         if (div1_idx == 4) {
 408                 pr_debug("%s: lowest clock %ld, need %d\n",
 409                         dev_name(&spi->dev), rate / 10 / 8, hz);
 410                 status = -EDOM;
 411                 goto done;
 412         }
 413
 414         /* we have to cache this and reset in uwire_chipselect as this is a
 415          * global parameter and another uwire device can change it under
 416          * us */
 417         ust->div1_idx = div1_idx;
 418         uwire_set_clk1_div(div1_idx);
 419
 420         rate /= div1;
 421
 422         switch (div2) {
 423         case 0:
 424         case 1:
 425         case 2:
 426                 flags |= UWIRE_FREQ_DIV_2;
 427                 rate /= 2;
 428                 break;
 429         case 3:
 430         case 4:
 431                 flags |= UWIRE_FREQ_DIV_4;
 432                 rate /= 4;
 433                 break;
 434         case 5:
 435         case 6:
 436         case 7:
 437         case 8:
 438                 flags |= UWIRE_FREQ_DIV_8;
 439                 rate /= 8;
 440                 break;
 441         }
 442         omap_uwire_configure_mode(spi->chip_select, flags);
 443         pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
 444                         __func__, flags,
 445                         clk_get_rate(uwire->ck) / 1000,
 446                         rate / 1000);
 447         status = 0;
 448 done:
 449         return status;
 450 }
 451
 452 static int uwire_setup(struct spi_device *spi)
 453 {
 454         struct uwire_state *ust = spi->controller_state;
 455
 456         if (ust == NULL) {
 457                 ust = kzalloc(sizeof(*ust), GFP_KERNEL);
 458                 if (ust == NULL)
 459                         return -ENOMEM;
 460                 spi->controller_state = ust;
 461         }
 462
 463         return uwire_setup_transfer(spi, NULL);
 464 }
 465
 466 static void uwire_cleanup(struct spi_device *spi)
 467 {
 468         kfree(spi->controller_state);
 469 }
 470
 471 static void uwire_off(struct uwire_spi *uwire)
 472 {
 473         uwire_write_reg(UWIRE_SR3, 0);
 474         clk_disable(uwire->ck);
 475         clk_put(uwire->ck);
 476         spi_master_put(uwire->bitbang.master);
 477 }
 478
 479 static int uwire_probe(struct platform_device *pdev)
 480 {
 481         struct spi_master       *master;
 482         struct uwire_spi        *uwire;
 483         int                     status;
 484
 485         master = spi_alloc_master(&pdev->dev, sizeof *uwire);
 486         if (!master)
 487                 return -ENODEV;
 488
 489         uwire = spi_master_get_devdata(master);
 490
 491         uwire_base = ioremap(UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
 492         if (!uwire_base) {
 493                 dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
 494                 spi_master_put(master);
 495                 return -ENOMEM;
 496         }
 497
 498         dev_set_drvdata(&pdev->dev, uwire);
 499
 500         uwire->ck = clk_get(&pdev->dev, "fck");
 501         if (IS_ERR(uwire->ck)) {
 502                 status = PTR_ERR(uwire->ck);
 503                 dev_dbg(&pdev->dev, "no functional clock?\n");
 504                 spi_master_put(master);
 505                 return status;
 506         }
 507         clk_enable(uwire->ck);
 508
 509         if (cpu_is_omap7xx())
 510                 uwire_idx_shift = 1;
 511         else
 512                 uwire_idx_shift = 2;
 513
 514         uwire_write_reg(UWIRE_SR3, 1);
 515
 516         /* the spi->mode bits understood by this driver: */
 517         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 518
 519         master->flags = SPI_MASTER_HALF_DUPLEX;
 520
 521         master->bus_num = 2;    /* "official" */
 522         master->num_chipselect = 4;
 523         master->setup = uwire_setup;
 524         master->cleanup = uwire_cleanup;
 525
 526         uwire->bitbang.master = master;
 527         uwire->bitbang.chipselect = uwire_chipselect;
 528         uwire->bitbang.setup_transfer = uwire_setup_transfer;
 529         uwire->bitbang.txrx_bufs = uwire_txrx;
 530
 531         status = spi_bitbang_start(&uwire->bitbang);
 532         if (status < 0) {
 533                 uwire_off(uwire);
 534                 iounmap(uwire_base);
 535         }
 536         return status;
 537 }
 538
 539 static int uwire_remove(struct platform_device *pdev)
 540 {
 541         struct uwire_spi        *uwire = dev_get_drvdata(&pdev->dev);
 542         int                     status;
 543
 544         // FIXME remove all child devices, somewhere ...
 545
 546         status = spi_bitbang_stop(&uwire->bitbang);
 547         uwire_off(uwire);
 548         iounmap(uwire_base);
 549         return status;
 550 }
 551
 552 /* work with hotplug and coldplug */
 553 MODULE_ALIAS("platform:omap_uwire");
 554
 555 static struct platform_driver uwire_driver = {
 556         .driver = {
 557                 .name           = "omap_uwire",
 558                 .owner          = THIS_MODULE,
 559         },
 560         .remove         = uwire_remove,
 561         // suspend ... unuse ck
 562         // resume ... use ck
 563 };
 564
 565 static int __init omap_uwire_init(void)
 566 {
 567         /* FIXME move these into the relevant board init code. also, include
 568          * H3 support; it uses tsc2101 like H2 (on a different chipselect).
 569          */
 570
 571         if (machine_is_omap_h2()) {
 572                 /* defaults: W21 SDO, U18 SDI, V19 SCL */
 573                 omap_cfg_reg(N14_1610_UWIRE_CS0);
 574                 omap_cfg_reg(N15_1610_UWIRE_CS1);
 575         }
 576         if (machine_is_omap_perseus2()) {
 577                 /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
 578                 int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
 579                 omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
 580         }
 581
 582         return platform_driver_probe(&uwire_driver, uwire_probe);
 583 }
 584
 585 static void __exit omap_uwire_exit(void)
 586 {
 587         platform_driver_unregister(&uwire_driver);
 588 }
 589
 590 subsys_initcall(omap_uwire_init);
 591 module_exit(omap_uwire_exit);
 592
 593 MODULE_LICENSE("GPL");
 594