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Merge tag 'v3.10.103' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / spi / spi-davinci.c
1 /*
2 * Copyright (C) 2009 Texas Instruments.
3 * Copyright (C) 2010 EF Johnson Technologies
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/interrupt.h>
21 #include <linux/io.h>
22 #include <linux/gpio.h>
23 #include <linux/module.h>
24 #include <linux/delay.h>
25 #include <linux/platform_device.h>
26 #include <linux/err.h>
27 #include <linux/clk.h>
28 #include <linux/dmaengine.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/edma.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/spi/spi.h>
34 #include <linux/spi/spi_bitbang.h>
35 #include <linux/slab.h>
36
37 #include <linux/platform_data/spi-davinci.h>
38
39 #define SPI_NO_RESOURCE ((resource_size_t)-1)
40
41 #define SPI_MAX_CHIPSELECT 2
42
43 #define CS_DEFAULT 0xFF
44
45 #define SPIFMT_PHASE_MASK BIT(16)
46 #define SPIFMT_POLARITY_MASK BIT(17)
47 #define SPIFMT_DISTIMER_MASK BIT(18)
48 #define SPIFMT_SHIFTDIR_MASK BIT(20)
49 #define SPIFMT_WAITENA_MASK BIT(21)
50 #define SPIFMT_PARITYENA_MASK BIT(22)
51 #define SPIFMT_ODD_PARITY_MASK BIT(23)
52 #define SPIFMT_WDELAY_MASK 0x3f000000u
53 #define SPIFMT_WDELAY_SHIFT 24
54 #define SPIFMT_PRESCALE_SHIFT 8
55
56 /* SPIPC0 */
57 #define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
58 #define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
59 #define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
60 #define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
61
62 #define SPIINT_MASKALL 0x0101035F
63 #define SPIINT_MASKINT 0x0000015F
64 #define SPI_INTLVL_1 0x000001FF
65 #define SPI_INTLVL_0 0x00000000
66
67 /* SPIDAT1 (upper 16 bit defines) */
68 #define SPIDAT1_CSHOLD_MASK BIT(12)
69
70 /* SPIGCR1 */
71 #define SPIGCR1_CLKMOD_MASK BIT(1)
72 #define SPIGCR1_MASTER_MASK BIT(0)
73 #define SPIGCR1_POWERDOWN_MASK BIT(8)
74 #define SPIGCR1_LOOPBACK_MASK BIT(16)
75 #define SPIGCR1_SPIENA_MASK BIT(24)
76
77 /* SPIBUF */
78 #define SPIBUF_TXFULL_MASK BIT(29)
79 #define SPIBUF_RXEMPTY_MASK BIT(31)
80
81 /* SPIDELAY */
82 #define SPIDELAY_C2TDELAY_SHIFT 24
83 #define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
84 #define SPIDELAY_T2CDELAY_SHIFT 16
85 #define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
86 #define SPIDELAY_T2EDELAY_SHIFT 8
87 #define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
88 #define SPIDELAY_C2EDELAY_SHIFT 0
89 #define SPIDELAY_C2EDELAY_MASK 0xFF
90
91 /* Error Masks */
92 #define SPIFLG_DLEN_ERR_MASK BIT(0)
93 #define SPIFLG_TIMEOUT_MASK BIT(1)
94 #define SPIFLG_PARERR_MASK BIT(2)
95 #define SPIFLG_DESYNC_MASK BIT(3)
96 #define SPIFLG_BITERR_MASK BIT(4)
97 #define SPIFLG_OVRRUN_MASK BIT(6)
98 #define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
99 #define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
100 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
101 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
102 | SPIFLG_OVRRUN_MASK)
103
104 #define SPIINT_DMA_REQ_EN BIT(16)
105
106 /* SPI Controller registers */
107 #define SPIGCR0 0x00
108 #define SPIGCR1 0x04
109 #define SPIINT 0x08
110 #define SPILVL 0x0c
111 #define SPIFLG 0x10
112 #define SPIPC0 0x14
113 #define SPIDAT1 0x3c
114 #define SPIBUF 0x40
115 #define SPIDELAY 0x48
116 #define SPIDEF 0x4c
117 #define SPIFMT0 0x50
118
119 /* SPI Controller driver's private data. */
120 struct davinci_spi {
121 struct spi_bitbang bitbang;
122 struct clk *clk;
123
124 u8 version;
125 resource_size_t pbase;
126 void __iomem *base;
127 u32 irq;
128 struct completion done;
129
130 const void *tx;
131 void *rx;
132 int rcount;
133 int wcount;
134
135 struct dma_chan *dma_rx;
136 struct dma_chan *dma_tx;
137 int dma_rx_chnum;
138 int dma_tx_chnum;
139
140 struct davinci_spi_platform_data pdata;
141
142 void (*get_rx)(u32 rx_data, struct davinci_spi *);
143 u32 (*get_tx)(struct davinci_spi *);
144
145 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
146 };
147
148 static struct davinci_spi_config davinci_spi_default_cfg;
149
150 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
151 {
152 if (dspi->rx) {
153 u8 *rx = dspi->rx;
154 *rx++ = (u8)data;
155 dspi->rx = rx;
156 }
157 }
158
159 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
160 {
161 if (dspi->rx) {
162 u16 *rx = dspi->rx;
163 *rx++ = (u16)data;
164 dspi->rx = rx;
165 }
166 }
167
168 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
169 {
170 u32 data = 0;
171 if (dspi->tx) {
172 const u8 *tx = dspi->tx;
173 data = *tx++;
174 dspi->tx = tx;
175 }
176 return data;
177 }
178
179 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
180 {
181 u32 data = 0;
182 if (dspi->tx) {
183 const u16 *tx = dspi->tx;
184 data = *tx++;
185 dspi->tx = tx;
186 }
187 return data;
188 }
189
190 static inline void set_io_bits(void __iomem *addr, u32 bits)
191 {
192 u32 v = ioread32(addr);
193
194 v |= bits;
195 iowrite32(v, addr);
196 }
197
198 static inline void clear_io_bits(void __iomem *addr, u32 bits)
199 {
200 u32 v = ioread32(addr);
201
202 v &= ~bits;
203 iowrite32(v, addr);
204 }
205
206 /*
207 * Interface to control the chip select signal
208 */
209 static void davinci_spi_chipselect(struct spi_device *spi, int value)
210 {
211 struct davinci_spi *dspi;
212 struct davinci_spi_platform_data *pdata;
213 u8 chip_sel = spi->chip_select;
214 u16 spidat1 = CS_DEFAULT;
215 bool gpio_chipsel = false;
216
217 dspi = spi_master_get_devdata(spi->master);
218 pdata = &dspi->pdata;
219
220 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
221 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
222 gpio_chipsel = true;
223
224 /*
225 * Board specific chip select logic decides the polarity and cs
226 * line for the controller
227 */
228 if (gpio_chipsel) {
229 if (value == BITBANG_CS_ACTIVE)
230 gpio_set_value(pdata->chip_sel[chip_sel], 0);
231 else
232 gpio_set_value(pdata->chip_sel[chip_sel], 1);
233 } else {
234 if (value == BITBANG_CS_ACTIVE) {
235 spidat1 |= SPIDAT1_CSHOLD_MASK;
236 spidat1 &= ~(0x1 << chip_sel);
237 }
238
239 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
240 }
241 }
242
243 /**
244 * davinci_spi_get_prescale - Calculates the correct prescale value
245 * @maxspeed_hz: the maximum rate the SPI clock can run at
246 *
247 * This function calculates the prescale value that generates a clock rate
248 * less than or equal to the specified maximum.
249 *
250 * Returns: calculated prescale - 1 for easy programming into SPI registers
251 * or negative error number if valid prescalar cannot be updated.
252 */
253 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
254 u32 max_speed_hz)
255 {
256 int ret;
257
258 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
259
260 if (ret < 3 || ret > 256)
261 return -EINVAL;
262
263 return ret - 1;
264 }
265
266 /**
267 * davinci_spi_setup_transfer - This functions will determine transfer method
268 * @spi: spi device on which data transfer to be done
269 * @t: spi transfer in which transfer info is filled
270 *
271 * This function determines data transfer method (8/16/32 bit transfer).
272 * It will also set the SPI Clock Control register according to
273 * SPI slave device freq.
274 */
275 static int davinci_spi_setup_transfer(struct spi_device *spi,
276 struct spi_transfer *t)
277 {
278
279 struct davinci_spi *dspi;
280 struct davinci_spi_config *spicfg;
281 u8 bits_per_word = 0;
282 u32 hz = 0, spifmt = 0, prescale = 0;
283
284 dspi = spi_master_get_devdata(spi->master);
285 spicfg = (struct davinci_spi_config *)spi->controller_data;
286 if (!spicfg)
287 spicfg = &davinci_spi_default_cfg;
288
289 if (t) {
290 bits_per_word = t->bits_per_word;
291 hz = t->speed_hz;
292 }
293
294 /* if bits_per_word is not set then set it default */
295 if (!bits_per_word)
296 bits_per_word = spi->bits_per_word;
297
298 /*
299 * Assign function pointer to appropriate transfer method
300 * 8bit, 16bit or 32bit transfer
301 */
302 if (bits_per_word <= 8 && bits_per_word >= 2) {
303 dspi->get_rx = davinci_spi_rx_buf_u8;
304 dspi->get_tx = davinci_spi_tx_buf_u8;
305 dspi->bytes_per_word[spi->chip_select] = 1;
306 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
307 dspi->get_rx = davinci_spi_rx_buf_u16;
308 dspi->get_tx = davinci_spi_tx_buf_u16;
309 dspi->bytes_per_word[spi->chip_select] = 2;
310 } else
311 return -EINVAL;
312
313 if (!hz)
314 hz = spi->max_speed_hz;
315
316 /* Set up SPIFMTn register, unique to this chipselect. */
317
318 prescale = davinci_spi_get_prescale(dspi, hz);
319 if (prescale < 0)
320 return prescale;
321
322 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
323
324 if (spi->mode & SPI_LSB_FIRST)
325 spifmt |= SPIFMT_SHIFTDIR_MASK;
326
327 if (spi->mode & SPI_CPOL)
328 spifmt |= SPIFMT_POLARITY_MASK;
329
330 if (!(spi->mode & SPI_CPHA))
331 spifmt |= SPIFMT_PHASE_MASK;
332
333 /*
334 * Version 1 hardware supports two basic SPI modes:
335 * - Standard SPI mode uses 4 pins, with chipselect
336 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
337 * (distinct from SPI_3WIRE, with just one data wire;
338 * or similar variants without MOSI or without MISO)
339 *
340 * Version 2 hardware supports an optional handshaking signal,
341 * so it can support two more modes:
342 * - 5 pin SPI variant is standard SPI plus SPI_READY
343 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
344 */
345
346 if (dspi->version == SPI_VERSION_2) {
347
348 u32 delay = 0;
349
350 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
351 & SPIFMT_WDELAY_MASK);
352
353 if (spicfg->odd_parity)
354 spifmt |= SPIFMT_ODD_PARITY_MASK;
355
356 if (spicfg->parity_enable)
357 spifmt |= SPIFMT_PARITYENA_MASK;
358
359 if (spicfg->timer_disable) {
360 spifmt |= SPIFMT_DISTIMER_MASK;
361 } else {
362 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
363 & SPIDELAY_C2TDELAY_MASK;
364 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
365 & SPIDELAY_T2CDELAY_MASK;
366 }
367
368 if (spi->mode & SPI_READY) {
369 spifmt |= SPIFMT_WAITENA_MASK;
370 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
371 & SPIDELAY_T2EDELAY_MASK;
372 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
373 & SPIDELAY_C2EDELAY_MASK;
374 }
375
376 iowrite32(delay, dspi->base + SPIDELAY);
377 }
378
379 iowrite32(spifmt, dspi->base + SPIFMT0);
380
381 return 0;
382 }
383
384 /**
385 * davinci_spi_setup - This functions will set default transfer method
386 * @spi: spi device on which data transfer to be done
387 *
388 * This functions sets the default transfer method.
389 */
390 static int davinci_spi_setup(struct spi_device *spi)
391 {
392 int retval = 0;
393 struct davinci_spi *dspi;
394 struct davinci_spi_platform_data *pdata;
395
396 dspi = spi_master_get_devdata(spi->master);
397 pdata = &dspi->pdata;
398
399 /* if bits per word length is zero then set it default 8 */
400 if (!spi->bits_per_word)
401 spi->bits_per_word = 8;
402
403 if (!(spi->mode & SPI_NO_CS)) {
404 if ((pdata->chip_sel == NULL) ||
405 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
406 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
407
408 }
409
410 if (spi->mode & SPI_READY)
411 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
412
413 if (spi->mode & SPI_LOOP)
414 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
415 else
416 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
417
418 return retval;
419 }
420
421 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
422 {
423 struct device *sdev = dspi->bitbang.master->dev.parent;
424
425 if (int_status & SPIFLG_TIMEOUT_MASK) {
426 dev_dbg(sdev, "SPI Time-out Error\n");
427 return -ETIMEDOUT;
428 }
429 if (int_status & SPIFLG_DESYNC_MASK) {
430 dev_dbg(sdev, "SPI Desynchronization Error\n");
431 return -EIO;
432 }
433 if (int_status & SPIFLG_BITERR_MASK) {
434 dev_dbg(sdev, "SPI Bit error\n");
435 return -EIO;
436 }
437
438 if (dspi->version == SPI_VERSION_2) {
439 if (int_status & SPIFLG_DLEN_ERR_MASK) {
440 dev_dbg(sdev, "SPI Data Length Error\n");
441 return -EIO;
442 }
443 if (int_status & SPIFLG_PARERR_MASK) {
444 dev_dbg(sdev, "SPI Parity Error\n");
445 return -EIO;
446 }
447 if (int_status & SPIFLG_OVRRUN_MASK) {
448 dev_dbg(sdev, "SPI Data Overrun error\n");
449 return -EIO;
450 }
451 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
452 dev_dbg(sdev, "SPI Buffer Init Active\n");
453 return -EBUSY;
454 }
455 }
456
457 return 0;
458 }
459
460 /**
461 * davinci_spi_process_events - check for and handle any SPI controller events
462 * @dspi: the controller data
463 *
464 * This function will check the SPIFLG register and handle any events that are
465 * detected there
466 */
467 static int davinci_spi_process_events(struct davinci_spi *dspi)
468 {
469 u32 buf, status, errors = 0, spidat1;
470
471 buf = ioread32(dspi->base + SPIBUF);
472
473 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
474 dspi->get_rx(buf & 0xFFFF, dspi);
475 dspi->rcount--;
476 }
477
478 status = ioread32(dspi->base + SPIFLG);
479
480 if (unlikely(status & SPIFLG_ERROR_MASK)) {
481 errors = status & SPIFLG_ERROR_MASK;
482 goto out;
483 }
484
485 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
486 spidat1 = ioread32(dspi->base + SPIDAT1);
487 dspi->wcount--;
488 spidat1 &= ~0xFFFF;
489 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
490 iowrite32(spidat1, dspi->base + SPIDAT1);
491 }
492
493 out:
494 return errors;
495 }
496
497 static void davinci_spi_dma_rx_callback(void *data)
498 {
499 struct davinci_spi *dspi = (struct davinci_spi *)data;
500
501 dspi->rcount = 0;
502
503 if (!dspi->wcount && !dspi->rcount)
504 complete(&dspi->done);
505 }
506
507 static void davinci_spi_dma_tx_callback(void *data)
508 {
509 struct davinci_spi *dspi = (struct davinci_spi *)data;
510
511 dspi->wcount = 0;
512
513 if (!dspi->wcount && !dspi->rcount)
514 complete(&dspi->done);
515 }
516
517 /**
518 * davinci_spi_bufs - functions which will handle transfer data
519 * @spi: spi device on which data transfer to be done
520 * @t: spi transfer in which transfer info is filled
521 *
522 * This function will put data to be transferred into data register
523 * of SPI controller and then wait until the completion will be marked
524 * by the IRQ Handler.
525 */
526 static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
527 {
528 struct davinci_spi *dspi;
529 int data_type, ret = -ENOMEM;
530 u32 tx_data, spidat1;
531 u32 errors = 0;
532 struct davinci_spi_config *spicfg;
533 struct davinci_spi_platform_data *pdata;
534 unsigned uninitialized_var(rx_buf_count);
535 void *dummy_buf = NULL;
536 struct scatterlist sg_rx, sg_tx;
537
538 dspi = spi_master_get_devdata(spi->master);
539 pdata = &dspi->pdata;
540 spicfg = (struct davinci_spi_config *)spi->controller_data;
541 if (!spicfg)
542 spicfg = &davinci_spi_default_cfg;
543
544 /* convert len to words based on bits_per_word */
545 data_type = dspi->bytes_per_word[spi->chip_select];
546
547 dspi->tx = t->tx_buf;
548 dspi->rx = t->rx_buf;
549 dspi->wcount = t->len / data_type;
550 dspi->rcount = dspi->wcount;
551
552 spidat1 = ioread32(dspi->base + SPIDAT1);
553
554 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
555 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
556
557 INIT_COMPLETION(dspi->done);
558
559 if (spicfg->io_type == SPI_IO_TYPE_INTR)
560 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
561
562 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
563 /* start the transfer */
564 dspi->wcount--;
565 tx_data = dspi->get_tx(dspi);
566 spidat1 &= 0xFFFF0000;
567 spidat1 |= tx_data & 0xFFFF;
568 iowrite32(spidat1, dspi->base + SPIDAT1);
569 } else {
570 struct dma_slave_config dma_rx_conf = {
571 .direction = DMA_DEV_TO_MEM,
572 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
573 .src_addr_width = data_type,
574 .src_maxburst = 1,
575 };
576 struct dma_slave_config dma_tx_conf = {
577 .direction = DMA_MEM_TO_DEV,
578 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
579 .dst_addr_width = data_type,
580 .dst_maxburst = 1,
581 };
582 struct dma_async_tx_descriptor *rxdesc;
583 struct dma_async_tx_descriptor *txdesc;
584 void *buf;
585
586 dummy_buf = kzalloc(t->len, GFP_KERNEL);
587 if (!dummy_buf)
588 goto err_alloc_dummy_buf;
589
590 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
591 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
592
593 sg_init_table(&sg_rx, 1);
594 if (!t->rx_buf)
595 buf = dummy_buf;
596 else
597 buf = t->rx_buf;
598 t->rx_dma = dma_map_single(&spi->dev, buf,
599 t->len, DMA_FROM_DEVICE);
600 if (!t->rx_dma) {
601 ret = -EFAULT;
602 goto err_rx_map;
603 }
604 sg_dma_address(&sg_rx) = t->rx_dma;
605 sg_dma_len(&sg_rx) = t->len;
606
607 sg_init_table(&sg_tx, 1);
608 if (!t->tx_buf)
609 buf = dummy_buf;
610 else
611 buf = (void *)t->tx_buf;
612 t->tx_dma = dma_map_single(&spi->dev, buf,
613 t->len, DMA_TO_DEVICE);
614 if (!t->tx_dma) {
615 ret = -EFAULT;
616 goto err_tx_map;
617 }
618 sg_dma_address(&sg_tx) = t->tx_dma;
619 sg_dma_len(&sg_tx) = t->len;
620
621 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
622 &sg_rx, 1, DMA_DEV_TO_MEM,
623 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
624 if (!rxdesc)
625 goto err_desc;
626
627 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
628 &sg_tx, 1, DMA_MEM_TO_DEV,
629 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
630 if (!txdesc)
631 goto err_desc;
632
633 rxdesc->callback = davinci_spi_dma_rx_callback;
634 rxdesc->callback_param = (void *)dspi;
635 txdesc->callback = davinci_spi_dma_tx_callback;
636 txdesc->callback_param = (void *)dspi;
637
638 if (pdata->cshold_bug)
639 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
640
641 dmaengine_submit(rxdesc);
642 dmaengine_submit(txdesc);
643
644 dma_async_issue_pending(dspi->dma_rx);
645 dma_async_issue_pending(dspi->dma_tx);
646
647 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
648 }
649
650 /* Wait for the transfer to complete */
651 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
652 wait_for_completion_interruptible(&(dspi->done));
653 } else {
654 while (dspi->rcount > 0 || dspi->wcount > 0) {
655 errors = davinci_spi_process_events(dspi);
656 if (errors)
657 break;
658 cpu_relax();
659 }
660 }
661
662 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
663 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
664 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
665
666 dma_unmap_single(&spi->dev, t->rx_dma,
667 t->len, DMA_FROM_DEVICE);
668 dma_unmap_single(&spi->dev, t->tx_dma,
669 t->len, DMA_TO_DEVICE);
670 kfree(dummy_buf);
671 }
672
673 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
674 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
675
676 /*
677 * Check for bit error, desync error,parity error,timeout error and
678 * receive overflow errors
679 */
680 if (errors) {
681 ret = davinci_spi_check_error(dspi, errors);
682 WARN(!ret, "%s: error reported but no error found!\n",
683 dev_name(&spi->dev));
684 return ret;
685 }
686
687 if (dspi->rcount != 0 || dspi->wcount != 0) {
688 dev_err(&spi->dev, "SPI data transfer error\n");
689 return -EIO;
690 }
691
692 return t->len;
693
694 err_desc:
695 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
696 err_tx_map:
697 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
698 err_rx_map:
699 kfree(dummy_buf);
700 err_alloc_dummy_buf:
701 return ret;
702 }
703
704 /**
705 * dummy_thread_fn - dummy thread function
706 * @irq: IRQ number for this SPI Master
707 * @context_data: structure for SPI Master controller davinci_spi
708 *
709 * This is to satisfy the request_threaded_irq() API so that the irq
710 * handler is called in interrupt context.
711 */
712 static irqreturn_t dummy_thread_fn(s32 irq, void *data)
713 {
714 return IRQ_HANDLED;
715 }
716
717 /**
718 * davinci_spi_irq - Interrupt handler for SPI Master Controller
719 * @irq: IRQ number for this SPI Master
720 * @context_data: structure for SPI Master controller davinci_spi
721 *
722 * ISR will determine that interrupt arrives either for READ or WRITE command.
723 * According to command it will do the appropriate action. It will check
724 * transfer length and if it is not zero then dispatch transfer command again.
725 * If transfer length is zero then it will indicate the COMPLETION so that
726 * davinci_spi_bufs function can go ahead.
727 */
728 static irqreturn_t davinci_spi_irq(s32 irq, void *data)
729 {
730 struct davinci_spi *dspi = data;
731 int status;
732
733 status = davinci_spi_process_events(dspi);
734 if (unlikely(status != 0))
735 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
736
737 if ((!dspi->rcount && !dspi->wcount) || status)
738 complete(&dspi->done);
739
740 return IRQ_HANDLED;
741 }
742
743 static int davinci_spi_request_dma(struct davinci_spi *dspi)
744 {
745 dma_cap_mask_t mask;
746 struct device *sdev = dspi->bitbang.master->dev.parent;
747 int r;
748
749 dma_cap_zero(mask);
750 dma_cap_set(DMA_SLAVE, mask);
751
752 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
753 &dspi->dma_rx_chnum);
754 if (!dspi->dma_rx) {
755 dev_err(sdev, "request RX DMA channel failed\n");
756 r = -ENODEV;
757 goto rx_dma_failed;
758 }
759
760 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
761 &dspi->dma_tx_chnum);
762 if (!dspi->dma_tx) {
763 dev_err(sdev, "request TX DMA channel failed\n");
764 r = -ENODEV;
765 goto tx_dma_failed;
766 }
767
768 return 0;
769
770 tx_dma_failed:
771 dma_release_channel(dspi->dma_rx);
772 rx_dma_failed:
773 return r;
774 }
775
776 #if defined(CONFIG_OF)
777 static const struct of_device_id davinci_spi_of_match[] = {
778 {
779 .compatible = "ti,dm6441-spi",
780 },
781 {
782 .compatible = "ti,da830-spi",
783 .data = (void *)SPI_VERSION_2,
784 },
785 { },
786 };
787 MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
788
789 /**
790 * spi_davinci_get_pdata - Get platform data from DTS binding
791 * @pdev: ptr to platform data
792 * @dspi: ptr to driver data
793 *
794 * Parses and populates pdata in dspi from device tree bindings.
795 *
796 * NOTE: Not all platform data params are supported currently.
797 */
798 static int spi_davinci_get_pdata(struct platform_device *pdev,
799 struct davinci_spi *dspi)
800 {
801 struct device_node *node = pdev->dev.of_node;
802 struct davinci_spi_platform_data *pdata;
803 unsigned int num_cs, intr_line = 0;
804 const struct of_device_id *match;
805
806 pdata = &dspi->pdata;
807
808 pdata->version = SPI_VERSION_1;
809 match = of_match_device(of_match_ptr(davinci_spi_of_match),
810 &pdev->dev);
811 if (!match)
812 return -ENODEV;
813
814 /* match data has the SPI version number for SPI_VERSION_2 */
815 if (match->data == (void *)SPI_VERSION_2)
816 pdata->version = SPI_VERSION_2;
817
818 /*
819 * default num_cs is 1 and all chipsel are internal to the chip
820 * indicated by chip_sel being NULL. GPIO based CS is not
821 * supported yet in DT bindings.
822 */
823 num_cs = 1;
824 of_property_read_u32(node, "num-cs", &num_cs);
825 pdata->num_chipselect = num_cs;
826 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
827 pdata->intr_line = intr_line;
828 return 0;
829 }
830 #else
831 #define davinci_spi_of_match NULL
832 static struct davinci_spi_platform_data
833 *spi_davinci_get_pdata(struct platform_device *pdev,
834 struct davinci_spi *dspi)
835 {
836 return -ENODEV;
837 }
838 #endif
839
840 /**
841 * davinci_spi_probe - probe function for SPI Master Controller
842 * @pdev: platform_device structure which contains plateform specific data
843 *
844 * According to Linux Device Model this function will be invoked by Linux
845 * with platform_device struct which contains the device specific info.
846 * This function will map the SPI controller's memory, register IRQ,
847 * Reset SPI controller and setting its registers to default value.
848 * It will invoke spi_bitbang_start to create work queue so that client driver
849 * can register transfer method to work queue.
850 */
851 static int davinci_spi_probe(struct platform_device *pdev)
852 {
853 struct spi_master *master;
854 struct davinci_spi *dspi;
855 struct davinci_spi_platform_data *pdata;
856 struct resource *r, *mem;
857 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
858 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
859 int i = 0, ret = 0;
860 u32 spipc0;
861
862 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
863 if (master == NULL) {
864 ret = -ENOMEM;
865 goto err;
866 }
867
868 dev_set_drvdata(&pdev->dev, master);
869
870 dspi = spi_master_get_devdata(master);
871 if (dspi == NULL) {
872 ret = -ENOENT;
873 goto free_master;
874 }
875
876 if (pdev->dev.platform_data) {
877 pdata = pdev->dev.platform_data;
878 dspi->pdata = *pdata;
879 } else {
880 /* update dspi pdata with that from the DT */
881 ret = spi_davinci_get_pdata(pdev, dspi);
882 if (ret < 0)
883 goto free_master;
884 }
885
886 /* pdata in dspi is now updated and point pdata to that */
887 pdata = &dspi->pdata;
888
889 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
890 if (r == NULL) {
891 ret = -ENOENT;
892 goto free_master;
893 }
894
895 dspi->pbase = r->start;
896
897 mem = request_mem_region(r->start, resource_size(r), pdev->name);
898 if (mem == NULL) {
899 ret = -EBUSY;
900 goto free_master;
901 }
902
903 dspi->base = ioremap(r->start, resource_size(r));
904 if (dspi->base == NULL) {
905 ret = -ENOMEM;
906 goto release_region;
907 }
908
909 dspi->irq = platform_get_irq(pdev, 0);
910 if (dspi->irq <= 0) {
911 ret = -EINVAL;
912 goto unmap_io;
913 }
914
915 ret = request_threaded_irq(dspi->irq, davinci_spi_irq, dummy_thread_fn,
916 0, dev_name(&pdev->dev), dspi);
917 if (ret)
918 goto unmap_io;
919
920 dspi->bitbang.master = spi_master_get(master);
921 if (dspi->bitbang.master == NULL) {
922 ret = -ENODEV;
923 goto irq_free;
924 }
925
926 dspi->clk = clk_get(&pdev->dev, NULL);
927 if (IS_ERR(dspi->clk)) {
928 ret = -ENODEV;
929 goto put_master;
930 }
931 clk_prepare_enable(dspi->clk);
932
933 master->dev.of_node = pdev->dev.of_node;
934 master->bus_num = pdev->id;
935 master->num_chipselect = pdata->num_chipselect;
936 master->setup = davinci_spi_setup;
937
938 dspi->bitbang.chipselect = davinci_spi_chipselect;
939 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
940
941 dspi->version = pdata->version;
942
943 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
944 if (dspi->version == SPI_VERSION_2)
945 dspi->bitbang.flags |= SPI_READY;
946
947 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
948 if (r)
949 dma_rx_chan = r->start;
950 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
951 if (r)
952 dma_tx_chan = r->start;
953
954 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
955 if (dma_rx_chan != SPI_NO_RESOURCE &&
956 dma_tx_chan != SPI_NO_RESOURCE) {
957 dspi->dma_rx_chnum = dma_rx_chan;
958 dspi->dma_tx_chnum = dma_tx_chan;
959
960 ret = davinci_spi_request_dma(dspi);
961 if (ret)
962 goto free_clk;
963
964 dev_info(&pdev->dev, "DMA: supported\n");
965 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
966 "event queue: %d\n", dma_rx_chan, dma_tx_chan,
967 pdata->dma_event_q);
968 }
969
970 dspi->get_rx = davinci_spi_rx_buf_u8;
971 dspi->get_tx = davinci_spi_tx_buf_u8;
972
973 init_completion(&dspi->done);
974
975 /* Reset In/OUT SPI module */
976 iowrite32(0, dspi->base + SPIGCR0);
977 udelay(100);
978 iowrite32(1, dspi->base + SPIGCR0);
979
980 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
981 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
982 iowrite32(spipc0, dspi->base + SPIPC0);
983
984 /* initialize chip selects */
985 if (pdata->chip_sel) {
986 for (i = 0; i < pdata->num_chipselect; i++) {
987 if (pdata->chip_sel[i] != SPI_INTERN_CS)
988 gpio_direction_output(pdata->chip_sel[i], 1);
989 }
990 }
991
992 if (pdata->intr_line)
993 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
994 else
995 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
996
997 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
998
999 /* master mode default */
1000 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1001 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1002 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
1003
1004 ret = spi_bitbang_start(&dspi->bitbang);
1005 if (ret)
1006 goto free_dma;
1007
1008 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
1009
1010 return ret;
1011
1012 free_dma:
1013 dma_release_channel(dspi->dma_rx);
1014 dma_release_channel(dspi->dma_tx);
1015 free_clk:
1016 clk_disable_unprepare(dspi->clk);
1017 clk_put(dspi->clk);
1018 put_master:
1019 spi_master_put(master);
1020 irq_free:
1021 free_irq(dspi->irq, dspi);
1022 unmap_io:
1023 iounmap(dspi->base);
1024 release_region:
1025 release_mem_region(dspi->pbase, resource_size(r));
1026 free_master:
1027 kfree(master);
1028 err:
1029 return ret;
1030 }
1031
1032 /**
1033 * davinci_spi_remove - remove function for SPI Master Controller
1034 * @pdev: platform_device structure which contains plateform specific data
1035 *
1036 * This function will do the reverse action of davinci_spi_probe function
1037 * It will free the IRQ and SPI controller's memory region.
1038 * It will also call spi_bitbang_stop to destroy the work queue which was
1039 * created by spi_bitbang_start.
1040 */
1041 static int davinci_spi_remove(struct platform_device *pdev)
1042 {
1043 struct davinci_spi *dspi;
1044 struct spi_master *master;
1045 struct resource *r;
1046
1047 master = dev_get_drvdata(&pdev->dev);
1048 dspi = spi_master_get_devdata(master);
1049
1050 spi_bitbang_stop(&dspi->bitbang);
1051
1052 clk_disable_unprepare(dspi->clk);
1053 clk_put(dspi->clk);
1054 spi_master_put(master);
1055 free_irq(dspi->irq, dspi);
1056 iounmap(dspi->base);
1057 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1058 release_mem_region(dspi->pbase, resource_size(r));
1059
1060 return 0;
1061 }
1062
1063 static struct platform_driver davinci_spi_driver = {
1064 .driver = {
1065 .name = "spi_davinci",
1066 .owner = THIS_MODULE,
1067 .of_match_table = davinci_spi_of_match,
1068 },
1069 .probe = davinci_spi_probe,
1070 .remove = davinci_spi_remove,
1071 };
1072 module_platform_driver(davinci_spi_driver);
1073
1074 MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1075 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)