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[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / scsi / stex.c
1 /*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
4 * Copyright (C) 2005-2009 Promise Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
14 */
15
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/kernel.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
21 #include <linux/time.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/interrupt.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/spinlock.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30 #include <asm/byteorder.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_device.h>
33 #include <scsi/scsi_cmnd.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_tcq.h>
36 #include <scsi/scsi_dbg.h>
37 #include <scsi/scsi_eh.h>
38
39 #define DRV_NAME "stex"
40 #define ST_DRIVER_VERSION "4.6.0000.4"
41 #define ST_VER_MAJOR 4
42 #define ST_VER_MINOR 6
43 #define ST_OEM 0
44 #define ST_BUILD_VER 4
45
46 enum {
47 /* MU register offset */
48 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
49 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
50 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
51 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
52 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
53 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
54 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
55 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
56 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
57 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
58
59 YIOA_STATUS = 0x00,
60 YH2I_INT = 0x20,
61 YINT_EN = 0x34,
62 YI2H_INT = 0x9c,
63 YI2H_INT_C = 0xa0,
64 YH2I_REQ = 0xc0,
65 YH2I_REQ_HI = 0xc4,
66
67 /* MU register value */
68 MU_INBOUND_DOORBELL_HANDSHAKE = (1 << 0),
69 MU_INBOUND_DOORBELL_REQHEADCHANGED = (1 << 1),
70 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = (1 << 2),
71 MU_INBOUND_DOORBELL_HMUSTOPPED = (1 << 3),
72 MU_INBOUND_DOORBELL_RESET = (1 << 4),
73
74 MU_OUTBOUND_DOORBELL_HANDSHAKE = (1 << 0),
75 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
76 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = (1 << 2),
77 MU_OUTBOUND_DOORBELL_BUSCHANGE = (1 << 3),
78 MU_OUTBOUND_DOORBELL_HASEVENT = (1 << 4),
79 MU_OUTBOUND_DOORBELL_REQUEST_RESET = (1 << 27),
80
81 /* MU status code */
82 MU_STATE_STARTING = 1,
83 MU_STATE_STARTED = 2,
84 MU_STATE_RESETTING = 3,
85 MU_STATE_FAILED = 4,
86
87 MU_MAX_DELAY = 120,
88 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
89 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
90 MU_HARD_RESET_WAIT = 30000,
91 HMU_PARTNER_TYPE = 2,
92
93 /* firmware returned values */
94 SRB_STATUS_SUCCESS = 0x01,
95 SRB_STATUS_ERROR = 0x04,
96 SRB_STATUS_BUSY = 0x05,
97 SRB_STATUS_INVALID_REQUEST = 0x06,
98 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
99 SRB_SEE_SENSE = 0x80,
100
101 /* task attribute */
102 TASK_ATTRIBUTE_SIMPLE = 0x0,
103 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
104 TASK_ATTRIBUTE_ORDERED = 0x2,
105 TASK_ATTRIBUTE_ACA = 0x4,
106
107 SS_STS_NORMAL = 0x80000000,
108 SS_STS_DONE = 0x40000000,
109 SS_STS_HANDSHAKE = 0x20000000,
110
111 SS_HEAD_HANDSHAKE = 0x80,
112
113 SS_H2I_INT_RESET = 0x100,
114
115 SS_I2H_REQUEST_RESET = 0x2000,
116
117 SS_MU_OPERATIONAL = 0x80000000,
118
119 STEX_CDB_LENGTH = 16,
120 STATUS_VAR_LEN = 128,
121
122 /* sg flags */
123 SG_CF_EOT = 0x80, /* end of table */
124 SG_CF_64B = 0x40, /* 64 bit item */
125 SG_CF_HOST = 0x20, /* sg in host memory */
126 MSG_DATA_DIR_ND = 0,
127 MSG_DATA_DIR_IN = 1,
128 MSG_DATA_DIR_OUT = 2,
129
130 st_shasta = 0,
131 st_vsc = 1,
132 st_yosemite = 2,
133 st_seq = 3,
134 st_yel = 4,
135
136 PASSTHRU_REQ_TYPE = 0x00000001,
137 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
138 ST_INTERNAL_TIMEOUT = 180,
139
140 ST_TO_CMD = 0,
141 ST_FROM_CMD = 1,
142
143 /* vendor specific commands of Promise */
144 MGT_CMD = 0xd8,
145 SINBAND_MGT_CMD = 0xd9,
146 ARRAY_CMD = 0xe0,
147 CONTROLLER_CMD = 0xe1,
148 DEBUGGING_CMD = 0xe2,
149 PASSTHRU_CMD = 0xe3,
150
151 PASSTHRU_GET_ADAPTER = 0x05,
152 PASSTHRU_GET_DRVVER = 0x10,
153
154 CTLR_CONFIG_CMD = 0x03,
155 CTLR_SHUTDOWN = 0x0d,
156
157 CTLR_POWER_STATE_CHANGE = 0x0e,
158 CTLR_POWER_SAVING = 0x01,
159
160 PASSTHRU_SIGNATURE = 0x4e415041,
161 MGT_CMD_SIGNATURE = 0xba,
162
163 INQUIRY_EVPD = 0x01,
164
165 ST_ADDITIONAL_MEM = 0x200000,
166 ST_ADDITIONAL_MEM_MIN = 0x80000,
167 };
168
169 struct st_sgitem {
170 u8 ctrl; /* SG_CF_xxx */
171 u8 reserved[3];
172 __le32 count;
173 __le64 addr;
174 };
175
176 struct st_ss_sgitem {
177 __le32 addr;
178 __le32 addr_hi;
179 __le32 count;
180 };
181
182 struct st_sgtable {
183 __le16 sg_count;
184 __le16 max_sg_count;
185 __le32 sz_in_byte;
186 };
187
188 struct st_msg_header {
189 __le64 handle;
190 u8 flag;
191 u8 channel;
192 __le16 timeout;
193 u32 reserved;
194 };
195
196 struct handshake_frame {
197 __le64 rb_phy; /* request payload queue physical address */
198 __le16 req_sz; /* size of each request payload */
199 __le16 req_cnt; /* count of reqs the buffer can hold */
200 __le16 status_sz; /* size of each status payload */
201 __le16 status_cnt; /* count of status the buffer can hold */
202 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
203 u8 partner_type; /* who sends this frame */
204 u8 reserved0[7];
205 __le32 partner_ver_major;
206 __le32 partner_ver_minor;
207 __le32 partner_ver_oem;
208 __le32 partner_ver_build;
209 __le32 extra_offset; /* NEW */
210 __le32 extra_size; /* NEW */
211 __le32 scratch_size;
212 u32 reserved1;
213 };
214
215 struct req_msg {
216 __le16 tag;
217 u8 lun;
218 u8 target;
219 u8 task_attr;
220 u8 task_manage;
221 u8 data_dir;
222 u8 payload_sz; /* payload size in 4-byte, not used */
223 u8 cdb[STEX_CDB_LENGTH];
224 u32 variable[0];
225 };
226
227 struct status_msg {
228 __le16 tag;
229 u8 lun;
230 u8 target;
231 u8 srb_status;
232 u8 scsi_status;
233 u8 reserved;
234 u8 payload_sz; /* payload size in 4-byte */
235 u8 variable[STATUS_VAR_LEN];
236 };
237
238 struct ver_info {
239 u32 major;
240 u32 minor;
241 u32 oem;
242 u32 build;
243 u32 reserved[2];
244 };
245
246 struct st_frame {
247 u32 base[6];
248 u32 rom_addr;
249
250 struct ver_info drv_ver;
251 struct ver_info bios_ver;
252
253 u32 bus;
254 u32 slot;
255 u32 irq_level;
256 u32 irq_vec;
257 u32 id;
258 u32 subid;
259
260 u32 dimm_size;
261 u8 dimm_type;
262 u8 reserved[3];
263
264 u32 channel;
265 u32 reserved1;
266 };
267
268 struct st_drvver {
269 u32 major;
270 u32 minor;
271 u32 oem;
272 u32 build;
273 u32 signature[2];
274 u8 console_id;
275 u8 host_no;
276 u8 reserved0[2];
277 u32 reserved[3];
278 };
279
280 struct st_ccb {
281 struct req_msg *req;
282 struct scsi_cmnd *cmd;
283
284 void *sense_buffer;
285 unsigned int sense_bufflen;
286 int sg_count;
287
288 u32 req_type;
289 u8 srb_status;
290 u8 scsi_status;
291 u8 reserved[2];
292 };
293
294 struct st_hba {
295 void __iomem *mmio_base; /* iomapped PCI memory space */
296 void *dma_mem;
297 dma_addr_t dma_handle;
298 size_t dma_size;
299
300 struct Scsi_Host *host;
301 struct pci_dev *pdev;
302
303 struct req_msg * (*alloc_rq) (struct st_hba *);
304 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
305 void (*send) (struct st_hba *, struct req_msg *, u16);
306
307 u32 req_head;
308 u32 req_tail;
309 u32 status_head;
310 u32 status_tail;
311
312 struct status_msg *status_buffer;
313 void *copy_buffer; /* temp buffer for driver-handled commands */
314 struct st_ccb *ccb;
315 struct st_ccb *wait_ccb;
316 __le32 *scratch;
317
318 char work_q_name[20];
319 struct workqueue_struct *work_q;
320 struct work_struct reset_work;
321 wait_queue_head_t reset_waitq;
322 unsigned int mu_status;
323 unsigned int cardtype;
324 int msi_enabled;
325 int out_req_cnt;
326 u32 extra_offset;
327 u16 rq_count;
328 u16 rq_size;
329 u16 sts_count;
330 };
331
332 struct st_card_info {
333 struct req_msg * (*alloc_rq) (struct st_hba *);
334 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
335 void (*send) (struct st_hba *, struct req_msg *, u16);
336 unsigned int max_id;
337 unsigned int max_lun;
338 unsigned int max_channel;
339 u16 rq_count;
340 u16 rq_size;
341 u16 sts_count;
342 };
343
344 static int msi;
345 module_param(msi, int, 0);
346 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
347
348 static const char console_inq_page[] =
349 {
350 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
351 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
352 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
353 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
354 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
355 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
356 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
357 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
358 };
359
360 MODULE_AUTHOR("Ed Lin");
361 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
362 MODULE_LICENSE("GPL");
363 MODULE_VERSION(ST_DRIVER_VERSION);
364
365 static void stex_gettime(__le64 *time)
366 {
367 struct timeval tv;
368
369 do_gettimeofday(&tv);
370 *time = cpu_to_le64(tv.tv_sec);
371 }
372
373 static struct status_msg *stex_get_status(struct st_hba *hba)
374 {
375 struct status_msg *status = hba->status_buffer + hba->status_tail;
376
377 ++hba->status_tail;
378 hba->status_tail %= hba->sts_count+1;
379
380 return status;
381 }
382
383 static void stex_invalid_field(struct scsi_cmnd *cmd,
384 void (*done)(struct scsi_cmnd *))
385 {
386 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
387
388 /* "Invalid field in cdb" */
389 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
390 0x0);
391 done(cmd);
392 }
393
394 static struct req_msg *stex_alloc_req(struct st_hba *hba)
395 {
396 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
397
398 ++hba->req_head;
399 hba->req_head %= hba->rq_count+1;
400
401 return req;
402 }
403
404 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
405 {
406 return (struct req_msg *)(hba->dma_mem +
407 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
408 }
409
410 static int stex_map_sg(struct st_hba *hba,
411 struct req_msg *req, struct st_ccb *ccb)
412 {
413 struct scsi_cmnd *cmd;
414 struct scatterlist *sg;
415 struct st_sgtable *dst;
416 struct st_sgitem *table;
417 int i, nseg;
418
419 cmd = ccb->cmd;
420 nseg = scsi_dma_map(cmd);
421 BUG_ON(nseg < 0);
422 if (nseg) {
423 dst = (struct st_sgtable *)req->variable;
424
425 ccb->sg_count = nseg;
426 dst->sg_count = cpu_to_le16((u16)nseg);
427 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
428 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
429
430 table = (struct st_sgitem *)(dst + 1);
431 scsi_for_each_sg(cmd, sg, nseg, i) {
432 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
433 table[i].addr = cpu_to_le64(sg_dma_address(sg));
434 table[i].ctrl = SG_CF_64B | SG_CF_HOST;
435 }
436 table[--i].ctrl |= SG_CF_EOT;
437 }
438
439 return nseg;
440 }
441
442 static int stex_ss_map_sg(struct st_hba *hba,
443 struct req_msg *req, struct st_ccb *ccb)
444 {
445 struct scsi_cmnd *cmd;
446 struct scatterlist *sg;
447 struct st_sgtable *dst;
448 struct st_ss_sgitem *table;
449 int i, nseg;
450
451 cmd = ccb->cmd;
452 nseg = scsi_dma_map(cmd);
453 BUG_ON(nseg < 0);
454 if (nseg) {
455 dst = (struct st_sgtable *)req->variable;
456
457 ccb->sg_count = nseg;
458 dst->sg_count = cpu_to_le16((u16)nseg);
459 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
460 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
461
462 table = (struct st_ss_sgitem *)(dst + 1);
463 scsi_for_each_sg(cmd, sg, nseg, i) {
464 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
465 table[i].addr =
466 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
467 table[i].addr_hi =
468 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
469 }
470 }
471
472 return nseg;
473 }
474
475 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
476 {
477 struct st_frame *p;
478 size_t count = sizeof(struct st_frame);
479
480 p = hba->copy_buffer;
481 scsi_sg_copy_to_buffer(ccb->cmd, p, count);
482 memset(p->base, 0, sizeof(u32)*6);
483 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
484 p->rom_addr = 0;
485
486 p->drv_ver.major = ST_VER_MAJOR;
487 p->drv_ver.minor = ST_VER_MINOR;
488 p->drv_ver.oem = ST_OEM;
489 p->drv_ver.build = ST_BUILD_VER;
490
491 p->bus = hba->pdev->bus->number;
492 p->slot = hba->pdev->devfn;
493 p->irq_level = 0;
494 p->irq_vec = hba->pdev->irq;
495 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
496 p->subid =
497 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
498
499 scsi_sg_copy_from_buffer(ccb->cmd, p, count);
500 }
501
502 static void
503 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
504 {
505 req->tag = cpu_to_le16(tag);
506
507 hba->ccb[tag].req = req;
508 hba->out_req_cnt++;
509
510 writel(hba->req_head, hba->mmio_base + IMR0);
511 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
512 readl(hba->mmio_base + IDBL); /* flush */
513 }
514
515 static void
516 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
517 {
518 struct scsi_cmnd *cmd;
519 struct st_msg_header *msg_h;
520 dma_addr_t addr;
521
522 req->tag = cpu_to_le16(tag);
523
524 hba->ccb[tag].req = req;
525 hba->out_req_cnt++;
526
527 cmd = hba->ccb[tag].cmd;
528 msg_h = (struct st_msg_header *)req - 1;
529 if (likely(cmd)) {
530 msg_h->channel = (u8)cmd->device->channel;
531 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
532 }
533 addr = hba->dma_handle + hba->req_head * hba->rq_size;
534 addr += (hba->ccb[tag].sg_count+4)/11;
535 msg_h->handle = cpu_to_le64(addr);
536
537 ++hba->req_head;
538 hba->req_head %= hba->rq_count+1;
539
540 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
541 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
542 writel(addr, hba->mmio_base + YH2I_REQ);
543 readl(hba->mmio_base + YH2I_REQ); /* flush */
544 }
545
546 static int
547 stex_slave_alloc(struct scsi_device *sdev)
548 {
549 /* Cheat: usually extracted from Inquiry data */
550 sdev->tagged_supported = 1;
551
552 scsi_activate_tcq(sdev, sdev->host->can_queue);
553
554 return 0;
555 }
556
557 static int
558 stex_slave_config(struct scsi_device *sdev)
559 {
560 sdev->use_10_for_rw = 1;
561 sdev->use_10_for_ms = 1;
562 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
563 sdev->tagged_supported = 1;
564
565 return 0;
566 }
567
568 static void
569 stex_slave_destroy(struct scsi_device *sdev)
570 {
571 scsi_deactivate_tcq(sdev, 1);
572 }
573
574 static int
575 stex_queuecommand_lck(struct scsi_cmnd *cmd, void (*done)(struct scsi_cmnd *))
576 {
577 struct st_hba *hba;
578 struct Scsi_Host *host;
579 unsigned int id, lun;
580 struct req_msg *req;
581 u16 tag;
582
583 host = cmd->device->host;
584 id = cmd->device->id;
585 lun = cmd->device->lun;
586 hba = (struct st_hba *) &host->hostdata[0];
587
588 if (unlikely(hba->mu_status == MU_STATE_RESETTING))
589 return SCSI_MLQUEUE_HOST_BUSY;
590
591 switch (cmd->cmnd[0]) {
592 case MODE_SENSE_10:
593 {
594 static char ms10_caching_page[12] =
595 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
596 unsigned char page;
597
598 page = cmd->cmnd[2] & 0x3f;
599 if (page == 0x8 || page == 0x3f) {
600 scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
601 sizeof(ms10_caching_page));
602 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
603 done(cmd);
604 } else
605 stex_invalid_field(cmd, done);
606 return 0;
607 }
608 case REPORT_LUNS:
609 /*
610 * The shasta firmware does not report actual luns in the
611 * target, so fail the command to force sequential lun scan.
612 * Also, the console device does not support this command.
613 */
614 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
615 stex_invalid_field(cmd, done);
616 return 0;
617 }
618 break;
619 case TEST_UNIT_READY:
620 if (id == host->max_id - 1) {
621 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
622 done(cmd);
623 return 0;
624 }
625 break;
626 case INQUIRY:
627 if (lun >= host->max_lun) {
628 cmd->result = DID_NO_CONNECT << 16;
629 done(cmd);
630 return 0;
631 }
632 if (id != host->max_id - 1)
633 break;
634 if (!lun && !cmd->device->channel &&
635 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
636 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
637 sizeof(console_inq_page));
638 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
639 done(cmd);
640 } else
641 stex_invalid_field(cmd, done);
642 return 0;
643 case PASSTHRU_CMD:
644 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
645 struct st_drvver ver;
646 size_t cp_len = sizeof(ver);
647
648 ver.major = ST_VER_MAJOR;
649 ver.minor = ST_VER_MINOR;
650 ver.oem = ST_OEM;
651 ver.build = ST_BUILD_VER;
652 ver.signature[0] = PASSTHRU_SIGNATURE;
653 ver.console_id = host->max_id - 1;
654 ver.host_no = hba->host->host_no;
655 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
656 cmd->result = sizeof(ver) == cp_len ?
657 DID_OK << 16 | COMMAND_COMPLETE << 8 :
658 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
659 done(cmd);
660 return 0;
661 }
662 default:
663 break;
664 }
665
666 cmd->scsi_done = done;
667
668 tag = cmd->request->tag;
669
670 if (unlikely(tag >= host->can_queue))
671 return SCSI_MLQUEUE_HOST_BUSY;
672
673 req = hba->alloc_rq(hba);
674
675 req->lun = lun;
676 req->target = id;
677
678 /* cdb */
679 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
680
681 if (cmd->sc_data_direction == DMA_FROM_DEVICE)
682 req->data_dir = MSG_DATA_DIR_IN;
683 else if (cmd->sc_data_direction == DMA_TO_DEVICE)
684 req->data_dir = MSG_DATA_DIR_OUT;
685 else
686 req->data_dir = MSG_DATA_DIR_ND;
687
688 hba->ccb[tag].cmd = cmd;
689 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
690 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
691
692 if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
693 hba->ccb[tag].sg_count = 0;
694 memset(&req->variable[0], 0, 8);
695 }
696
697 hba->send(hba, req, tag);
698 return 0;
699 }
700
701 static DEF_SCSI_QCMD(stex_queuecommand)
702
703 static void stex_scsi_done(struct st_ccb *ccb)
704 {
705 struct scsi_cmnd *cmd = ccb->cmd;
706 int result;
707
708 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
709 result = ccb->scsi_status;
710 switch (ccb->scsi_status) {
711 case SAM_STAT_GOOD:
712 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
713 break;
714 case SAM_STAT_CHECK_CONDITION:
715 result |= DRIVER_SENSE << 24;
716 break;
717 case SAM_STAT_BUSY:
718 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
719 break;
720 default:
721 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
722 break;
723 }
724 }
725 else if (ccb->srb_status & SRB_SEE_SENSE)
726 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
727 else switch (ccb->srb_status) {
728 case SRB_STATUS_SELECTION_TIMEOUT:
729 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
730 break;
731 case SRB_STATUS_BUSY:
732 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
733 break;
734 case SRB_STATUS_INVALID_REQUEST:
735 case SRB_STATUS_ERROR:
736 default:
737 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
738 break;
739 }
740
741 cmd->result = result;
742 cmd->scsi_done(cmd);
743 }
744
745 static void stex_copy_data(struct st_ccb *ccb,
746 struct status_msg *resp, unsigned int variable)
747 {
748 if (resp->scsi_status != SAM_STAT_GOOD) {
749 if (ccb->sense_buffer != NULL)
750 memcpy(ccb->sense_buffer, resp->variable,
751 min(variable, ccb->sense_bufflen));
752 return;
753 }
754
755 if (ccb->cmd == NULL)
756 return;
757 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
758 }
759
760 static void stex_check_cmd(struct st_hba *hba,
761 struct st_ccb *ccb, struct status_msg *resp)
762 {
763 if (ccb->cmd->cmnd[0] == MGT_CMD &&
764 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
765 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
766 le32_to_cpu(*(__le32 *)&resp->variable[0]));
767 }
768
769 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
770 {
771 void __iomem *base = hba->mmio_base;
772 struct status_msg *resp;
773 struct st_ccb *ccb;
774 unsigned int size;
775 u16 tag;
776
777 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
778 return;
779
780 /* status payloads */
781 hba->status_head = readl(base + OMR1);
782 if (unlikely(hba->status_head > hba->sts_count)) {
783 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
784 pci_name(hba->pdev));
785 return;
786 }
787
788 /*
789 * it's not a valid status payload if:
790 * 1. there are no pending requests(e.g. during init stage)
791 * 2. there are some pending requests, but the controller is in
792 * reset status, and its type is not st_yosemite
793 * firmware of st_yosemite in reset status will return pending requests
794 * to driver, so we allow it to pass
795 */
796 if (unlikely(hba->out_req_cnt <= 0 ||
797 (hba->mu_status == MU_STATE_RESETTING &&
798 hba->cardtype != st_yosemite))) {
799 hba->status_tail = hba->status_head;
800 goto update_status;
801 }
802
803 while (hba->status_tail != hba->status_head) {
804 resp = stex_get_status(hba);
805 tag = le16_to_cpu(resp->tag);
806 if (unlikely(tag >= hba->host->can_queue)) {
807 printk(KERN_WARNING DRV_NAME
808 "(%s): invalid tag\n", pci_name(hba->pdev));
809 continue;
810 }
811
812 hba->out_req_cnt--;
813 ccb = &hba->ccb[tag];
814 if (unlikely(hba->wait_ccb == ccb))
815 hba->wait_ccb = NULL;
816 if (unlikely(ccb->req == NULL)) {
817 printk(KERN_WARNING DRV_NAME
818 "(%s): lagging req\n", pci_name(hba->pdev));
819 continue;
820 }
821
822 size = resp->payload_sz * sizeof(u32); /* payload size */
823 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
824 size > sizeof(*resp))) {
825 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
826 pci_name(hba->pdev));
827 } else {
828 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
829 if (size)
830 stex_copy_data(ccb, resp, size);
831 }
832
833 ccb->req = NULL;
834 ccb->srb_status = resp->srb_status;
835 ccb->scsi_status = resp->scsi_status;
836
837 if (likely(ccb->cmd != NULL)) {
838 if (hba->cardtype == st_yosemite)
839 stex_check_cmd(hba, ccb, resp);
840
841 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
842 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
843 stex_controller_info(hba, ccb);
844
845 scsi_dma_unmap(ccb->cmd);
846 stex_scsi_done(ccb);
847 } else
848 ccb->req_type = 0;
849 }
850
851 update_status:
852 writel(hba->status_head, base + IMR1);
853 readl(base + IMR1); /* flush */
854 }
855
856 static irqreturn_t stex_intr(int irq, void *__hba)
857 {
858 struct st_hba *hba = __hba;
859 void __iomem *base = hba->mmio_base;
860 u32 data;
861 unsigned long flags;
862
863 spin_lock_irqsave(hba->host->host_lock, flags);
864
865 data = readl(base + ODBL);
866
867 if (data && data != 0xffffffff) {
868 /* clear the interrupt */
869 writel(data, base + ODBL);
870 readl(base + ODBL); /* flush */
871 stex_mu_intr(hba, data);
872 spin_unlock_irqrestore(hba->host->host_lock, flags);
873 if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
874 hba->cardtype == st_shasta))
875 queue_work(hba->work_q, &hba->reset_work);
876 return IRQ_HANDLED;
877 }
878
879 spin_unlock_irqrestore(hba->host->host_lock, flags);
880
881 return IRQ_NONE;
882 }
883
884 static void stex_ss_mu_intr(struct st_hba *hba)
885 {
886 struct status_msg *resp;
887 struct st_ccb *ccb;
888 __le32 *scratch;
889 unsigned int size;
890 int count = 0;
891 u32 value;
892 u16 tag;
893
894 if (unlikely(hba->out_req_cnt <= 0 ||
895 hba->mu_status == MU_STATE_RESETTING))
896 return;
897
898 while (count < hba->sts_count) {
899 scratch = hba->scratch + hba->status_tail;
900 value = le32_to_cpu(*scratch);
901 if (unlikely(!(value & SS_STS_NORMAL)))
902 return;
903
904 resp = hba->status_buffer + hba->status_tail;
905 *scratch = 0;
906 ++count;
907 ++hba->status_tail;
908 hba->status_tail %= hba->sts_count+1;
909
910 tag = (u16)value;
911 if (unlikely(tag >= hba->host->can_queue)) {
912 printk(KERN_WARNING DRV_NAME
913 "(%s): invalid tag\n", pci_name(hba->pdev));
914 continue;
915 }
916
917 hba->out_req_cnt--;
918 ccb = &hba->ccb[tag];
919 if (unlikely(hba->wait_ccb == ccb))
920 hba->wait_ccb = NULL;
921 if (unlikely(ccb->req == NULL)) {
922 printk(KERN_WARNING DRV_NAME
923 "(%s): lagging req\n", pci_name(hba->pdev));
924 continue;
925 }
926
927 ccb->req = NULL;
928 if (likely(value & SS_STS_DONE)) { /* normal case */
929 ccb->srb_status = SRB_STATUS_SUCCESS;
930 ccb->scsi_status = SAM_STAT_GOOD;
931 } else {
932 ccb->srb_status = resp->srb_status;
933 ccb->scsi_status = resp->scsi_status;
934 size = resp->payload_sz * sizeof(u32);
935 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
936 size > sizeof(*resp))) {
937 printk(KERN_WARNING DRV_NAME
938 "(%s): bad status size\n",
939 pci_name(hba->pdev));
940 } else {
941 size -= sizeof(*resp) - STATUS_VAR_LEN;
942 if (size)
943 stex_copy_data(ccb, resp, size);
944 }
945 if (likely(ccb->cmd != NULL))
946 stex_check_cmd(hba, ccb, resp);
947 }
948
949 if (likely(ccb->cmd != NULL)) {
950 scsi_dma_unmap(ccb->cmd);
951 stex_scsi_done(ccb);
952 } else
953 ccb->req_type = 0;
954 }
955 }
956
957 static irqreturn_t stex_ss_intr(int irq, void *__hba)
958 {
959 struct st_hba *hba = __hba;
960 void __iomem *base = hba->mmio_base;
961 u32 data;
962 unsigned long flags;
963
964 spin_lock_irqsave(hba->host->host_lock, flags);
965
966 data = readl(base + YI2H_INT);
967 if (data && data != 0xffffffff) {
968 /* clear the interrupt */
969 writel(data, base + YI2H_INT_C);
970 stex_ss_mu_intr(hba);
971 spin_unlock_irqrestore(hba->host->host_lock, flags);
972 if (unlikely(data & SS_I2H_REQUEST_RESET))
973 queue_work(hba->work_q, &hba->reset_work);
974 return IRQ_HANDLED;
975 }
976
977 spin_unlock_irqrestore(hba->host->host_lock, flags);
978
979 return IRQ_NONE;
980 }
981
982 static int stex_common_handshake(struct st_hba *hba)
983 {
984 void __iomem *base = hba->mmio_base;
985 struct handshake_frame *h;
986 dma_addr_t status_phys;
987 u32 data;
988 unsigned long before;
989
990 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
991 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
992 readl(base + IDBL);
993 before = jiffies;
994 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
995 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
996 printk(KERN_ERR DRV_NAME
997 "(%s): no handshake signature\n",
998 pci_name(hba->pdev));
999 return -1;
1000 }
1001 rmb();
1002 msleep(1);
1003 }
1004 }
1005
1006 udelay(10);
1007
1008 data = readl(base + OMR1);
1009 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1010 data &= 0x0000ffff;
1011 if (hba->host->can_queue > data) {
1012 hba->host->can_queue = data;
1013 hba->host->cmd_per_lun = data;
1014 }
1015 }
1016
1017 h = (struct handshake_frame *)hba->status_buffer;
1018 h->rb_phy = cpu_to_le64(hba->dma_handle);
1019 h->req_sz = cpu_to_le16(hba->rq_size);
1020 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1021 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1022 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1023 stex_gettime(&h->hosttime);
1024 h->partner_type = HMU_PARTNER_TYPE;
1025 if (hba->extra_offset) {
1026 h->extra_offset = cpu_to_le32(hba->extra_offset);
1027 h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1028 } else
1029 h->extra_offset = h->extra_size = 0;
1030
1031 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1032 writel(status_phys, base + IMR0);
1033 readl(base + IMR0);
1034 writel((status_phys >> 16) >> 16, base + IMR1);
1035 readl(base + IMR1);
1036
1037 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1038 readl(base + OMR0);
1039 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1040 readl(base + IDBL); /* flush */
1041
1042 udelay(10);
1043 before = jiffies;
1044 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1045 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1046 printk(KERN_ERR DRV_NAME
1047 "(%s): no signature after handshake frame\n",
1048 pci_name(hba->pdev));
1049 return -1;
1050 }
1051 rmb();
1052 msleep(1);
1053 }
1054
1055 writel(0, base + IMR0);
1056 readl(base + IMR0);
1057 writel(0, base + OMR0);
1058 readl(base + OMR0);
1059 writel(0, base + IMR1);
1060 readl(base + IMR1);
1061 writel(0, base + OMR1);
1062 readl(base + OMR1); /* flush */
1063 return 0;
1064 }
1065
1066 static int stex_ss_handshake(struct st_hba *hba)
1067 {
1068 void __iomem *base = hba->mmio_base;
1069 struct st_msg_header *msg_h;
1070 struct handshake_frame *h;
1071 __le32 *scratch;
1072 u32 data, scratch_size;
1073 unsigned long before;
1074 int ret = 0;
1075
1076 before = jiffies;
1077 while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1078 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1079 printk(KERN_ERR DRV_NAME
1080 "(%s): firmware not operational\n",
1081 pci_name(hba->pdev));
1082 return -1;
1083 }
1084 msleep(1);
1085 }
1086
1087 msg_h = (struct st_msg_header *)hba->dma_mem;
1088 msg_h->handle = cpu_to_le64(hba->dma_handle);
1089 msg_h->flag = SS_HEAD_HANDSHAKE;
1090
1091 h = (struct handshake_frame *)(msg_h + 1);
1092 h->rb_phy = cpu_to_le64(hba->dma_handle);
1093 h->req_sz = cpu_to_le16(hba->rq_size);
1094 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1095 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1096 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1097 stex_gettime(&h->hosttime);
1098 h->partner_type = HMU_PARTNER_TYPE;
1099 h->extra_offset = h->extra_size = 0;
1100 scratch_size = (hba->sts_count+1)*sizeof(u32);
1101 h->scratch_size = cpu_to_le32(scratch_size);
1102
1103 data = readl(base + YINT_EN);
1104 data &= ~4;
1105 writel(data, base + YINT_EN);
1106 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1107 readl(base + YH2I_REQ_HI);
1108 writel(hba->dma_handle, base + YH2I_REQ);
1109 readl(base + YH2I_REQ); /* flush */
1110
1111 scratch = hba->scratch;
1112 before = jiffies;
1113 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1114 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1115 printk(KERN_ERR DRV_NAME
1116 "(%s): no signature after handshake frame\n",
1117 pci_name(hba->pdev));
1118 ret = -1;
1119 break;
1120 }
1121 rmb();
1122 msleep(1);
1123 }
1124
1125 memset(scratch, 0, scratch_size);
1126 msg_h->flag = 0;
1127 return ret;
1128 }
1129
1130 static int stex_handshake(struct st_hba *hba)
1131 {
1132 int err;
1133 unsigned long flags;
1134 unsigned int mu_status;
1135
1136 err = (hba->cardtype == st_yel) ?
1137 stex_ss_handshake(hba) : stex_common_handshake(hba);
1138 spin_lock_irqsave(hba->host->host_lock, flags);
1139 mu_status = hba->mu_status;
1140 if (err == 0) {
1141 hba->req_head = 0;
1142 hba->req_tail = 0;
1143 hba->status_head = 0;
1144 hba->status_tail = 0;
1145 hba->out_req_cnt = 0;
1146 hba->mu_status = MU_STATE_STARTED;
1147 } else
1148 hba->mu_status = MU_STATE_FAILED;
1149 if (mu_status == MU_STATE_RESETTING)
1150 wake_up_all(&hba->reset_waitq);
1151 spin_unlock_irqrestore(hba->host->host_lock, flags);
1152 return err;
1153 }
1154
1155 static int stex_abort(struct scsi_cmnd *cmd)
1156 {
1157 struct Scsi_Host *host = cmd->device->host;
1158 struct st_hba *hba = (struct st_hba *)host->hostdata;
1159 u16 tag = cmd->request->tag;
1160 void __iomem *base;
1161 u32 data;
1162 int result = SUCCESS;
1163 unsigned long flags;
1164
1165 printk(KERN_INFO DRV_NAME
1166 "(%s): aborting command\n", pci_name(hba->pdev));
1167 scsi_print_command(cmd);
1168
1169 base = hba->mmio_base;
1170 spin_lock_irqsave(host->host_lock, flags);
1171 if (tag < host->can_queue &&
1172 hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1173 hba->wait_ccb = &hba->ccb[tag];
1174 else
1175 goto out;
1176
1177 if (hba->cardtype == st_yel) {
1178 data = readl(base + YI2H_INT);
1179 if (data == 0 || data == 0xffffffff)
1180 goto fail_out;
1181
1182 writel(data, base + YI2H_INT_C);
1183 stex_ss_mu_intr(hba);
1184 } else {
1185 data = readl(base + ODBL);
1186 if (data == 0 || data == 0xffffffff)
1187 goto fail_out;
1188
1189 writel(data, base + ODBL);
1190 readl(base + ODBL); /* flush */
1191
1192 stex_mu_intr(hba, data);
1193 }
1194 if (hba->wait_ccb == NULL) {
1195 printk(KERN_WARNING DRV_NAME
1196 "(%s): lost interrupt\n", pci_name(hba->pdev));
1197 goto out;
1198 }
1199
1200 fail_out:
1201 scsi_dma_unmap(cmd);
1202 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1203 hba->wait_ccb = NULL;
1204 result = FAILED;
1205 out:
1206 spin_unlock_irqrestore(host->host_lock, flags);
1207 return result;
1208 }
1209
1210 static void stex_hard_reset(struct st_hba *hba)
1211 {
1212 struct pci_bus *bus;
1213 int i;
1214 u16 pci_cmd;
1215 u8 pci_bctl;
1216
1217 for (i = 0; i < 16; i++)
1218 pci_read_config_dword(hba->pdev, i * 4,
1219 &hba->pdev->saved_config_space[i]);
1220
1221 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1222 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1223 bus = hba->pdev->bus;
1224 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1225 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1226 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1227
1228 /*
1229 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1230 * require more time to finish bus reset. Use 100 ms here for safety
1231 */
1232 msleep(100);
1233 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1234 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1235
1236 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1237 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1238 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1239 break;
1240 msleep(1);
1241 }
1242
1243 ssleep(5);
1244 for (i = 0; i < 16; i++)
1245 pci_write_config_dword(hba->pdev, i * 4,
1246 hba->pdev->saved_config_space[i]);
1247 }
1248
1249 static int stex_yos_reset(struct st_hba *hba)
1250 {
1251 void __iomem *base;
1252 unsigned long flags, before;
1253 int ret = 0;
1254
1255 base = hba->mmio_base;
1256 writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1257 readl(base + IDBL); /* flush */
1258 before = jiffies;
1259 while (hba->out_req_cnt > 0) {
1260 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1261 printk(KERN_WARNING DRV_NAME
1262 "(%s): reset timeout\n", pci_name(hba->pdev));
1263 ret = -1;
1264 break;
1265 }
1266 msleep(1);
1267 }
1268
1269 spin_lock_irqsave(hba->host->host_lock, flags);
1270 if (ret == -1)
1271 hba->mu_status = MU_STATE_FAILED;
1272 else
1273 hba->mu_status = MU_STATE_STARTED;
1274 wake_up_all(&hba->reset_waitq);
1275 spin_unlock_irqrestore(hba->host->host_lock, flags);
1276
1277 return ret;
1278 }
1279
1280 static void stex_ss_reset(struct st_hba *hba)
1281 {
1282 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1283 readl(hba->mmio_base + YH2I_INT);
1284 ssleep(5);
1285 }
1286
1287 static int stex_do_reset(struct st_hba *hba)
1288 {
1289 struct st_ccb *ccb;
1290 unsigned long flags;
1291 unsigned int mu_status = MU_STATE_RESETTING;
1292 u16 tag;
1293
1294 spin_lock_irqsave(hba->host->host_lock, flags);
1295 if (hba->mu_status == MU_STATE_STARTING) {
1296 spin_unlock_irqrestore(hba->host->host_lock, flags);
1297 printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1298 pci_name(hba->pdev));
1299 return 0;
1300 }
1301 while (hba->mu_status == MU_STATE_RESETTING) {
1302 spin_unlock_irqrestore(hba->host->host_lock, flags);
1303 wait_event_timeout(hba->reset_waitq,
1304 hba->mu_status != MU_STATE_RESETTING,
1305 MU_MAX_DELAY * HZ);
1306 spin_lock_irqsave(hba->host->host_lock, flags);
1307 mu_status = hba->mu_status;
1308 }
1309
1310 if (mu_status != MU_STATE_RESETTING) {
1311 spin_unlock_irqrestore(hba->host->host_lock, flags);
1312 return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1313 }
1314
1315 hba->mu_status = MU_STATE_RESETTING;
1316 spin_unlock_irqrestore(hba->host->host_lock, flags);
1317
1318 if (hba->cardtype == st_yosemite)
1319 return stex_yos_reset(hba);
1320
1321 if (hba->cardtype == st_shasta)
1322 stex_hard_reset(hba);
1323 else if (hba->cardtype == st_yel)
1324 stex_ss_reset(hba);
1325
1326 spin_lock_irqsave(hba->host->host_lock, flags);
1327 for (tag = 0; tag < hba->host->can_queue; tag++) {
1328 ccb = &hba->ccb[tag];
1329 if (ccb->req == NULL)
1330 continue;
1331 ccb->req = NULL;
1332 if (ccb->cmd) {
1333 scsi_dma_unmap(ccb->cmd);
1334 ccb->cmd->result = DID_RESET << 16;
1335 ccb->cmd->scsi_done(ccb->cmd);
1336 ccb->cmd = NULL;
1337 }
1338 }
1339 spin_unlock_irqrestore(hba->host->host_lock, flags);
1340
1341 if (stex_handshake(hba) == 0)
1342 return 0;
1343
1344 printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1345 pci_name(hba->pdev));
1346 return -1;
1347 }
1348
1349 static int stex_reset(struct scsi_cmnd *cmd)
1350 {
1351 struct st_hba *hba;
1352
1353 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1354
1355 printk(KERN_INFO DRV_NAME
1356 "(%s): resetting host\n", pci_name(hba->pdev));
1357 scsi_print_command(cmd);
1358
1359 return stex_do_reset(hba) ? FAILED : SUCCESS;
1360 }
1361
1362 static void stex_reset_work(struct work_struct *work)
1363 {
1364 struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1365
1366 stex_do_reset(hba);
1367 }
1368
1369 static int stex_biosparam(struct scsi_device *sdev,
1370 struct block_device *bdev, sector_t capacity, int geom[])
1371 {
1372 int heads = 255, sectors = 63;
1373
1374 if (capacity < 0x200000) {
1375 heads = 64;
1376 sectors = 32;
1377 }
1378
1379 sector_div(capacity, heads * sectors);
1380
1381 geom[0] = heads;
1382 geom[1] = sectors;
1383 geom[2] = capacity;
1384
1385 return 0;
1386 }
1387
1388 static struct scsi_host_template driver_template = {
1389 .module = THIS_MODULE,
1390 .name = DRV_NAME,
1391 .proc_name = DRV_NAME,
1392 .bios_param = stex_biosparam,
1393 .queuecommand = stex_queuecommand,
1394 .slave_alloc = stex_slave_alloc,
1395 .slave_configure = stex_slave_config,
1396 .slave_destroy = stex_slave_destroy,
1397 .eh_abort_handler = stex_abort,
1398 .eh_host_reset_handler = stex_reset,
1399 .this_id = -1,
1400 };
1401
1402 static struct pci_device_id stex_pci_tbl[] = {
1403 /* st_shasta */
1404 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1405 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1406 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1407 st_shasta }, /* SuperTrak EX12350 */
1408 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1409 st_shasta }, /* SuperTrak EX4350 */
1410 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1411 st_shasta }, /* SuperTrak EX24350 */
1412
1413 /* st_vsc */
1414 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1415
1416 /* st_yosemite */
1417 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1418
1419 /* st_seq */
1420 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1421
1422 /* st_yel */
1423 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1424 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1425 { } /* terminate list */
1426 };
1427
1428 static struct st_card_info stex_card_info[] = {
1429 /* st_shasta */
1430 {
1431 .max_id = 17,
1432 .max_lun = 8,
1433 .max_channel = 0,
1434 .rq_count = 32,
1435 .rq_size = 1048,
1436 .sts_count = 32,
1437 .alloc_rq = stex_alloc_req,
1438 .map_sg = stex_map_sg,
1439 .send = stex_send_cmd,
1440 },
1441
1442 /* st_vsc */
1443 {
1444 .max_id = 129,
1445 .max_lun = 1,
1446 .max_channel = 0,
1447 .rq_count = 32,
1448 .rq_size = 1048,
1449 .sts_count = 32,
1450 .alloc_rq = stex_alloc_req,
1451 .map_sg = stex_map_sg,
1452 .send = stex_send_cmd,
1453 },
1454
1455 /* st_yosemite */
1456 {
1457 .max_id = 2,
1458 .max_lun = 256,
1459 .max_channel = 0,
1460 .rq_count = 256,
1461 .rq_size = 1048,
1462 .sts_count = 256,
1463 .alloc_rq = stex_alloc_req,
1464 .map_sg = stex_map_sg,
1465 .send = stex_send_cmd,
1466 },
1467
1468 /* st_seq */
1469 {
1470 .max_id = 129,
1471 .max_lun = 1,
1472 .max_channel = 0,
1473 .rq_count = 32,
1474 .rq_size = 1048,
1475 .sts_count = 32,
1476 .alloc_rq = stex_alloc_req,
1477 .map_sg = stex_map_sg,
1478 .send = stex_send_cmd,
1479 },
1480
1481 /* st_yel */
1482 {
1483 .max_id = 129,
1484 .max_lun = 256,
1485 .max_channel = 3,
1486 .rq_count = 801,
1487 .rq_size = 512,
1488 .sts_count = 801,
1489 .alloc_rq = stex_ss_alloc_req,
1490 .map_sg = stex_ss_map_sg,
1491 .send = stex_ss_send_cmd,
1492 },
1493 };
1494
1495 static int stex_set_dma_mask(struct pci_dev * pdev)
1496 {
1497 int ret;
1498
1499 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1500 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
1501 return 0;
1502 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1503 if (!ret)
1504 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1505 return ret;
1506 }
1507
1508 static int stex_request_irq(struct st_hba *hba)
1509 {
1510 struct pci_dev *pdev = hba->pdev;
1511 int status;
1512
1513 if (msi) {
1514 status = pci_enable_msi(pdev);
1515 if (status != 0)
1516 printk(KERN_ERR DRV_NAME
1517 "(%s): error %d setting up MSI\n",
1518 pci_name(pdev), status);
1519 else
1520 hba->msi_enabled = 1;
1521 } else
1522 hba->msi_enabled = 0;
1523
1524 status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1525 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1526
1527 if (status != 0) {
1528 if (hba->msi_enabled)
1529 pci_disable_msi(pdev);
1530 }
1531 return status;
1532 }
1533
1534 static void stex_free_irq(struct st_hba *hba)
1535 {
1536 struct pci_dev *pdev = hba->pdev;
1537
1538 free_irq(pdev->irq, hba);
1539 if (hba->msi_enabled)
1540 pci_disable_msi(pdev);
1541 }
1542
1543 static int __devinit
1544 stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1545 {
1546 struct st_hba *hba;
1547 struct Scsi_Host *host;
1548 const struct st_card_info *ci = NULL;
1549 u32 sts_offset, cp_offset, scratch_offset;
1550 int err;
1551
1552 err = pci_enable_device(pdev);
1553 if (err)
1554 return err;
1555
1556 pci_set_master(pdev);
1557
1558 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1559
1560 if (!host) {
1561 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1562 pci_name(pdev));
1563 err = -ENOMEM;
1564 goto out_disable;
1565 }
1566
1567 hba = (struct st_hba *)host->hostdata;
1568 memset(hba, 0, sizeof(struct st_hba));
1569
1570 err = pci_request_regions(pdev, DRV_NAME);
1571 if (err < 0) {
1572 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1573 pci_name(pdev));
1574 goto out_scsi_host_put;
1575 }
1576
1577 hba->mmio_base = pci_ioremap_bar(pdev, 0);
1578 if ( !hba->mmio_base) {
1579 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1580 pci_name(pdev));
1581 err = -ENOMEM;
1582 goto out_release_regions;
1583 }
1584
1585 err = stex_set_dma_mask(pdev);
1586 if (err) {
1587 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1588 pci_name(pdev));
1589 goto out_iounmap;
1590 }
1591
1592 hba->cardtype = (unsigned int) id->driver_data;
1593 ci = &stex_card_info[hba->cardtype];
1594 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1595 if (hba->cardtype == st_yel)
1596 sts_offset += (ci->sts_count+1) * sizeof(u32);
1597 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1598 hba->dma_size = cp_offset + sizeof(struct st_frame);
1599 if (hba->cardtype == st_seq ||
1600 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1601 hba->extra_offset = hba->dma_size;
1602 hba->dma_size += ST_ADDITIONAL_MEM;
1603 }
1604 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1605 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1606 if (!hba->dma_mem) {
1607 /* Retry minimum coherent mapping for st_seq and st_vsc */
1608 if (hba->cardtype == st_seq ||
1609 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1610 printk(KERN_WARNING DRV_NAME
1611 "(%s): allocating min buffer for controller\n",
1612 pci_name(pdev));
1613 hba->dma_size = hba->extra_offset
1614 + ST_ADDITIONAL_MEM_MIN;
1615 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1616 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1617 }
1618
1619 if (!hba->dma_mem) {
1620 err = -ENOMEM;
1621 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1622 pci_name(pdev));
1623 goto out_iounmap;
1624 }
1625 }
1626
1627 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1628 if (!hba->ccb) {
1629 err = -ENOMEM;
1630 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1631 pci_name(pdev));
1632 goto out_pci_free;
1633 }
1634
1635 if (hba->cardtype == st_yel)
1636 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1637 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1638 hba->copy_buffer = hba->dma_mem + cp_offset;
1639 hba->rq_count = ci->rq_count;
1640 hba->rq_size = ci->rq_size;
1641 hba->sts_count = ci->sts_count;
1642 hba->alloc_rq = ci->alloc_rq;
1643 hba->map_sg = ci->map_sg;
1644 hba->send = ci->send;
1645 hba->mu_status = MU_STATE_STARTING;
1646
1647 if (hba->cardtype == st_yel)
1648 host->sg_tablesize = 38;
1649 else
1650 host->sg_tablesize = 32;
1651 host->can_queue = ci->rq_count;
1652 host->cmd_per_lun = ci->rq_count;
1653 host->max_id = ci->max_id;
1654 host->max_lun = ci->max_lun;
1655 host->max_channel = ci->max_channel;
1656 host->unique_id = host->host_no;
1657 host->max_cmd_len = STEX_CDB_LENGTH;
1658
1659 hba->host = host;
1660 hba->pdev = pdev;
1661 init_waitqueue_head(&hba->reset_waitq);
1662
1663 snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1664 "stex_wq_%d", host->host_no);
1665 hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1666 if (!hba->work_q) {
1667 printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1668 pci_name(pdev));
1669 err = -ENOMEM;
1670 goto out_ccb_free;
1671 }
1672 INIT_WORK(&hba->reset_work, stex_reset_work);
1673
1674 err = stex_request_irq(hba);
1675 if (err) {
1676 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1677 pci_name(pdev));
1678 goto out_free_wq;
1679 }
1680
1681 err = stex_handshake(hba);
1682 if (err)
1683 goto out_free_irq;
1684
1685 err = scsi_init_shared_tag_map(host, host->can_queue);
1686 if (err) {
1687 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1688 pci_name(pdev));
1689 goto out_free_irq;
1690 }
1691
1692 pci_set_drvdata(pdev, hba);
1693
1694 err = scsi_add_host(host, &pdev->dev);
1695 if (err) {
1696 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1697 pci_name(pdev));
1698 goto out_free_irq;
1699 }
1700
1701 scsi_scan_host(host);
1702
1703 return 0;
1704
1705 out_free_irq:
1706 stex_free_irq(hba);
1707 out_free_wq:
1708 destroy_workqueue(hba->work_q);
1709 out_ccb_free:
1710 kfree(hba->ccb);
1711 out_pci_free:
1712 dma_free_coherent(&pdev->dev, hba->dma_size,
1713 hba->dma_mem, hba->dma_handle);
1714 out_iounmap:
1715 iounmap(hba->mmio_base);
1716 out_release_regions:
1717 pci_release_regions(pdev);
1718 out_scsi_host_put:
1719 scsi_host_put(host);
1720 out_disable:
1721 pci_disable_device(pdev);
1722
1723 return err;
1724 }
1725
1726 static void stex_hba_stop(struct st_hba *hba)
1727 {
1728 struct req_msg *req;
1729 struct st_msg_header *msg_h;
1730 unsigned long flags;
1731 unsigned long before;
1732 u16 tag = 0;
1733
1734 spin_lock_irqsave(hba->host->host_lock, flags);
1735 req = hba->alloc_rq(hba);
1736 if (hba->cardtype == st_yel) {
1737 msg_h = (struct st_msg_header *)req - 1;
1738 memset(msg_h, 0, hba->rq_size);
1739 } else
1740 memset(req, 0, hba->rq_size);
1741
1742 if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
1743 req->cdb[0] = MGT_CMD;
1744 req->cdb[1] = MGT_CMD_SIGNATURE;
1745 req->cdb[2] = CTLR_CONFIG_CMD;
1746 req->cdb[3] = CTLR_SHUTDOWN;
1747 } else {
1748 req->cdb[0] = CONTROLLER_CMD;
1749 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1750 req->cdb[2] = CTLR_POWER_SAVING;
1751 }
1752
1753 hba->ccb[tag].cmd = NULL;
1754 hba->ccb[tag].sg_count = 0;
1755 hba->ccb[tag].sense_bufflen = 0;
1756 hba->ccb[tag].sense_buffer = NULL;
1757 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1758
1759 hba->send(hba, req, tag);
1760 spin_unlock_irqrestore(hba->host->host_lock, flags);
1761
1762 before = jiffies;
1763 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1764 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1765 hba->ccb[tag].req_type = 0;
1766 return;
1767 }
1768 msleep(1);
1769 }
1770 }
1771
1772 static void stex_hba_free(struct st_hba *hba)
1773 {
1774 stex_free_irq(hba);
1775
1776 destroy_workqueue(hba->work_q);
1777
1778 iounmap(hba->mmio_base);
1779
1780 pci_release_regions(hba->pdev);
1781
1782 kfree(hba->ccb);
1783
1784 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1785 hba->dma_mem, hba->dma_handle);
1786 }
1787
1788 static void stex_remove(struct pci_dev *pdev)
1789 {
1790 struct st_hba *hba = pci_get_drvdata(pdev);
1791
1792 scsi_remove_host(hba->host);
1793
1794 pci_set_drvdata(pdev, NULL);
1795
1796 stex_hba_stop(hba);
1797
1798 stex_hba_free(hba);
1799
1800 scsi_host_put(hba->host);
1801
1802 pci_disable_device(pdev);
1803 }
1804
1805 static void stex_shutdown(struct pci_dev *pdev)
1806 {
1807 struct st_hba *hba = pci_get_drvdata(pdev);
1808
1809 stex_hba_stop(hba);
1810 }
1811
1812 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1813
1814 static struct pci_driver stex_pci_driver = {
1815 .name = DRV_NAME,
1816 .id_table = stex_pci_tbl,
1817 .probe = stex_probe,
1818 .remove = __devexit_p(stex_remove),
1819 .shutdown = stex_shutdown,
1820 };
1821
1822 static int __init stex_init(void)
1823 {
1824 printk(KERN_INFO DRV_NAME
1825 ": Promise SuperTrak EX Driver version: %s\n",
1826 ST_DRIVER_VERSION);
1827
1828 return pci_register_driver(&stex_pci_driver);
1829 }
1830
1831 static void __exit stex_exit(void)
1832 {
1833 pci_unregister_driver(&stex_pci_driver);
1834 }
1835
1836 module_init(stex_init);
1837 module_exit(stex_exit);
kernel source for telekom puls (alcatel/mediatek)