drivers/scsi/ncr53c8xx.h

   1 /******************************************************************************
   2 **  Device driver for the PCI-SCSI NCR538XX controller family.
   3 **
   4 **  Copyright (C) 1994  Wolfgang Stanglmeier
   5 **  Copyright (C) 1998-2001  Gerard Roudier <groudier@free.fr>
   6 **
   7 **  This program is free software; you can redistribute it and/or modify
   8 **  it under the terms of the GNU General Public License as published by
   9 **  the Free Software Foundation; either version 2 of the License, or
  10 **  (at your option) any later version.
  11 **
  12 **  This program is distributed in the hope that it will be useful,
  13 **  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 **  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 **  GNU General Public License for more details.
  16 **
  17 **  You should have received a copy of the GNU General Public License
  18 **  along with this program; if not, write to the Free Software
  19 **  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 **
  21 **-----------------------------------------------------------------------------
  22 **
  23 **  This driver has been ported to Linux from the FreeBSD NCR53C8XX driver
  24 **  and is currently maintained by
  25 **
  26 **          Gerard Roudier              <groudier@free.fr>
  27 **
  28 **  Being given that this driver originates from the FreeBSD version, and
  29 **  in order to keep synergy on both, any suggested enhancements and corrections
  30 **  received on Linux are automatically a potential candidate for the FreeBSD
  31 **  version.
  32 **
  33 **  The original driver has been written for 386bsd and FreeBSD by
  34 **          Wolfgang Stanglmeier        <wolf@cologne.de>
  35 **          Stefan Esser                <se@mi.Uni-Koeln.de>
  36 **
  37 **  And has been ported to NetBSD by
  38 **          Charles M. Hannum           <mycroft@gnu.ai.mit.edu>
  39 **
  40 **  NVRAM detection and reading.
  41 **    Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
  42 **
  43 **  Added support for MIPS big endian systems.
  44 **    Carsten Langgaard, carstenl@mips.com
  45 **    Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  46 **
  47 **  Added support for HP PARISC big endian systems.
  48 **    Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  49 **
  50 *******************************************************************************
  51 */
  52
  53 #ifndef NCR53C8XX_H
  54 #define NCR53C8XX_H
  55
  56 #include <scsi/scsi_host.h>
  57
  58
  59 /*
  60 **      If you want a driver as small as possible, donnot define the
  61 **      following options.
  62 */
  63 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
  64 #define SCSI_NCR_DEBUG_INFO_SUPPORT
  65
  66 /*
  67 **      To disable integrity checking, do not define the
  68 **      following option.
  69 */
  70 #ifdef  CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
  71 #       define SCSI_NCR_ENABLE_INTEGRITY_CHECK
  72 #endif
  73
  74 /* ---------------------------------------------------------------------
  75 ** Take into account kernel configured parameters.
  76 ** Most of these options can be overridden at startup by a command line.
  77 ** ---------------------------------------------------------------------
  78 */
  79
  80 /*
  81  * For Ultra2 and Ultra3 SCSI support option, use special features.
  82  *
  83  * Value (default) means:
  84  *      bit 0 : all features enabled, except:
  85  *              bit 1 : PCI Write And Invalidate.
  86  *              bit 2 : Data Phase Mismatch handling from SCRIPTS.
  87  *
  88  * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
  89  * enabled by the driver.
  90  */
  91 #define SCSI_NCR_SETUP_SPECIAL_FEATURES         (3)
  92
  93 #define SCSI_NCR_MAX_SYNC                       (80)
  94
  95 /*
  96  * Allow tags from 2 to 256, default 8
  97  */
  98 #ifdef  CONFIG_SCSI_NCR53C8XX_MAX_TAGS
  99 #if     CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
 100 #define SCSI_NCR_MAX_TAGS       (2)
 101 #elif   CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
 102 #define SCSI_NCR_MAX_TAGS       (256)
 103 #else
 104 #define SCSI_NCR_MAX_TAGS       CONFIG_SCSI_NCR53C8XX_MAX_TAGS
 105 #endif
 106 #else
 107 #define SCSI_NCR_MAX_TAGS       (8)
 108 #endif
 109
 110 /*
 111  * Allow tagged command queuing support if configured with default number
 112  * of tags set to max (see above).
 113  */
 114 #ifdef  CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
 115 #define SCSI_NCR_SETUP_DEFAULT_TAGS     CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
 116 #elif   defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
 117 #define SCSI_NCR_SETUP_DEFAULT_TAGS     SCSI_NCR_MAX_TAGS
 118 #else
 119 #define SCSI_NCR_SETUP_DEFAULT_TAGS     (0)
 120 #endif
 121
 122 /*
 123  * Immediate arbitration
 124  */
 125 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
 126 #define SCSI_NCR_IARB_SUPPORT
 127 #endif
 128
 129 /*
 130  * Sync transfer frequency at startup.
 131  * Allow from 5Mhz to 80Mhz default 20 Mhz.
 132  */
 133 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
 134 #define CONFIG_SCSI_NCR53C8XX_SYNC      (20)
 135 #elif   CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
 136 #undef  CONFIG_SCSI_NCR53C8XX_SYNC
 137 #define CONFIG_SCSI_NCR53C8XX_SYNC      SCSI_NCR_MAX_SYNC
 138 #endif
 139
 140 #if     CONFIG_SCSI_NCR53C8XX_SYNC == 0
 141 #define SCSI_NCR_SETUP_DEFAULT_SYNC     (255)
 142 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 5
 143 #define SCSI_NCR_SETUP_DEFAULT_SYNC     (50)
 144 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 20
 145 #define SCSI_NCR_SETUP_DEFAULT_SYNC     (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
 146 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 33
 147 #define SCSI_NCR_SETUP_DEFAULT_SYNC     (11)
 148 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 40
 149 #define SCSI_NCR_SETUP_DEFAULT_SYNC     (10)
 150 #else
 151 #define SCSI_NCR_SETUP_DEFAULT_SYNC     (9)
 152 #endif
 153
 154 /*
 155  * Disallow disconnections at boot-up
 156  */
 157 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
 158 #define SCSI_NCR_SETUP_DISCONNECTION    (0)
 159 #else
 160 #define SCSI_NCR_SETUP_DISCONNECTION    (1)
 161 #endif
 162
 163 /*
 164  * Force synchronous negotiation for all targets
 165  */
 166 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
 167 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO  (1)
 168 #else
 169 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO  (0)
 170 #endif
 171
 172 /*
 173  * Disable master parity checking (flawed hardwares need that)
 174  */
 175 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
 176 #define SCSI_NCR_SETUP_MASTER_PARITY    (0)
 177 #else
 178 #define SCSI_NCR_SETUP_MASTER_PARITY    (1)
 179 #endif
 180
 181 /*
 182  * Disable scsi parity checking (flawed devices may need that)
 183  */
 184 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
 185 #define SCSI_NCR_SETUP_SCSI_PARITY      (0)
 186 #else
 187 #define SCSI_NCR_SETUP_SCSI_PARITY      (1)
 188 #endif
 189
 190 /*
 191  * Settle time after reset at boot-up
 192  */
 193 #define SCSI_NCR_SETUP_SETTLE_TIME      (2)
 194
 195 /*
 196 **      Bridge quirks work-around option defaulted to 1.
 197 */
 198 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
 199 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT   1
 200 #endif
 201
 202 /*
 203 **      Work-around common bridge misbehaviour.
 204 **
 205 **      - Do not flush posted writes in the opposite
 206 **        direction on read.
 207 **      - May reorder DMA writes to memory.
 208 **
 209 **      This option should not affect performances
 210 **      significantly, so it is the default.
 211 */
 212 #if     SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
 213 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
 214 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
 215 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
 216
 217 /*
 218 **      Same as option 1, but also deal with
 219 **      misconfigured interrupts.
 220 **
 221 **      - Edge triggered instead of level sensitive.
 222 **      - No interrupt line connected.
 223 **      - IRQ number misconfigured.
 224 **
 225 **      If no interrupt is delivered, the driver will
 226 **      catch the interrupt conditions 10 times per
 227 **      second. No need to say that this option is
 228 **      not recommended.
 229 */
 230 #elif   SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
 231 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
 232 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
 233 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
 234 #define SCSI_NCR_PCIQ_BROKEN_INTR
 235
 236 /*
 237 **      Some bridge designers decided to flush
 238 **      everything prior to deliver the interrupt.
 239 **      This option tries to deal with such a
 240 **      behaviour.
 241 */
 242 #elif   SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
 243 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
 244 #endif
 245
 246 /*
 247 **      Other parameters not configurable with "make config"
 248 **      Avoid to change these constants, unless you know what you are doing.
 249 */
 250
 251 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
 252 #define SCSI_NCR_MAX_SCATTER    (127)
 253 #define SCSI_NCR_MAX_TARGET     (16)
 254
 255 /*
 256 **   Compute some desirable value for CAN_QUEUE
 257 **   and CMD_PER_LUN.
 258 **   The driver will use lower values if these
 259 **   ones appear to be too large.
 260 */
 261 #define SCSI_NCR_CAN_QUEUE      (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
 262 #define SCSI_NCR_CMD_PER_LUN    (SCSI_NCR_MAX_TAGS)
 263
 264 #define SCSI_NCR_SG_TABLESIZE   (SCSI_NCR_MAX_SCATTER)
 265 #define SCSI_NCR_TIMER_INTERVAL (HZ)
 266
 267 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
 268 #define SCSI_NCR_MAX_LUN        (16)
 269 #else
 270 #define SCSI_NCR_MAX_LUN        (1)
 271 #endif
 272
 273 /*
 274  *  IO functions definition for big/little endian CPU support.
 275  *  For now, the NCR is only supported in little endian addressing mode,
 276  */
 277
 278 #ifdef  __BIG_ENDIAN
 279
 280 #define inw_l2b         inw
 281 #define inl_l2b         inl
 282 #define outw_b2l        outw
 283 #define outl_b2l        outl
 284
 285 #define readb_raw       readb
 286 #define writeb_raw      writeb
 287
 288 #if defined(SCSI_NCR_BIG_ENDIAN)
 289 #define readw_l2b       __raw_readw
 290 #define readl_l2b       __raw_readl
 291 #define writew_b2l      __raw_writew
 292 #define writel_b2l      __raw_writel
 293 #define readw_raw       __raw_readw
 294 #define readl_raw       __raw_readl
 295 #define writew_raw      __raw_writew
 296 #define writel_raw      __raw_writel
 297 #else   /* Other big-endian */
 298 #define readw_l2b       readw
 299 #define readl_l2b       readl
 300 #define writew_b2l      writew
 301 #define writel_b2l      writel
 302 #define readw_raw       readw
 303 #define readl_raw       readl
 304 #define writew_raw      writew
 305 #define writel_raw      writel
 306 #endif
 307
 308 #else   /* little endian */
 309
 310 #define inw_raw         inw
 311 #define inl_raw         inl
 312 #define outw_raw        outw
 313 #define outl_raw        outl
 314
 315 #define readb_raw       readb
 316 #define readw_raw       readw
 317 #define readl_raw       readl
 318 #define writeb_raw      writeb
 319 #define writew_raw      writew
 320 #define writel_raw      writel
 321
 322 #endif
 323
 324 #if !defined(__hppa__) && !defined(__mips__)
 325 #ifdef  SCSI_NCR_BIG_ENDIAN
 326 #error  "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
 327 #endif
 328 #endif
 329
 330 #define MEMORY_BARRIER()        mb()
 331
 332
 333 /*
 334  *  If the NCR uses big endian addressing mode over the
 335  *  PCI, actual io register addresses for byte and word
 336  *  accesses must be changed according to lane routing.
 337  *  Btw, ncr_offb() and ncr_offw() macros only apply to
 338  *  constants and so donnot generate bloated code.
 339  */
 340
 341 #if     defined(SCSI_NCR_BIG_ENDIAN)
 342
 343 #define ncr_offb(o)     (((o)&~3)+((~((o)&3))&3))
 344 #define ncr_offw(o)     (((o)&~3)+((~((o)&3))&2))
 345
 346 #else
 347
 348 #define ncr_offb(o)     (o)
 349 #define ncr_offw(o)     (o)
 350
 351 #endif
 352
 353 /*
 354  *  If the CPU and the NCR use same endian-ness addressing,
 355  *  no byte reordering is needed for script patching.
 356  *  Macro cpu_to_scr() is to be used for script patching.
 357  *  Macro scr_to_cpu() is to be used for getting a DWORD
 358  *  from the script.
 359  */
 360
 361 #if     defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
 362
 363 #define cpu_to_scr(dw)  cpu_to_le32(dw)
 364 #define scr_to_cpu(dw)  le32_to_cpu(dw)
 365
 366 #elif   defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
 367
 368 #define cpu_to_scr(dw)  cpu_to_be32(dw)
 369 #define scr_to_cpu(dw)  be32_to_cpu(dw)
 370
 371 #else
 372
 373 #define cpu_to_scr(dw)  (dw)
 374 #define scr_to_cpu(dw)  (dw)
 375
 376 #endif
 377
 378 /*
 379  *  Access to the controller chip.
 380  *
 381  *  If the CPU and the NCR use same endian-ness addressing,
 382  *  no byte reordering is needed for accessing chip io
 383  *  registers. Functions suffixed by '_raw' are assumed
 384  *  to access the chip over the PCI without doing byte
 385  *  reordering. Functions suffixed by '_l2b' are
 386  *  assumed to perform little-endian to big-endian byte
 387  *  reordering, those suffixed by '_b2l' blah, blah,
 388  *  blah, ...
 389  */
 390
 391 /*
 392  *  MEMORY mapped IO input / output
 393  */
 394
 395 #define INB_OFF(o)              readb_raw((char __iomem *)np->reg + ncr_offb(o))
 396 #define OUTB_OFF(o, val)        writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
 397
 398 #if     defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
 399
 400 #define INW_OFF(o)              readw_l2b((char __iomem *)np->reg + ncr_offw(o))
 401 #define INL_OFF(o)              readl_l2b((char __iomem *)np->reg + (o))
 402
 403 #define OUTW_OFF(o, val)        writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
 404 #define OUTL_OFF(o, val)        writel_b2l((val), (char __iomem *)np->reg + (o))
 405
 406 #elif   defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
 407
 408 #define INW_OFF(o)              readw_b2l((char __iomem *)np->reg + ncr_offw(o))
 409 #define INL_OFF(o)              readl_b2l((char __iomem *)np->reg + (o))
 410
 411 #define OUTW_OFF(o, val)        writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
 412 #define OUTL_OFF(o, val)        writel_l2b((val), (char __iomem *)np->reg + (o))
 413
 414 #else
 415
 416 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
 417 /* Only 8 or 32 bit transfers allowed */
 418 #define INW_OFF(o)              (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
 419 #else
 420 #define INW_OFF(o)              readw_raw((char __iomem *)np->reg + ncr_offw(o))
 421 #endif
 422 #define INL_OFF(o)              readl_raw((char __iomem *)np->reg + (o))
 423
 424 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
 425 /* Only 8 or 32 bit transfers allowed */
 426 #define OUTW_OFF(o, val)        do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
 427 #else
 428 #define OUTW_OFF(o, val)        writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
 429 #endif
 430 #define OUTL_OFF(o, val)        writel_raw((val), (char __iomem *)np->reg + (o))
 431
 432 #endif
 433
 434 #define INB(r)          INB_OFF (offsetof(struct ncr_reg,r))
 435 #define INW(r)          INW_OFF (offsetof(struct ncr_reg,r))
 436 #define INL(r)          INL_OFF (offsetof(struct ncr_reg,r))
 437
 438 #define OUTB(r, val)    OUTB_OFF (offsetof(struct ncr_reg,r), (val))
 439 #define OUTW(r, val)    OUTW_OFF (offsetof(struct ncr_reg,r), (val))
 440 #define OUTL(r, val)    OUTL_OFF (offsetof(struct ncr_reg,r), (val))
 441
 442 /*
 443  *  Set bit field ON, OFF
 444  */
 445
 446 #define OUTONB(r, m)    OUTB(r, INB(r) | (m))
 447 #define OUTOFFB(r, m)   OUTB(r, INB(r) & ~(m))
 448 #define OUTONW(r, m)    OUTW(r, INW(r) | (m))
 449 #define OUTOFFW(r, m)   OUTW(r, INW(r) & ~(m))
 450 #define OUTONL(r, m)    OUTL(r, INL(r) | (m))
 451 #define OUTOFFL(r, m)   OUTL(r, INL(r) & ~(m))
 452
 453 /*
 454  *  We normally want the chip to have a consistent view
 455  *  of driver internal data structures when we restart it.
 456  *  Thus these macros.
 457  */
 458 #define OUTL_DSP(v)                             \
 459         do {                                    \
 460                 MEMORY_BARRIER();               \
 461                 OUTL (nc_dsp, (v));             \
 462         } while (0)
 463
 464 #define OUTONB_STD()                            \
 465         do {                                    \
 466                 MEMORY_BARRIER();               \
 467                 OUTONB (nc_dcntl, (STD|NOCOM)); \
 468         } while (0)
 469
 470
 471 /*
 472 **   NCR53C8XX devices features table.
 473 */
 474 struct ncr_chip {
 475         unsigned short  revision_id;
 476         unsigned char   burst_max;      /* log-base-2 of max burst */
 477         unsigned char   offset_max;
 478         unsigned char   nr_divisor;
 479         unsigned int    features;
 480 #define FE_LED0         (1<<0)
 481 #define FE_WIDE         (1<<1)    /* Wide data transfers */
 482 #define FE_ULTRA        (1<<2)    /* Ultra speed 20Mtrans/sec */
 483 #define FE_DBLR         (1<<4)    /* Clock doubler present */
 484 #define FE_QUAD         (1<<5)    /* Clock quadrupler present */
 485 #define FE_ERL          (1<<6)    /* Enable read line */
 486 #define FE_CLSE         (1<<7)    /* Cache line size enable */
 487 #define FE_WRIE         (1<<8)    /* Write & Invalidate enable */
 488 #define FE_ERMP         (1<<9)    /* Enable read multiple */
 489 #define FE_BOF          (1<<10)   /* Burst opcode fetch */
 490 #define FE_DFS          (1<<11)   /* DMA fifo size */
 491 #define FE_PFEN         (1<<12)   /* Prefetch enable */
 492 #define FE_LDSTR        (1<<13)   /* Load/Store supported */
 493 #define FE_RAM          (1<<14)   /* On chip RAM present */
 494 #define FE_VARCLK       (1<<15)   /* SCSI clock may vary */
 495 #define FE_RAM8K        (1<<16)   /* On chip RAM sized 8Kb */
 496 #define FE_64BIT        (1<<17)   /* Have a 64-bit PCI interface */
 497 #define FE_IO256        (1<<18)   /* Requires full 256 bytes in PCI space */
 498 #define FE_NOPM         (1<<19)   /* Scripts handles phase mismatch */
 499 #define FE_LEDC         (1<<20)   /* Hardware control of LED */
 500 #define FE_DIFF         (1<<21)   /* Support Differential SCSI */
 501 #define FE_66MHZ        (1<<23)   /* 66MHz PCI Support */
 502 #define FE_DAC          (1<<24)   /* Support DAC cycles (64 bit addressing) */
 503 #define FE_ISTAT1       (1<<25)   /* Have ISTAT1, MBOX0, MBOX1 registers */
 504 #define FE_DAC_IN_USE   (1<<26)   /* Platform does DAC cycles */
 505 #define FE_EHP          (1<<27)   /* 720: Even host parity */
 506 #define FE_MUX          (1<<28)   /* 720: Multiplexed bus */
 507 #define FE_EA           (1<<29)   /* 720: Enable Ack */
 508
 509 #define FE_CACHE_SET    (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
 510 #define FE_SCSI_SET     (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
 511 #define FE_SPECIAL_SET  (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
 512 };
 513
 514
 515 /*
 516 **      Driver setup structure.
 517 **
 518 **      This structure is initialized from linux config options.
 519 **      It can be overridden at boot-up by the boot command line.
 520 */
 521 #define SCSI_NCR_MAX_EXCLUDES 8
 522 struct ncr_driver_setup {
 523         u8      master_parity;
 524         u8      scsi_parity;
 525         u8      disconnection;
 526         u8      special_features;
 527         u8      force_sync_nego;
 528         u8      reverse_probe;
 529         u8      pci_fix_up;
 530         u8      use_nvram;
 531         u8      verbose;
 532         u8      default_tags;
 533         u16     default_sync;
 534         u16     debug;
 535         u8      burst_max;
 536         u8      led_pin;
 537         u8      max_wide;
 538         u8      settle_delay;
 539         u8      diff_support;
 540         u8      irqm;
 541         u8      bus_check;
 542         u8      optimize;
 543         u8      recovery;
 544         u8      host_id;
 545         u16     iarb;
 546         u32     excludes[SCSI_NCR_MAX_EXCLUDES];
 547         char    tag_ctrl[100];
 548 };
 549
 550 /*
 551 **      Initial setup.
 552 **      Can be overridden at startup by a command line.
 553 */
 554 #define SCSI_NCR_DRIVER_SETUP                   \
 555 {                                               \
 556         SCSI_NCR_SETUP_MASTER_PARITY,           \
 557         SCSI_NCR_SETUP_SCSI_PARITY,             \
 558         SCSI_NCR_SETUP_DISCONNECTION,           \
 559         SCSI_NCR_SETUP_SPECIAL_FEATURES,        \
 560         SCSI_NCR_SETUP_FORCE_SYNC_NEGO,         \
 561         0,                                      \
 562         0,                                      \
 563         1,                                      \
 564         0,                                      \
 565         SCSI_NCR_SETUP_DEFAULT_TAGS,            \
 566         SCSI_NCR_SETUP_DEFAULT_SYNC,            \
 567         0x00,                                   \
 568         7,                                      \
 569         0,                                      \
 570         1,                                      \
 571         SCSI_NCR_SETUP_SETTLE_TIME,             \
 572         0,                                      \
 573         0,                                      \
 574         1,                                      \
 575         0,                                      \
 576         0,                                      \
 577         255,                                    \
 578         0x00                                    \
 579 }
 580
 581 /*
 582 **      Boot fail safe setup.
 583 **      Override initial setup from boot command line:
 584 **      ncr53c8xx=safe:y
 585 */
 586 #define SCSI_NCR_DRIVER_SAFE_SETUP              \
 587 {                                               \
 588         0,                                      \
 589         1,                                      \
 590         0,                                      \
 591         0,                                      \
 592         0,                                      \
 593         0,                                      \
 594         0,                                      \
 595         1,                                      \
 596         2,                                      \
 597         0,                                      \
 598         255,                                    \
 599         0x00,                                   \
 600         255,                                    \
 601         0,                                      \
 602         0,                                      \
 603         10,                                     \
 604         1,                                      \
 605         1,                                      \
 606         1,                                      \
 607         0,                                      \
 608         0,                                      \
 609         255                                     \
 610 }
 611
 612 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
 613
 614 /*-----------------------------------------------------------------
 615 **
 616 **      The ncr 53c810 register structure.
 617 **
 618 **-----------------------------------------------------------------
 619 */
 620
 621 struct ncr_reg {
 622 /*00*/  u8      nc_scntl0;    /* full arb., ena parity, par->ATN  */
 623
 624 /*01*/  u8      nc_scntl1;    /* no reset                         */
 625         #define   ISCON   0x10  /* connected to scsi                */
 626         #define   CRST    0x08  /* force reset                      */
 627         #define   IARB    0x02  /* immediate arbitration            */
 628
 629 /*02*/  u8      nc_scntl2;    /* no disconnect expected           */
 630         #define   SDU     0x80  /* cmd: disconnect will raise error */
 631         #define   CHM     0x40  /* sta: chained mode                */
 632         #define   WSS     0x08  /* sta: wide scsi send           [W]*/
 633         #define   WSR     0x01  /* sta: wide scsi received       [W]*/
 634
 635 /*03*/  u8      nc_scntl3;    /* cnf system clock dependent       */
 636         #define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
 637         #define   ULTRA   0x80  /* cmd: ULTRA enable                */
 638                                 /* bits 0-2, 7 rsvd for C1010       */
 639
 640 /*04*/  u8      nc_scid;        /* cnf host adapter scsi address    */
 641         #define   RRE     0x40  /* r/w:e enable response to resel.  */
 642         #define   SRE     0x20  /* r/w:e enable response to select  */
 643
 644 /*05*/  u8      nc_sxfer;       /* ### Sync speed and count         */
 645                                 /* bits 6-7 rsvd for C1010          */
 646
 647 /*06*/  u8      nc_sdid;        /* ### Destination-ID               */
 648
 649 /*07*/  u8      nc_gpreg;       /* ??? IO-Pins                      */
 650
 651 /*08*/  u8      nc_sfbr;        /* ### First byte in phase          */
 652
 653 /*09*/  u8      nc_socl;
 654         #define   CREQ    0x80  /* r/w: SCSI-REQ                    */
 655         #define   CACK    0x40  /* r/w: SCSI-ACK                    */
 656         #define   CBSY    0x20  /* r/w: SCSI-BSY                    */
 657         #define   CSEL    0x10  /* r/w: SCSI-SEL                    */
 658         #define   CATN    0x08  /* r/w: SCSI-ATN                    */
 659         #define   CMSG    0x04  /* r/w: SCSI-MSG                    */
 660         #define   CC_D    0x02  /* r/w: SCSI-C_D                    */
 661         #define   CI_O    0x01  /* r/w: SCSI-I_O                    */
 662
 663 /*0a*/  u8      nc_ssid;
 664
 665 /*0b*/  u8      nc_sbcl;
 666
 667 /*0c*/  u8      nc_dstat;
 668         #define   DFE     0x80  /* sta: dma fifo empty              */
 669         #define   MDPE    0x40  /* int: master data parity error    */
 670         #define   BF      0x20  /* int: script: bus fault           */
 671         #define   ABRT    0x10  /* int: script: command aborted     */
 672         #define   SSI     0x08  /* int: script: single step         */
 673         #define   SIR     0x04  /* int: script: interrupt instruct. */
 674         #define   IID     0x01  /* int: script: illegal instruct.   */
 675
 676 /*0d*/  u8      nc_sstat0;
 677         #define   ILF     0x80  /* sta: data in SIDL register lsb   */
 678         #define   ORF     0x40  /* sta: data in SODR register lsb   */
 679         #define   OLF     0x20  /* sta: data in SODL register lsb   */
 680         #define   AIP     0x10  /* sta: arbitration in progress     */
 681         #define   LOA     0x08  /* sta: arbitration lost            */
 682         #define   WOA     0x04  /* sta: arbitration won             */
 683         #define   IRST    0x02  /* sta: scsi reset signal           */
 684         #define   SDP     0x01  /* sta: scsi parity signal          */
 685
 686 /*0e*/  u8      nc_sstat1;
 687         #define   FF3210  0xf0  /* sta: bytes in the scsi fifo      */
 688
 689 /*0f*/  u8      nc_sstat2;
 690         #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
 691         #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
 692         #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
 693         #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
 694         #define   LDSC    0x02  /* sta: disconnect & reconnect      */
 695
 696 /*10*/  u8      nc_dsa; /* --> Base page                    */
 697 /*11*/  u8      nc_dsa1;
 698 /*12*/  u8      nc_dsa2;
 699 /*13*/  u8      nc_dsa3;
 700
 701 /*14*/  u8      nc_istat;       /* --> Main Command and status      */
 702         #define   CABRT   0x80  /* cmd: abort current operation     */
 703         #define   SRST    0x40  /* mod: reset chip                  */
 704         #define   SIGP    0x20  /* r/w: message from host to ncr    */
 705         #define   SEM     0x10  /* r/w: message between host + ncr  */
 706         #define   CON     0x08  /* sta: connected to scsi           */
 707         #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
 708         #define   SIP     0x02  /* sta: scsi-interrupt              */
 709         #define   DIP     0x01  /* sta: host/script interrupt       */
 710
 711 /*15*/  u8      nc_istat1;      /* 896 and later cores only */
 712         #define   FLSH    0x04  /* sta: chip is flushing            */
 713         #define   SRUN    0x02  /* sta: scripts are running         */
 714         #define   SIRQD   0x01  /* r/w: disable INT pin             */
 715
 716 /*16*/  u8      nc_mbox0;       /* 896 and later cores only */
 717 /*17*/  u8      nc_mbox1;       /* 896 and later cores only */
 718
 719 /*18*/  u8      nc_ctest0;
 720         #define   EHP     0x04  /* 720 even host parity             */
 721 /*19*/  u8      nc_ctest1;
 722
 723 /*1a*/  u8      nc_ctest2;
 724         #define   CSIGP   0x40
 725                                 /* bits 0-2,7 rsvd for C1010        */
 726
 727 /*1b*/  u8      nc_ctest3;
 728         #define   FLF     0x08  /* cmd: flush dma fifo              */
 729         #define   CLF     0x04  /* cmd: clear dma fifo              */
 730         #define   FM      0x02  /* mod: fetch pin mode              */
 731         #define   WRIE    0x01  /* mod: write and invalidate enable */
 732                                 /* bits 4-7 rsvd for C1010          */
 733
 734 /*1c*/  u32    nc_temp; /* ### Temporary stack              */
 735
 736 /*20*/  u8      nc_dfifo;
 737 /*21*/  u8      nc_ctest4;
 738         #define   MUX     0x80  /* 720 host bus multiplex mode      */
 739         #define   BDIS    0x80  /* mod: burst disable               */
 740         #define   MPEE    0x08  /* mod: master parity error enable  */
 741
 742 /*22*/  u8      nc_ctest5;
 743         #define   DFS     0x20  /* mod: dma fifo size               */
 744                                 /* bits 0-1, 3-7 rsvd for C1010          */
 745 /*23*/  u8      nc_ctest6;
 746
 747 /*24*/  u32    nc_dbc;  /* ### Byte count and command       */
 748 /*28*/  u32    nc_dnad; /* ### Next command register        */
 749 /*2c*/  u32    nc_dsp;  /* --> Script Pointer               */
 750 /*30*/  u32    nc_dsps; /* --> Script pointer save/opcode#2 */
 751
 752 /*34*/  u8      nc_scratcha;  /* Temporary register a            */
 753 /*35*/  u8      nc_scratcha1;
 754 /*36*/  u8      nc_scratcha2;
 755 /*37*/  u8      nc_scratcha3;
 756
 757 /*38*/  u8      nc_dmode;
 758         #define   BL_2    0x80  /* mod: burst length shift value +2 */
 759         #define   BL_1    0x40  /* mod: burst length shift value +1 */
 760         #define   ERL     0x08  /* mod: enable read line            */
 761         #define   ERMP    0x04  /* mod: enable read multiple        */
 762         #define   BOF     0x02  /* mod: burst op code fetch         */
 763
 764 /*39*/  u8      nc_dien;
 765 /*3a*/  u8      nc_sbr;
 766
 767 /*3b*/  u8      nc_dcntl;       /* --> Script execution control     */
 768         #define   CLSE    0x80  /* mod: cache line size enable      */
 769         #define   PFF     0x40  /* cmd: pre-fetch flush             */
 770         #define   PFEN    0x20  /* mod: pre-fetch enable            */
 771         #define   EA      0x20  /* mod: 720 enable-ack              */
 772         #define   SSM     0x10  /* mod: single step mode            */
 773         #define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
 774         #define   STD     0x04  /* cmd: start dma mode              */
 775         #define   IRQD    0x02  /* mod: irq disable                 */
 776         #define   NOCOM   0x01  /* cmd: protect sfbr while reselect */
 777                                 /* bits 0-1 rsvd for C1010          */
 778
 779 /*3c*/  u32     nc_adder;
 780
 781 /*40*/  u16     nc_sien;        /* -->: interrupt enable            */
 782 /*42*/  u16     nc_sist;        /* <--: interrupt status            */
 783         #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
 784         #define   STO     0x0400/* sta: timeout (select)            */
 785         #define   GEN     0x0200/* sta: timeout (general)           */
 786         #define   HTH     0x0100/* sta: timeout (handshake)         */
 787         #define   MA      0x80  /* sta: phase mismatch              */
 788         #define   CMP     0x40  /* sta: arbitration complete        */
 789         #define   SEL     0x20  /* sta: selected by another device  */
 790         #define   RSL     0x10  /* sta: reselected by another device*/
 791         #define   SGE     0x08  /* sta: gross error (over/underflow)*/
 792         #define   UDC     0x04  /* sta: unexpected disconnect       */
 793         #define   RST     0x02  /* sta: scsi bus reset detected     */
 794         #define   PAR     0x01  /* sta: scsi parity error           */
 795
 796 /*44*/  u8      nc_slpar;
 797 /*45*/  u8      nc_swide;
 798 /*46*/  u8      nc_macntl;
 799 /*47*/  u8      nc_gpcntl;
 800 /*48*/  u8      nc_stime0;    /* cmd: timeout for select&handshake*/
 801 /*49*/  u8      nc_stime1;    /* cmd: timeout user defined        */
 802 /*4a*/  u16   nc_respid;    /* sta: Reselect-IDs                */
 803
 804 /*4c*/  u8      nc_stest0;
 805
 806 /*4d*/  u8      nc_stest1;
 807         #define   SCLK    0x80  /* Use the PCI clock as SCSI clock      */
 808         #define   DBLEN   0x08  /* clock doubler running                */
 809         #define   DBLSEL  0x04  /* clock doubler selected               */
 810
 811
 812 /*4e*/  u8      nc_stest2;
 813         #define   ROF     0x40  /* reset scsi offset (after gross error!) */
 814         #define   DIF     0x20  /* 720 SCSI differential mode             */
 815         #define   EXT     0x02  /* extended filtering                     */
 816
 817 /*4f*/  u8      nc_stest3;
 818         #define   TE     0x80   /* c: tolerAnt enable */
 819         #define   HSC    0x20   /* c: Halt SCSI Clock */
 820         #define   CSF    0x02   /* c: clear scsi fifo */
 821
 822 /*50*/  u16   nc_sidl;  /* Lowlevel: latched from scsi data */
 823 /*52*/  u8      nc_stest4;
 824         #define   SMODE  0xc0   /* SCSI bus mode      (895/6 only) */
 825         #define    SMODE_HVD 0x40       /* High Voltage Differential       */
 826         #define    SMODE_SE  0x80       /* Single Ended                    */
 827         #define    SMODE_LVD 0xc0       /* Low Voltage Differential        */
 828         #define   LCKFRQ 0x20   /* Frequency Lock (895/6 only)     */
 829                                 /* bits 0-5 rsvd for C1010          */
 830
 831 /*53*/  u8      nc_53_;
 832 /*54*/  u16     nc_sodl;        /* Lowlevel: data out to scsi data  */
 833 /*56*/  u8      nc_ccntl0;      /* Chip Control 0 (896)             */
 834         #define   ENPMJ  0x80   /* Enable Phase Mismatch Jump       */
 835         #define   PMJCTL 0x40   /* Phase Mismatch Jump Control      */
 836         #define   ENNDJ  0x20   /* Enable Non Data PM Jump          */
 837         #define   DISFC  0x10   /* Disable Auto FIFO Clear          */
 838         #define   DILS   0x02   /* Disable Internal Load/Store      */
 839         #define   DPR    0x01   /* Disable Pipe Req                 */
 840
 841 /*57*/  u8      nc_ccntl1;      /* Chip Control 1 (896)             */
 842         #define   ZMOD   0x80   /* High Impedance Mode              */
 843         #define   DIC    0x10   /* Disable Internal Cycles          */
 844         #define   DDAC   0x08   /* Disable Dual Address Cycle       */
 845         #define   XTIMOD 0x04   /* 64-bit Table Ind. Indexing Mode  */
 846         #define   EXTIBMV 0x02  /* Enable 64-bit Table Ind. BMOV    */
 847         #define   EXDBMV 0x01   /* Enable 64-bit Direct BMOV        */
 848
 849 /*58*/  u16     nc_sbdl;        /* Lowlevel: data from scsi data    */
 850 /*5a*/  u16     nc_5a_;
 851
 852 /*5c*/  u8      nc_scr0;        /* Working register B               */
 853 /*5d*/  u8      nc_scr1;        /*                                  */
 854 /*5e*/  u8      nc_scr2;        /*                                  */
 855 /*5f*/  u8      nc_scr3;        /*                                  */
 856
 857 /*60*/  u8      nc_scrx[64];    /* Working register C-R             */
 858 /*a0*/  u32     nc_mmrs;        /* Memory Move Read Selector        */
 859 /*a4*/  u32     nc_mmws;        /* Memory Move Write Selector       */
 860 /*a8*/  u32     nc_sfs;         /* Script Fetch Selector            */
 861 /*ac*/  u32     nc_drs;         /* DSA Relative Selector            */
 862 /*b0*/  u32     nc_sbms;        /* Static Block Move Selector       */
 863 /*b4*/  u32     nc_dbms;        /* Dynamic Block Move Selector      */
 864 /*b8*/  u32     nc_dnad64;      /* DMA Next Address 64              */
 865 /*bc*/  u16     nc_scntl4;      /* C1010 only                       */
 866         #define   U3EN   0x80   /* Enable Ultra 3                   */
 867         #define   AIPEN  0x40   /* Allow check upper byte lanes     */
 868         #define   XCLKH_DT 0x08 /* Extra clock of data hold on DT
 869                                         transfer edge               */
 870         #define   XCLKH_ST 0x04 /* Extra clock of data hold on ST
 871                                         transfer edge               */
 872
 873 /*be*/  u8      nc_aipcntl0;    /* Epat Control 1 C1010 only        */
 874 /*bf*/  u8      nc_aipcntl1;    /* AIP Control C1010_66 Only        */
 875
 876 /*c0*/  u32     nc_pmjad1;      /* Phase Mismatch Jump Address 1    */
 877 /*c4*/  u32     nc_pmjad2;      /* Phase Mismatch Jump Address 2    */
 878 /*c8*/  u8      nc_rbc;         /* Remaining Byte Count             */
 879 /*c9*/  u8      nc_rbc1;        /*                                  */
 880 /*ca*/  u8      nc_rbc2;        /*                                  */
 881 /*cb*/  u8      nc_rbc3;        /*                                  */
 882
 883 /*cc*/  u8      nc_ua;          /* Updated Address                  */
 884 /*cd*/  u8      nc_ua1;         /*                                  */
 885 /*ce*/  u8      nc_ua2;         /*                                  */
 886 /*cf*/  u8      nc_ua3;         /*                                  */
 887 /*d0*/  u32     nc_esa;         /* Entry Storage Address            */
 888 /*d4*/  u8      nc_ia;          /* Instruction Address              */
 889 /*d5*/  u8      nc_ia1;
 890 /*d6*/  u8      nc_ia2;
 891 /*d7*/  u8      nc_ia3;
 892 /*d8*/  u32     nc_sbc;         /* SCSI Byte Count (3 bytes only)   */
 893 /*dc*/  u32     nc_csbc;        /* Cumulative SCSI Byte Count       */
 894
 895                                 /* Following for C1010 only         */
 896 /*e0*/  u16     nc_crcpad;      /* CRC Value                        */
 897 /*e2*/  u8      nc_crccntl0;    /* CRC control register             */
 898         #define   SNDCRC  0x10  /* Send CRC Request                 */
 899 /*e3*/  u8      nc_crccntl1;    /* CRC control register             */
 900 /*e4*/  u32     nc_crcdata;     /* CRC data register                */
 901 /*e8*/  u32     nc_e8_;         /* rsvd                             */
 902 /*ec*/  u32     nc_ec_;         /* rsvd                             */
 903 /*f0*/  u16     nc_dfbc;        /* DMA FIFO byte count              */
 904
 905 };
 906
 907 /*-----------------------------------------------------------
 908 **
 909 **      Utility macros for the script.
 910 **
 911 **-----------------------------------------------------------
 912 */
 913
 914 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
 915 #define REG(r) REGJ (nc_, r)
 916
 917 typedef u32 ncrcmd;
 918
 919 /*-----------------------------------------------------------
 920 **
 921 **      SCSI phases
 922 **
 923 **      DT phases illegal for ncr driver.
 924 **
 925 **-----------------------------------------------------------
 926 */
 927
 928 #define SCR_DATA_OUT    0x00000000
 929 #define SCR_DATA_IN     0x01000000
 930 #define SCR_COMMAND     0x02000000
 931 #define SCR_STATUS      0x03000000
 932 #define SCR_DT_DATA_OUT 0x04000000
 933 #define SCR_DT_DATA_IN  0x05000000
 934 #define SCR_MSG_OUT     0x06000000
 935 #define SCR_MSG_IN      0x07000000
 936
 937 #define SCR_ILG_OUT     0x04000000
 938 #define SCR_ILG_IN      0x05000000
 939
 940 /*-----------------------------------------------------------
 941 **
 942 **      Data transfer via SCSI.
 943 **
 944 **-----------------------------------------------------------
 945 **
 946 **      MOVE_ABS (LEN)
 947 **      <<start address>>
 948 **
 949 **      MOVE_IND (LEN)
 950 **      <<dnad_offset>>
 951 **
 952 **      MOVE_TBL
 953 **      <<dnad_offset>>
 954 **
 955 **-----------------------------------------------------------
 956 */
 957
 958 #define OPC_MOVE          0x08000000
 959
 960 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
 961 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
 962 #define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
 963
 964 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
 965 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
 966 #define SCR_CHMOV_TBL     (0x10000000)
 967
 968 struct scr_tblmove {
 969         u32  size;
 970         u32  addr;
 971 };
 972
 973 /*-----------------------------------------------------------
 974 **
 975 **      Selection
 976 **
 977 **-----------------------------------------------------------
 978 **
 979 **      SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
 980 **      <<alternate_address>>
 981 **
 982 **      SEL_TBL | << dnad_offset>>  [ | REL_JMP]
 983 **      <<alternate_address>>
 984 **
 985 **-----------------------------------------------------------
 986 */
 987
 988 #define SCR_SEL_ABS     0x40000000
 989 #define SCR_SEL_ABS_ATN 0x41000000
 990 #define SCR_SEL_TBL     0x42000000
 991 #define SCR_SEL_TBL_ATN 0x43000000
 992
 993
 994 #ifdef SCSI_NCR_BIG_ENDIAN
 995 struct scr_tblsel {
 996         u8      sel_scntl3;
 997         u8      sel_id;
 998         u8      sel_sxfer;
 999         u8      sel_scntl4;
1000 };
1001 #else
1002 struct scr_tblsel {
1003         u8      sel_scntl4;
1004         u8      sel_sxfer;
1005         u8      sel_id;
1006         u8      sel_scntl3;
1007 };
1008 #endif
1009
1010 #define SCR_JMP_REL     0x04000000
1011 #define SCR_ID(id)      (((u32)(id)) << 16)
1012
1013 /*-----------------------------------------------------------
1014 **
1015 **      Waiting for Disconnect or Reselect
1016 **
1017 **-----------------------------------------------------------
1018 **
1019 **      WAIT_DISC
1020 **      dummy: <<alternate_address>>
1021 **
1022 **      WAIT_RESEL
1023 **      <<alternate_address>>
1024 **
1025 **-----------------------------------------------------------
1026 */
1027
1028 #define SCR_WAIT_DISC   0x48000000
1029 #define SCR_WAIT_RESEL  0x50000000
1030
1031 /*-----------------------------------------------------------
1032 **
1033 **      Bit Set / Reset
1034 **
1035 **-----------------------------------------------------------
1036 **
1037 **      SET (flags {|.. })
1038 **
1039 **      CLR (flags {|.. })
1040 **
1041 **-----------------------------------------------------------
1042 */
1043
1044 #define SCR_SET(f)     (0x58000000 | (f))
1045 #define SCR_CLR(f)     (0x60000000 | (f))
1046
1047 #define SCR_CARRY       0x00000400
1048 #define SCR_TRG         0x00000200
1049 #define SCR_ACK         0x00000040
1050 #define SCR_ATN         0x00000008
1051
1052
1053
1054
1055 /*-----------------------------------------------------------
1056 **
1057 **      Memory to memory move
1058 **
1059 **-----------------------------------------------------------
1060 **
1061 **      COPY (bytecount)
1062 **      << source_address >>
1063 **      << destination_address >>
1064 **
1065 **      SCR_COPY   sets the NO FLUSH option by default.
1066 **      SCR_COPY_F does not set this option.
1067 **
1068 **      For chips which do not support this option,
1069 **      ncr_copy_and_bind() will remove this bit.
1070 **-----------------------------------------------------------
1071 */
1072
1073 #define SCR_NO_FLUSH 0x01000000
1074
1075 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1076 #define SCR_COPY_F(n) (0xc0000000 | (n))
1077
1078 /*-----------------------------------------------------------
1079 **
1080 **      Register move and binary operations
1081 **
1082 **-----------------------------------------------------------
1083 **
1084 **      SFBR_REG (reg, op, data)        reg  = SFBR op data
1085 **      << 0 >>
1086 **
1087 **      REG_SFBR (reg, op, data)        SFBR = reg op data
1088 **      << 0 >>
1089 **
1090 **      REG_REG  (reg, op, data)        reg  = reg op data
1091 **      << 0 >>
1092 **
1093 **-----------------------------------------------------------
1094 **      On 810A, 860, 825A, 875, 895 and 896 chips the content
1095 **      of SFBR register can be used as data (SCR_SFBR_DATA).
1096 **      The 896 has additional IO registers starting at
1097 **      offset 0x80. Bit 7 of register offset is stored in
1098 **      bit 7 of the SCRIPTS instruction first DWORD.
1099 **-----------------------------------------------------------
1100 */
1101
1102 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1103
1104 #define SCR_SFBR_REG(reg,op,data) \
1105         (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1106
1107 #define SCR_REG_SFBR(reg,op,data) \
1108         (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1109
1110 #define SCR_REG_REG(reg,op,data) \
1111         (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1112
1113
1114 #define      SCR_LOAD   0x00000000
1115 #define      SCR_SHL    0x01000000
1116 #define      SCR_OR     0x02000000
1117 #define      SCR_XOR    0x03000000
1118 #define      SCR_AND    0x04000000
1119 #define      SCR_SHR    0x05000000
1120 #define      SCR_ADD    0x06000000
1121 #define      SCR_ADDC   0x07000000
1122
1123 #define      SCR_SFBR_DATA   (0x00800000>>8ul)  /* Use SFBR as data */
1124
1125 /*-----------------------------------------------------------
1126 **
1127 **      FROM_REG (reg)            SFBR = reg
1128 **      << 0 >>
1129 **
1130 **      TO_REG   (reg)            reg  = SFBR
1131 **      << 0 >>
1132 **
1133 **      LOAD_REG (reg, data)      reg  = <data>
1134 **      << 0 >>
1135 **
1136 **      LOAD_SFBR(data)           SFBR = <data>
1137 **      << 0 >>
1138 **
1139 **-----------------------------------------------------------
1140 */
1141
1142 #define SCR_FROM_REG(reg) \
1143         SCR_REG_SFBR(reg,SCR_OR,0)
1144
1145 #define SCR_TO_REG(reg) \
1146         SCR_SFBR_REG(reg,SCR_OR,0)
1147
1148 #define SCR_LOAD_REG(reg,data) \
1149         SCR_REG_REG(reg,SCR_LOAD,data)
1150
1151 #define SCR_LOAD_SFBR(data) \
1152         (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1153
1154 /*-----------------------------------------------------------
1155 **
1156 **      LOAD  from memory   to register.
1157 **      STORE from register to memory.
1158 **
1159 **      Only supported by 810A, 860, 825A, 875, 895 and 896.
1160 **
1161 **-----------------------------------------------------------
1162 **
1163 **      LOAD_ABS (LEN)
1164 **      <<start address>>
1165 **
1166 **      LOAD_REL (LEN)        (DSA relative)
1167 **      <<dsa_offset>>
1168 **
1169 **-----------------------------------------------------------
1170 */
1171
1172 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1173 #define SCR_NO_FLUSH2   0x02000000
1174 #define SCR_DSA_REL2    0x10000000
1175
1176 #define SCR_LOAD_R(reg, how, n) \
1177         (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1178
1179 #define SCR_STORE_R(reg, how, n) \
1180         (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1181
1182 #define SCR_LOAD_ABS(reg, n)    SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1183 #define SCR_LOAD_REL(reg, n)    SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1184 #define SCR_LOAD_ABS_F(reg, n)  SCR_LOAD_R(reg, 0, n)
1185 #define SCR_LOAD_REL_F(reg, n)  SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1186
1187 #define SCR_STORE_ABS(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1188 #define SCR_STORE_REL(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1189 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1190 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1191
1192
1193 /*-----------------------------------------------------------
1194 **
1195 **      Waiting for Disconnect or Reselect
1196 **
1197 **-----------------------------------------------------------
1198 **
1199 **      JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
1200 **      <<address>>
1201 **
1202 **      JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
1203 **      <<distance>>
1204 **
1205 **      CALL            [ | IFTRUE/IFFALSE ( ... ) ]
1206 **      <<address>>
1207 **
1208 **      CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
1209 **      <<distance>>
1210 **
1211 **      RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
1212 **      <<dummy>>
1213 **
1214 **      INT             [ | IFTRUE/IFFALSE ( ... ) ]
1215 **      <<ident>>
1216 **
1217 **      INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
1218 **      <<ident>>
1219 **
1220 **      Conditions:
1221 **           WHEN (phase)
1222 **           IF   (phase)
1223 **           CARRYSET
1224 **           DATA (data, mask)
1225 **
1226 **-----------------------------------------------------------
1227 */
1228
1229 #define SCR_NO_OP       0x80000000
1230 #define SCR_JUMP        0x80080000
1231 #define SCR_JUMP64      0x80480000
1232 #define SCR_JUMPR       0x80880000
1233 #define SCR_CALL        0x88080000
1234 #define SCR_CALLR       0x88880000
1235 #define SCR_RETURN      0x90080000
1236 #define SCR_INT         0x98080000
1237 #define SCR_INT_FLY     0x98180000
1238
1239 #define IFFALSE(arg)   (0x00080000 | (arg))
1240 #define IFTRUE(arg)    (0x00000000 | (arg))
1241
1242 #define WHEN(phase)    (0x00030000 | (phase))
1243 #define IF(phase)      (0x00020000 | (phase))
1244
1245 #define DATA(D)        (0x00040000 | ((D) & 0xff))
1246 #define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1247
1248 #define CARRYSET       (0x00200000)
1249
1250 /*-----------------------------------------------------------
1251 **
1252 **      SCSI  constants.
1253 **
1254 **-----------------------------------------------------------
1255 */
1256
1257 /*
1258 **      Status
1259 */
1260
1261 #define S_GOOD          (0x00)
1262 #define S_CHECK_COND    (0x02)
1263 #define S_COND_MET      (0x04)
1264 #define S_BUSY          (0x08)
1265 #define S_INT           (0x10)
1266 #define S_INT_COND_MET  (0x14)
1267 #define S_CONFLICT      (0x18)
1268 #define S_TERMINATED    (0x20)
1269 #define S_QUEUE_FULL    (0x28)
1270 #define S_ILLEGAL       (0xff)
1271 #define S_SENSE         (0x80)
1272
1273 /*
1274  * End of ncrreg from FreeBSD
1275  */
1276
1277 /*
1278         Build a scatter/gather entry.
1279         see sym53c8xx_2/sym_hipd.h for more detailed sym_build_sge()
1280         implementation ;)
1281  */
1282
1283 #define ncr_build_sge(np, data, badd, len)      \
1284 do {                                            \
1285         (data)->addr = cpu_to_scr(badd);        \
1286         (data)->size = cpu_to_scr(len);         \
1287 } while (0)
1288
1289 /*==========================================================
1290 **
1291 **      Structures used by the detection routine to transmit
1292 **      device configuration to the attach function.
1293 **
1294 **==========================================================
1295 */
1296 struct ncr_slot {
1297         u_long  base;
1298         u_long  base_2;
1299         u_long  base_c;
1300         u_long  base_2_c;
1301         void __iomem *base_v;
1302         void __iomem *base_2_v;
1303         int     irq;
1304 /* port and reg fields to use INB, OUTB macros */
1305         volatile struct ncr_reg __iomem *reg;
1306 };
1307
1308 /*==========================================================
1309 **
1310 **      Structure used by detection routine to save data on
1311 **      each detected board for attach.
1312 **
1313 **==========================================================
1314 */
1315 struct ncr_device {
1316         struct device  *dev;
1317         struct ncr_slot  slot;
1318         struct ncr_chip  chip;
1319         u_char host_id;
1320         u8 differential;
1321 };
1322
1323 extern struct Scsi_Host *ncr_attach(struct scsi_host_template *tpnt, int unit, struct ncr_device *device);
1324 extern void ncr53c8xx_release(struct Scsi_Host *host);
1325 irqreturn_t ncr53c8xx_intr(int irq, void *dev_id);
1326 extern int ncr53c8xx_init(void);
1327 extern void ncr53c8xx_exit(void);
1328
1329 #endif /* NCR53C8XX_H */