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Merge master.kernel.org:/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / sbus / char / bpp.c
1 /*
2 * drivers/sbus/char/bpp.c
3 *
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
7 *
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
10 */
11
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/fs.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/smp_lock.h>
19 #include <linux/spinlock.h>
20 #include <linux/timer.h>
21 #include <linux/ioport.h>
22 #include <linux/major.h>
23 #include <linux/devfs_fs_kernel.h>
24
25 #include <asm/uaccess.h>
26 #include <asm/io.h>
27
28 #if defined(__i386__)
29 # include <asm/system.h>
30 #endif
31
32 #if defined(__sparc__)
33 # include <linux/init.h>
34 # include <linux/delay.h> /* udelay() */
35
36 # include <asm/oplib.h> /* OpenProm Library */
37 # include <asm/sbus.h>
38 #endif
39
40 #include <asm/bpp.h>
41
42 #define BPP_PROBE_CODE 0x55
43 #define BPP_DELAY 100
44
45 static const unsigned BPP_MAJOR = LP_MAJOR;
46 static const char* dev_name = "bpp";
47
48 /* When switching from compatibility to a mode where I can read, try
49 the following mode first. */
50
51 /* const unsigned char DEFAULT_ECP = 0x10; */
52 static const unsigned char DEFAULT_ECP = 0x30;
53 static const unsigned char DEFAULT_NIBBLE = 0x00;
54
55 /*
56 * These are 1284 time constraints, in units of jiffies.
57 */
58
59 static const unsigned long TIME_PSetup = 1;
60 static const unsigned long TIME_PResponse = 6;
61 static const unsigned long TIME_IDLE_LIMIT = 2000;
62
63 /*
64 * One instance per supported subdevice...
65 */
66 # define BPP_NO 3
67
68 enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
69
70 struct inst {
71 unsigned present : 1; /* True if the hardware exists */
72 unsigned enhanced : 1; /* True if the hardware in "enhanced" */
73 unsigned opened : 1; /* True if the device is opened already */
74 unsigned run_flag : 1; /* True if waiting for a repeate byte */
75
76 unsigned char direction; /* 0 --> out, 0x20 --> IN */
77 unsigned char pp_state; /* State of host controlled pins. */
78 enum IEEE_Mode mode;
79
80 unsigned char run_length;
81 unsigned char repeat_byte;
82 };
83
84 static struct inst instances[BPP_NO];
85
86 #if defined(__i386__)
87
88 static const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
89
90 /*
91 * These are for data access.
92 * Control lines accesses are hidden in set_bits() and get_bits().
93 * The exception is the probe procedure, which is system-dependent.
94 */
95 #define bpp_outb_p(data, base) outb_p((data), (base))
96 #define bpp_inb(base) inb(base)
97 #define bpp_inb_p(base) inb_p(base)
98
99 /*
100 * This method takes the pin values mask and sets the hardware pins to
101 * the requested value: 1 == high voltage, 0 == low voltage. This
102 * burries the annoying PC bit inversion and preserves the direction
103 * flag.
104 */
105 static void set_pins(unsigned short pins, unsigned minor)
106 {
107 unsigned char bits = instances[minor].direction; /* == 0x20 */
108
109 if (! (pins & BPP_PP_nStrobe)) bits |= 1;
110 if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
111 if ( pins & BPP_PP_nInit) bits |= 4;
112 if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
113
114 instances[minor].pp_state = bits;
115
116 outb_p(bits, base_addrs[minor]+2);
117 }
118
119 static unsigned short get_pins(unsigned minor)
120 {
121 unsigned short bits = 0;
122
123 unsigned value = instances[minor].pp_state;
124 if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
125 if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
126 if (value & 0x04) bits |= BPP_PP_nInit;
127 if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
128
129 value = inb_p(base_addrs[minor]+1);
130 if (value & 0x08) bits |= BPP_GP_nFault;
131 if (value & 0x10) bits |= BPP_GP_Select;
132 if (value & 0x20) bits |= BPP_GP_PError;
133 if (value & 0x40) bits |= BPP_GP_nAck;
134 if (! (value & 0x80)) bits |= BPP_GP_Busy;
135
136 return bits;
137 }
138
139 #endif /* __i386__ */
140
141 #if defined(__sparc__)
142
143 /*
144 * Register block
145 */
146 /* DMA registers */
147 #define BPP_CSR 0x00
148 #define BPP_ADDR 0x04
149 #define BPP_BCNT 0x08
150 #define BPP_TST_CSR 0x0C
151 /* Parallel Port registers */
152 #define BPP_HCR 0x10
153 #define BPP_OCR 0x12
154 #define BPP_DR 0x14
155 #define BPP_TCR 0x15
156 #define BPP_OR 0x16
157 #define BPP_IR 0x17
158 #define BPP_ICR 0x18
159 #define BPP_SIZE 0x1A
160
161 /* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
162 #define P_DEV_ID_MASK 0xf0000000 /* R */
163 #define P_DEV_ID_ZEBRA 0x40000000
164 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
165 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
166 #define P_A_LOADED 0x04000000 /* R */
167 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
168 #define P_EN_NEXT 0x01000000 /* RW */
169 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
170 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
171 of P-FIFO on loading of P_ADDR*/
172 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
173 #define P_BURST_8 0x00000000
174 #define P_BURST_4 0x00040000
175 #define P_BURST_1 0x00080000 /* "No burst" write */
176 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
177 P_EN_NEXT=1 */
178 #define P_EN_CNT 0x00002000 /* RW */
179 #define P_EN_DMA 0x00000200 /* RW */
180 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
181 #define P_RESET 0x00000080 /* RW */
182 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
183 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
184 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
185 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
186 #define P_ERR_PEND 0x00000002 /* R */
187 #define P_INT_PEND 0x00000001 /* R */
188
189 /* BPP_HCR. Time is in increments of SBus clock. */
190 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
191 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
192 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
193
194 /* BPP_OCR. */
195 #define P_OCR_MEM_CLR 0x8000
196 #define P_OCR_DATA_SRC 0x4000 /* ) */
197 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
198 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
199 #define P_OCR_ACK_DSEL 0x0800 /* ) */
200 #define P_OCR_EN_DIAG 0x0400
201 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
202 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
203 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
204 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
205 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
206 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
207
208 /* BPP_TCR */
209 #define P_TCR_DIR 0x08
210 #define P_TCR_BUSY 0x04
211 #define P_TCR_ACK 0x02
212 #define P_TCR_DS 0x01 /* Strobe */
213
214 /* BPP_OR */
215 #define P_OR_V3 0x20 /* ) */
216 #define P_OR_V2 0x10 /* ) on Zebra only */
217 #define P_OR_V1 0x08 /* ) */
218 #define P_OR_INIT 0x04
219 #define P_OR_AFXN 0x02 /* Auto Feed */
220 #define P_OR_SLCT_IN 0x01
221
222 /* BPP_IR */
223 #define P_IR_PE 0x04
224 #define P_IR_SLCT 0x02
225 #define P_IR_ERR 0x01
226
227 /* BPP_ICR */
228 #define P_DS_IRQ 0x8000 /* RW1 */
229 #define P_ACK_IRQ 0x4000 /* RW1 */
230 #define P_BUSY_IRQ 0x2000 /* RW1 */
231 #define P_PE_IRQ 0x1000 /* RW1 */
232 #define P_SLCT_IRQ 0x0800 /* RW1 */
233 #define P_ERR_IRQ 0x0400 /* RW1 */
234 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
235 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
236 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
237 #define P_BUSY_IRQ_EN 0x0040 /* RW */
238 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
239 #define P_PE_IRQ_EN 0x0010 /* RW */
240 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
241 #define P_SLCT_IRQ_EN 0x0004 /* RW */
242 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
243 #define P_ERR_IRQ_EN 0x0001 /* RW */
244
245 static void __iomem *base_addrs[BPP_NO];
246
247 #define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
248 #define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
249 #define bpp_inb(base) sbus_readb((base) + BPP_DR)
250
251 static void set_pins(unsigned short pins, unsigned minor)
252 {
253 void __iomem *base = base_addrs[minor];
254 unsigned char bits_tcr = 0, bits_or = 0;
255
256 if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
257 if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
258
259 if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
260 if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
261 if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
262
263 sbus_writeb(bits_or, base + BPP_OR);
264 sbus_writeb(bits_tcr, base + BPP_TCR);
265 }
266
267 /*
268 * i386 people read output pins from a software image.
269 * We may get them back from hardware.
270 * Again, inversion of pins must he buried here.
271 */
272 static unsigned short get_pins(unsigned minor)
273 {
274 void __iomem *base = base_addrs[minor];
275 unsigned short bits = 0;
276 unsigned value_tcr = sbus_readb(base + BPP_TCR);
277 unsigned value_ir = sbus_readb(base + BPP_IR);
278 unsigned value_or = sbus_readb(base + BPP_OR);
279
280 if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
281 if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
282 if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
283 if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
284
285 if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
286 if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
287 if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
288 if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
289 if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
290
291 return bits;
292 }
293
294 #endif /* __sparc__ */
295
296 static void snooze(unsigned long snooze_time, unsigned minor)
297 {
298 schedule_timeout_uninterruptible(snooze_time + 1);
299 }
300
301 static int wait_for(unsigned short set, unsigned short clr,
302 unsigned long delay, unsigned minor)
303 {
304 unsigned short pins = get_pins(minor);
305
306 unsigned long extime = 0;
307
308 /*
309 * Try a real fast scan for the first jiffy, in case the device
310 * responds real good. The first while loop guesses an expire
311 * time accounting for possible wraparound of jiffies.
312 */
313 while (time_after_eq(jiffies, extime)) extime = jiffies + 1;
314 while ( (time_before(jiffies, extime))
315 && (((pins & set) != set) || ((pins & clr) != 0)) ) {
316 pins = get_pins(minor);
317 }
318
319 delay -= 1;
320
321 /*
322 * If my delay expired or the pins are still not where I want
323 * them, then resort to using the timer and greatly reduce my
324 * sample rate. If the peripheral is going to be slow, this will
325 * give the CPU up to some more worthy process.
326 */
327 while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
328
329 snooze(1, minor);
330 pins = get_pins(minor);
331 delay -= 1;
332 }
333
334 if (delay == 0) return -1;
335 else return pins;
336 }
337
338 /*
339 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
340 * errno means something broke, and I do not yet know how to fix it.
341 */
342 static int negotiate(unsigned char mode, unsigned minor)
343 {
344 int rc;
345 unsigned short pins = get_pins(minor);
346 if (pins & BPP_PP_nSelectIn) return -EIO;
347
348
349 /* Event 0: Write the mode to the data lines */
350 bpp_outb_p(mode, base_addrs[minor]);
351
352 snooze(TIME_PSetup, minor);
353
354 /* Event 1: Strobe the mode code into the peripheral */
355 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
356
357 /* Wait for Event 2: Peripheral responds as a 1284 device. */
358 rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
359 BPP_GP_nAck,
360 TIME_PResponse,
361 minor);
362
363 if (rc == -1) return -ETIMEDOUT;
364
365 /* Event 3: latch extensibility request */
366 set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
367
368 /* ... quick nap while peripheral ponders the byte i'm sending...*/
369 snooze(1, minor);
370
371 /* Event 4: restore strobe, to ACK peripheral's response. */
372 set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
373
374 /* Wait for Event 6: Peripheral latches response bits */
375 rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
376 if (rc == -1) return -EIO;
377
378 /* A 1284 device cannot refuse nibble mode */
379 if (mode == DEFAULT_NIBBLE) return 0;
380
381 if (pins & BPP_GP_Select) return 0;
382
383 return -EPROTONOSUPPORT;
384 }
385
386 static int terminate(unsigned minor)
387 {
388 int rc;
389
390 /* Event 22: Request termination of 1284 mode */
391 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
392
393 /* Wait for Events 23 and 24: ACK termination request. */
394 rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
395 BPP_GP_nAck,
396 TIME_PSetup+TIME_PResponse,
397 minor);
398
399 instances[minor].direction = 0;
400 instances[minor].mode = COMPATIBILITY;
401
402 if (rc == -1) {
403 return -EIO;
404 }
405
406 /* Event 25: Handshake by lowering nAutoFd */
407 set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
408
409 /* Event 26: Peripheral wiggles lines... */
410
411 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
412 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
413 if (rc == -1) {
414 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
415 return -EIO;
416 }
417
418 /* Event 28: Finish phase by raising nAutoFd */
419 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
420
421 return 0;
422 }
423
424 static DEFINE_SPINLOCK(bpp_open_lock);
425
426 /*
427 * Allow only one process to open the device at a time.
428 */
429 static int bpp_open(struct inode *inode, struct file *f)
430 {
431 unsigned minor = iminor(inode);
432 int ret;
433
434 spin_lock(&bpp_open_lock);
435 ret = 0;
436 if (minor >= BPP_NO) {
437 ret = -ENODEV;
438 } else {
439 if (! instances[minor].present) {
440 ret = -ENODEV;
441 } else {
442 if (instances[minor].opened)
443 ret = -EBUSY;
444 else
445 instances[minor].opened = 1;
446 }
447 }
448 spin_unlock(&bpp_open_lock);
449
450 return ret;
451 }
452
453 /*
454 * When the process closes the device, this method is called to clean
455 * up and reset the hardware. Always leave the device in compatibility
456 * mode as this is a reasonable place to clean up from messes made by
457 * ioctls, or other mayhem.
458 */
459 static int bpp_release(struct inode *inode, struct file *f)
460 {
461 unsigned minor = iminor(inode);
462
463 spin_lock(&bpp_open_lock);
464 instances[minor].opened = 0;
465
466 if (instances[minor].mode != COMPATIBILITY)
467 terminate(minor);
468
469 spin_unlock(&bpp_open_lock);
470
471 return 0;
472 }
473
474 static long read_nibble(unsigned minor, char __user *c, unsigned long cnt)
475 {
476 unsigned long remaining = cnt;
477 long rc;
478
479 while (remaining > 0) {
480 unsigned char byte = 0;
481 int pins;
482
483 /* Event 7: request nibble */
484 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
485
486 /* Wait for event 9: Peripher strobes first nibble */
487 pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
488 if (pins == -1) return -ETIMEDOUT;
489
490 /* Event 10: I handshake nibble */
491 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
492 if (pins & BPP_GP_nFault) byte |= 0x01;
493 if (pins & BPP_GP_Select) byte |= 0x02;
494 if (pins & BPP_GP_PError) byte |= 0x04;
495 if (pins & BPP_GP_Busy) byte |= 0x08;
496
497 /* Wait for event 11: Peripheral handshakes nibble */
498 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
499
500 /* Event 7: request nibble */
501 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
502
503 /* Wait for event 9: Peripher strobes first nibble */
504 pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
505 if (rc == -1) return -ETIMEDOUT;
506
507 /* Event 10: I handshake nibble */
508 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
509 if (pins & BPP_GP_nFault) byte |= 0x10;
510 if (pins & BPP_GP_Select) byte |= 0x20;
511 if (pins & BPP_GP_PError) byte |= 0x40;
512 if (pins & BPP_GP_Busy) byte |= 0x80;
513
514 if (put_user(byte, c))
515 return -EFAULT;
516 c += 1;
517 remaining -= 1;
518
519 /* Wait for event 11: Peripheral handshakes nibble */
520 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
521 if (rc == -1) return -EIO;
522 }
523
524 return cnt - remaining;
525 }
526
527 static long read_ecp(unsigned minor, char __user *c, unsigned long cnt)
528 {
529 unsigned long remaining;
530 long rc;
531
532 /* Turn ECP mode from forward to reverse if needed. */
533 if (! instances[minor].direction) {
534 unsigned short pins = get_pins(minor);
535
536 /* Event 38: Turn the bus around */
537 instances[minor].direction = 0x20;
538 pins &= ~BPP_PP_nAutoFd;
539 set_pins(pins, minor);
540
541 /* Event 39: Set pins for reverse mode. */
542 snooze(TIME_PSetup, minor);
543 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
544
545 /* Wait for event 40: Peripheral ready to be strobed */
546 rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
547 if (rc == -1) return -ETIMEDOUT;
548 }
549
550 remaining = cnt;
551
552 while (remaining > 0) {
553
554 /* If there is a run length for a repeated byte, repeat */
555 /* that byte a few times. */
556 if (instances[minor].run_length && !instances[minor].run_flag) {
557
558 char buffer[128];
559 unsigned idx;
560 unsigned repeat = remaining < instances[minor].run_length
561 ? remaining
562 : instances[minor].run_length;
563
564 for (idx = 0 ; idx < repeat ; idx += 1)
565 buffer[idx] = instances[minor].repeat_byte;
566
567 if (copy_to_user(c, buffer, repeat))
568 return -EFAULT;
569 remaining -= repeat;
570 c += repeat;
571 instances[minor].run_length -= repeat;
572 }
573
574 if (remaining == 0) break;
575
576
577 /* Wait for Event 43: Data active on the bus. */
578 rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
579 if (rc == -1) break;
580
581 if (rc & BPP_GP_Busy) {
582 /* OK, this is data. read it in. */
583 unsigned char byte = bpp_inb(base_addrs[minor]);
584 if (put_user(byte, c))
585 return -EFAULT;
586 c += 1;
587 remaining -= 1;
588
589 if (instances[minor].run_flag) {
590 instances[minor].repeat_byte = byte;
591 instances[minor].run_flag = 0;
592 }
593
594 } else {
595 unsigned char byte = bpp_inb(base_addrs[minor]);
596 if (byte & 0x80) {
597 printk("bpp%d: "
598 "Ignoring ECP channel %u from device.\n",
599 minor, byte & 0x7f);
600 } else {
601 instances[minor].run_length = byte;
602 instances[minor].run_flag = 1;
603 }
604 }
605
606 /* Event 44: I got it. */
607 set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
608
609 /* Wait for event 45: peripheral handshake */
610 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
611 if (rc == -1) return -ETIMEDOUT;
612
613 /* Event 46: Finish handshake */
614 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
615
616 }
617
618
619 return cnt - remaining;
620 }
621
622 static ssize_t bpp_read(struct file *f, char __user *c, size_t cnt, loff_t * ppos)
623 {
624 long rc;
625 unsigned minor = iminor(f->f_dentry->d_inode);
626 if (minor >= BPP_NO) return -ENODEV;
627 if (!instances[minor].present) return -ENODEV;
628
629 switch (instances[minor].mode) {
630
631 default:
632 if (instances[minor].mode != COMPATIBILITY)
633 terminate(minor);
634
635 if (instances[minor].enhanced) {
636 /* For now, do all reads with ECP-RLE mode */
637 unsigned short pins;
638
639 rc = negotiate(DEFAULT_ECP, minor);
640 if (rc < 0) break;
641
642 instances[minor].mode = ECP_RLE;
643
644 /* Event 30: set nAutoFd low to setup for ECP mode */
645 pins = get_pins(minor);
646 pins &= ~BPP_PP_nAutoFd;
647 set_pins(pins, minor);
648
649 /* Wait for Event 31: peripheral ready */
650 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
651 if (rc == -1) return -ETIMEDOUT;
652
653 rc = read_ecp(minor, c, cnt);
654
655 } else {
656 rc = negotiate(DEFAULT_NIBBLE, minor);
657 if (rc < 0) break;
658
659 instances[minor].mode = NIBBLE;
660
661 rc = read_nibble(minor, c, cnt);
662 }
663 break;
664
665 case NIBBLE:
666 rc = read_nibble(minor, c, cnt);
667 break;
668
669 case ECP:
670 case ECP_RLE:
671 rc = read_ecp(minor, c, cnt);
672 break;
673
674 }
675
676
677 return rc;
678 }
679
680 /*
681 * Compatibility mode handshaking is a matter of writing data,
682 * strobing it, and waiting for the printer to stop being busy.
683 */
684 static long write_compat(unsigned minor, const char __user *c, unsigned long cnt)
685 {
686 long rc;
687 unsigned short pins = get_pins(minor);
688
689 unsigned long remaining = cnt;
690
691
692 while (remaining > 0) {
693 unsigned char byte;
694
695 if (get_user(byte, c))
696 return -EFAULT;
697 c += 1;
698
699 rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
700 if (rc == -1) return -ETIMEDOUT;
701
702 bpp_outb_p(byte, base_addrs[minor]);
703 remaining -= 1;
704 /* snooze(1, minor); */
705
706 pins &= ~BPP_PP_nStrobe;
707 set_pins(pins, minor);
708
709 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
710
711 pins |= BPP_PP_nStrobe;
712 set_pins(pins, minor);
713 }
714
715 return cnt - remaining;
716 }
717
718 /*
719 * Write data using ECP mode. Watch out that the port may be set up
720 * for reading. If so, turn the port around.
721 */
722 static long write_ecp(unsigned minor, const char __user *c, unsigned long cnt)
723 {
724 unsigned short pins = get_pins(minor);
725 unsigned long remaining = cnt;
726
727 if (instances[minor].direction) {
728 int rc;
729
730 /* Event 47 Request bus be turned around */
731 pins |= BPP_PP_nInit;
732 set_pins(pins, minor);
733
734 /* Wait for Event 49: Peripheral relinquished bus */
735 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
736
737 pins |= BPP_PP_nAutoFd;
738 instances[minor].direction = 0;
739 set_pins(pins, minor);
740 }
741
742 while (remaining > 0) {
743 unsigned char byte;
744 int rc;
745
746 if (get_user(byte, c))
747 return -EFAULT;
748
749 rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
750 if (rc == -1) return -ETIMEDOUT;
751
752 c += 1;
753
754 bpp_outb_p(byte, base_addrs[minor]);
755
756 pins &= ~BPP_PP_nStrobe;
757 set_pins(pins, minor);
758
759 pins |= BPP_PP_nStrobe;
760 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
761 if (rc == -1) return -EIO;
762
763 set_pins(pins, minor);
764 }
765
766 return cnt - remaining;
767 }
768
769 /*
770 * Write to the peripheral. Be sensitive of the current mode. If I'm
771 * in a mode that can be turned around (ECP) then just do
772 * that. Otherwise, terminate and do my writing in compat mode. This
773 * is the safest course as any device can handle it.
774 */
775 static ssize_t bpp_write(struct file *f, const char __user *c, size_t cnt, loff_t * ppos)
776 {
777 long errno = 0;
778 unsigned minor = iminor(f->f_dentry->d_inode);
779 if (minor >= BPP_NO) return -ENODEV;
780 if (!instances[minor].present) return -ENODEV;
781
782 switch (instances[minor].mode) {
783
784 case ECP:
785 case ECP_RLE:
786 errno = write_ecp(minor, c, cnt);
787 break;
788 case COMPATIBILITY:
789 errno = write_compat(minor, c, cnt);
790 break;
791 default:
792 terminate(minor);
793 errno = write_compat(minor, c, cnt);
794 }
795
796 return errno;
797 }
798
799 static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
800 unsigned long arg)
801 {
802 int errno = 0;
803
804 unsigned minor = iminor(inode);
805 if (minor >= BPP_NO) return -ENODEV;
806 if (!instances[minor].present) return -ENODEV;
807
808
809 switch (cmd) {
810
811 case BPP_PUT_PINS:
812 set_pins(arg, minor);
813 break;
814
815 case BPP_GET_PINS:
816 errno = get_pins(minor);
817 break;
818
819 case BPP_PUT_DATA:
820 bpp_outb_p(arg, base_addrs[minor]);
821 break;
822
823 case BPP_GET_DATA:
824 errno = bpp_inb_p(base_addrs[minor]);
825 break;
826
827 case BPP_SET_INPUT:
828 if (arg)
829 if (instances[minor].enhanced) {
830 unsigned short bits = get_pins(minor);
831 instances[minor].direction = 0x20;
832 set_pins(bits, minor);
833 } else {
834 errno = -ENOTTY;
835 }
836 else {
837 unsigned short bits = get_pins(minor);
838 instances[minor].direction = 0x00;
839 set_pins(bits, minor);
840 }
841 break;
842
843 default:
844 errno = -EINVAL;
845 }
846
847 return errno;
848 }
849
850 static struct file_operations bpp_fops = {
851 .owner = THIS_MODULE,
852 .read = bpp_read,
853 .write = bpp_write,
854 .ioctl = bpp_ioctl,
855 .open = bpp_open,
856 .release = bpp_release,
857 };
858
859 #if defined(__i386__)
860
861 #define collectLptPorts() {}
862
863 static void probeLptPort(unsigned idx)
864 {
865 unsigned int testvalue;
866 const unsigned short lpAddr = base_addrs[idx];
867
868 instances[idx].present = 0;
869 instances[idx].enhanced = 0;
870 instances[idx].direction = 0;
871 instances[idx].mode = COMPATIBILITY;
872 instances[idx].run_length = 0;
873 instances[idx].run_flag = 0;
874 if (!request_region(lpAddr,3, dev_name)) return;
875
876 /*
877 * First, make sure the instance exists. Do this by writing to
878 * the data latch and reading the value back. If the port *is*
879 * present, test to see if it supports extended-mode
880 * operation. This will be required for IEEE1284 reverse
881 * transfers.
882 */
883
884 outb_p(BPP_PROBE_CODE, lpAddr);
885 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
886 ;
887 testvalue = inb_p(lpAddr);
888 if (testvalue == BPP_PROBE_CODE) {
889 unsigned save;
890 instances[idx].present = 1;
891
892 save = inb_p(lpAddr+2);
893 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
894 ;
895 outb_p(save|0x20, lpAddr+2);
896 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
897 ;
898 outb_p(~BPP_PROBE_CODE, lpAddr);
899 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
900 ;
901 testvalue = inb_p(lpAddr);
902 if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
903 instances[idx].enhanced = 0;
904 else
905 instances[idx].enhanced = 1;
906 outb_p(save, lpAddr+2);
907 }
908 else {
909 release_region(lpAddr,3);
910 }
911 /*
912 * Leave the port in compat idle mode.
913 */
914 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
915
916 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
917 instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
918 }
919
920 static inline void freeLptPort(int idx)
921 {
922 release_region(base_addrs[idx], 3);
923 }
924
925 #endif
926
927 #if defined(__sparc__)
928
929 static void __iomem *map_bpp(struct sbus_dev *dev, int idx)
930 {
931 return sbus_ioremap(&dev->resource[0], 0, BPP_SIZE, "bpp");
932 }
933
934 static int collectLptPorts(void)
935 {
936 struct sbus_bus *bus;
937 struct sbus_dev *dev;
938 int count;
939
940 count = 0;
941 for_all_sbusdev(dev, bus) {
942 if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
943 if (count >= BPP_NO) {
944 printk(KERN_NOTICE
945 "bpp: More than %d bpp ports,"
946 " rest is ignored\n", BPP_NO);
947 return count;
948 }
949 base_addrs[count] = map_bpp(dev, count);
950 count++;
951 }
952 }
953 return count;
954 }
955
956 static void probeLptPort(unsigned idx)
957 {
958 void __iomem *rp = base_addrs[idx];
959 __u32 csr;
960 char *brand;
961
962 instances[idx].present = 0;
963 instances[idx].enhanced = 0;
964 instances[idx].direction = 0;
965 instances[idx].mode = COMPATIBILITY;
966 instances[idx].run_length = 0;
967 instances[idx].run_flag = 0;
968
969 if (!rp) return;
970
971 instances[idx].present = 1;
972 instances[idx].enhanced = 1; /* Sure */
973
974 csr = sbus_readl(rp + BPP_CSR);
975 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
976 udelay(20);
977 csr = sbus_readl(rp + BPP_CSR);
978 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
979 printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
980 }
981 }
982 printk("bpp%d: reset with 0x%08x ..", idx, csr);
983 sbus_writel((csr | P_RESET) & ~P_INT_EN, rp + BPP_CSR);
984 udelay(500);
985 sbus_writel(sbus_readl(rp + BPP_CSR) & ~P_RESET, rp + BPP_CSR);
986 csr = sbus_readl(rp + BPP_CSR);
987 printk(" done with csr=0x%08x ocr=0x%04x\n",
988 csr, sbus_readw(rp + BPP_OCR));
989
990 switch (csr & P_DEV_ID_MASK) {
991 case P_DEV_ID_ZEBRA:
992 brand = "Zebra";
993 break;
994 case P_DEV_ID_L64854:
995 brand = "DMA2";
996 break;
997 default:
998 brand = "Unknown";
999 }
1000 printk("bpp%d: %s at %p\n", idx, brand, rp);
1001
1002 /*
1003 * Leave the port in compat idle mode.
1004 */
1005 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
1006
1007 return;
1008 }
1009
1010 static inline void freeLptPort(int idx)
1011 {
1012 sbus_iounmap(base_addrs[idx], BPP_SIZE);
1013 }
1014
1015 #endif
1016
1017 static int __init bpp_init(void)
1018 {
1019 int rc;
1020 unsigned idx;
1021
1022 rc = collectLptPorts();
1023 if (rc == 0)
1024 return -ENODEV;
1025
1026 rc = register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
1027 if (rc < 0)
1028 return rc;
1029
1030 for (idx = 0; idx < BPP_NO; idx++) {
1031 instances[idx].opened = 0;
1032 probeLptPort(idx);
1033 }
1034 devfs_mk_dir("bpp");
1035 for (idx = 0; idx < BPP_NO; idx++) {
1036 devfs_mk_cdev(MKDEV(BPP_MAJOR, idx),
1037 S_IFCHR | S_IRUSR | S_IWUSR, "bpp/%d", idx);
1038 }
1039
1040 return 0;
1041 }
1042
1043 static void __exit bpp_cleanup(void)
1044 {
1045 unsigned idx;
1046
1047 for (idx = 0; idx < BPP_NO; idx++)
1048 devfs_remove("bpp/%d", idx);
1049 devfs_remove("bpp");
1050 unregister_chrdev(BPP_MAJOR, dev_name);
1051
1052 for (idx = 0; idx < BPP_NO; idx++) {
1053 if (instances[idx].present)
1054 freeLptPort(idx);
1055 }
1056 }
1057
1058 module_init(bpp_init);
1059 module_exit(bpp_cleanup);
1060
1061 MODULE_LICENSE("GPL");
1062
kernel source for telekom puls (alcatel/mediatek)