drivers/pinctrl/pinctrl-sirf.c

   1 /*
   2  * pinmux driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/init.h>
  10 #include <linux/module.h>
  11 #include <linux/irq.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/io.h>
  14 #include <linux/slab.h>
  15 #include <linux/err.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/irqchip/chained_irq.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinmux.h>
  20 #include <linux/pinctrl/consumer.h>
  21 #include <linux/pinctrl/machine.h>
  22 #include <linux/of.h>
  23 #include <linux/of_address.h>
  24 #include <linux/of_device.h>
  25 #include <linux/of_platform.h>
  26 #include <linux/bitops.h>
  27 #include <linux/gpio.h>
  28 #include <linux/of_gpio.h>
  29
  30 #define DRIVER_NAME "pinmux-sirf"
  31
  32 #define SIRFSOC_NUM_PADS    622
  33 #define SIRFSOC_RSC_PIN_MUX 0x4
  34
  35 #define SIRFSOC_GPIO_PAD_EN(g)          ((g)*0x100 + 0x84)
  36 #define SIRFSOC_GPIO_PAD_EN_CLR(g)      ((g)*0x100 + 0x90)
  37 #define SIRFSOC_GPIO_CTRL(g, i)                 ((g)*0x100 + (i)*4)
  38 #define SIRFSOC_GPIO_DSP_EN0                    (0x80)
  39 #define SIRFSOC_GPIO_INT_STATUS(g)              ((g)*0x100 + 0x8C)
  40
  41 #define SIRFSOC_GPIO_CTL_INTR_LOW_MASK          0x1
  42 #define SIRFSOC_GPIO_CTL_INTR_HIGH_MASK         0x2
  43 #define SIRFSOC_GPIO_CTL_INTR_TYPE_MASK         0x4
  44 #define SIRFSOC_GPIO_CTL_INTR_EN_MASK           0x8
  45 #define SIRFSOC_GPIO_CTL_INTR_STS_MASK          0x10
  46 #define SIRFSOC_GPIO_CTL_OUT_EN_MASK            0x20
  47 #define SIRFSOC_GPIO_CTL_DATAOUT_MASK           0x40
  48 #define SIRFSOC_GPIO_CTL_DATAIN_MASK            0x80
  49 #define SIRFSOC_GPIO_CTL_PULL_MASK              0x100
  50 #define SIRFSOC_GPIO_CTL_PULL_HIGH              0x200
  51 #define SIRFSOC_GPIO_CTL_DSP_INT                0x400
  52
  53 #define SIRFSOC_GPIO_NO_OF_BANKS        5
  54 #define SIRFSOC_GPIO_BANK_SIZE          32
  55 #define SIRFSOC_GPIO_NUM(bank, index)   (((bank)*(32)) + (index))
  56
  57 struct sirfsoc_gpio_bank {
  58         struct of_mm_gpio_chip chip;
  59         struct irq_domain *domain;
  60         int id;
  61         int parent_irq;
  62         spinlock_t lock;
  63         bool is_marco; /* for marco, some registers are different with prima2 */
  64 };
  65
  66 static struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
  67 static DEFINE_SPINLOCK(sgpio_lock);
  68
  69 /*
  70  * pad list for the pinmux subsystem
  71  * refer to CS-131858-DC-6A.xls
  72  */
  73 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
  74         PINCTRL_PIN(0, "gpio0-0"),
  75         PINCTRL_PIN(1, "gpio0-1"),
  76         PINCTRL_PIN(2, "gpio0-2"),
  77         PINCTRL_PIN(3, "gpio0-3"),
  78         PINCTRL_PIN(4, "pwm0"),
  79         PINCTRL_PIN(5, "pwm1"),
  80         PINCTRL_PIN(6, "pwm2"),
  81         PINCTRL_PIN(7, "pwm3"),
  82         PINCTRL_PIN(8, "warm_rst_b"),
  83         PINCTRL_PIN(9, "odo_0"),
  84         PINCTRL_PIN(10, "odo_1"),
  85         PINCTRL_PIN(11, "dr_dir"),
  86         PINCTRL_PIN(12, "viprom_fa"),
  87         PINCTRL_PIN(13, "scl_1"),
  88         PINCTRL_PIN(14, "ntrst"),
  89         PINCTRL_PIN(15, "sda_1"),
  90         PINCTRL_PIN(16, "x_ldd[16]"),
  91         PINCTRL_PIN(17, "x_ldd[17]"),
  92         PINCTRL_PIN(18, "x_ldd[18]"),
  93         PINCTRL_PIN(19, "x_ldd[19]"),
  94         PINCTRL_PIN(20, "x_ldd[20]"),
  95         PINCTRL_PIN(21, "x_ldd[21]"),
  96         PINCTRL_PIN(22, "x_ldd[22]"),
  97         PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
  98         PINCTRL_PIN(24, "gps_sgn"),
  99         PINCTRL_PIN(25, "gps_mag"),
 100         PINCTRL_PIN(26, "gps_clk"),
 101         PINCTRL_PIN(27, "sd_cd_b_1"),
 102         PINCTRL_PIN(28, "sd_vcc_on_1"),
 103         PINCTRL_PIN(29, "sd_wp_b_1"),
 104         PINCTRL_PIN(30, "sd_clk_3"),
 105         PINCTRL_PIN(31, "sd_cmd_3"),
 106
 107         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
 108         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
 109         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
 110         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
 111         PINCTRL_PIN(36, "x_sd_clk_4"),
 112         PINCTRL_PIN(37, "x_sd_cmd_4"),
 113         PINCTRL_PIN(38, "x_sd_dat_4[0]"),
 114         PINCTRL_PIN(39, "x_sd_dat_4[1]"),
 115         PINCTRL_PIN(40, "x_sd_dat_4[2]"),
 116         PINCTRL_PIN(41, "x_sd_dat_4[3]"),
 117         PINCTRL_PIN(42, "x_cko_1"),
 118         PINCTRL_PIN(43, "x_ac97_bit_clk"),
 119         PINCTRL_PIN(44, "x_ac97_dout"),
 120         PINCTRL_PIN(45, "x_ac97_din"),
 121         PINCTRL_PIN(46, "x_ac97_sync"),
 122         PINCTRL_PIN(47, "x_txd_1"),
 123         PINCTRL_PIN(48, "x_txd_2"),
 124         PINCTRL_PIN(49, "x_rxd_1"),
 125         PINCTRL_PIN(50, "x_rxd_2"),
 126         PINCTRL_PIN(51, "x_usclk_0"),
 127         PINCTRL_PIN(52, "x_utxd_0"),
 128         PINCTRL_PIN(53, "x_urxd_0"),
 129         PINCTRL_PIN(54, "x_utfs_0"),
 130         PINCTRL_PIN(55, "x_urfs_0"),
 131         PINCTRL_PIN(56, "x_usclk_1"),
 132         PINCTRL_PIN(57, "x_utxd_1"),
 133         PINCTRL_PIN(58, "x_urxd_1"),
 134         PINCTRL_PIN(59, "x_utfs_1"),
 135         PINCTRL_PIN(60, "x_urfs_1"),
 136         PINCTRL_PIN(61, "x_usclk_2"),
 137         PINCTRL_PIN(62, "x_utxd_2"),
 138         PINCTRL_PIN(63, "x_urxd_2"),
 139
 140         PINCTRL_PIN(64, "x_utfs_2"),
 141         PINCTRL_PIN(65, "x_urfs_2"),
 142         PINCTRL_PIN(66, "x_df_we_b"),
 143         PINCTRL_PIN(67, "x_df_re_b"),
 144         PINCTRL_PIN(68, "x_txd_0"),
 145         PINCTRL_PIN(69, "x_rxd_0"),
 146         PINCTRL_PIN(78, "x_cko_0"),
 147         PINCTRL_PIN(79, "x_vip_pxd[7]"),
 148         PINCTRL_PIN(80, "x_vip_pxd[6]"),
 149         PINCTRL_PIN(81, "x_vip_pxd[5]"),
 150         PINCTRL_PIN(82, "x_vip_pxd[4]"),
 151         PINCTRL_PIN(83, "x_vip_pxd[3]"),
 152         PINCTRL_PIN(84, "x_vip_pxd[2]"),
 153         PINCTRL_PIN(85, "x_vip_pxd[1]"),
 154         PINCTRL_PIN(86, "x_vip_pxd[0]"),
 155         PINCTRL_PIN(87, "x_vip_vsync"),
 156         PINCTRL_PIN(88, "x_vip_hsync"),
 157         PINCTRL_PIN(89, "x_vip_pxclk"),
 158         PINCTRL_PIN(90, "x_sda_0"),
 159         PINCTRL_PIN(91, "x_scl_0"),
 160         PINCTRL_PIN(92, "x_df_ry_by"),
 161         PINCTRL_PIN(93, "x_df_cs_b[1]"),
 162         PINCTRL_PIN(94, "x_df_cs_b[0]"),
 163         PINCTRL_PIN(95, "x_l_pclk"),
 164
 165         PINCTRL_PIN(96, "x_l_lck"),
 166         PINCTRL_PIN(97, "x_l_fck"),
 167         PINCTRL_PIN(98, "x_l_de"),
 168         PINCTRL_PIN(99, "x_ldd[0]"),
 169         PINCTRL_PIN(100, "x_ldd[1]"),
 170         PINCTRL_PIN(101, "x_ldd[2]"),
 171         PINCTRL_PIN(102, "x_ldd[3]"),
 172         PINCTRL_PIN(103, "x_ldd[4]"),
 173         PINCTRL_PIN(104, "x_ldd[5]"),
 174         PINCTRL_PIN(105, "x_ldd[6]"),
 175         PINCTRL_PIN(106, "x_ldd[7]"),
 176         PINCTRL_PIN(107, "x_ldd[8]"),
 177         PINCTRL_PIN(108, "x_ldd[9]"),
 178         PINCTRL_PIN(109, "x_ldd[10]"),
 179         PINCTRL_PIN(110, "x_ldd[11]"),
 180         PINCTRL_PIN(111, "x_ldd[12]"),
 181         PINCTRL_PIN(112, "x_ldd[13]"),
 182         PINCTRL_PIN(113, "x_ldd[14]"),
 183         PINCTRL_PIN(114, "x_ldd[15]"),
 184 };
 185
 186 /**
 187  * @dev: a pointer back to containing device
 188  * @virtbase: the offset to the controller in virtual memory
 189  */
 190 struct sirfsoc_pmx {
 191         struct device *dev;
 192         struct pinctrl_dev *pmx;
 193         void __iomem *gpio_virtbase;
 194         void __iomem *rsc_virtbase;
 195         bool is_marco;
 196 };
 197
 198 /* SIRFSOC_GPIO_PAD_EN set */
 199 struct sirfsoc_muxmask {
 200         unsigned long group;
 201         unsigned long mask;
 202 };
 203
 204 struct sirfsoc_padmux {
 205         unsigned long muxmask_counts;
 206         const struct sirfsoc_muxmask *muxmask;
 207         /* RSC_PIN_MUX set */
 208         unsigned long funcmask;
 209         unsigned long funcval;
 210 };
 211
 212  /**
 213  * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
 214  * @name: the name of this specific pin group
 215  * @pins: an array of discrete physical pins used in this group, taken
 216  *      from the driver-local pin enumeration space
 217  * @num_pins: the number of pins in this group array, i.e. the number of
 218  *      elements in .pins so we can iterate over that array
 219  */
 220 struct sirfsoc_pin_group {
 221         const char *name;
 222         const unsigned int *pins;
 223         const unsigned num_pins;
 224 };
 225
 226 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
 227         {
 228                 .group = 3,
 229                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 230                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 231                         BIT(17) | BIT(18),
 232         }, {
 233                 .group = 2,
 234                 .mask = BIT(31),
 235         },
 236 };
 237
 238 static const struct sirfsoc_padmux lcd_16bits_padmux = {
 239         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
 240         .muxmask = lcd_16bits_sirfsoc_muxmask,
 241         .funcmask = BIT(4),
 242         .funcval = 0,
 243 };
 244
 245 static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 246         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 247
 248 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
 249         {
 250                 .group = 3,
 251                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 252                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 253                         BIT(17) | BIT(18),
 254         }, {
 255                 .group = 2,
 256                 .mask = BIT(31),
 257         }, {
 258                 .group = 0,
 259                 .mask = BIT(16) | BIT(17),
 260         },
 261 };
 262
 263 static const struct sirfsoc_padmux lcd_18bits_padmux = {
 264         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
 265         .muxmask = lcd_18bits_muxmask,
 266         .funcmask = BIT(4),
 267         .funcval = 0,
 268 };
 269
 270 static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 271         105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
 272
 273 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
 274         {
 275                 .group = 3,
 276                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 277                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 278                         BIT(17) | BIT(18),
 279         }, {
 280                 .group = 2,
 281                 .mask = BIT(31),
 282         }, {
 283                 .group = 0,
 284                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 285         },
 286 };
 287
 288 static const struct sirfsoc_padmux lcd_24bits_padmux = {
 289         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
 290         .muxmask = lcd_24bits_muxmask,
 291         .funcmask = BIT(4),
 292         .funcval = 0,
 293 };
 294
 295 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 296         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 297
 298 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
 299         {
 300                 .group = 3,
 301                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 302                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 303                         BIT(17) | BIT(18),
 304         }, {
 305                 .group = 2,
 306                 .mask = BIT(31),
 307         }, {
 308                 .group = 0,
 309                 .mask = BIT(23),
 310         },
 311 };
 312
 313 static const struct sirfsoc_padmux lcdrom_padmux = {
 314         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
 315         .muxmask = lcdrom_muxmask,
 316         .funcmask = BIT(4),
 317         .funcval = BIT(4),
 318 };
 319
 320 static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 321         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 322
 323 static const struct sirfsoc_muxmask uart0_muxmask[] = {
 324         {
 325                 .group = 2,
 326                 .mask = BIT(4) | BIT(5),
 327         }, {
 328                 .group = 1,
 329                 .mask = BIT(23) | BIT(28),
 330         },
 331 };
 332
 333 static const struct sirfsoc_padmux uart0_padmux = {
 334         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
 335         .muxmask = uart0_muxmask,
 336         .funcmask = BIT(9),
 337         .funcval = BIT(9),
 338 };
 339
 340 static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
 341
 342 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
 343         {
 344                 .group = 2,
 345                 .mask = BIT(4) | BIT(5),
 346         },
 347 };
 348
 349 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
 350         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
 351         .muxmask = uart0_nostreamctrl_muxmask,
 352 };
 353
 354 static const unsigned uart0_nostreamctrl_pins[] = { 68, 39 };
 355
 356 static const struct sirfsoc_muxmask uart1_muxmask[] = {
 357         {
 358                 .group = 1,
 359                 .mask = BIT(15) | BIT(17),
 360         },
 361 };
 362
 363 static const struct sirfsoc_padmux uart1_padmux = {
 364         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
 365         .muxmask = uart1_muxmask,
 366 };
 367
 368 static const unsigned uart1_pins[] = { 47, 49 };
 369
 370 static const struct sirfsoc_muxmask uart2_muxmask[] = {
 371         {
 372                 .group = 1,
 373                 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
 374         },
 375 };
 376
 377 static const struct sirfsoc_padmux uart2_padmux = {
 378         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
 379         .muxmask = uart2_muxmask,
 380         .funcmask = BIT(10),
 381         .funcval = BIT(10),
 382 };
 383
 384 static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
 385
 386 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
 387         {
 388                 .group = 1,
 389                 .mask = BIT(16) | BIT(18),
 390         },
 391 };
 392
 393 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
 394         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
 395         .muxmask = uart2_nostreamctrl_muxmask,
 396 };
 397
 398 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
 399
 400 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
 401         {
 402                 .group = 0,
 403                 .mask = BIT(30) | BIT(31),
 404         }, {
 405                 .group = 1,
 406                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 407         },
 408 };
 409
 410 static const struct sirfsoc_padmux sdmmc3_padmux = {
 411         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
 412         .muxmask = sdmmc3_muxmask,
 413         .funcmask = BIT(7),
 414         .funcval = 0,
 415 };
 416
 417 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
 418
 419 static const struct sirfsoc_muxmask spi0_muxmask[] = {
 420         {
 421                 .group = 1,
 422                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 423         },
 424 };
 425
 426 static const struct sirfsoc_padmux spi0_padmux = {
 427         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
 428         .muxmask = spi0_muxmask,
 429         .funcmask = BIT(7),
 430         .funcval = BIT(7),
 431 };
 432
 433 static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
 434
 435 static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
 436         {
 437                 .group = 1,
 438                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
 439         },
 440 };
 441
 442 static const struct sirfsoc_padmux sdmmc4_padmux = {
 443         .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
 444         .muxmask = sdmmc4_muxmask,
 445 };
 446
 447 static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
 448
 449 static const struct sirfsoc_muxmask cko1_muxmask[] = {
 450         {
 451                 .group = 1,
 452                 .mask = BIT(10),
 453         },
 454 };
 455
 456 static const struct sirfsoc_padmux cko1_padmux = {
 457         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
 458         .muxmask = cko1_muxmask,
 459         .funcmask = BIT(3),
 460         .funcval = 0,
 461 };
 462
 463 static const unsigned cko1_pins[] = { 42 };
 464
 465 static const struct sirfsoc_muxmask i2s_muxmask[] = {
 466         {
 467                 .group = 1,
 468                 .mask =
 469                         BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
 470                                 | BIT(23) | BIT(28),
 471         },
 472 };
 473
 474 static const struct sirfsoc_padmux i2s_padmux = {
 475         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
 476         .muxmask = i2s_muxmask,
 477         .funcmask = BIT(3) | BIT(9),
 478         .funcval = BIT(3),
 479 };
 480
 481 static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
 482
 483 static const struct sirfsoc_muxmask ac97_muxmask[] = {
 484         {
 485                 .group = 1,
 486                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 487         },
 488 };
 489
 490 static const struct sirfsoc_padmux ac97_padmux = {
 491         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
 492         .muxmask = ac97_muxmask,
 493         .funcmask = BIT(8),
 494         .funcval = 0,
 495 };
 496
 497 static const unsigned ac97_pins[] = { 33, 34, 35, 36 };
 498
 499 static const struct sirfsoc_muxmask spi1_muxmask[] = {
 500         {
 501                 .group = 1,
 502                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 503         },
 504 };
 505
 506 static const struct sirfsoc_padmux spi1_padmux = {
 507         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
 508         .muxmask = spi1_muxmask,
 509         .funcmask = BIT(8),
 510         .funcval = BIT(8),
 511 };
 512
 513 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
 514
 515 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
 516         {
 517                 .group = 0,
 518                 .mask = BIT(27) | BIT(28) | BIT(29),
 519         },
 520 };
 521
 522 static const struct sirfsoc_padmux sdmmc1_padmux = {
 523         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
 524         .muxmask = sdmmc1_muxmask,
 525 };
 526
 527 static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
 528
 529 static const struct sirfsoc_muxmask gps_muxmask[] = {
 530         {
 531                 .group = 0,
 532                 .mask = BIT(24) | BIT(25) | BIT(26),
 533         },
 534 };
 535
 536 static const struct sirfsoc_padmux gps_padmux = {
 537         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
 538         .muxmask = gps_muxmask,
 539         .funcmask = BIT(12) | BIT(13) | BIT(14),
 540         .funcval = BIT(12),
 541 };
 542
 543 static const unsigned gps_pins[] = { 24, 25, 26 };
 544
 545 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
 546         {
 547                 .group = 0,
 548                 .mask = BIT(24) | BIT(25) | BIT(26),
 549         }, {
 550                 .group = 1,
 551                 .mask = BIT(29),
 552         }, {
 553                 .group = 2,
 554                 .mask = BIT(0) | BIT(1),
 555         },
 556 };
 557
 558 static const struct sirfsoc_padmux sdmmc5_padmux = {
 559         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
 560         .muxmask = sdmmc5_muxmask,
 561         .funcmask = BIT(13) | BIT(14),
 562         .funcval = BIT(13) | BIT(14),
 563 };
 564
 565 static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 };
 566
 567 static const struct sirfsoc_muxmask usp0_muxmask[] = {
 568         {
 569                 .group = 1,
 570                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 571         },
 572 };
 573
 574 static const struct sirfsoc_padmux usp0_padmux = {
 575         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
 576         .muxmask = usp0_muxmask,
 577         .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
 578         .funcval = 0,
 579 };
 580
 581 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
 582
 583 static const struct sirfsoc_muxmask usp1_muxmask[] = {
 584         {
 585                 .group = 1,
 586                 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
 587         },
 588 };
 589
 590 static const struct sirfsoc_padmux usp1_padmux = {
 591         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
 592         .muxmask = usp1_muxmask,
 593         .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
 594         .funcval = 0,
 595 };
 596
 597 static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
 598
 599 static const struct sirfsoc_muxmask usp2_muxmask[] = {
 600         {
 601                 .group = 1,
 602                 .mask = BIT(29) | BIT(30) | BIT(31),
 603         }, {
 604                 .group = 2,
 605                 .mask = BIT(0) | BIT(1),
 606         },
 607 };
 608
 609 static const struct sirfsoc_padmux usp2_padmux = {
 610         .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
 611         .muxmask = usp2_muxmask,
 612         .funcmask = BIT(13) | BIT(14),
 613         .funcval = 0,
 614 };
 615
 616 static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
 617
 618 static const struct sirfsoc_muxmask nand_muxmask[] = {
 619         {
 620                 .group = 2,
 621                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
 622         },
 623 };
 624
 625 static const struct sirfsoc_padmux nand_padmux = {
 626         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
 627         .muxmask = nand_muxmask,
 628         .funcmask = BIT(5),
 629         .funcval = 0,
 630 };
 631
 632 static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
 633
 634 static const struct sirfsoc_padmux sdmmc0_padmux = {
 635         .muxmask_counts = 0,
 636         .funcmask = BIT(5),
 637         .funcval = 0,
 638 };
 639
 640 static const unsigned sdmmc0_pins[] = { };
 641
 642 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
 643         {
 644                 .group = 2,
 645                 .mask = BIT(2) | BIT(3),
 646         },
 647 };
 648
 649 static const struct sirfsoc_padmux sdmmc2_padmux = {
 650         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
 651         .muxmask = sdmmc2_muxmask,
 652         .funcmask = BIT(5),
 653         .funcval = BIT(5),
 654 };
 655
 656 static const unsigned sdmmc2_pins[] = { 66, 67 };
 657
 658 static const struct sirfsoc_muxmask cko0_muxmask[] = {
 659         {
 660                 .group = 2,
 661                 .mask = BIT(14),
 662         },
 663 };
 664
 665 static const struct sirfsoc_padmux cko0_padmux = {
 666         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
 667         .muxmask = cko0_muxmask,
 668 };
 669
 670 static const unsigned cko0_pins[] = { 78 };
 671
 672 static const struct sirfsoc_muxmask vip_muxmask[] = {
 673         {
 674                 .group = 2,
 675                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
 676                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
 677                         BIT(25),
 678         },
 679 };
 680
 681 static const struct sirfsoc_padmux vip_padmux = {
 682         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
 683         .muxmask = vip_muxmask,
 684         .funcmask = BIT(0),
 685         .funcval = 0,
 686 };
 687
 688 static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
 689
 690 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
 691         {
 692                 .group = 2,
 693                 .mask = BIT(26) | BIT(27),
 694         },
 695 };
 696
 697 static const struct sirfsoc_padmux i2c0_padmux = {
 698         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
 699         .muxmask = i2c0_muxmask,
 700 };
 701
 702 static const unsigned i2c0_pins[] = { 90, 91 };
 703
 704 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
 705         {
 706                 .group = 0,
 707                 .mask = BIT(13) | BIT(15),
 708         },
 709 };
 710
 711 static const struct sirfsoc_padmux i2c1_padmux = {
 712         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
 713         .muxmask = i2c1_muxmask,
 714 };
 715
 716 static const unsigned i2c1_pins[] = { 13, 15 };
 717
 718 static const struct sirfsoc_muxmask viprom_muxmask[] = {
 719         {
 720                 .group = 2,
 721                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
 722                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
 723                         BIT(25),
 724         }, {
 725                 .group = 0,
 726                 .mask = BIT(12),
 727         },
 728 };
 729
 730 static const struct sirfsoc_padmux viprom_padmux = {
 731         .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
 732         .muxmask = viprom_muxmask,
 733         .funcmask = BIT(0),
 734         .funcval = BIT(0),
 735 };
 736
 737 static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
 738
 739 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
 740         {
 741                 .group = 0,
 742                 .mask = BIT(4),
 743         },
 744 };
 745
 746 static const struct sirfsoc_padmux pwm0_padmux = {
 747         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
 748         .muxmask = pwm0_muxmask,
 749         .funcmask = BIT(12),
 750         .funcval = 0,
 751 };
 752
 753 static const unsigned pwm0_pins[] = { 4 };
 754
 755 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
 756         {
 757                 .group = 0,
 758                 .mask = BIT(5),
 759         },
 760 };
 761
 762 static const struct sirfsoc_padmux pwm1_padmux = {
 763         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
 764         .muxmask = pwm1_muxmask,
 765 };
 766
 767 static const unsigned pwm1_pins[] = { 5 };
 768
 769 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
 770         {
 771                 .group = 0,
 772                 .mask = BIT(6),
 773         },
 774 };
 775
 776 static const struct sirfsoc_padmux pwm2_padmux = {
 777         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
 778         .muxmask = pwm2_muxmask,
 779 };
 780
 781 static const unsigned pwm2_pins[] = { 6 };
 782
 783 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
 784         {
 785                 .group = 0,
 786                 .mask = BIT(7),
 787         },
 788 };
 789
 790 static const struct sirfsoc_padmux pwm3_padmux = {
 791         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
 792         .muxmask = pwm3_muxmask,
 793 };
 794
 795 static const unsigned pwm3_pins[] = { 7 };
 796
 797 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
 798         {
 799                 .group = 0,
 800                 .mask = BIT(8),
 801         },
 802 };
 803
 804 static const struct sirfsoc_padmux warm_rst_padmux = {
 805         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
 806         .muxmask = warm_rst_muxmask,
 807 };
 808
 809 static const unsigned warm_rst_pins[] = { 8 };
 810
 811 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
 812         {
 813                 .group = 1,
 814                 .mask = BIT(22),
 815         },
 816 };
 817 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
 818         .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
 819         .muxmask = usb0_utmi_drvbus_muxmask,
 820         .funcmask = BIT(6),
 821         .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
 822 };
 823
 824 static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
 825
 826 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
 827         {
 828                 .group = 1,
 829                 .mask = BIT(27),
 830         },
 831 };
 832
 833 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
 834         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
 835         .muxmask = usb1_utmi_drvbus_muxmask,
 836         .funcmask = BIT(11),
 837         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
 838 };
 839
 840 static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
 841
 842 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
 843         {
 844                 .group = 0,
 845                 .mask = BIT(9) | BIT(10) | BIT(11),
 846         },
 847 };
 848
 849 static const struct sirfsoc_padmux pulse_count_padmux = {
 850         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
 851         .muxmask = pulse_count_muxmask,
 852 };
 853
 854 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
 855
 856 #define SIRFSOC_PIN_GROUP(n, p)  \
 857         {                       \
 858                 .name = n,      \
 859                 .pins = p,      \
 860                 .num_pins = ARRAY_SIZE(p),      \
 861         }
 862
 863 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
 864         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
 865         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
 866         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
 867         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
 868         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
 869         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
 870         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
 871         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
 872         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
 873         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
 874         SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
 875         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
 876         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
 877         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
 878         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
 879         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
 880         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
 881         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
 882         SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
 883         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
 884         SIRFSOC_PIN_GROUP("cko0_rstgrp", cko0_pins),
 885         SIRFSOC_PIN_GROUP("cko1_rstgrp", cko1_pins),
 886         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
 887         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
 888         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
 889         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
 890         SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
 891         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
 892         SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
 893         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
 894         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
 895         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
 896         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
 897         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
 898         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
 899         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
 900         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 901 };
 902
 903 static int sirfsoc_get_groups_count(struct pinctrl_dev *pctldev)
 904 {
 905         return ARRAY_SIZE(sirfsoc_pin_groups);
 906 }
 907
 908 static const char *sirfsoc_get_group_name(struct pinctrl_dev *pctldev,
 909                                        unsigned selector)
 910 {
 911         return sirfsoc_pin_groups[selector].name;
 912 }
 913
 914 static int sirfsoc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
 915                                const unsigned **pins,
 916                                unsigned *num_pins)
 917 {
 918         *pins = sirfsoc_pin_groups[selector].pins;
 919         *num_pins = sirfsoc_pin_groups[selector].num_pins;
 920         return 0;
 921 }
 922
 923 static void sirfsoc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 924                    unsigned offset)
 925 {
 926         seq_printf(s, " " DRIVER_NAME);
 927 }
 928
 929 static int sirfsoc_dt_node_to_map(struct pinctrl_dev *pctldev,
 930                                  struct device_node *np_config,
 931                                  struct pinctrl_map **map, unsigned *num_maps)
 932 {
 933         struct sirfsoc_pmx *spmx = pinctrl_dev_get_drvdata(pctldev);
 934         struct device_node *np;
 935         struct property *prop;
 936         const char *function, *group;
 937         int ret, index = 0, count = 0;
 938
 939         /* calculate number of maps required */
 940         for_each_child_of_node(np_config, np) {
 941                 ret = of_property_read_string(np, "sirf,function", &function);
 942                 if (ret < 0)
 943                         return ret;
 944
 945                 ret = of_property_count_strings(np, "sirf,pins");
 946                 if (ret < 0)
 947                         return ret;
 948
 949                 count += ret;
 950         }
 951
 952         if (!count) {
 953                 dev_err(spmx->dev, "No child nodes passed via DT\n");
 954                 return -ENODEV;
 955         }
 956
 957         *map = kzalloc(sizeof(**map) * count, GFP_KERNEL);
 958         if (!*map)
 959                 return -ENOMEM;
 960
 961         for_each_child_of_node(np_config, np) {
 962                 of_property_read_string(np, "sirf,function", &function);
 963                 of_property_for_each_string(np, "sirf,pins", prop, group) {
 964                         (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
 965                         (*map)[index].data.mux.group = group;
 966                         (*map)[index].data.mux.function = function;
 967                         index++;
 968                 }
 969         }
 970
 971         *num_maps = count;
 972
 973         return 0;
 974 }
 975
 976 static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
 977                 struct pinctrl_map *map, unsigned num_maps)
 978 {
 979         kfree(map);
 980 }
 981
 982 static const struct pinctrl_ops sirfsoc_pctrl_ops = {
 983         .get_groups_count = sirfsoc_get_groups_count,
 984         .get_group_name = sirfsoc_get_group_name,
 985         .get_group_pins = sirfsoc_get_group_pins,
 986         .pin_dbg_show = sirfsoc_pin_dbg_show,
 987         .dt_node_to_map = sirfsoc_dt_node_to_map,
 988         .dt_free_map = sirfsoc_dt_free_map,
 989 };
 990
 991 struct sirfsoc_pmx_func {
 992         const char *name;
 993         const char * const *groups;
 994         const unsigned num_groups;
 995         const struct sirfsoc_padmux *padmux;
 996 };
 997
 998 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
 999 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
1000 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
1001 static const char * const lcdromgrp[] = { "lcdromgrp" };
1002 static const char * const uart0grp[] = { "uart0grp" };
1003 static const char * const uart1grp[] = { "uart1grp" };
1004 static const char * const uart2grp[] = { "uart2grp" };
1005 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
1006 static const char * const usp0grp[] = { "usp0grp" };
1007 static const char * const usp1grp[] = { "usp1grp" };
1008 static const char * const usp2grp[] = { "usp2grp" };
1009 static const char * const i2c0grp[] = { "i2c0grp" };
1010 static const char * const i2c1grp[] = { "i2c1grp" };
1011 static const char * const pwm0grp[] = { "pwm0grp" };
1012 static const char * const pwm1grp[] = { "pwm1grp" };
1013 static const char * const pwm2grp[] = { "pwm2grp" };
1014 static const char * const pwm3grp[] = { "pwm3grp" };
1015 static const char * const vipgrp[] = { "vipgrp" };
1016 static const char * const vipromgrp[] = { "vipromgrp" };
1017 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
1018 static const char * const cko0grp[] = { "cko0grp" };
1019 static const char * const cko1grp[] = { "cko1grp" };
1020 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
1021 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
1022 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
1023 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
1024 static const char * const sdmmc4grp[] = { "sdmmc4grp" };
1025 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
1026 static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
1027 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
1028 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
1029 static const char * const i2sgrp[] = { "i2sgrp" };
1030 static const char * const ac97grp[] = { "ac97grp" };
1031 static const char * const nandgrp[] = { "nandgrp" };
1032 static const char * const spi0grp[] = { "spi0grp" };
1033 static const char * const spi1grp[] = { "spi1grp" };
1034 static const char * const gpsgrp[] = { "gpsgrp" };
1035
1036 #define SIRFSOC_PMX_FUNCTION(n, g, m)           \
1037         {                                       \
1038                 .name = n,                      \
1039                 .groups = g,                    \
1040                 .num_groups = ARRAY_SIZE(g),    \
1041                 .padmux = &m,                   \
1042         }
1043
1044 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
1045         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
1046         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
1047         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
1048         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
1049         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
1050         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
1051         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
1052         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
1053         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
1054         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1055         SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
1056         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
1057         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1058         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1059         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1060         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1061         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1062         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1063         SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
1064         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1065         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1066         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1067         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1068         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1069         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1070         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1071         SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1072         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1073         SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1074         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1075         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1076         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1077         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1078         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1079         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1080         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1081         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1082 };
1083
1084 static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector,
1085         bool enable)
1086 {
1087         int i;
1088         const struct sirfsoc_padmux *mux = sirfsoc_pmx_functions[selector].padmux;
1089         const struct sirfsoc_muxmask *mask = mux->muxmask;
1090
1091         for (i = 0; i < mux->muxmask_counts; i++) {
1092                 u32 muxval;
1093                 if (!spmx->is_marco) {
1094                         muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1095                         if (enable)
1096                                 muxval = muxval & ~mask[i].mask;
1097                         else
1098                                 muxval = muxval | mask[i].mask;
1099                         writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(mask[i].group));
1100                 } else {
1101                         if (enable)
1102                                 writel(mask[i].mask, spmx->gpio_virtbase +
1103                                         SIRFSOC_GPIO_PAD_EN_CLR(mask[i].group));
1104                         else
1105                                 writel(mask[i].mask, spmx->gpio_virtbase +
1106                                         SIRFSOC_GPIO_PAD_EN(mask[i].group));
1107                 }
1108         }
1109
1110         if (mux->funcmask && enable) {
1111                 u32 func_en_val;
1112                 func_en_val =
1113                         readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1114                 func_en_val =
1115                         (func_en_val & ~mux->funcmask) | (mux->
1116                                 funcval);
1117                 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
1118         }
1119 }
1120
1121 static int sirfsoc_pinmux_enable(struct pinctrl_dev *pmxdev, unsigned selector,
1122         unsigned group)
1123 {
1124         struct sirfsoc_pmx *spmx;
1125
1126         spmx = pinctrl_dev_get_drvdata(pmxdev);
1127         sirfsoc_pinmux_endisable(spmx, selector, true);
1128
1129         return 0;
1130 }
1131
1132 static void sirfsoc_pinmux_disable(struct pinctrl_dev *pmxdev, unsigned selector,
1133         unsigned group)
1134 {
1135         struct sirfsoc_pmx *spmx;
1136
1137         spmx = pinctrl_dev_get_drvdata(pmxdev);
1138         sirfsoc_pinmux_endisable(spmx, selector, false);
1139 }
1140
1141 static int sirfsoc_pinmux_get_funcs_count(struct pinctrl_dev *pmxdev)
1142 {
1143         return ARRAY_SIZE(sirfsoc_pmx_functions);
1144 }
1145
1146 static const char *sirfsoc_pinmux_get_func_name(struct pinctrl_dev *pctldev,
1147                                           unsigned selector)
1148 {
1149         return sirfsoc_pmx_functions[selector].name;
1150 }
1151
1152 static int sirfsoc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1153                                const char * const **groups,
1154                                unsigned * const num_groups)
1155 {
1156         *groups = sirfsoc_pmx_functions[selector].groups;
1157         *num_groups = sirfsoc_pmx_functions[selector].num_groups;
1158         return 0;
1159 }
1160
1161 static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1162         struct pinctrl_gpio_range *range, unsigned offset)
1163 {
1164         struct sirfsoc_pmx *spmx;
1165
1166         int group = range->id;
1167
1168         u32 muxval;
1169
1170         spmx = pinctrl_dev_get_drvdata(pmxdev);
1171
1172         if (!spmx->is_marco) {
1173                 muxval = readl(spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1174                 muxval = muxval | (1 << (offset - range->pin_base));
1175                 writel(muxval, spmx->gpio_virtbase + SIRFSOC_GPIO_PAD_EN(group));
1176         } else {
1177                 writel(1 << (offset - range->pin_base), spmx->gpio_virtbase +
1178                         SIRFSOC_GPIO_PAD_EN(group));
1179         }
1180
1181         return 0;
1182 }
1183
1184 static const struct pinmux_ops sirfsoc_pinmux_ops = {
1185         .enable = sirfsoc_pinmux_enable,
1186         .disable = sirfsoc_pinmux_disable,
1187         .get_functions_count = sirfsoc_pinmux_get_funcs_count,
1188         .get_function_name = sirfsoc_pinmux_get_func_name,
1189         .get_function_groups = sirfsoc_pinmux_get_groups,
1190         .gpio_request_enable = sirfsoc_pinmux_request_gpio,
1191 };
1192
1193 static struct pinctrl_desc sirfsoc_pinmux_desc = {
1194         .name = DRIVER_NAME,
1195         .pins = sirfsoc_pads,
1196         .npins = ARRAY_SIZE(sirfsoc_pads),
1197         .pctlops = &sirfsoc_pctrl_ops,
1198         .pmxops = &sirfsoc_pinmux_ops,
1199         .owner = THIS_MODULE,
1200 };
1201
1202 /*
1203  * Todo: bind irq_chip to every pinctrl_gpio_range
1204  */
1205 static struct pinctrl_gpio_range sirfsoc_gpio_ranges[] = {
1206         {
1207                 .name = "sirfsoc-gpio*",
1208                 .id = 0,
1209                 .base = 0,
1210                 .pin_base = 0,
1211                 .npins = 32,
1212         }, {
1213                 .name = "sirfsoc-gpio*",
1214                 .id = 1,
1215                 .base = 32,
1216                 .pin_base = 32,
1217                 .npins = 32,
1218         }, {
1219                 .name = "sirfsoc-gpio*",
1220                 .id = 2,
1221                 .base = 64,
1222                 .pin_base = 64,
1223                 .npins = 32,
1224         }, {
1225                 .name = "sirfsoc-gpio*",
1226                 .id = 3,
1227                 .base = 96,
1228                 .pin_base = 96,
1229                 .npins = 19,
1230         },
1231 };
1232
1233 static void __iomem *sirfsoc_rsc_of_iomap(void)
1234 {
1235         const struct of_device_id rsc_ids[]  = {
1236                 { .compatible = "sirf,prima2-rsc" },
1237                 { .compatible = "sirf,marco-rsc" },
1238                 {}
1239         };
1240         struct device_node *np;
1241
1242         np = of_find_matching_node(NULL, rsc_ids);
1243         if (!np)
1244                 panic("unable to find compatible rsc node in dtb\n");
1245
1246         return of_iomap(np, 0);
1247 }
1248
1249 static int sirfsoc_gpio_of_xlate(struct gpio_chip *gc,
1250        const struct of_phandle_args *gpiospec,
1251        u32 *flags)
1252 {
1253        if (gpiospec->args[0] > SIRFSOC_GPIO_NO_OF_BANKS * SIRFSOC_GPIO_BANK_SIZE)
1254                return -EINVAL;
1255
1256        if (gc != &sgpio_bank[gpiospec->args[0] / SIRFSOC_GPIO_BANK_SIZE].chip.gc)
1257                return -EINVAL;
1258
1259        if (flags)
1260                *flags = gpiospec->args[1];
1261
1262        return gpiospec->args[0] % SIRFSOC_GPIO_BANK_SIZE;
1263 }
1264
1265 static int sirfsoc_pinmux_probe(struct platform_device *pdev)
1266 {
1267         int ret;
1268         struct sirfsoc_pmx *spmx;
1269         struct device_node *np = pdev->dev.of_node;
1270         int i;
1271
1272         /* Create state holders etc for this driver */
1273         spmx = devm_kzalloc(&pdev->dev, sizeof(*spmx), GFP_KERNEL);
1274         if (!spmx)
1275                 return -ENOMEM;
1276
1277         spmx->dev = &pdev->dev;
1278
1279         platform_set_drvdata(pdev, spmx);
1280
1281         spmx->gpio_virtbase = of_iomap(np, 0);
1282         if (!spmx->gpio_virtbase) {
1283                 ret = -ENOMEM;
1284                 dev_err(&pdev->dev, "can't map gpio registers\n");
1285                 goto out_no_gpio_remap;
1286         }
1287
1288         spmx->rsc_virtbase = sirfsoc_rsc_of_iomap();
1289         if (!spmx->rsc_virtbase) {
1290                 ret = -ENOMEM;
1291                 dev_err(&pdev->dev, "can't map rsc registers\n");
1292                 goto out_no_rsc_remap;
1293         }
1294
1295         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1296                 spmx->is_marco = 1;
1297
1298         /* Now register the pin controller and all pins it handles */
1299         spmx->pmx = pinctrl_register(&sirfsoc_pinmux_desc, &pdev->dev, spmx);
1300         if (!spmx->pmx) {
1301                 dev_err(&pdev->dev, "could not register SIRFSOC pinmux driver\n");
1302                 ret = -EINVAL;
1303                 goto out_no_pmx;
1304         }
1305
1306         for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
1307                 sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
1308                 pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
1309         }
1310
1311         dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
1312
1313         return 0;
1314
1315 out_no_pmx:
1316         iounmap(spmx->rsc_virtbase);
1317 out_no_rsc_remap:
1318         iounmap(spmx->gpio_virtbase);
1319 out_no_gpio_remap:
1320         platform_set_drvdata(pdev, NULL);
1321         return ret;
1322 }
1323
1324 static const struct of_device_id pinmux_ids[] = {
1325         { .compatible = "sirf,prima2-pinctrl" },
1326         { .compatible = "sirf,marco-pinctrl" },
1327         {}
1328 };
1329
1330 static struct platform_driver sirfsoc_pinmux_driver = {
1331         .driver = {
1332                 .name = DRIVER_NAME,
1333                 .owner = THIS_MODULE,
1334                 .of_match_table = pinmux_ids,
1335         },
1336         .probe = sirfsoc_pinmux_probe,
1337 };
1338
1339 static int __init sirfsoc_pinmux_init(void)
1340 {
1341         return platform_driver_register(&sirfsoc_pinmux_driver);
1342 }
1343 arch_initcall(sirfsoc_pinmux_init);
1344
1345 static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1346 {
1347         struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
1348                 struct sirfsoc_gpio_bank, chip);
1349
1350         return irq_create_mapping(bank->domain, offset);
1351 }
1352
1353 static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
1354 {
1355         return gpio % SIRFSOC_GPIO_BANK_SIZE;
1356 }
1357
1358 static inline struct sirfsoc_gpio_bank *sirfsoc_gpio_to_bank(unsigned int gpio)
1359 {
1360         return &sgpio_bank[gpio / SIRFSOC_GPIO_BANK_SIZE];
1361 }
1362
1363 static inline struct sirfsoc_gpio_bank *sirfsoc_irqchip_to_bank(struct gpio_chip *chip)
1364 {
1365         return container_of(to_of_mm_gpio_chip(chip), struct sirfsoc_gpio_bank, chip);
1366 }
1367
1368 static void sirfsoc_gpio_irq_ack(struct irq_data *d)
1369 {
1370         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1371         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1372         u32 val, offset;
1373         unsigned long flags;
1374
1375         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1376
1377         spin_lock_irqsave(&sgpio_lock, flags);
1378
1379         val = readl(bank->chip.regs + offset);
1380
1381         writel(val, bank->chip.regs + offset);
1382
1383         spin_unlock_irqrestore(&sgpio_lock, flags);
1384 }
1385
1386 static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_bank *bank, int idx)
1387 {
1388         u32 val, offset;
1389         unsigned long flags;
1390
1391         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1392
1393         spin_lock_irqsave(&sgpio_lock, flags);
1394
1395         val = readl(bank->chip.regs + offset);
1396         val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1397         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1398         writel(val, bank->chip.regs + offset);
1399
1400         spin_unlock_irqrestore(&sgpio_lock, flags);
1401 }
1402
1403 static void sirfsoc_gpio_irq_mask(struct irq_data *d)
1404 {
1405         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1406
1407         __sirfsoc_gpio_irq_mask(bank, d->hwirq % SIRFSOC_GPIO_BANK_SIZE);
1408 }
1409
1410 static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
1411 {
1412         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1413         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1414         u32 val, offset;
1415         unsigned long flags;
1416
1417         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1418
1419         spin_lock_irqsave(&sgpio_lock, flags);
1420
1421         val = readl(bank->chip.regs + offset);
1422         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1423         val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1424         writel(val, bank->chip.regs + offset);
1425
1426         spin_unlock_irqrestore(&sgpio_lock, flags);
1427 }
1428
1429 static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
1430 {
1431         struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
1432         int idx = d->hwirq % SIRFSOC_GPIO_BANK_SIZE;
1433         u32 val, offset;
1434         unsigned long flags;
1435
1436         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1437
1438         spin_lock_irqsave(&sgpio_lock, flags);
1439
1440         val = readl(bank->chip.regs + offset);
1441         val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
1442
1443         switch (type) {
1444         case IRQ_TYPE_NONE:
1445                 break;
1446         case IRQ_TYPE_EDGE_RISING:
1447                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1448                 val &= ~SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1449                 break;
1450         case IRQ_TYPE_EDGE_FALLING:
1451                 val &= ~SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1452                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1453                 break;
1454         case IRQ_TYPE_EDGE_BOTH:
1455                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_LOW_MASK |
1456                          SIRFSOC_GPIO_CTL_INTR_TYPE_MASK;
1457                 break;
1458         case IRQ_TYPE_LEVEL_LOW:
1459                 val &= ~(SIRFSOC_GPIO_CTL_INTR_HIGH_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1460                 val |= SIRFSOC_GPIO_CTL_INTR_LOW_MASK;
1461                 break;
1462         case IRQ_TYPE_LEVEL_HIGH:
1463                 val |= SIRFSOC_GPIO_CTL_INTR_HIGH_MASK;
1464                 val &= ~(SIRFSOC_GPIO_CTL_INTR_LOW_MASK | SIRFSOC_GPIO_CTL_INTR_TYPE_MASK);
1465                 break;
1466         }
1467
1468         writel(val, bank->chip.regs + offset);
1469
1470         spin_unlock_irqrestore(&sgpio_lock, flags);
1471
1472         return 0;
1473 }
1474
1475 static struct irq_chip sirfsoc_irq_chip = {
1476         .name = "sirf-gpio-irq",
1477         .irq_ack = sirfsoc_gpio_irq_ack,
1478         .irq_mask = sirfsoc_gpio_irq_mask,
1479         .irq_unmask = sirfsoc_gpio_irq_unmask,
1480         .irq_set_type = sirfsoc_gpio_irq_type,
1481 };
1482
1483 static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
1484 {
1485         struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq);
1486         u32 status, ctrl;
1487         int idx = 0;
1488         struct irq_chip *chip = irq_get_chip(irq);
1489
1490         chained_irq_enter(chip, desc);
1491
1492         status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
1493         if (!status) {
1494                 printk(KERN_WARNING
1495                         "%s: gpio id %d status %#x no interrupt is flaged\n",
1496                         __func__, bank->id, status);
1497                 handle_bad_irq(irq, desc);
1498                 return;
1499         }
1500
1501         while (status) {
1502                 ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx));
1503
1504                 /*
1505                  * Here we must check whether the corresponding GPIO's interrupt
1506                  * has been enabled, otherwise just skip it
1507                  */
1508                 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
1509                         pr_debug("%s: gpio id %d idx %d happens\n",
1510                                 __func__, bank->id, idx);
1511                         generic_handle_irq(irq_find_mapping(bank->domain, idx));
1512                 }
1513
1514                 idx++;
1515                 status = status >> 1;
1516         }
1517
1518         chained_irq_exit(chip, desc);
1519 }
1520
1521 static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
1522 {
1523         u32 val;
1524
1525         val = readl(bank->chip.regs + ctrl_offset);
1526         val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1527         writel(val, bank->chip.regs + ctrl_offset);
1528 }
1529
1530 static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
1531 {
1532         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1533         unsigned long flags;
1534
1535         if (pinctrl_request_gpio(chip->base + offset))
1536                 return -ENODEV;
1537
1538         spin_lock_irqsave(&bank->lock, flags);
1539
1540         /*
1541          * default status:
1542          * set direction as input and mask irq
1543          */
1544         sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1545         __sirfsoc_gpio_irq_mask(bank, offset);
1546
1547         spin_unlock_irqrestore(&bank->lock, flags);
1548
1549         return 0;
1550 }
1551
1552 static void sirfsoc_gpio_free(struct gpio_chip *chip, unsigned offset)
1553 {
1554         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1555         unsigned long flags;
1556
1557         spin_lock_irqsave(&bank->lock, flags);
1558
1559         __sirfsoc_gpio_irq_mask(bank, offset);
1560         sirfsoc_gpio_set_input(bank, SIRFSOC_GPIO_CTRL(bank->id, offset));
1561
1562         spin_unlock_irqrestore(&bank->lock, flags);
1563
1564         pinctrl_free_gpio(chip->base + offset);
1565 }
1566
1567 static int sirfsoc_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1568 {
1569         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1570         int idx = sirfsoc_gpio_to_offset(gpio);
1571         unsigned long flags;
1572         unsigned offset;
1573
1574         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1575
1576         spin_lock_irqsave(&bank->lock, flags);
1577
1578         sirfsoc_gpio_set_input(bank, offset);
1579
1580         spin_unlock_irqrestore(&bank->lock, flags);
1581
1582         return 0;
1583 }
1584
1585 static inline void sirfsoc_gpio_set_output(struct sirfsoc_gpio_bank *bank, unsigned offset,
1586         int value)
1587 {
1588         u32 out_ctrl;
1589         unsigned long flags;
1590
1591         spin_lock_irqsave(&bank->lock, flags);
1592
1593         out_ctrl = readl(bank->chip.regs + offset);
1594         if (value)
1595                 out_ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1596         else
1597                 out_ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1598
1599         out_ctrl &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
1600         out_ctrl |= SIRFSOC_GPIO_CTL_OUT_EN_MASK;
1601         writel(out_ctrl, bank->chip.regs + offset);
1602
1603         spin_unlock_irqrestore(&bank->lock, flags);
1604 }
1605
1606 static int sirfsoc_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1607 {
1608         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1609         int idx = sirfsoc_gpio_to_offset(gpio);
1610         u32 offset;
1611         unsigned long flags;
1612
1613         offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
1614
1615         spin_lock_irqsave(&sgpio_lock, flags);
1616
1617         sirfsoc_gpio_set_output(bank, offset, value);
1618
1619         spin_unlock_irqrestore(&sgpio_lock, flags);
1620
1621         return 0;
1622 }
1623
1624 static int sirfsoc_gpio_get_value(struct gpio_chip *chip, unsigned offset)
1625 {
1626         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1627         u32 val;
1628         unsigned long flags;
1629
1630         spin_lock_irqsave(&bank->lock, flags);
1631
1632         val = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1633
1634         spin_unlock_irqrestore(&bank->lock, flags);
1635
1636         return !!(val & SIRFSOC_GPIO_CTL_DATAIN_MASK);
1637 }
1638
1639 static void sirfsoc_gpio_set_value(struct gpio_chip *chip, unsigned offset,
1640         int value)
1641 {
1642         struct sirfsoc_gpio_bank *bank = sirfsoc_irqchip_to_bank(chip);
1643         u32 ctrl;
1644         unsigned long flags;
1645
1646         spin_lock_irqsave(&bank->lock, flags);
1647
1648         ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1649         if (value)
1650                 ctrl |= SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1651         else
1652                 ctrl &= ~SIRFSOC_GPIO_CTL_DATAOUT_MASK;
1653         writel(ctrl, bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, offset));
1654
1655         spin_unlock_irqrestore(&bank->lock, flags);
1656 }
1657
1658 static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1659                                 irq_hw_number_t hwirq)
1660 {
1661         struct sirfsoc_gpio_bank *bank = d->host_data;
1662
1663         if (!bank)
1664                 return -EINVAL;
1665
1666         irq_set_chip(irq, &sirfsoc_irq_chip);
1667         irq_set_handler(irq, handle_level_irq);
1668         irq_set_chip_data(irq, bank);
1669         set_irq_flags(irq, IRQF_VALID);
1670
1671         return 0;
1672 }
1673
1674 const struct irq_domain_ops sirfsoc_gpio_irq_simple_ops = {
1675         .map = sirfsoc_gpio_irq_map,
1676         .xlate = irq_domain_xlate_twocell,
1677 };
1678
1679 static void sirfsoc_gpio_set_pullup(const u32 *pullups)
1680 {
1681         int i, n;
1682         const unsigned long *p = (const unsigned long *)pullups;
1683
1684         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1685                 for_each_set_bit(n, p + i, BITS_PER_LONG) {
1686                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1687                         u32 val = readl(sgpio_bank[i].chip.regs + offset);
1688                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1689                         val |= SIRFSOC_GPIO_CTL_PULL_HIGH;
1690                         writel(val, sgpio_bank[i].chip.regs + offset);
1691                 }
1692         }
1693 }
1694
1695 static void sirfsoc_gpio_set_pulldown(const u32 *pulldowns)
1696 {
1697         int i, n;
1698         const unsigned long *p = (const unsigned long *)pulldowns;
1699
1700         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1701                 for_each_set_bit(n, p + i, BITS_PER_LONG) {
1702                         u32 offset = SIRFSOC_GPIO_CTRL(i, n);
1703                         u32 val = readl(sgpio_bank[i].chip.regs + offset);
1704                         val |= SIRFSOC_GPIO_CTL_PULL_MASK;
1705                         val &= ~SIRFSOC_GPIO_CTL_PULL_HIGH;
1706                         writel(val, sgpio_bank[i].chip.regs + offset);
1707                 }
1708         }
1709 }
1710
1711 static int sirfsoc_gpio_probe(struct device_node *np)
1712 {
1713         int i, err = 0;
1714         struct sirfsoc_gpio_bank *bank;
1715         void *regs;
1716         struct platform_device *pdev;
1717         bool is_marco = false;
1718
1719         u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
1720
1721         pdev = of_find_device_by_node(np);
1722         if (!pdev)
1723                 return -ENODEV;
1724
1725         regs = of_iomap(np, 0);
1726         if (!regs)
1727                 return -ENOMEM;
1728
1729         if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
1730                 is_marco = 1;
1731
1732         for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
1733                 bank = &sgpio_bank[i];
1734                 spin_lock_init(&bank->lock);
1735                 bank->chip.gc.request = sirfsoc_gpio_request;
1736                 bank->chip.gc.free = sirfsoc_gpio_free;
1737                 bank->chip.gc.direction_input = sirfsoc_gpio_direction_input;
1738                 bank->chip.gc.get = sirfsoc_gpio_get_value;
1739                 bank->chip.gc.direction_output = sirfsoc_gpio_direction_output;
1740                 bank->chip.gc.set = sirfsoc_gpio_set_value;
1741                 bank->chip.gc.to_irq = sirfsoc_gpio_to_irq;
1742                 bank->chip.gc.base = i * SIRFSOC_GPIO_BANK_SIZE;
1743                 bank->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE;
1744                 bank->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
1745                 bank->chip.gc.of_node = np;
1746                 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
1747                 bank->chip.gc.of_gpio_n_cells = 2;
1748                 bank->chip.regs = regs;
1749                 bank->id = i;
1750                 bank->is_marco = is_marco;
1751                 bank->parent_irq = platform_get_irq(pdev, i);
1752                 if (bank->parent_irq < 0) {
1753                         err = bank->parent_irq;
1754                         goto out;
1755                 }
1756
1757                 err = gpiochip_add(&bank->chip.gc);
1758                 if (err) {
1759                         pr_err("%s: error in probe function with status %d\n",
1760                                 np->full_name, err);
1761                         goto out;
1762                 }
1763
1764                 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE,
1765                                                 &sirfsoc_gpio_irq_simple_ops, bank);
1766
1767                 if (!bank->domain) {
1768                         pr_err("%s: Failed to create irqdomain\n", np->full_name);
1769                         err = -ENOSYS;
1770                         goto out;
1771                 }
1772
1773                 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
1774                 irq_set_handler_data(bank->parent_irq, bank);
1775         }
1776
1777         if (!of_property_read_u32_array(np, "sirf,pullups", pullups,
1778                 SIRFSOC_GPIO_NO_OF_BANKS))
1779                 sirfsoc_gpio_set_pullup(pullups);
1780
1781         if (!of_property_read_u32_array(np, "sirf,pulldowns", pulldowns,
1782                 SIRFSOC_GPIO_NO_OF_BANKS))
1783                 sirfsoc_gpio_set_pulldown(pulldowns);
1784
1785         return 0;
1786
1787 out:
1788         iounmap(regs);
1789         return err;
1790 }
1791
1792 static int __init sirfsoc_gpio_init(void)
1793 {
1794
1795         struct device_node *np;
1796
1797         np = of_find_matching_node(NULL, pinmux_ids);
1798
1799         if (!np)
1800                 return -ENODEV;
1801
1802         return sirfsoc_gpio_probe(np);
1803 }
1804 subsys_initcall(sirfsoc_gpio_init);
1805
1806 MODULE_AUTHOR("Rongjun Ying <rongjun.ying@csr.com>, "
1807         "Yuping Luo <yuping.luo@csr.com>, "
1808         "Barry Song <baohua.song@csr.com>");
1809 MODULE_DESCRIPTION("SIRFSOC pin control driver");
1810 MODULE_LICENSE("GPL");