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Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-exynos.c
1 /*
2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
8 *
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
19 */
20
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/of_irq.h>
28 #include <linux/io.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/err.h>
32
33 #include "pinctrl-samsung.h"
34 #include "pinctrl-exynos.h"
35
36
37 static struct samsung_pin_bank_type bank_type_off = {
38 .fld_width = { 4, 1, 2, 2, 2, 2, },
39 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
40 };
41
42 static struct samsung_pin_bank_type bank_type_alive = {
43 .fld_width = { 4, 1, 2, 2, },
44 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
45 };
46
47 /* list of external wakeup controllers supported */
48 static const struct of_device_id exynos_wkup_irq_ids[] = {
49 { .compatible = "samsung,exynos4210-wakeup-eint", },
50 { }
51 };
52
53 static void exynos_gpio_irq_unmask(struct irq_data *irqd)
54 {
55 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
56 struct samsung_pinctrl_drv_data *d = bank->drvdata;
57 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
58 unsigned long mask;
59
60 mask = readl(d->virt_base + reg_mask);
61 mask &= ~(1 << irqd->hwirq);
62 writel(mask, d->virt_base + reg_mask);
63 }
64
65 static void exynos_gpio_irq_mask(struct irq_data *irqd)
66 {
67 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
68 struct samsung_pinctrl_drv_data *d = bank->drvdata;
69 unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
70 unsigned long mask;
71
72 mask = readl(d->virt_base + reg_mask);
73 mask |= 1 << irqd->hwirq;
74 writel(mask, d->virt_base + reg_mask);
75 }
76
77 static void exynos_gpio_irq_ack(struct irq_data *irqd)
78 {
79 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
80 struct samsung_pinctrl_drv_data *d = bank->drvdata;
81 unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset;
82
83 writel(1 << irqd->hwirq, d->virt_base + reg_pend);
84 }
85
86 static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
87 {
88 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
89 struct samsung_pin_bank_type *bank_type = bank->type;
90 struct samsung_pinctrl_drv_data *d = bank->drvdata;
91 struct samsung_pin_ctrl *ctrl = d->ctrl;
92 unsigned int pin = irqd->hwirq;
93 unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
94 unsigned int con, trig_type;
95 unsigned long reg_con = ctrl->geint_con + bank->eint_offset;
96 unsigned long flags;
97 unsigned int mask;
98
99 switch (type) {
100 case IRQ_TYPE_EDGE_RISING:
101 trig_type = EXYNOS_EINT_EDGE_RISING;
102 break;
103 case IRQ_TYPE_EDGE_FALLING:
104 trig_type = EXYNOS_EINT_EDGE_FALLING;
105 break;
106 case IRQ_TYPE_EDGE_BOTH:
107 trig_type = EXYNOS_EINT_EDGE_BOTH;
108 break;
109 case IRQ_TYPE_LEVEL_HIGH:
110 trig_type = EXYNOS_EINT_LEVEL_HIGH;
111 break;
112 case IRQ_TYPE_LEVEL_LOW:
113 trig_type = EXYNOS_EINT_LEVEL_LOW;
114 break;
115 default:
116 pr_err("unsupported external interrupt type\n");
117 return -EINVAL;
118 }
119
120 if (type & IRQ_TYPE_EDGE_BOTH)
121 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
122 else
123 __irq_set_handler_locked(irqd->irq, handle_level_irq);
124
125 con = readl(d->virt_base + reg_con);
126 con &= ~(EXYNOS_EINT_CON_MASK << shift);
127 con |= trig_type << shift;
128 writel(con, d->virt_base + reg_con);
129
130 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
131 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
132 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
133
134 spin_lock_irqsave(&bank->slock, flags);
135
136 con = readl(d->virt_base + reg_con);
137 con &= ~(mask << shift);
138 con |= EXYNOS_EINT_FUNC << shift;
139 writel(con, d->virt_base + reg_con);
140
141 spin_unlock_irqrestore(&bank->slock, flags);
142
143 return 0;
144 }
145
146 /*
147 * irq_chip for gpio interrupts.
148 */
149 static struct irq_chip exynos_gpio_irq_chip = {
150 .name = "exynos_gpio_irq_chip",
151 .irq_unmask = exynos_gpio_irq_unmask,
152 .irq_mask = exynos_gpio_irq_mask,
153 .irq_ack = exynos_gpio_irq_ack,
154 .irq_set_type = exynos_gpio_irq_set_type,
155 };
156
157 static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
158 irq_hw_number_t hw)
159 {
160 struct samsung_pin_bank *b = h->host_data;
161
162 irq_set_chip_data(virq, b);
163 irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
164 handle_level_irq);
165 set_irq_flags(virq, IRQF_VALID);
166 return 0;
167 }
168
169 /*
170 * irq domain callbacks for external gpio interrupt controller.
171 */
172 static const struct irq_domain_ops exynos_gpio_irqd_ops = {
173 .map = exynos_gpio_irq_map,
174 .xlate = irq_domain_xlate_twocell,
175 };
176
177 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
178 {
179 struct samsung_pinctrl_drv_data *d = data;
180 struct samsung_pin_ctrl *ctrl = d->ctrl;
181 struct samsung_pin_bank *bank = ctrl->pin_banks;
182 unsigned int svc, group, pin, virq;
183
184 svc = readl(d->virt_base + ctrl->svc);
185 group = EXYNOS_SVC_GROUP(svc);
186 pin = svc & EXYNOS_SVC_NUM_MASK;
187
188 if (!group)
189 return IRQ_HANDLED;
190 bank += (group - 1);
191
192 virq = irq_linear_revmap(bank->irq_domain, pin);
193 if (!virq)
194 return IRQ_NONE;
195 generic_handle_irq(virq);
196 return IRQ_HANDLED;
197 }
198
199 /*
200 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
201 * @d: driver data of samsung pinctrl driver.
202 */
203 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
204 {
205 struct samsung_pin_bank *bank;
206 struct device *dev = d->dev;
207 unsigned int ret;
208 unsigned int i;
209
210 if (!d->irq) {
211 dev_err(dev, "irq number not available\n");
212 return -EINVAL;
213 }
214
215 ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
216 0, dev_name(dev), d);
217 if (ret) {
218 dev_err(dev, "irq request failed\n");
219 return -ENXIO;
220 }
221
222 bank = d->ctrl->pin_banks;
223 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
224 if (bank->eint_type != EINT_TYPE_GPIO)
225 continue;
226 bank->irq_domain = irq_domain_add_linear(bank->of_node,
227 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
228 if (!bank->irq_domain) {
229 dev_err(dev, "gpio irq domain add failed\n");
230 return -ENXIO;
231 }
232 }
233
234 return 0;
235 }
236
237 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
238 {
239 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
240 struct samsung_pinctrl_drv_data *d = b->drvdata;
241 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
242 unsigned long mask;
243
244 mask = readl(d->virt_base + reg_mask);
245 mask &= ~(1 << irqd->hwirq);
246 writel(mask, d->virt_base + reg_mask);
247 }
248
249 static void exynos_wkup_irq_mask(struct irq_data *irqd)
250 {
251 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
252 struct samsung_pinctrl_drv_data *d = b->drvdata;
253 unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
254 unsigned long mask;
255
256 mask = readl(d->virt_base + reg_mask);
257 mask |= 1 << irqd->hwirq;
258 writel(mask, d->virt_base + reg_mask);
259 }
260
261 static void exynos_wkup_irq_ack(struct irq_data *irqd)
262 {
263 struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
264 struct samsung_pinctrl_drv_data *d = b->drvdata;
265 unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
266
267 writel(1 << irqd->hwirq, d->virt_base + pend);
268 }
269
270 static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
271 {
272 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
273 struct samsung_pin_bank_type *bank_type = bank->type;
274 struct samsung_pinctrl_drv_data *d = bank->drvdata;
275 unsigned int pin = irqd->hwirq;
276 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
277 unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
278 unsigned long con, trig_type;
279 unsigned long flags;
280 unsigned int mask;
281
282 switch (type) {
283 case IRQ_TYPE_EDGE_RISING:
284 trig_type = EXYNOS_EINT_EDGE_RISING;
285 break;
286 case IRQ_TYPE_EDGE_FALLING:
287 trig_type = EXYNOS_EINT_EDGE_FALLING;
288 break;
289 case IRQ_TYPE_EDGE_BOTH:
290 trig_type = EXYNOS_EINT_EDGE_BOTH;
291 break;
292 case IRQ_TYPE_LEVEL_HIGH:
293 trig_type = EXYNOS_EINT_LEVEL_HIGH;
294 break;
295 case IRQ_TYPE_LEVEL_LOW:
296 trig_type = EXYNOS_EINT_LEVEL_LOW;
297 break;
298 default:
299 pr_err("unsupported external interrupt type\n");
300 return -EINVAL;
301 }
302
303 if (type & IRQ_TYPE_EDGE_BOTH)
304 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
305 else
306 __irq_set_handler_locked(irqd->irq, handle_level_irq);
307
308 con = readl(d->virt_base + reg_con);
309 con &= ~(EXYNOS_EINT_CON_MASK << shift);
310 con |= trig_type << shift;
311 writel(con, d->virt_base + reg_con);
312
313 reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
314 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
315 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
316
317 spin_lock_irqsave(&bank->slock, flags);
318
319 con = readl(d->virt_base + reg_con);
320 con &= ~(mask << shift);
321 con |= EXYNOS_EINT_FUNC << shift;
322 writel(con, d->virt_base + reg_con);
323
324 spin_unlock_irqrestore(&bank->slock, flags);
325
326 return 0;
327 }
328
329 /*
330 * irq_chip for wakeup interrupts
331 */
332 static struct irq_chip exynos_wkup_irq_chip = {
333 .name = "exynos_wkup_irq_chip",
334 .irq_unmask = exynos_wkup_irq_unmask,
335 .irq_mask = exynos_wkup_irq_mask,
336 .irq_ack = exynos_wkup_irq_ack,
337 .irq_set_type = exynos_wkup_irq_set_type,
338 };
339
340 /* interrupt handler for wakeup interrupts 0..15 */
341 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
342 {
343 struct exynos_weint_data *eintd = irq_get_handler_data(irq);
344 struct samsung_pin_bank *bank = eintd->bank;
345 struct irq_chip *chip = irq_get_chip(irq);
346 int eint_irq;
347
348 chained_irq_enter(chip, desc);
349 chip->irq_mask(&desc->irq_data);
350
351 if (chip->irq_ack)
352 chip->irq_ack(&desc->irq_data);
353
354 eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
355 generic_handle_irq(eint_irq);
356 chip->irq_unmask(&desc->irq_data);
357 chained_irq_exit(chip, desc);
358 }
359
360 static inline void exynos_irq_demux_eint(unsigned long pend,
361 struct irq_domain *domain)
362 {
363 unsigned int irq;
364
365 while (pend) {
366 irq = fls(pend) - 1;
367 generic_handle_irq(irq_find_mapping(domain, irq));
368 pend &= ~(1 << irq);
369 }
370 }
371
372 /* interrupt handler for wakeup interrupt 16 */
373 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
374 {
375 struct irq_chip *chip = irq_get_chip(irq);
376 struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
377 struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
378 struct samsung_pin_ctrl *ctrl = d->ctrl;
379 unsigned long pend;
380 unsigned long mask;
381 int i;
382
383 chained_irq_enter(chip, desc);
384
385 for (i = 0; i < eintd->nr_banks; ++i) {
386 struct samsung_pin_bank *b = eintd->banks[i];
387 pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset);
388 mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset);
389 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
390 }
391
392 chained_irq_exit(chip, desc);
393 }
394
395 static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
396 irq_hw_number_t hw)
397 {
398 irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
399 irq_set_chip_data(virq, h->host_data);
400 set_irq_flags(virq, IRQF_VALID);
401 return 0;
402 }
403
404 /*
405 * irq domain callbacks for external wakeup interrupt controller.
406 */
407 static const struct irq_domain_ops exynos_wkup_irqd_ops = {
408 .map = exynos_wkup_irq_map,
409 .xlate = irq_domain_xlate_twocell,
410 };
411
412 /*
413 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
414 * @d: driver data of samsung pinctrl driver.
415 */
416 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
417 {
418 struct device *dev = d->dev;
419 struct device_node *wkup_np = NULL;
420 struct device_node *np;
421 struct samsung_pin_bank *bank;
422 struct exynos_weint_data *weint_data;
423 struct exynos_muxed_weint_data *muxed_data;
424 unsigned int muxed_banks = 0;
425 unsigned int i;
426 int idx, irq;
427
428 for_each_child_of_node(dev->of_node, np) {
429 if (of_match_node(exynos_wkup_irq_ids, np)) {
430 wkup_np = np;
431 break;
432 }
433 }
434 if (!wkup_np)
435 return -ENODEV;
436
437 bank = d->ctrl->pin_banks;
438 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
439 if (bank->eint_type != EINT_TYPE_WKUP)
440 continue;
441
442 bank->irq_domain = irq_domain_add_linear(bank->of_node,
443 bank->nr_pins, &exynos_wkup_irqd_ops, bank);
444 if (!bank->irq_domain) {
445 dev_err(dev, "wkup irq domain add failed\n");
446 return -ENXIO;
447 }
448
449 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
450 bank->eint_type = EINT_TYPE_WKUP_MUX;
451 ++muxed_banks;
452 continue;
453 }
454
455 weint_data = devm_kzalloc(dev, bank->nr_pins
456 * sizeof(*weint_data), GFP_KERNEL);
457 if (!weint_data) {
458 dev_err(dev, "could not allocate memory for weint_data\n");
459 return -ENOMEM;
460 }
461
462 for (idx = 0; idx < bank->nr_pins; ++idx) {
463 irq = irq_of_parse_and_map(bank->of_node, idx);
464 if (!irq) {
465 dev_err(dev, "irq number for eint-%s-%d not found\n",
466 bank->name, idx);
467 continue;
468 }
469 weint_data[idx].irq = idx;
470 weint_data[idx].bank = bank;
471 irq_set_handler_data(irq, &weint_data[idx]);
472 irq_set_chained_handler(irq, exynos_irq_eint0_15);
473 }
474 }
475
476 if (!muxed_banks)
477 return 0;
478
479 irq = irq_of_parse_and_map(wkup_np, 0);
480 if (!irq) {
481 dev_err(dev, "irq number for muxed EINTs not found\n");
482 return 0;
483 }
484
485 muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
486 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
487 if (!muxed_data) {
488 dev_err(dev, "could not allocate memory for muxed_data\n");
489 return -ENOMEM;
490 }
491
492 irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
493 irq_set_handler_data(irq, muxed_data);
494
495 bank = d->ctrl->pin_banks;
496 idx = 0;
497 for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
498 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
499 continue;
500
501 muxed_data->banks[idx++] = bank;
502 }
503 muxed_data->nr_banks = muxed_banks;
504
505 return 0;
506 }
507
508 /* pin banks of exynos4210 pin-controller 0 */
509 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
510 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
511 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
512 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
513 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
514 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
515 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
516 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
517 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
518 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
519 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
520 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
521 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
522 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
523 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
524 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
525 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
526 };
527
528 /* pin banks of exynos4210 pin-controller 1 */
529 static struct samsung_pin_bank exynos4210_pin_banks1[] = {
530 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
531 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
532 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
533 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
534 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
535 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
536 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
537 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
538 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
539 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
540 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
541 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
542 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
543 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
544 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
545 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
546 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
547 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
548 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
549 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
550 };
551
552 /* pin banks of exynos4210 pin-controller 2 */
553 static struct samsung_pin_bank exynos4210_pin_banks2[] = {
554 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
555 };
556
557 /*
558 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
559 * three gpio/pin-mux/pinconfig controllers.
560 */
561 struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
562 {
563 /* pin-controller instance 0 data */
564 .pin_banks = exynos4210_pin_banks0,
565 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
566 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
567 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
568 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
569 .svc = EXYNOS_SVC_OFFSET,
570 .eint_gpio_init = exynos_eint_gpio_init,
571 .label = "exynos4210-gpio-ctrl0",
572 }, {
573 /* pin-controller instance 1 data */
574 .pin_banks = exynos4210_pin_banks1,
575 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
576 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
577 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
578 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
579 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
580 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
581 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
582 .svc = EXYNOS_SVC_OFFSET,
583 .eint_gpio_init = exynos_eint_gpio_init,
584 .eint_wkup_init = exynos_eint_wkup_init,
585 .label = "exynos4210-gpio-ctrl1",
586 }, {
587 /* pin-controller instance 2 data */
588 .pin_banks = exynos4210_pin_banks2,
589 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
590 .label = "exynos4210-gpio-ctrl2",
591 },
592 };
593
594 /* pin banks of exynos4x12 pin-controller 0 */
595 static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
596 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
597 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
598 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
599 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
600 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
601 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
602 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
603 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
604 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
605 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
606 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
607 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
608 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
609 };
610
611 /* pin banks of exynos4x12 pin-controller 1 */
612 static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
613 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
614 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
615 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
616 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
617 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
618 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
619 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
620 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
621 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
622 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
623 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
624 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
625 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
626 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
627 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
628 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
629 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
630 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
631 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
632 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
633 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
634 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
635 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
636 };
637
638 /* pin banks of exynos4x12 pin-controller 2 */
639 static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
640 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
641 };
642
643 /* pin banks of exynos4x12 pin-controller 3 */
644 static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
645 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
646 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
647 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
648 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
649 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
650 };
651
652 /*
653 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
654 * four gpio/pin-mux/pinconfig controllers.
655 */
656 struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
657 {
658 /* pin-controller instance 0 data */
659 .pin_banks = exynos4x12_pin_banks0,
660 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
661 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
662 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
663 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
664 .svc = EXYNOS_SVC_OFFSET,
665 .eint_gpio_init = exynos_eint_gpio_init,
666 .label = "exynos4x12-gpio-ctrl0",
667 }, {
668 /* pin-controller instance 1 data */
669 .pin_banks = exynos4x12_pin_banks1,
670 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
671 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
672 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
673 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
674 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
675 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
676 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
677 .svc = EXYNOS_SVC_OFFSET,
678 .eint_gpio_init = exynos_eint_gpio_init,
679 .eint_wkup_init = exynos_eint_wkup_init,
680 .label = "exynos4x12-gpio-ctrl1",
681 }, {
682 /* pin-controller instance 2 data */
683 .pin_banks = exynos4x12_pin_banks2,
684 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
685 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
686 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
687 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
688 .svc = EXYNOS_SVC_OFFSET,
689 .eint_gpio_init = exynos_eint_gpio_init,
690 .label = "exynos4x12-gpio-ctrl2",
691 }, {
692 /* pin-controller instance 3 data */
693 .pin_banks = exynos4x12_pin_banks3,
694 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
695 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
696 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
697 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
698 .svc = EXYNOS_SVC_OFFSET,
699 .eint_gpio_init = exynos_eint_gpio_init,
700 .label = "exynos4x12-gpio-ctrl3",
701 },
702 };
703
704 /* pin banks of exynos5250 pin-controller 0 */
705 static struct samsung_pin_bank exynos5250_pin_banks0[] = {
706 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
707 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
708 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
709 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
710 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
711 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
712 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
713 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
714 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
715 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
716 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
717 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
718 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
719 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
720 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
721 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
722 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
723 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
724 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
725 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
726 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
727 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
728 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
729 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
730 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
731 };
732
733 /* pin banks of exynos5250 pin-controller 1 */
734 static struct samsung_pin_bank exynos5250_pin_banks1[] = {
735 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
736 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
737 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
738 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
739 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
740 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
741 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
742 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
743 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
744 };
745
746 /* pin banks of exynos5250 pin-controller 2 */
747 static struct samsung_pin_bank exynos5250_pin_banks2[] = {
748 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
749 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
750 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
751 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
752 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
753 };
754
755 /* pin banks of exynos5250 pin-controller 3 */
756 static struct samsung_pin_bank exynos5250_pin_banks3[] = {
757 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
758 };
759
760 /*
761 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
762 * four gpio/pin-mux/pinconfig controllers.
763 */
764 struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
765 {
766 /* pin-controller instance 0 data */
767 .pin_banks = exynos5250_pin_banks0,
768 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
769 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
770 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
771 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
772 .weint_con = EXYNOS_WKUP_ECON_OFFSET,
773 .weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
774 .weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
775 .svc = EXYNOS_SVC_OFFSET,
776 .eint_gpio_init = exynos_eint_gpio_init,
777 .eint_wkup_init = exynos_eint_wkup_init,
778 .label = "exynos5250-gpio-ctrl0",
779 }, {
780 /* pin-controller instance 1 data */
781 .pin_banks = exynos5250_pin_banks1,
782 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
783 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
784 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
785 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
786 .svc = EXYNOS_SVC_OFFSET,
787 .eint_gpio_init = exynos_eint_gpio_init,
788 .label = "exynos5250-gpio-ctrl1",
789 }, {
790 /* pin-controller instance 2 data */
791 .pin_banks = exynos5250_pin_banks2,
792 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
793 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
794 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
795 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
796 .svc = EXYNOS_SVC_OFFSET,
797 .eint_gpio_init = exynos_eint_gpio_init,
798 .label = "exynos5250-gpio-ctrl2",
799 }, {
800 /* pin-controller instance 3 data */
801 .pin_banks = exynos5250_pin_banks3,
802 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
803 .geint_con = EXYNOS_GPIO_ECON_OFFSET,
804 .geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
805 .geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
806 .svc = EXYNOS_SVC_OFFSET,
807 .eint_gpio_init = exynos_eint_gpio_init,
808 .label = "exynos5250-gpio-ctrl3",
809 },
810 };
kernel source for telekom puls (alcatel/mediatek)