2 * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This file contains the Samsung Exynos specific information required by the
17 * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
18 * external gpio and wakeup interrupt support.
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/irqchip/chained_irq.h>
27 #include <linux/of_irq.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/err.h>
33 #include "pinctrl-samsung.h"
34 #include "pinctrl-exynos.h"
37 static struct samsung_pin_bank_type bank_type_off
= {
38 .fld_width
= { 4, 1, 2, 2, 2, 2, },
39 .reg_offset
= { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
42 static struct samsung_pin_bank_type bank_type_alive
= {
43 .fld_width
= { 4, 1, 2, 2, },
44 .reg_offset
= { 0x00, 0x04, 0x08, 0x0c, },
47 /* list of external wakeup controllers supported */
48 static const struct of_device_id exynos_wkup_irq_ids
[] = {
49 { .compatible
= "samsung,exynos4210-wakeup-eint", },
53 static void exynos_gpio_irq_unmask(struct irq_data
*irqd
)
55 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
56 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
57 unsigned long reg_mask
= d
->ctrl
->geint_mask
+ bank
->eint_offset
;
60 mask
= readl(d
->virt_base
+ reg_mask
);
61 mask
&= ~(1 << irqd
->hwirq
);
62 writel(mask
, d
->virt_base
+ reg_mask
);
65 static void exynos_gpio_irq_mask(struct irq_data
*irqd
)
67 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
68 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
69 unsigned long reg_mask
= d
->ctrl
->geint_mask
+ bank
->eint_offset
;
72 mask
= readl(d
->virt_base
+ reg_mask
);
73 mask
|= 1 << irqd
->hwirq
;
74 writel(mask
, d
->virt_base
+ reg_mask
);
77 static void exynos_gpio_irq_ack(struct irq_data
*irqd
)
79 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
80 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
81 unsigned long reg_pend
= d
->ctrl
->geint_pend
+ bank
->eint_offset
;
83 writel(1 << irqd
->hwirq
, d
->virt_base
+ reg_pend
);
86 static int exynos_gpio_irq_set_type(struct irq_data
*irqd
, unsigned int type
)
88 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
89 struct samsung_pin_bank_type
*bank_type
= bank
->type
;
90 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
91 struct samsung_pin_ctrl
*ctrl
= d
->ctrl
;
92 unsigned int pin
= irqd
->hwirq
;
93 unsigned int shift
= EXYNOS_EINT_CON_LEN
* pin
;
94 unsigned int con
, trig_type
;
95 unsigned long reg_con
= ctrl
->geint_con
+ bank
->eint_offset
;
100 case IRQ_TYPE_EDGE_RISING
:
101 trig_type
= EXYNOS_EINT_EDGE_RISING
;
103 case IRQ_TYPE_EDGE_FALLING
:
104 trig_type
= EXYNOS_EINT_EDGE_FALLING
;
106 case IRQ_TYPE_EDGE_BOTH
:
107 trig_type
= EXYNOS_EINT_EDGE_BOTH
;
109 case IRQ_TYPE_LEVEL_HIGH
:
110 trig_type
= EXYNOS_EINT_LEVEL_HIGH
;
112 case IRQ_TYPE_LEVEL_LOW
:
113 trig_type
= EXYNOS_EINT_LEVEL_LOW
;
116 pr_err("unsupported external interrupt type\n");
120 if (type
& IRQ_TYPE_EDGE_BOTH
)
121 __irq_set_handler_locked(irqd
->irq
, handle_edge_irq
);
123 __irq_set_handler_locked(irqd
->irq
, handle_level_irq
);
125 con
= readl(d
->virt_base
+ reg_con
);
126 con
&= ~(EXYNOS_EINT_CON_MASK
<< shift
);
127 con
|= trig_type
<< shift
;
128 writel(con
, d
->virt_base
+ reg_con
);
130 reg_con
= bank
->pctl_offset
+ bank_type
->reg_offset
[PINCFG_TYPE_FUNC
];
131 shift
= pin
* bank_type
->fld_width
[PINCFG_TYPE_FUNC
];
132 mask
= (1 << bank_type
->fld_width
[PINCFG_TYPE_FUNC
]) - 1;
134 spin_lock_irqsave(&bank
->slock
, flags
);
136 con
= readl(d
->virt_base
+ reg_con
);
137 con
&= ~(mask
<< shift
);
138 con
|= EXYNOS_EINT_FUNC
<< shift
;
139 writel(con
, d
->virt_base
+ reg_con
);
141 spin_unlock_irqrestore(&bank
->slock
, flags
);
147 * irq_chip for gpio interrupts.
149 static struct irq_chip exynos_gpio_irq_chip
= {
150 .name
= "exynos_gpio_irq_chip",
151 .irq_unmask
= exynos_gpio_irq_unmask
,
152 .irq_mask
= exynos_gpio_irq_mask
,
153 .irq_ack
= exynos_gpio_irq_ack
,
154 .irq_set_type
= exynos_gpio_irq_set_type
,
157 static int exynos_gpio_irq_map(struct irq_domain
*h
, unsigned int virq
,
160 struct samsung_pin_bank
*b
= h
->host_data
;
162 irq_set_chip_data(virq
, b
);
163 irq_set_chip_and_handler(virq
, &exynos_gpio_irq_chip
,
165 set_irq_flags(virq
, IRQF_VALID
);
170 * irq domain callbacks for external gpio interrupt controller.
172 static const struct irq_domain_ops exynos_gpio_irqd_ops
= {
173 .map
= exynos_gpio_irq_map
,
174 .xlate
= irq_domain_xlate_twocell
,
177 static irqreturn_t
exynos_eint_gpio_irq(int irq
, void *data
)
179 struct samsung_pinctrl_drv_data
*d
= data
;
180 struct samsung_pin_ctrl
*ctrl
= d
->ctrl
;
181 struct samsung_pin_bank
*bank
= ctrl
->pin_banks
;
182 unsigned int svc
, group
, pin
, virq
;
184 svc
= readl(d
->virt_base
+ ctrl
->svc
);
185 group
= EXYNOS_SVC_GROUP(svc
);
186 pin
= svc
& EXYNOS_SVC_NUM_MASK
;
192 virq
= irq_linear_revmap(bank
->irq_domain
, pin
);
195 generic_handle_irq(virq
);
199 struct exynos_eint_gpio_save
{
206 * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
207 * @d: driver data of samsung pinctrl driver.
209 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data
*d
)
211 struct samsung_pin_bank
*bank
;
212 struct device
*dev
= d
->dev
;
217 dev_err(dev
, "irq number not available\n");
221 ret
= devm_request_irq(dev
, d
->irq
, exynos_eint_gpio_irq
,
222 0, dev_name(dev
), d
);
224 dev_err(dev
, "irq request failed\n");
228 bank
= d
->ctrl
->pin_banks
;
229 for (i
= 0; i
< d
->ctrl
->nr_banks
; ++i
, ++bank
) {
230 if (bank
->eint_type
!= EINT_TYPE_GPIO
)
232 bank
->irq_domain
= irq_domain_add_linear(bank
->of_node
,
233 bank
->nr_pins
, &exynos_gpio_irqd_ops
, bank
);
234 if (!bank
->irq_domain
) {
235 dev_err(dev
, "gpio irq domain add failed\n");
240 bank
->soc_priv
= devm_kzalloc(d
->dev
,
241 sizeof(struct exynos_eint_gpio_save
), GFP_KERNEL
);
242 if (!bank
->soc_priv
) {
243 irq_domain_remove(bank
->irq_domain
);
252 for (--i
, --bank
; i
>= 0; --i
, --bank
) {
253 if (bank
->eint_type
!= EINT_TYPE_GPIO
)
255 irq_domain_remove(bank
->irq_domain
);
261 static void exynos_wkup_irq_unmask(struct irq_data
*irqd
)
263 struct samsung_pin_bank
*b
= irq_data_get_irq_chip_data(irqd
);
264 struct samsung_pinctrl_drv_data
*d
= b
->drvdata
;
265 unsigned long reg_mask
= d
->ctrl
->weint_mask
+ b
->eint_offset
;
268 mask
= readl(d
->virt_base
+ reg_mask
);
269 mask
&= ~(1 << irqd
->hwirq
);
270 writel(mask
, d
->virt_base
+ reg_mask
);
273 static void exynos_wkup_irq_mask(struct irq_data
*irqd
)
275 struct samsung_pin_bank
*b
= irq_data_get_irq_chip_data(irqd
);
276 struct samsung_pinctrl_drv_data
*d
= b
->drvdata
;
277 unsigned long reg_mask
= d
->ctrl
->weint_mask
+ b
->eint_offset
;
280 mask
= readl(d
->virt_base
+ reg_mask
);
281 mask
|= 1 << irqd
->hwirq
;
282 writel(mask
, d
->virt_base
+ reg_mask
);
285 static void exynos_wkup_irq_ack(struct irq_data
*irqd
)
287 struct samsung_pin_bank
*b
= irq_data_get_irq_chip_data(irqd
);
288 struct samsung_pinctrl_drv_data
*d
= b
->drvdata
;
289 unsigned long pend
= d
->ctrl
->weint_pend
+ b
->eint_offset
;
291 writel(1 << irqd
->hwirq
, d
->virt_base
+ pend
);
294 static int exynos_wkup_irq_set_type(struct irq_data
*irqd
, unsigned int type
)
296 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
297 struct samsung_pin_bank_type
*bank_type
= bank
->type
;
298 struct samsung_pinctrl_drv_data
*d
= bank
->drvdata
;
299 unsigned int pin
= irqd
->hwirq
;
300 unsigned long reg_con
= d
->ctrl
->weint_con
+ bank
->eint_offset
;
301 unsigned long shift
= EXYNOS_EINT_CON_LEN
* pin
;
302 unsigned long con
, trig_type
;
307 case IRQ_TYPE_EDGE_RISING
:
308 trig_type
= EXYNOS_EINT_EDGE_RISING
;
310 case IRQ_TYPE_EDGE_FALLING
:
311 trig_type
= EXYNOS_EINT_EDGE_FALLING
;
313 case IRQ_TYPE_EDGE_BOTH
:
314 trig_type
= EXYNOS_EINT_EDGE_BOTH
;
316 case IRQ_TYPE_LEVEL_HIGH
:
317 trig_type
= EXYNOS_EINT_LEVEL_HIGH
;
319 case IRQ_TYPE_LEVEL_LOW
:
320 trig_type
= EXYNOS_EINT_LEVEL_LOW
;
323 pr_err("unsupported external interrupt type\n");
327 if (type
& IRQ_TYPE_EDGE_BOTH
)
328 __irq_set_handler_locked(irqd
->irq
, handle_edge_irq
);
330 __irq_set_handler_locked(irqd
->irq
, handle_level_irq
);
332 con
= readl(d
->virt_base
+ reg_con
);
333 con
&= ~(EXYNOS_EINT_CON_MASK
<< shift
);
334 con
|= trig_type
<< shift
;
335 writel(con
, d
->virt_base
+ reg_con
);
337 reg_con
= bank
->pctl_offset
+ bank_type
->reg_offset
[PINCFG_TYPE_FUNC
];
338 shift
= pin
* bank_type
->fld_width
[PINCFG_TYPE_FUNC
];
339 mask
= (1 << bank_type
->fld_width
[PINCFG_TYPE_FUNC
]) - 1;
341 spin_lock_irqsave(&bank
->slock
, flags
);
343 con
= readl(d
->virt_base
+ reg_con
);
344 con
&= ~(mask
<< shift
);
345 con
|= EXYNOS_EINT_FUNC
<< shift
;
346 writel(con
, d
->virt_base
+ reg_con
);
348 spin_unlock_irqrestore(&bank
->slock
, flags
);
353 static u32 exynos_eint_wake_mask
= 0xffffffff;
355 u32
exynos_get_eint_wake_mask(void)
357 return exynos_eint_wake_mask
;
360 static int exynos_wkup_irq_set_wake(struct irq_data
*irqd
, unsigned int on
)
362 struct samsung_pin_bank
*bank
= irq_data_get_irq_chip_data(irqd
);
363 unsigned long bit
= 1UL << (2 * bank
->eint_offset
+ irqd
->hwirq
);
365 pr_info("wake %s for irq %d\n", on
? "enabled" : "disabled", irqd
->irq
);
368 exynos_eint_wake_mask
|= bit
;
370 exynos_eint_wake_mask
&= ~bit
;
376 * irq_chip for wakeup interrupts
378 static struct irq_chip exynos_wkup_irq_chip
= {
379 .name
= "exynos_wkup_irq_chip",
380 .irq_unmask
= exynos_wkup_irq_unmask
,
381 .irq_mask
= exynos_wkup_irq_mask
,
382 .irq_ack
= exynos_wkup_irq_ack
,
383 .irq_set_type
= exynos_wkup_irq_set_type
,
384 .irq_set_wake
= exynos_wkup_irq_set_wake
,
387 /* interrupt handler for wakeup interrupts 0..15 */
388 static void exynos_irq_eint0_15(unsigned int irq
, struct irq_desc
*desc
)
390 struct exynos_weint_data
*eintd
= irq_get_handler_data(irq
);
391 struct samsung_pin_bank
*bank
= eintd
->bank
;
392 struct irq_chip
*chip
= irq_get_chip(irq
);
395 chained_irq_enter(chip
, desc
);
396 chip
->irq_mask(&desc
->irq_data
);
399 chip
->irq_ack(&desc
->irq_data
);
401 eint_irq
= irq_linear_revmap(bank
->irq_domain
, eintd
->irq
);
402 generic_handle_irq(eint_irq
);
403 chip
->irq_unmask(&desc
->irq_data
);
404 chained_irq_exit(chip
, desc
);
407 static inline void exynos_irq_demux_eint(unsigned long pend
,
408 struct irq_domain
*domain
)
414 generic_handle_irq(irq_find_mapping(domain
, irq
));
419 /* interrupt handler for wakeup interrupt 16 */
420 static void exynos_irq_demux_eint16_31(unsigned int irq
, struct irq_desc
*desc
)
422 struct irq_chip
*chip
= irq_get_chip(irq
);
423 struct exynos_muxed_weint_data
*eintd
= irq_get_handler_data(irq
);
424 struct samsung_pinctrl_drv_data
*d
= eintd
->banks
[0]->drvdata
;
425 struct samsung_pin_ctrl
*ctrl
= d
->ctrl
;
430 chained_irq_enter(chip
, desc
);
432 for (i
= 0; i
< eintd
->nr_banks
; ++i
) {
433 struct samsung_pin_bank
*b
= eintd
->banks
[i
];
434 pend
= readl(d
->virt_base
+ ctrl
->weint_pend
+ b
->eint_offset
);
435 mask
= readl(d
->virt_base
+ ctrl
->weint_mask
+ b
->eint_offset
);
436 exynos_irq_demux_eint(pend
& ~mask
, b
->irq_domain
);
439 chained_irq_exit(chip
, desc
);
442 static int exynos_wkup_irq_map(struct irq_domain
*h
, unsigned int virq
,
445 irq_set_chip_and_handler(virq
, &exynos_wkup_irq_chip
, handle_level_irq
);
446 irq_set_chip_data(virq
, h
->host_data
);
447 set_irq_flags(virq
, IRQF_VALID
);
452 * irq domain callbacks for external wakeup interrupt controller.
454 static const struct irq_domain_ops exynos_wkup_irqd_ops
= {
455 .map
= exynos_wkup_irq_map
,
456 .xlate
= irq_domain_xlate_twocell
,
460 * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
461 * @d: driver data of samsung pinctrl driver.
463 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data
*d
)
465 struct device
*dev
= d
->dev
;
466 struct device_node
*wkup_np
= NULL
;
467 struct device_node
*np
;
468 struct samsung_pin_bank
*bank
;
469 struct exynos_weint_data
*weint_data
;
470 struct exynos_muxed_weint_data
*muxed_data
;
471 unsigned int muxed_banks
= 0;
475 for_each_child_of_node(dev
->of_node
, np
) {
476 if (of_match_node(exynos_wkup_irq_ids
, np
)) {
484 bank
= d
->ctrl
->pin_banks
;
485 for (i
= 0; i
< d
->ctrl
->nr_banks
; ++i
, ++bank
) {
486 if (bank
->eint_type
!= EINT_TYPE_WKUP
)
489 bank
->irq_domain
= irq_domain_add_linear(bank
->of_node
,
490 bank
->nr_pins
, &exynos_wkup_irqd_ops
, bank
);
491 if (!bank
->irq_domain
) {
492 dev_err(dev
, "wkup irq domain add failed\n");
496 if (!of_find_property(bank
->of_node
, "interrupts", NULL
)) {
497 bank
->eint_type
= EINT_TYPE_WKUP_MUX
;
502 weint_data
= devm_kzalloc(dev
, bank
->nr_pins
503 * sizeof(*weint_data
), GFP_KERNEL
);
505 dev_err(dev
, "could not allocate memory for weint_data\n");
509 for (idx
= 0; idx
< bank
->nr_pins
; ++idx
) {
510 irq
= irq_of_parse_and_map(bank
->of_node
, idx
);
512 dev_err(dev
, "irq number for eint-%s-%d not found\n",
516 weint_data
[idx
].irq
= idx
;
517 weint_data
[idx
].bank
= bank
;
518 irq_set_handler_data(irq
, &weint_data
[idx
]);
519 irq_set_chained_handler(irq
, exynos_irq_eint0_15
);
526 irq
= irq_of_parse_and_map(wkup_np
, 0);
528 dev_err(dev
, "irq number for muxed EINTs not found\n");
532 muxed_data
= devm_kzalloc(dev
, sizeof(*muxed_data
)
533 + muxed_banks
*sizeof(struct samsung_pin_bank
*), GFP_KERNEL
);
535 dev_err(dev
, "could not allocate memory for muxed_data\n");
539 irq_set_chained_handler(irq
, exynos_irq_demux_eint16_31
);
540 irq_set_handler_data(irq
, muxed_data
);
542 bank
= d
->ctrl
->pin_banks
;
544 for (i
= 0; i
< d
->ctrl
->nr_banks
; ++i
, ++bank
) {
545 if (bank
->eint_type
!= EINT_TYPE_WKUP_MUX
)
548 muxed_data
->banks
[idx
++] = bank
;
550 muxed_data
->nr_banks
= muxed_banks
;
555 static void exynos_pinctrl_suspend_bank(
556 struct samsung_pinctrl_drv_data
*drvdata
,
557 struct samsung_pin_bank
*bank
)
559 struct exynos_eint_gpio_save
*save
= bank
->soc_priv
;
560 void __iomem
*regs
= drvdata
->virt_base
;
562 save
->eint_con
= readl(regs
+ EXYNOS_GPIO_ECON_OFFSET
563 + bank
->eint_offset
);
564 save
->eint_fltcon0
= readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
565 + 2 * bank
->eint_offset
);
566 save
->eint_fltcon1
= readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
567 + 2 * bank
->eint_offset
+ 4);
569 pr_debug("%s: save con %#010x\n", bank
->name
, save
->eint_con
);
570 pr_debug("%s: save fltcon0 %#010x\n", bank
->name
, save
->eint_fltcon0
);
571 pr_debug("%s: save fltcon1 %#010x\n", bank
->name
, save
->eint_fltcon1
);
574 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data
*drvdata
)
576 struct samsung_pin_ctrl
*ctrl
= drvdata
->ctrl
;
577 struct samsung_pin_bank
*bank
= ctrl
->pin_banks
;
580 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
)
581 if (bank
->eint_type
== EINT_TYPE_GPIO
)
582 exynos_pinctrl_suspend_bank(drvdata
, bank
);
585 static void exynos_pinctrl_resume_bank(
586 struct samsung_pinctrl_drv_data
*drvdata
,
587 struct samsung_pin_bank
*bank
)
589 struct exynos_eint_gpio_save
*save
= bank
->soc_priv
;
590 void __iomem
*regs
= drvdata
->virt_base
;
592 pr_debug("%s: con %#010x => %#010x\n", bank
->name
,
593 readl(regs
+ EXYNOS_GPIO_ECON_OFFSET
594 + bank
->eint_offset
), save
->eint_con
);
595 pr_debug("%s: fltcon0 %#010x => %#010x\n", bank
->name
,
596 readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
597 + 2 * bank
->eint_offset
), save
->eint_fltcon0
);
598 pr_debug("%s: fltcon1 %#010x => %#010x\n", bank
->name
,
599 readl(regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
600 + 2 * bank
->eint_offset
+ 4), save
->eint_fltcon1
);
602 writel(save
->eint_con
, regs
+ EXYNOS_GPIO_ECON_OFFSET
603 + bank
->eint_offset
);
604 writel(save
->eint_fltcon0
, regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
605 + 2 * bank
->eint_offset
);
606 writel(save
->eint_fltcon1
, regs
+ EXYNOS_GPIO_EFLTCON_OFFSET
607 + 2 * bank
->eint_offset
+ 4);
610 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data
*drvdata
)
612 struct samsung_pin_ctrl
*ctrl
= drvdata
->ctrl
;
613 struct samsung_pin_bank
*bank
= ctrl
->pin_banks
;
616 for (i
= 0; i
< ctrl
->nr_banks
; ++i
, ++bank
)
617 if (bank
->eint_type
== EINT_TYPE_GPIO
)
618 exynos_pinctrl_resume_bank(drvdata
, bank
);
621 /* pin banks of exynos4210 pin-controller 0 */
622 static struct samsung_pin_bank exynos4210_pin_banks0
[] = {
623 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
624 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
625 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
626 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
627 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
628 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
629 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
630 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
631 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
632 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
633 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
634 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
635 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
636 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
637 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
638 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
641 /* pin banks of exynos4210 pin-controller 1 */
642 static struct samsung_pin_bank exynos4210_pin_banks1
[] = {
643 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
644 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
645 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
646 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
647 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
648 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
649 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
650 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
651 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
652 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
653 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
654 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
655 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
656 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
657 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
658 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
659 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
660 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
661 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
662 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
665 /* pin banks of exynos4210 pin-controller 2 */
666 static struct samsung_pin_bank exynos4210_pin_banks2
[] = {
667 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
671 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
672 * three gpio/pin-mux/pinconfig controllers.
674 struct samsung_pin_ctrl exynos4210_pin_ctrl
[] = {
676 /* pin-controller instance 0 data */
677 .pin_banks
= exynos4210_pin_banks0
,
678 .nr_banks
= ARRAY_SIZE(exynos4210_pin_banks0
),
679 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
680 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
681 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
682 .svc
= EXYNOS_SVC_OFFSET
,
683 .eint_gpio_init
= exynos_eint_gpio_init
,
684 .suspend
= exynos_pinctrl_suspend
,
685 .resume
= exynos_pinctrl_resume
,
686 .label
= "exynos4210-gpio-ctrl0",
688 /* pin-controller instance 1 data */
689 .pin_banks
= exynos4210_pin_banks1
,
690 .nr_banks
= ARRAY_SIZE(exynos4210_pin_banks1
),
691 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
692 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
693 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
694 .weint_con
= EXYNOS_WKUP_ECON_OFFSET
,
695 .weint_mask
= EXYNOS_WKUP_EMASK_OFFSET
,
696 .weint_pend
= EXYNOS_WKUP_EPEND_OFFSET
,
697 .svc
= EXYNOS_SVC_OFFSET
,
698 .eint_gpio_init
= exynos_eint_gpio_init
,
699 .eint_wkup_init
= exynos_eint_wkup_init
,
700 .suspend
= exynos_pinctrl_suspend
,
701 .resume
= exynos_pinctrl_resume
,
702 .label
= "exynos4210-gpio-ctrl1",
704 /* pin-controller instance 2 data */
705 .pin_banks
= exynos4210_pin_banks2
,
706 .nr_banks
= ARRAY_SIZE(exynos4210_pin_banks2
),
707 .label
= "exynos4210-gpio-ctrl2",
711 /* pin banks of exynos4x12 pin-controller 0 */
712 static struct samsung_pin_bank exynos4x12_pin_banks0
[] = {
713 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
714 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
715 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
716 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
717 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
718 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
719 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
720 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
721 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
722 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
723 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
724 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
725 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
728 /* pin banks of exynos4x12 pin-controller 1 */
729 static struct samsung_pin_bank exynos4x12_pin_banks1
[] = {
730 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
731 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
732 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
733 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
734 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
735 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
736 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
737 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
738 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
739 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
740 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
741 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
742 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
743 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
744 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
745 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
746 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
747 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
748 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
749 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
750 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
751 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
752 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
755 /* pin banks of exynos4x12 pin-controller 2 */
756 static struct samsung_pin_bank exynos4x12_pin_banks2
[] = {
757 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
760 /* pin banks of exynos4x12 pin-controller 3 */
761 static struct samsung_pin_bank exynos4x12_pin_banks3
[] = {
762 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
763 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
764 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
765 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
766 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
770 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
771 * four gpio/pin-mux/pinconfig controllers.
773 struct samsung_pin_ctrl exynos4x12_pin_ctrl
[] = {
775 /* pin-controller instance 0 data */
776 .pin_banks
= exynos4x12_pin_banks0
,
777 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks0
),
778 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
779 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
780 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
781 .svc
= EXYNOS_SVC_OFFSET
,
782 .eint_gpio_init
= exynos_eint_gpio_init
,
783 .suspend
= exynos_pinctrl_suspend
,
784 .resume
= exynos_pinctrl_resume
,
785 .label
= "exynos4x12-gpio-ctrl0",
787 /* pin-controller instance 1 data */
788 .pin_banks
= exynos4x12_pin_banks1
,
789 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks1
),
790 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
791 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
792 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
793 .weint_con
= EXYNOS_WKUP_ECON_OFFSET
,
794 .weint_mask
= EXYNOS_WKUP_EMASK_OFFSET
,
795 .weint_pend
= EXYNOS_WKUP_EPEND_OFFSET
,
796 .svc
= EXYNOS_SVC_OFFSET
,
797 .eint_gpio_init
= exynos_eint_gpio_init
,
798 .eint_wkup_init
= exynos_eint_wkup_init
,
799 .suspend
= exynos_pinctrl_suspend
,
800 .resume
= exynos_pinctrl_resume
,
801 .label
= "exynos4x12-gpio-ctrl1",
803 /* pin-controller instance 2 data */
804 .pin_banks
= exynos4x12_pin_banks2
,
805 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks2
),
806 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
807 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
808 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
809 .svc
= EXYNOS_SVC_OFFSET
,
810 .eint_gpio_init
= exynos_eint_gpio_init
,
811 .suspend
= exynos_pinctrl_suspend
,
812 .resume
= exynos_pinctrl_resume
,
813 .label
= "exynos4x12-gpio-ctrl2",
815 /* pin-controller instance 3 data */
816 .pin_banks
= exynos4x12_pin_banks3
,
817 .nr_banks
= ARRAY_SIZE(exynos4x12_pin_banks3
),
818 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
819 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
820 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
821 .svc
= EXYNOS_SVC_OFFSET
,
822 .eint_gpio_init
= exynos_eint_gpio_init
,
823 .suspend
= exynos_pinctrl_suspend
,
824 .resume
= exynos_pinctrl_resume
,
825 .label
= "exynos4x12-gpio-ctrl3",
829 /* pin banks of exynos5250 pin-controller 0 */
830 static struct samsung_pin_bank exynos5250_pin_banks0
[] = {
831 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
832 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
833 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
834 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
835 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
836 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
837 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
838 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
839 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
840 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
841 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
842 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
843 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
844 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
845 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
846 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
847 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
848 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
849 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
850 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
851 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
852 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
853 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
854 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
855 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
858 /* pin banks of exynos5250 pin-controller 1 */
859 static struct samsung_pin_bank exynos5250_pin_banks1
[] = {
860 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
861 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
862 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
863 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
864 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
865 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
866 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
867 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
868 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
871 /* pin banks of exynos5250 pin-controller 2 */
872 static struct samsung_pin_bank exynos5250_pin_banks2
[] = {
873 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
874 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
875 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
876 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
877 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
880 /* pin banks of exynos5250 pin-controller 3 */
881 static struct samsung_pin_bank exynos5250_pin_banks3
[] = {
882 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
886 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
887 * four gpio/pin-mux/pinconfig controllers.
889 struct samsung_pin_ctrl exynos5250_pin_ctrl
[] = {
891 /* pin-controller instance 0 data */
892 .pin_banks
= exynos5250_pin_banks0
,
893 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks0
),
894 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
895 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
896 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
897 .weint_con
= EXYNOS_WKUP_ECON_OFFSET
,
898 .weint_mask
= EXYNOS_WKUP_EMASK_OFFSET
,
899 .weint_pend
= EXYNOS_WKUP_EPEND_OFFSET
,
900 .svc
= EXYNOS_SVC_OFFSET
,
901 .eint_gpio_init
= exynos_eint_gpio_init
,
902 .eint_wkup_init
= exynos_eint_wkup_init
,
903 .suspend
= exynos_pinctrl_suspend
,
904 .resume
= exynos_pinctrl_resume
,
905 .label
= "exynos5250-gpio-ctrl0",
907 /* pin-controller instance 1 data */
908 .pin_banks
= exynos5250_pin_banks1
,
909 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks1
),
910 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
911 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
912 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
913 .svc
= EXYNOS_SVC_OFFSET
,
914 .eint_gpio_init
= exynos_eint_gpio_init
,
915 .suspend
= exynos_pinctrl_suspend
,
916 .resume
= exynos_pinctrl_resume
,
917 .label
= "exynos5250-gpio-ctrl1",
919 /* pin-controller instance 2 data */
920 .pin_banks
= exynos5250_pin_banks2
,
921 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks2
),
922 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
923 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
924 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
925 .svc
= EXYNOS_SVC_OFFSET
,
926 .eint_gpio_init
= exynos_eint_gpio_init
,
927 .suspend
= exynos_pinctrl_suspend
,
928 .resume
= exynos_pinctrl_resume
,
929 .label
= "exynos5250-gpio-ctrl2",
931 /* pin-controller instance 3 data */
932 .pin_banks
= exynos5250_pin_banks3
,
933 .nr_banks
= ARRAY_SIZE(exynos5250_pin_banks3
),
934 .geint_con
= EXYNOS_GPIO_ECON_OFFSET
,
935 .geint_mask
= EXYNOS_GPIO_EMASK_OFFSET
,
936 .geint_pend
= EXYNOS_GPIO_EPEND_OFFSET
,
937 .svc
= EXYNOS_SVC_OFFSET
,
938 .eint_gpio_init
= exynos_eint_gpio_init
,
939 .suspend
= exynos_pinctrl_suspend
,
940 .resume
= exynos_pinctrl_resume
,
941 .label
= "exynos5250-gpio-ctrl3",