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Merge tag 'for-v3.10' of git://git.infradead.org/users/cbou/linux-pstore
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-bcm2835.c
1 /*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/irqdesc.h>
31 #include <linux/irqdomain.h>
32 #include <linux/module.h>
33 #include <linux/of_address.h>
34 #include <linux/of.h>
35 #include <linux/of_irq.h>
36 #include <linux/pinctrl/consumer.h>
37 #include <linux/pinctrl/machine.h>
38 #include <linux/pinctrl/pinconf.h>
39 #include <linux/pinctrl/pinctrl.h>
40 #include <linux/pinctrl/pinmux.h>
41 #include <linux/platform_device.h>
42 #include <linux/seq_file.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45 #include <linux/types.h>
46
47 #define MODULE_NAME "pinctrl-bcm2835"
48 #define BCM2835_NUM_GPIOS 54
49 #define BCM2835_NUM_BANKS 2
50
51 #define BCM2835_PIN_BITMAP_SZ \
52 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53
54 /* GPIO register offsets */
55 #define GPFSEL0 0x0 /* Function Select */
56 #define GPSET0 0x1c /* Pin Output Set */
57 #define GPCLR0 0x28 /* Pin Output Clear */
58 #define GPLEV0 0x34 /* Pin Level */
59 #define GPEDS0 0x40 /* Pin Event Detect Status */
60 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
61 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
62 #define GPHEN0 0x64 /* Pin High Detect Enable */
63 #define GPLEN0 0x70 /* Pin Low Detect Enable */
64 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
65 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
66 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
67 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
68
69 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
70 #define FSEL_SHIFT(p) (((p) % 10) * 3)
71 #define GPIO_REG_OFFSET(p) ((p) / 32)
72 #define GPIO_REG_SHIFT(p) ((p) % 32)
73
74 enum bcm2835_pinconf_param {
75 /* argument: bcm2835_pinconf_pull */
76 BCM2835_PINCONF_PARAM_PULL,
77 };
78
79 enum bcm2835_pinconf_pull {
80 BCM2835_PINCONFIG_PULL_NONE,
81 BCM2835_PINCONFIG_PULL_DOWN,
82 BCM2835_PINCONFIG_PULL_UP,
83 };
84
85 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
86 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
87 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
88
89 struct bcm2835_gpio_irqdata {
90 struct bcm2835_pinctrl *pc;
91 int bank;
92 };
93
94 struct bcm2835_pinctrl {
95 struct device *dev;
96 void __iomem *base;
97 int irq[BCM2835_NUM_BANKS];
98
99 /* note: locking assumes each bank will have its own unsigned long */
100 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
101 unsigned int irq_type[BCM2835_NUM_GPIOS];
102
103 struct pinctrl_dev *pctl_dev;
104 struct irq_domain *irq_domain;
105 struct gpio_chip gpio_chip;
106 struct pinctrl_gpio_range gpio_range;
107
108 struct bcm2835_gpio_irqdata irq_data[BCM2835_NUM_BANKS];
109 spinlock_t irq_lock[BCM2835_NUM_BANKS];
110 };
111
112 static struct lock_class_key gpio_lock_class;
113
114 /* pins are just named GPIO0..GPIO53 */
115 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
116 struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
117 BCM2835_GPIO_PIN(0),
118 BCM2835_GPIO_PIN(1),
119 BCM2835_GPIO_PIN(2),
120 BCM2835_GPIO_PIN(3),
121 BCM2835_GPIO_PIN(4),
122 BCM2835_GPIO_PIN(5),
123 BCM2835_GPIO_PIN(6),
124 BCM2835_GPIO_PIN(7),
125 BCM2835_GPIO_PIN(8),
126 BCM2835_GPIO_PIN(9),
127 BCM2835_GPIO_PIN(10),
128 BCM2835_GPIO_PIN(11),
129 BCM2835_GPIO_PIN(12),
130 BCM2835_GPIO_PIN(13),
131 BCM2835_GPIO_PIN(14),
132 BCM2835_GPIO_PIN(15),
133 BCM2835_GPIO_PIN(16),
134 BCM2835_GPIO_PIN(17),
135 BCM2835_GPIO_PIN(18),
136 BCM2835_GPIO_PIN(19),
137 BCM2835_GPIO_PIN(20),
138 BCM2835_GPIO_PIN(21),
139 BCM2835_GPIO_PIN(22),
140 BCM2835_GPIO_PIN(23),
141 BCM2835_GPIO_PIN(24),
142 BCM2835_GPIO_PIN(25),
143 BCM2835_GPIO_PIN(26),
144 BCM2835_GPIO_PIN(27),
145 BCM2835_GPIO_PIN(28),
146 BCM2835_GPIO_PIN(29),
147 BCM2835_GPIO_PIN(30),
148 BCM2835_GPIO_PIN(31),
149 BCM2835_GPIO_PIN(32),
150 BCM2835_GPIO_PIN(33),
151 BCM2835_GPIO_PIN(34),
152 BCM2835_GPIO_PIN(35),
153 BCM2835_GPIO_PIN(36),
154 BCM2835_GPIO_PIN(37),
155 BCM2835_GPIO_PIN(38),
156 BCM2835_GPIO_PIN(39),
157 BCM2835_GPIO_PIN(40),
158 BCM2835_GPIO_PIN(41),
159 BCM2835_GPIO_PIN(42),
160 BCM2835_GPIO_PIN(43),
161 BCM2835_GPIO_PIN(44),
162 BCM2835_GPIO_PIN(45),
163 BCM2835_GPIO_PIN(46),
164 BCM2835_GPIO_PIN(47),
165 BCM2835_GPIO_PIN(48),
166 BCM2835_GPIO_PIN(49),
167 BCM2835_GPIO_PIN(50),
168 BCM2835_GPIO_PIN(51),
169 BCM2835_GPIO_PIN(52),
170 BCM2835_GPIO_PIN(53),
171 };
172
173 /* one pin per group */
174 static const char * const bcm2835_gpio_groups[] = {
175 "gpio0",
176 "gpio1",
177 "gpio2",
178 "gpio3",
179 "gpio4",
180 "gpio5",
181 "gpio6",
182 "gpio7",
183 "gpio8",
184 "gpio9",
185 "gpio10",
186 "gpio11",
187 "gpio12",
188 "gpio13",
189 "gpio14",
190 "gpio15",
191 "gpio16",
192 "gpio17",
193 "gpio18",
194 "gpio19",
195 "gpio20",
196 "gpio21",
197 "gpio22",
198 "gpio23",
199 "gpio24",
200 "gpio25",
201 "gpio26",
202 "gpio27",
203 "gpio28",
204 "gpio29",
205 "gpio30",
206 "gpio31",
207 "gpio32",
208 "gpio33",
209 "gpio34",
210 "gpio35",
211 "gpio36",
212 "gpio37",
213 "gpio38",
214 "gpio39",
215 "gpio40",
216 "gpio41",
217 "gpio42",
218 "gpio43",
219 "gpio44",
220 "gpio45",
221 "gpio46",
222 "gpio47",
223 "gpio48",
224 "gpio49",
225 "gpio50",
226 "gpio51",
227 "gpio52",
228 "gpio53",
229 };
230
231 enum bcm2835_fsel {
232 BCM2835_FSEL_GPIO_IN = 0,
233 BCM2835_FSEL_GPIO_OUT = 1,
234 BCM2835_FSEL_ALT0 = 4,
235 BCM2835_FSEL_ALT1 = 5,
236 BCM2835_FSEL_ALT2 = 6,
237 BCM2835_FSEL_ALT3 = 7,
238 BCM2835_FSEL_ALT4 = 3,
239 BCM2835_FSEL_ALT5 = 2,
240 BCM2835_FSEL_COUNT = 8,
241 BCM2835_FSEL_MASK = 0x7,
242 };
243
244 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
245 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
246 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
247 [BCM2835_FSEL_ALT0] = "alt0",
248 [BCM2835_FSEL_ALT1] = "alt1",
249 [BCM2835_FSEL_ALT2] = "alt2",
250 [BCM2835_FSEL_ALT3] = "alt3",
251 [BCM2835_FSEL_ALT4] = "alt4",
252 [BCM2835_FSEL_ALT5] = "alt5",
253 };
254
255 static const char * const irq_type_names[] = {
256 [IRQ_TYPE_NONE] = "none",
257 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
258 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
259 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
260 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
261 [IRQ_TYPE_LEVEL_LOW] = "level-low",
262 };
263
264 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
265 {
266 return readl(pc->base + reg);
267 }
268
269 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
270 u32 val)
271 {
272 writel(val, pc->base + reg);
273 }
274
275 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
276 unsigned bit)
277 {
278 reg += GPIO_REG_OFFSET(bit) * 4;
279 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
280 }
281
282 /* note NOT a read/modify/write cycle */
283 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
284 unsigned reg, unsigned bit)
285 {
286 reg += GPIO_REG_OFFSET(bit) * 4;
287 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
288 }
289
290 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
291 struct bcm2835_pinctrl *pc, unsigned pin)
292 {
293 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
294 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
295
296 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
297 bcm2835_functions[status]);
298
299 return status;
300 }
301
302 static inline void bcm2835_pinctrl_fsel_set(
303 struct bcm2835_pinctrl *pc, unsigned pin,
304 enum bcm2835_fsel fsel)
305 {
306 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
307 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
308
309 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
310 bcm2835_functions[cur]);
311
312 if (cur == fsel)
313 return;
314
315 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
316 /* always transition through GPIO_IN */
317 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
318 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
319
320 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
321 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
322 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
323 }
324
325 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
326 val |= fsel << FSEL_SHIFT(pin);
327
328 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
329 bcm2835_functions[fsel]);
330 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
331 }
332
333 static int bcm2835_gpio_request(struct gpio_chip *chip, unsigned offset)
334 {
335 return pinctrl_request_gpio(chip->base + offset);
336 }
337
338 static void bcm2835_gpio_free(struct gpio_chip *chip, unsigned offset)
339 {
340 pinctrl_free_gpio(chip->base + offset);
341 }
342
343 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
344 {
345 return pinctrl_gpio_direction_input(chip->base + offset);
346 }
347
348 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
349 {
350 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
351
352 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
353 }
354
355 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
356 unsigned offset, int value)
357 {
358 return pinctrl_gpio_direction_output(chip->base + offset);
359 }
360
361 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
362 {
363 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
364
365 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
366 }
367
368 static int bcm2835_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
369 {
370 struct bcm2835_pinctrl *pc = dev_get_drvdata(chip->dev);
371
372 return irq_linear_revmap(pc->irq_domain, offset);
373 }
374
375 static struct gpio_chip bcm2835_gpio_chip = {
376 .label = MODULE_NAME,
377 .owner = THIS_MODULE,
378 .request = bcm2835_gpio_request,
379 .free = bcm2835_gpio_free,
380 .direction_input = bcm2835_gpio_direction_input,
381 .direction_output = bcm2835_gpio_direction_output,
382 .get = bcm2835_gpio_get,
383 .set = bcm2835_gpio_set,
384 .to_irq = bcm2835_gpio_to_irq,
385 .base = -1,
386 .ngpio = BCM2835_NUM_GPIOS,
387 .can_sleep = 0,
388 };
389
390 static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
391 {
392 struct bcm2835_gpio_irqdata *irqdata = dev_id;
393 struct bcm2835_pinctrl *pc = irqdata->pc;
394 int bank = irqdata->bank;
395 unsigned long events;
396 unsigned offset;
397 unsigned gpio;
398 unsigned int type;
399
400 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
401 events &= pc->enabled_irq_map[bank];
402 for_each_set_bit(offset, &events, 32) {
403 gpio = (32 * bank) + offset;
404 type = pc->irq_type[gpio];
405
406 /* ack edge triggered IRQs immediately */
407 if (!(type & IRQ_TYPE_LEVEL_MASK))
408 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
409
410 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
411
412 /* ack level triggered IRQ after handling them */
413 if (type & IRQ_TYPE_LEVEL_MASK)
414 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
415 }
416 return events ? IRQ_HANDLED : IRQ_NONE;
417 }
418
419 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
420 unsigned reg, unsigned offset, bool enable)
421 {
422 u32 value;
423 reg += GPIO_REG_OFFSET(offset) * 4;
424 value = bcm2835_gpio_rd(pc, reg);
425 if (enable)
426 value |= BIT(GPIO_REG_SHIFT(offset));
427 else
428 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
429 bcm2835_gpio_wr(pc, reg, value);
430 }
431
432 /* fast path for IRQ handler */
433 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
434 unsigned offset, bool enable)
435 {
436 switch (pc->irq_type[offset]) {
437 case IRQ_TYPE_EDGE_RISING:
438 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
439 break;
440
441 case IRQ_TYPE_EDGE_FALLING:
442 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
443 break;
444
445 case IRQ_TYPE_EDGE_BOTH:
446 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
447 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
448 break;
449
450 case IRQ_TYPE_LEVEL_HIGH:
451 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
452 break;
453
454 case IRQ_TYPE_LEVEL_LOW:
455 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
456 break;
457 }
458 }
459
460 static void bcm2835_gpio_irq_enable(struct irq_data *data)
461 {
462 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
463 unsigned gpio = irqd_to_hwirq(data);
464 unsigned offset = GPIO_REG_SHIFT(gpio);
465 unsigned bank = GPIO_REG_OFFSET(gpio);
466 unsigned long flags;
467
468 spin_lock_irqsave(&pc->irq_lock[bank], flags);
469 set_bit(offset, &pc->enabled_irq_map[bank]);
470 bcm2835_gpio_irq_config(pc, gpio, true);
471 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
472 }
473
474 static void bcm2835_gpio_irq_disable(struct irq_data *data)
475 {
476 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
477 unsigned gpio = irqd_to_hwirq(data);
478 unsigned offset = GPIO_REG_SHIFT(gpio);
479 unsigned bank = GPIO_REG_OFFSET(gpio);
480 unsigned long flags;
481
482 spin_lock_irqsave(&pc->irq_lock[bank], flags);
483 bcm2835_gpio_irq_config(pc, gpio, false);
484 clear_bit(offset, &pc->enabled_irq_map[bank]);
485 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
486 }
487
488 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
489 unsigned offset, unsigned int type)
490 {
491 switch (type) {
492 case IRQ_TYPE_NONE:
493 case IRQ_TYPE_EDGE_RISING:
494 case IRQ_TYPE_EDGE_FALLING:
495 case IRQ_TYPE_EDGE_BOTH:
496 case IRQ_TYPE_LEVEL_HIGH:
497 case IRQ_TYPE_LEVEL_LOW:
498 pc->irq_type[offset] = type;
499 break;
500
501 default:
502 return -EINVAL;
503 }
504 return 0;
505 }
506
507 /* slower path for reconfiguring IRQ type */
508 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
509 unsigned offset, unsigned int type)
510 {
511 switch (type) {
512 case IRQ_TYPE_NONE:
513 if (pc->irq_type[offset] != type) {
514 bcm2835_gpio_irq_config(pc, offset, false);
515 pc->irq_type[offset] = type;
516 }
517 break;
518
519 case IRQ_TYPE_EDGE_RISING:
520 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
521 /* RISING already enabled, disable FALLING */
522 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
523 bcm2835_gpio_irq_config(pc, offset, false);
524 pc->irq_type[offset] = type;
525 } else if (pc->irq_type[offset] != type) {
526 bcm2835_gpio_irq_config(pc, offset, false);
527 pc->irq_type[offset] = type;
528 bcm2835_gpio_irq_config(pc, offset, true);
529 }
530 break;
531
532 case IRQ_TYPE_EDGE_FALLING:
533 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
534 /* FALLING already enabled, disable RISING */
535 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
536 bcm2835_gpio_irq_config(pc, offset, false);
537 pc->irq_type[offset] = type;
538 } else if (pc->irq_type[offset] != type) {
539 bcm2835_gpio_irq_config(pc, offset, false);
540 pc->irq_type[offset] = type;
541 bcm2835_gpio_irq_config(pc, offset, true);
542 }
543 break;
544
545 case IRQ_TYPE_EDGE_BOTH:
546 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
547 /* RISING already enabled, enable FALLING too */
548 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
549 bcm2835_gpio_irq_config(pc, offset, true);
550 pc->irq_type[offset] = type;
551 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
552 /* FALLING already enabled, enable RISING too */
553 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
554 bcm2835_gpio_irq_config(pc, offset, true);
555 pc->irq_type[offset] = type;
556 } else if (pc->irq_type[offset] != type) {
557 bcm2835_gpio_irq_config(pc, offset, false);
558 pc->irq_type[offset] = type;
559 bcm2835_gpio_irq_config(pc, offset, true);
560 }
561 break;
562
563 case IRQ_TYPE_LEVEL_HIGH:
564 case IRQ_TYPE_LEVEL_LOW:
565 if (pc->irq_type[offset] != type) {
566 bcm2835_gpio_irq_config(pc, offset, false);
567 pc->irq_type[offset] = type;
568 bcm2835_gpio_irq_config(pc, offset, true);
569 }
570 break;
571
572 default:
573 return -EINVAL;
574 }
575 return 0;
576 }
577
578 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
579 {
580 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
581 unsigned gpio = irqd_to_hwirq(data);
582 unsigned offset = GPIO_REG_SHIFT(gpio);
583 unsigned bank = GPIO_REG_OFFSET(gpio);
584 unsigned long flags;
585 int ret;
586
587 spin_lock_irqsave(&pc->irq_lock[bank], flags);
588
589 if (test_bit(offset, &pc->enabled_irq_map[bank]))
590 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
591 else
592 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
593
594 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
595
596 return ret;
597 }
598
599 static struct irq_chip bcm2835_gpio_irq_chip = {
600 .name = MODULE_NAME,
601 .irq_enable = bcm2835_gpio_irq_enable,
602 .irq_disable = bcm2835_gpio_irq_disable,
603 .irq_set_type = bcm2835_gpio_irq_set_type,
604 };
605
606 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
607 {
608 return ARRAY_SIZE(bcm2835_gpio_groups);
609 }
610
611 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
612 unsigned selector)
613 {
614 return bcm2835_gpio_groups[selector];
615 }
616
617 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
618 unsigned selector,
619 const unsigned **pins,
620 unsigned *num_pins)
621 {
622 *pins = &bcm2835_gpio_pins[selector].number;
623 *num_pins = 1;
624
625 return 0;
626 }
627
628 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
629 struct seq_file *s,
630 unsigned offset)
631 {
632 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
633 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
634 const char *fname = bcm2835_functions[fsel];
635 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
636 int irq = irq_find_mapping(pc->irq_domain, offset);
637
638 seq_printf(s, "function %s in %s; irq %d (%s)",
639 fname, value ? "hi" : "lo",
640 irq, irq_type_names[pc->irq_type[offset]]);
641 }
642
643 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
644 struct pinctrl_map *maps, unsigned num_maps)
645 {
646 int i;
647
648 for (i = 0; i < num_maps; i++)
649 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
650 kfree(maps[i].data.configs.configs);
651
652 kfree(maps);
653 }
654
655 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
656 struct device_node *np, u32 pin, u32 fnum,
657 struct pinctrl_map **maps)
658 {
659 struct pinctrl_map *map = *maps;
660
661 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
662 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
663 of_node_full_name(np), fnum);
664 return -EINVAL;
665 }
666
667 map->type = PIN_MAP_TYPE_MUX_GROUP;
668 map->data.mux.group = bcm2835_gpio_groups[pin];
669 map->data.mux.function = bcm2835_functions[fnum];
670 (*maps)++;
671
672 return 0;
673 }
674
675 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
676 struct device_node *np, u32 pin, u32 pull,
677 struct pinctrl_map **maps)
678 {
679 struct pinctrl_map *map = *maps;
680 unsigned long *configs;
681
682 if (pull > 2) {
683 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
684 of_node_full_name(np), pull);
685 return -EINVAL;
686 }
687
688 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
689 if (!configs)
690 return -ENOMEM;
691 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
692
693 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
694 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
695 map->data.configs.configs = configs;
696 map->data.configs.num_configs = 1;
697 (*maps)++;
698
699 return 0;
700 }
701
702 static inline u32 prop_u32(struct property *p, int i)
703 {
704 return be32_to_cpup(((__be32 *)p->value) + i);
705 }
706
707 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
708 struct device_node *np,
709 struct pinctrl_map **map, unsigned *num_maps)
710 {
711 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
712 struct property *pins, *funcs, *pulls;
713 int num_pins, num_funcs, num_pulls, maps_per_pin;
714 struct pinctrl_map *maps, *cur_map;
715 int i, err;
716 u32 pin, func, pull;
717
718 pins = of_find_property(np, "brcm,pins", NULL);
719 if (!pins) {
720 dev_err(pc->dev, "%s: missing brcm,pins property\n",
721 of_node_full_name(np));
722 return -EINVAL;
723 }
724
725 funcs = of_find_property(np, "brcm,function", NULL);
726 pulls = of_find_property(np, "brcm,pull", NULL);
727
728 if (!funcs && !pulls) {
729 dev_err(pc->dev,
730 "%s: neither brcm,function nor brcm,pull specified\n",
731 of_node_full_name(np));
732 return -EINVAL;
733 }
734
735 num_pins = pins->length / 4;
736 num_funcs = funcs ? (funcs->length / 4) : 0;
737 num_pulls = pulls ? (pulls->length / 4) : 0;
738
739 if (num_funcs > 1 && num_funcs != num_pins) {
740 dev_err(pc->dev,
741 "%s: brcm,function must have 1 or %d entries\n",
742 of_node_full_name(np), num_pins);
743 return -EINVAL;
744 }
745
746 if (num_pulls > 1 && num_pulls != num_pins) {
747 dev_err(pc->dev,
748 "%s: brcm,pull must have 1 or %d entries\n",
749 of_node_full_name(np), num_pins);
750 return -EINVAL;
751 }
752
753 maps_per_pin = 0;
754 if (num_funcs)
755 maps_per_pin++;
756 if (num_pulls)
757 maps_per_pin++;
758 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
759 GFP_KERNEL);
760 if (!maps)
761 return -ENOMEM;
762
763 for (i = 0; i < num_pins; i++) {
764 pin = prop_u32(pins, i);
765 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
766 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
767 of_node_full_name(np), pin);
768 err = -EINVAL;
769 goto out;
770 }
771
772 if (num_funcs) {
773 func = prop_u32(funcs, (num_funcs > 1) ? i : 0);
774 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
775 func, &cur_map);
776 if (err)
777 goto out;
778 }
779 if (num_pulls) {
780 pull = prop_u32(pulls, (num_pulls > 1) ? i : 0);
781 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
782 pull, &cur_map);
783 if (err)
784 goto out;
785 }
786 }
787
788 *map = maps;
789 *num_maps = num_pins * maps_per_pin;
790
791 return 0;
792
793 out:
794 kfree(maps);
795 return err;
796 }
797
798 static const struct pinctrl_ops bcm2835_pctl_ops = {
799 .get_groups_count = bcm2835_pctl_get_groups_count,
800 .get_group_name = bcm2835_pctl_get_group_name,
801 .get_group_pins = bcm2835_pctl_get_group_pins,
802 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
803 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
804 .dt_free_map = bcm2835_pctl_dt_free_map,
805 };
806
807 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
808 {
809 return BCM2835_FSEL_COUNT;
810 }
811
812 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
813 unsigned selector)
814 {
815 return bcm2835_functions[selector];
816 }
817
818 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
819 unsigned selector,
820 const char * const **groups,
821 unsigned * const num_groups)
822 {
823 /* every pin can do every function */
824 *groups = bcm2835_gpio_groups;
825 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
826
827 return 0;
828 }
829
830 static int bcm2835_pmx_enable(struct pinctrl_dev *pctldev,
831 unsigned func_selector,
832 unsigned group_selector)
833 {
834 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
835
836 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
837
838 return 0;
839 }
840
841 static void bcm2835_pmx_disable(struct pinctrl_dev *pctldev,
842 unsigned func_selector,
843 unsigned group_selector)
844 {
845 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
846
847 /* disable by setting to GPIO_IN */
848 bcm2835_pinctrl_fsel_set(pc, group_selector, BCM2835_FSEL_GPIO_IN);
849 }
850
851 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
852 struct pinctrl_gpio_range *range,
853 unsigned offset)
854 {
855 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
856
857 /* disable by setting to GPIO_IN */
858 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
859 }
860
861 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
862 struct pinctrl_gpio_range *range,
863 unsigned offset,
864 bool input)
865 {
866 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
867 enum bcm2835_fsel fsel = input ?
868 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
869
870 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
871
872 return 0;
873 }
874
875 static const struct pinmux_ops bcm2835_pmx_ops = {
876 .get_functions_count = bcm2835_pmx_get_functions_count,
877 .get_function_name = bcm2835_pmx_get_function_name,
878 .get_function_groups = bcm2835_pmx_get_function_groups,
879 .enable = bcm2835_pmx_enable,
880 .disable = bcm2835_pmx_disable,
881 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
882 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
883 };
884
885 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
886 unsigned pin, unsigned long *config)
887 {
888 /* No way to read back config in HW */
889 return -ENOTSUPP;
890 }
891
892 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
893 unsigned pin, unsigned long config)
894 {
895 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
896 enum bcm2835_pinconf_param param = BCM2835_PINCONF_UNPACK_PARAM(config);
897 u16 arg = BCM2835_PINCONF_UNPACK_ARG(config);
898 u32 off, bit;
899
900 if (param != BCM2835_PINCONF_PARAM_PULL)
901 return -EINVAL;
902
903 off = GPIO_REG_OFFSET(pin);
904 bit = GPIO_REG_SHIFT(pin);
905
906 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
907 /*
908 * Docs say to wait 150 cycles, but not of what. We assume a
909 * 1 MHz clock here, which is pretty slow...
910 */
911 udelay(150);
912 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
913 udelay(150);
914 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
915
916 return 0;
917 }
918
919 static const struct pinconf_ops bcm2835_pinconf_ops = {
920 .pin_config_get = bcm2835_pinconf_get,
921 .pin_config_set = bcm2835_pinconf_set,
922 };
923
924 static struct pinctrl_desc bcm2835_pinctrl_desc = {
925 .name = MODULE_NAME,
926 .pins = bcm2835_gpio_pins,
927 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
928 .pctlops = &bcm2835_pctl_ops,
929 .pmxops = &bcm2835_pmx_ops,
930 .confops = &bcm2835_pinconf_ops,
931 .owner = THIS_MODULE,
932 };
933
934 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
935 .name = MODULE_NAME,
936 .npins = BCM2835_NUM_GPIOS,
937 };
938
939 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
940 {
941 struct device *dev = &pdev->dev;
942 struct device_node *np = dev->of_node;
943 struct bcm2835_pinctrl *pc;
944 struct resource iomem;
945 int err, i;
946 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
947 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
948
949 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
950 if (!pc)
951 return -ENOMEM;
952
953 platform_set_drvdata(pdev, pc);
954 pc->dev = dev;
955
956 err = of_address_to_resource(np, 0, &iomem);
957 if (err) {
958 dev_err(dev, "could not get IO memory\n");
959 return err;
960 }
961
962 pc->base = devm_ioremap_resource(dev, &iomem);
963 if (IS_ERR(pc->base))
964 return PTR_ERR(pc->base);
965
966 pc->gpio_chip = bcm2835_gpio_chip;
967 pc->gpio_chip.dev = dev;
968 pc->gpio_chip.of_node = np;
969
970 pc->irq_domain = irq_domain_add_linear(np, BCM2835_NUM_GPIOS,
971 &irq_domain_simple_ops, NULL);
972 if (!pc->irq_domain) {
973 dev_err(dev, "could not create IRQ domain\n");
974 return -ENOMEM;
975 }
976
977 for (i = 0; i < BCM2835_NUM_GPIOS; i++) {
978 int irq = irq_create_mapping(pc->irq_domain, i);
979 irq_set_lockdep_class(irq, &gpio_lock_class);
980 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
981 handle_simple_irq);
982 irq_set_chip_data(irq, pc);
983 set_irq_flags(irq, IRQF_VALID);
984 }
985
986 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
987 unsigned long events;
988 unsigned offset;
989 int len;
990 char *name;
991
992 /* clear event detection flags */
993 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
994 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
995 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
996 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
997 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
998 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
999
1000 /* clear all the events */
1001 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1002 for_each_set_bit(offset, &events, 32)
1003 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1004
1005 pc->irq[i] = irq_of_parse_and_map(np, i);
1006 pc->irq_data[i].pc = pc;
1007 pc->irq_data[i].bank = i;
1008 spin_lock_init(&pc->irq_lock[i]);
1009
1010 len = strlen(dev_name(pc->dev)) + 16;
1011 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1012 if (!name)
1013 return -ENOMEM;
1014 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1015
1016 err = devm_request_irq(dev, pc->irq[i],
1017 bcm2835_gpio_irq_handler, IRQF_SHARED,
1018 name, &pc->irq_data[i]);
1019 if (err) {
1020 dev_err(dev, "unable to request IRQ %d\n", pc->irq[i]);
1021 return err;
1022 }
1023 }
1024
1025 err = gpiochip_add(&pc->gpio_chip);
1026 if (err) {
1027 dev_err(dev, "could not add GPIO chip\n");
1028 return err;
1029 }
1030
1031 pc->pctl_dev = pinctrl_register(&bcm2835_pinctrl_desc, dev, pc);
1032 if (!pc->pctl_dev) {
1033 gpiochip_remove(&pc->gpio_chip);
1034 return -EINVAL;
1035 }
1036
1037 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1038 pc->gpio_range.base = pc->gpio_chip.base;
1039 pc->gpio_range.gc = &pc->gpio_chip;
1040 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1041
1042 return 0;
1043 }
1044
1045 static int bcm2835_pinctrl_remove(struct platform_device *pdev)
1046 {
1047 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1048
1049 pinctrl_unregister(pc->pctl_dev);
1050 gpiochip_remove(&pc->gpio_chip);
1051
1052 return 0;
1053 }
1054
1055 static struct of_device_id bcm2835_pinctrl_match[] = {
1056 { .compatible = "brcm,bcm2835-gpio" },
1057 {}
1058 };
1059 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1060
1061 static struct platform_driver bcm2835_pinctrl_driver = {
1062 .probe = bcm2835_pinctrl_probe,
1063 .remove = bcm2835_pinctrl_remove,
1064 .driver = {
1065 .name = MODULE_NAME,
1066 .owner = THIS_MODULE,
1067 .of_match_table = bcm2835_pinctrl_match,
1068 },
1069 };
1070 module_platform_driver(bcm2835_pinctrl_driver);
1071
1072 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1073 MODULE_DESCRIPTION("BCM2835 Pin control driver");
1074 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)