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drivers: power: report battery voltage in AOSP compatible format
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / pinctrl / pinctrl-abx500.c
1 /*
2 * Copyright (C) ST-Ericsson SA 2013
3 *
4 * Author: Patrice Chotard <patrice.chotard@st.com>
5 * License terms: GNU General Public License (GPL) version 2
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/err.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/gpio.h>
21 #include <linux/irq.h>
22 #include <linux/irqdomain.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/mfd/abx500.h>
26 #include <linux/mfd/abx500/ab8500.h>
27 #include <linux/mfd/abx500/ab8500-gpio.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/pinctrl/pinmux.h>
31 #include <linux/pinctrl/pinconf.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33
34 #include "pinctrl-abx500.h"
35
36 /*
37 * The AB9540 and AB8540 GPIO support are extended versions
38 * of the AB8500 GPIO support.
39 * The AB9540 supports an additional (7th) register so that
40 * more GPIO may be configured and used.
41 * The AB8540 supports 4 new gpios (GPIOx_VBAT) that have
42 * internal pull-up and pull-down capabilities.
43 */
44
45 /*
46 * GPIO registers offset
47 * Bank: 0x10
48 */
49 #define AB8500_GPIO_SEL1_REG 0x00
50 #define AB8500_GPIO_SEL2_REG 0x01
51 #define AB8500_GPIO_SEL3_REG 0x02
52 #define AB8500_GPIO_SEL4_REG 0x03
53 #define AB8500_GPIO_SEL5_REG 0x04
54 #define AB8500_GPIO_SEL6_REG 0x05
55 #define AB9540_GPIO_SEL7_REG 0x06
56
57 #define AB8500_GPIO_DIR1_REG 0x10
58 #define AB8500_GPIO_DIR2_REG 0x11
59 #define AB8500_GPIO_DIR3_REG 0x12
60 #define AB8500_GPIO_DIR4_REG 0x13
61 #define AB8500_GPIO_DIR5_REG 0x14
62 #define AB8500_GPIO_DIR6_REG 0x15
63 #define AB9540_GPIO_DIR7_REG 0x16
64
65 #define AB8500_GPIO_OUT1_REG 0x20
66 #define AB8500_GPIO_OUT2_REG 0x21
67 #define AB8500_GPIO_OUT3_REG 0x22
68 #define AB8500_GPIO_OUT4_REG 0x23
69 #define AB8500_GPIO_OUT5_REG 0x24
70 #define AB8500_GPIO_OUT6_REG 0x25
71 #define AB9540_GPIO_OUT7_REG 0x26
72
73 #define AB8500_GPIO_PUD1_REG 0x30
74 #define AB8500_GPIO_PUD2_REG 0x31
75 #define AB8500_GPIO_PUD3_REG 0x32
76 #define AB8500_GPIO_PUD4_REG 0x33
77 #define AB8500_GPIO_PUD5_REG 0x34
78 #define AB8500_GPIO_PUD6_REG 0x35
79 #define AB9540_GPIO_PUD7_REG 0x36
80
81 #define AB8500_GPIO_IN1_REG 0x40
82 #define AB8500_GPIO_IN2_REG 0x41
83 #define AB8500_GPIO_IN3_REG 0x42
84 #define AB8500_GPIO_IN4_REG 0x43
85 #define AB8500_GPIO_IN5_REG 0x44
86 #define AB8500_GPIO_IN6_REG 0x45
87 #define AB9540_GPIO_IN7_REG 0x46
88 #define AB8540_GPIO_VINSEL_REG 0x47
89 #define AB8540_GPIO_PULL_UPDOWN_REG 0x48
90 #define AB8500_GPIO_ALTFUN_REG 0x50
91 #define AB8540_GPIO_PULL_UPDOWN_MASK 0x03
92 #define AB8540_GPIO_VINSEL_MASK 0x03
93 #define AB8540_GPIOX_VBAT_START 51
94 #define AB8540_GPIOX_VBAT_END 54
95
96 struct abx500_pinctrl {
97 struct device *dev;
98 struct pinctrl_dev *pctldev;
99 struct abx500_pinctrl_soc_data *soc;
100 struct gpio_chip chip;
101 struct ab8500 *parent;
102 struct mutex lock;
103 struct abx500_gpio_irq_cluster *irq_cluster;
104 int irq_cluster_size;
105 };
106
107 /**
108 * to_abx500_pinctrl() - get the pointer to abx500_pinctrl
109 * @chip: Member of the structure abx500_pinctrl
110 */
111 static inline struct abx500_pinctrl *to_abx500_pinctrl(struct gpio_chip *chip)
112 {
113 return container_of(chip, struct abx500_pinctrl, chip);
114 }
115
116 static int abx500_gpio_get_bit(struct gpio_chip *chip, u8 reg,
117 unsigned offset, bool *bit)
118 {
119 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
120 u8 pos = offset % 8;
121 u8 val;
122 int ret;
123
124 reg += offset / 8;
125 ret = abx500_get_register_interruptible(pct->dev,
126 AB8500_MISC, reg, &val);
127
128 *bit = !!(val & BIT(pos));
129
130 if (ret < 0)
131 dev_err(pct->dev,
132 "%s read reg =%x, offset=%x failed\n",
133 __func__, reg, offset);
134
135 return ret;
136 }
137
138 static int abx500_gpio_set_bits(struct gpio_chip *chip, u8 reg,
139 unsigned offset, int val)
140 {
141 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
142 u8 pos = offset % 8;
143 int ret;
144
145 reg += offset / 8;
146 ret = abx500_mask_and_set_register_interruptible(pct->dev,
147 AB8500_MISC, reg, BIT(pos), val << pos);
148 if (ret < 0)
149 dev_err(pct->dev, "%s write failed\n", __func__);
150
151 return ret;
152 }
153
154 /**
155 * abx500_gpio_get() - Get the particular GPIO value
156 * @chip: Gpio device
157 * @offset: GPIO number to read
158 */
159 static int abx500_gpio_get(struct gpio_chip *chip, unsigned offset)
160 {
161 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
162 bool bit;
163 int ret;
164
165 ret = abx500_gpio_get_bit(chip, AB8500_GPIO_IN1_REG,
166 offset, &bit);
167 if (ret < 0) {
168 dev_err(pct->dev, "%s failed\n", __func__);
169 return ret;
170 }
171
172 return bit;
173 }
174
175 static void abx500_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
176 {
177 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
178 int ret;
179
180 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
181 if (ret < 0)
182 dev_err(pct->dev, "%s write failed\n", __func__);
183 }
184
185 static int abx500_config_pull_updown(struct abx500_pinctrl *pct,
186 int offset, enum abx500_gpio_pull_updown val)
187 {
188 u8 pos;
189 int ret;
190 struct pullud *pullud;
191
192 if (!pct->soc->pullud) {
193 dev_err(pct->dev, "%s AB chip doesn't support pull up/down feature",
194 __func__);
195 ret = -EPERM;
196 goto out;
197 }
198
199 pullud = pct->soc->pullud;
200
201 if ((offset < pullud->first_pin)
202 || (offset > pullud->last_pin)) {
203 ret = -EINVAL;
204 goto out;
205 }
206
207 pos = offset << 1;
208
209 ret = abx500_mask_and_set_register_interruptible(pct->dev,
210 AB8500_MISC, AB8540_GPIO_PULL_UPDOWN_REG,
211 AB8540_GPIO_PULL_UPDOWN_MASK << pos, val << pos);
212
213 out:
214 if (ret < 0)
215 dev_err(pct->dev, "%s failed (%d)\n", __func__, ret);
216
217 return ret;
218 }
219
220 static int abx500_gpio_direction_output(struct gpio_chip *chip,
221 unsigned offset,
222 int val)
223 {
224 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
225 struct pullud *pullud = pct->soc->pullud;
226 unsigned gpio;
227 int ret;
228
229 /* set direction as output */
230 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 1);
231 if (ret < 0)
232 return ret;
233
234 /* disable pull down */
235 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG, offset, 1);
236 if (ret < 0)
237 return ret;
238
239 /* if supported, disable both pull down and pull up */
240 gpio = offset + 1;
241 if (pullud && gpio >= pullud->first_pin && gpio <= pullud->last_pin) {
242 ret = abx500_config_pull_updown(pct,
243 gpio,
244 ABX500_GPIO_PULL_NONE);
245 if (ret < 0)
246 return ret;
247 }
248
249 /* set the output as 1 or 0 */
250 return abx500_gpio_set_bits(chip, AB8500_GPIO_OUT1_REG, offset, val);
251 }
252
253 static int abx500_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
254 {
255 /* set the register as input */
256 return abx500_gpio_set_bits(chip, AB8500_GPIO_DIR1_REG, offset, 0);
257 }
258
259 static int abx500_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
260 {
261 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
262 /* The AB8500 GPIO numbers are off by one */
263 int gpio = offset + 1;
264 int hwirq;
265 int i;
266
267 for (i = 0; i < pct->irq_cluster_size; i++) {
268 struct abx500_gpio_irq_cluster *cluster =
269 &pct->irq_cluster[i];
270
271 if (gpio >= cluster->start && gpio <= cluster->end) {
272 /*
273 * The ABx500 GPIO's associated IRQs are clustered together
274 * throughout the interrupt numbers at irregular intervals.
275 * To solve this quandry, we have placed the read-in values
276 * into the cluster information table.
277 */
278 hwirq = gpio - cluster->start + cluster->to_irq;
279 return irq_create_mapping(pct->parent->domain, hwirq);
280 }
281 }
282
283 return -EINVAL;
284 }
285
286 static int abx500_set_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
287 unsigned gpio, int alt_setting)
288 {
289 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
290 struct alternate_functions af = pct->soc->alternate_functions[gpio];
291 int ret;
292 int val;
293 unsigned offset;
294
295 const char *modes[] = {
296 [ABX500_DEFAULT] = "default",
297 [ABX500_ALT_A] = "altA",
298 [ABX500_ALT_B] = "altB",
299 [ABX500_ALT_C] = "altC",
300 };
301
302 /* sanity check */
303 if (((alt_setting == ABX500_ALT_A) && (af.gpiosel_bit == UNUSED)) ||
304 ((alt_setting == ABX500_ALT_B) && (af.alt_bit1 == UNUSED)) ||
305 ((alt_setting == ABX500_ALT_C) && (af.alt_bit2 == UNUSED))) {
306 dev_dbg(pct->dev, "pin %d doesn't support %s mode\n", gpio,
307 modes[alt_setting]);
308 return -EINVAL;
309 }
310
311 /* on ABx5xx, there is no GPIO0, so adjust the offset */
312 offset = gpio - 1;
313
314 switch (alt_setting) {
315 case ABX500_DEFAULT:
316 /*
317 * for ABx5xx family, default mode is always selected by
318 * writing 0 to GPIOSELx register, except for pins which
319 * support at least ALT_B mode, default mode is selected
320 * by writing 1 to GPIOSELx register
321 */
322 val = 0;
323 if (af.alt_bit1 != UNUSED)
324 val++;
325
326 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
327 offset, val);
328 break;
329
330 case ABX500_ALT_A:
331 /*
332 * for ABx5xx family, alt_a mode is always selected by
333 * writing 1 to GPIOSELx register, except for pins which
334 * support at least ALT_B mode, alt_a mode is selected
335 * by writing 0 to GPIOSELx register and 0 in ALTFUNC
336 * register
337 */
338 if (af.alt_bit1 != UNUSED) {
339 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
340 offset, 0);
341 ret = abx500_gpio_set_bits(chip,
342 AB8500_GPIO_ALTFUN_REG,
343 af.alt_bit1,
344 !!(af.alta_val && BIT(0)));
345 if (af.alt_bit2 != UNUSED)
346 ret = abx500_gpio_set_bits(chip,
347 AB8500_GPIO_ALTFUN_REG,
348 af.alt_bit2,
349 !!(af.alta_val && BIT(1)));
350 } else
351 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
352 offset, 1);
353 break;
354
355 case ABX500_ALT_B:
356 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
357 offset, 0);
358 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
359 af.alt_bit1, !!(af.altb_val && BIT(0)));
360 if (af.alt_bit2 != UNUSED)
361 ret = abx500_gpio_set_bits(chip,
362 AB8500_GPIO_ALTFUN_REG,
363 af.alt_bit2,
364 !!(af.altb_val && BIT(1)));
365 break;
366
367 case ABX500_ALT_C:
368 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_SEL1_REG,
369 offset, 0);
370 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
371 af.alt_bit2, !!(af.altc_val && BIT(0)));
372 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_ALTFUN_REG,
373 af.alt_bit2, !!(af.altc_val && BIT(1)));
374 break;
375
376 default:
377 dev_dbg(pct->dev, "unknow alt_setting %d\n", alt_setting);
378
379 return -EINVAL;
380 }
381
382 return ret;
383 }
384
385 static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
386 unsigned gpio)
387 {
388 u8 mode;
389 bool bit_mode;
390 bool alt_bit1;
391 bool alt_bit2;
392 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
393 struct alternate_functions af = pct->soc->alternate_functions[gpio];
394 /* on ABx5xx, there is no GPIO0, so adjust the offset */
395 unsigned offset = gpio - 1;
396
397 /*
398 * if gpiosel_bit is set to unused,
399 * it means no GPIO or special case
400 */
401 if (af.gpiosel_bit == UNUSED)
402 return ABX500_DEFAULT;
403
404 /* read GpioSelx register */
405 abx500_gpio_get_bit(chip, AB8500_GPIO_SEL1_REG + (offset / 8),
406 af.gpiosel_bit, &bit_mode);
407 mode = bit_mode;
408
409 /* sanity check */
410 if ((af.alt_bit1 < UNUSED) || (af.alt_bit1 > 7) ||
411 (af.alt_bit2 < UNUSED) || (af.alt_bit2 > 7)) {
412 dev_err(pct->dev,
413 "alt_bitX value not in correct range (-1 to 7)\n");
414 return -EINVAL;
415 }
416
417 /* if alt_bit2 is used, alt_bit1 must be used too */
418 if ((af.alt_bit2 != UNUSED) && (af.alt_bit1 == UNUSED)) {
419 dev_err(pct->dev,
420 "if alt_bit2 is used, alt_bit1 can't be unused\n");
421 return -EINVAL;
422 }
423
424 /* check if pin use AlternateFunction register */
425 if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
426 return mode;
427 /*
428 * if pin GPIOSEL bit is set and pin supports alternate function,
429 * it means DEFAULT mode
430 */
431 if (mode)
432 return ABX500_DEFAULT;
433
434 /*
435 * pin use the AlternatFunction register
436 * read alt_bit1 value
437 */
438 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG,
439 af.alt_bit1, &alt_bit1);
440
441 if (af.alt_bit2 != UNUSED)
442 /* read alt_bit2 value */
443 abx500_gpio_get_bit(chip, AB8500_GPIO_ALTFUN_REG, af.alt_bit2,
444 &alt_bit2);
445 else
446 alt_bit2 = 0;
447
448 mode = (alt_bit2 << 1) + alt_bit1;
449 if (mode == af.alta_val)
450 return ABX500_ALT_A;
451 else if (mode == af.altb_val)
452 return ABX500_ALT_B;
453 else
454 return ABX500_ALT_C;
455 }
456
457 #ifdef CONFIG_DEBUG_FS
458
459 #include <linux/seq_file.h>
460
461 static void abx500_gpio_dbg_show_one(struct seq_file *s,
462 struct pinctrl_dev *pctldev,
463 struct gpio_chip *chip,
464 unsigned offset, unsigned gpio)
465 {
466 const char *label = gpiochip_is_requested(chip, offset - 1);
467 u8 gpio_offset = offset - 1;
468 int mode = -1;
469 bool is_out;
470 bool pull;
471
472 const char *modes[] = {
473 [ABX500_DEFAULT] = "default",
474 [ABX500_ALT_A] = "altA",
475 [ABX500_ALT_B] = "altB",
476 [ABX500_ALT_C] = "altC",
477 };
478
479 abx500_gpio_get_bit(chip, AB8500_GPIO_DIR1_REG, gpio_offset, &is_out);
480 abx500_gpio_get_bit(chip, AB8500_GPIO_PUD1_REG, gpio_offset, &pull);
481
482 if (pctldev)
483 mode = abx500_get_mode(pctldev, chip, offset);
484
485 seq_printf(s, " gpio-%-3d (%-20.20s) %-3s %-9s %s",
486 gpio, label ?: "(none)",
487 is_out ? "out" : "in ",
488 is_out ?
489 (chip->get
490 ? (chip->get(chip, offset) ? "hi" : "lo")
491 : "? ")
492 : (pull ? "pull up" : "pull down"),
493 (mode < 0) ? "unknown" : modes[mode]);
494 }
495
496 static void abx500_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
497 {
498 unsigned i;
499 unsigned gpio = chip->base;
500 struct abx500_pinctrl *pct = to_abx500_pinctrl(chip);
501 struct pinctrl_dev *pctldev = pct->pctldev;
502
503 for (i = 0; i < chip->ngpio; i++, gpio++) {
504 /* On AB8500, there is no GPIO0, the first is the GPIO 1 */
505 abx500_gpio_dbg_show_one(s, pctldev, chip, i + 1, gpio);
506 seq_printf(s, "\n");
507 }
508 }
509
510 #else
511 static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
512 struct pinctrl_dev *pctldev,
513 struct gpio_chip *chip,
514 unsigned offset, unsigned gpio)
515 {
516 }
517 #define abx500_gpio_dbg_show NULL
518 #endif
519
520 static int abx500_gpio_request(struct gpio_chip *chip, unsigned offset)
521 {
522 int gpio = chip->base + offset;
523
524 return pinctrl_request_gpio(gpio);
525 }
526
527 static void abx500_gpio_free(struct gpio_chip *chip, unsigned offset)
528 {
529 int gpio = chip->base + offset;
530
531 pinctrl_free_gpio(gpio);
532 }
533
534 static struct gpio_chip abx500gpio_chip = {
535 .label = "abx500-gpio",
536 .owner = THIS_MODULE,
537 .request = abx500_gpio_request,
538 .free = abx500_gpio_free,
539 .direction_input = abx500_gpio_direction_input,
540 .get = abx500_gpio_get,
541 .direction_output = abx500_gpio_direction_output,
542 .set = abx500_gpio_set,
543 .to_irq = abx500_gpio_to_irq,
544 .dbg_show = abx500_gpio_dbg_show,
545 };
546
547 static int abx500_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
548 {
549 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
550
551 return pct->soc->nfunctions;
552 }
553
554 static const char *abx500_pmx_get_func_name(struct pinctrl_dev *pctldev,
555 unsigned function)
556 {
557 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
558
559 return pct->soc->functions[function].name;
560 }
561
562 static int abx500_pmx_get_func_groups(struct pinctrl_dev *pctldev,
563 unsigned function,
564 const char * const **groups,
565 unsigned * const num_groups)
566 {
567 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
568
569 *groups = pct->soc->functions[function].groups;
570 *num_groups = pct->soc->functions[function].ngroups;
571
572 return 0;
573 }
574
575 static int abx500_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
576 unsigned group)
577 {
578 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
579 struct gpio_chip *chip = &pct->chip;
580 const struct abx500_pingroup *g;
581 int i;
582 int ret = 0;
583
584 g = &pct->soc->groups[group];
585 if (g->altsetting < 0)
586 return -EINVAL;
587
588 dev_dbg(pct->dev, "enable group %s, %u pins\n", g->name, g->npins);
589
590 for (i = 0; i < g->npins; i++) {
591 dev_dbg(pct->dev, "setting pin %d to altsetting %d\n",
592 g->pins[i], g->altsetting);
593
594 ret = abx500_set_mode(pctldev, chip, g->pins[i], g->altsetting);
595 }
596
597 return ret;
598 }
599
600 static void abx500_pmx_disable(struct pinctrl_dev *pctldev,
601 unsigned function, unsigned group)
602 {
603 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
604 const struct abx500_pingroup *g;
605
606 g = &pct->soc->groups[group];
607 if (g->altsetting < 0)
608 return;
609
610 /* FIXME: poke out the mux, set the pin to some default state? */
611 dev_dbg(pct->dev, "disable group %s, %u pins\n", g->name, g->npins);
612 }
613
614 static int abx500_gpio_request_enable(struct pinctrl_dev *pctldev,
615 struct pinctrl_gpio_range *range,
616 unsigned offset)
617 {
618 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
619 const struct abx500_pinrange *p;
620 int ret;
621 int i;
622
623 /*
624 * Different ranges have different ways to enable GPIO function on a
625 * pin, so refer back to our local range type, where we handily define
626 * what altfunc enables GPIO for a certain pin.
627 */
628 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
629 p = &pct->soc->gpio_ranges[i];
630 if ((offset >= p->offset) &&
631 (offset < (p->offset + p->npins)))
632 break;
633 }
634
635 if (i == pct->soc->gpio_num_ranges) {
636 dev_err(pct->dev, "%s failed to locate range\n", __func__);
637 return -ENODEV;
638 }
639
640 dev_dbg(pct->dev, "enable GPIO by altfunc %d at gpio %d\n",
641 p->altfunc, offset);
642
643 ret = abx500_set_mode(pct->pctldev, &pct->chip,
644 offset, p->altfunc);
645 if (ret < 0) {
646 dev_err(pct->dev, "%s setting altfunc failed\n", __func__);
647 return ret;
648 }
649
650 return ret;
651 }
652
653 static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
654 struct pinctrl_gpio_range *range,
655 unsigned offset)
656 {
657 }
658
659 static const struct pinmux_ops abx500_pinmux_ops = {
660 .get_functions_count = abx500_pmx_get_funcs_cnt,
661 .get_function_name = abx500_pmx_get_func_name,
662 .get_function_groups = abx500_pmx_get_func_groups,
663 .enable = abx500_pmx_enable,
664 .disable = abx500_pmx_disable,
665 .gpio_request_enable = abx500_gpio_request_enable,
666 .gpio_disable_free = abx500_gpio_disable_free,
667 };
668
669 static int abx500_get_groups_cnt(struct pinctrl_dev *pctldev)
670 {
671 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
672
673 return pct->soc->ngroups;
674 }
675
676 static const char *abx500_get_group_name(struct pinctrl_dev *pctldev,
677 unsigned selector)
678 {
679 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
680
681 return pct->soc->groups[selector].name;
682 }
683
684 static int abx500_get_group_pins(struct pinctrl_dev *pctldev,
685 unsigned selector,
686 const unsigned **pins,
687 unsigned *num_pins)
688 {
689 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
690
691 *pins = pct->soc->groups[selector].pins;
692 *num_pins = pct->soc->groups[selector].npins;
693
694 return 0;
695 }
696
697 static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
698 struct seq_file *s, unsigned offset)
699 {
700 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
701 struct gpio_chip *chip = &pct->chip;
702
703 abx500_gpio_dbg_show_one(s, pctldev, chip, offset,
704 chip->base + offset - 1);
705 }
706
707 static const struct pinctrl_ops abx500_pinctrl_ops = {
708 .get_groups_count = abx500_get_groups_cnt,
709 .get_group_name = abx500_get_group_name,
710 .get_group_pins = abx500_get_group_pins,
711 .pin_dbg_show = abx500_pin_dbg_show,
712 };
713
714 static int abx500_pin_config_get(struct pinctrl_dev *pctldev,
715 unsigned pin,
716 unsigned long *config)
717 {
718 return -ENOSYS;
719 }
720
721 static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
722 unsigned pin,
723 unsigned long config)
724 {
725 struct abx500_pinctrl *pct = pinctrl_dev_get_drvdata(pctldev);
726 struct pullud *pullud = pct->soc->pullud;
727 struct gpio_chip *chip = &pct->chip;
728 unsigned offset;
729 int ret;
730 enum pin_config_param param = pinconf_to_config_param(config);
731 enum pin_config_param argument = pinconf_to_config_argument(config);
732
733 dev_dbg(chip->dev, "pin %d [%#lx]: %s %s\n",
734 pin, config, (param == PIN_CONFIG_OUTPUT) ? "output " : "input",
735 (param == PIN_CONFIG_OUTPUT) ? (argument ? "high" : "low") :
736 (argument ? "pull up" : "pull down"));
737
738 /* on ABx500, there is no GPIO0, so adjust the offset */
739 offset = pin - 1;
740
741 switch (param) {
742 case PIN_CONFIG_BIAS_PULL_DOWN:
743 /*
744 * if argument = 1 set the pull down
745 * else clear the pull down
746 */
747 ret = abx500_gpio_direction_input(chip, offset);
748 /*
749 * Some chips only support pull down, while some actually
750 * support both pull up and pull down. Such chips have
751 * a "pullud" range specified for the pins that support
752 * both features. If the pin is not within that range, we
753 * fall back to the old bit set that only support pull down.
754 */
755 if (pullud &&
756 pin >= pullud->first_pin &&
757 pin <= pullud->last_pin)
758 ret = abx500_config_pull_updown(pct,
759 pin,
760 argument ? ABX500_GPIO_PULL_DOWN : ABX500_GPIO_PULL_NONE);
761 else
762 /* Chip only supports pull down */
763 ret = abx500_gpio_set_bits(chip, AB8500_GPIO_PUD1_REG,
764 offset, argument ? 0 : 1);
765 break;
766
767 case PIN_CONFIG_OUTPUT:
768 ret = abx500_gpio_direction_output(chip, offset, argument);
769
770 break;
771
772 default:
773 dev_err(chip->dev, "illegal configuration requested\n");
774
775 return -EINVAL;
776 }
777
778 return ret;
779 }
780
781 static const struct pinconf_ops abx500_pinconf_ops = {
782 .pin_config_get = abx500_pin_config_get,
783 .pin_config_set = abx500_pin_config_set,
784 };
785
786 static struct pinctrl_desc abx500_pinctrl_desc = {
787 .name = "pinctrl-abx500",
788 .pctlops = &abx500_pinctrl_ops,
789 .pmxops = &abx500_pinmux_ops,
790 .confops = &abx500_pinconf_ops,
791 .owner = THIS_MODULE,
792 };
793
794 static int abx500_get_gpio_num(struct abx500_pinctrl_soc_data *soc)
795 {
796 unsigned int lowest = 0;
797 unsigned int highest = 0;
798 unsigned int npins = 0;
799 int i;
800
801 /*
802 * Compute number of GPIOs from the last SoC gpio range descriptors
803 * These ranges may include "holes" but the GPIO number space shall
804 * still be homogeneous, so we need to detect and account for any
805 * such holes so that these are included in the number of GPIO pins.
806 */
807 for (i = 0; i < soc->gpio_num_ranges; i++) {
808 unsigned gstart;
809 unsigned gend;
810 const struct abx500_pinrange *p;
811
812 p = &soc->gpio_ranges[i];
813 gstart = p->offset;
814 gend = p->offset + p->npins - 1;
815
816 if (i == 0) {
817 /* First iteration, set start values */
818 lowest = gstart;
819 highest = gend;
820 } else {
821 if (gstart < lowest)
822 lowest = gstart;
823 if (gend > highest)
824 highest = gend;
825 }
826 }
827 /* this gives the absolute number of pins */
828 npins = highest - lowest + 1;
829 return npins;
830 }
831
832 static const struct of_device_id abx500_gpio_match[] = {
833 { .compatible = "stericsson,ab8500-gpio", .data = (void *)PINCTRL_AB8500, },
834 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
835 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
836 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
837 { }
838 };
839
840 static int abx500_gpio_probe(struct platform_device *pdev)
841 {
842 struct ab8500_platform_data *abx500_pdata =
843 dev_get_platdata(pdev->dev.parent);
844 struct abx500_gpio_platform_data *pdata = NULL;
845 struct device_node *np = pdev->dev.of_node;
846 struct abx500_pinctrl *pct;
847 const struct platform_device_id *platid = platform_get_device_id(pdev);
848 unsigned int id = -1;
849 int ret, err;
850 int i;
851
852 if (abx500_pdata)
853 pdata = abx500_pdata->gpio;
854
855 if (!(pdata || np)) {
856 dev_err(&pdev->dev, "gpio dt and platform data missing\n");
857 return -ENODEV;
858 }
859
860 pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
861 GFP_KERNEL);
862 if (pct == NULL) {
863 dev_err(&pdev->dev,
864 "failed to allocate memory for pct\n");
865 return -ENOMEM;
866 }
867
868 pct->dev = &pdev->dev;
869 pct->parent = dev_get_drvdata(pdev->dev.parent);
870 pct->chip = abx500gpio_chip;
871 pct->chip.dev = &pdev->dev;
872 pct->chip.base = (np) ? -1 : pdata->gpio_base;
873
874 if (platid)
875 id = platid->driver_data;
876 else if (np) {
877 const struct of_device_id *match;
878
879 match = of_match_device(abx500_gpio_match, &pdev->dev);
880 if (match)
881 id = (unsigned long)match->data;
882 }
883
884 /* initialize the lock */
885 mutex_init(&pct->lock);
886
887 /* Poke in other ASIC variants here */
888 switch (id) {
889 case PINCTRL_AB8500:
890 abx500_pinctrl_ab8500_init(&pct->soc);
891 break;
892 case PINCTRL_AB8540:
893 abx500_pinctrl_ab8540_init(&pct->soc);
894 break;
895 case PINCTRL_AB9540:
896 abx500_pinctrl_ab9540_init(&pct->soc);
897 break;
898 case PINCTRL_AB8505:
899 abx500_pinctrl_ab8505_init(&pct->soc);
900 break;
901 default:
902 dev_err(&pdev->dev, "Unsupported pinctrl sub driver (%d)\n", id);
903 mutex_destroy(&pct->lock);
904 return -EINVAL;
905 }
906
907 if (!pct->soc) {
908 dev_err(&pdev->dev, "Invalid SOC data\n");
909 mutex_destroy(&pct->lock);
910 return -EINVAL;
911 }
912
913 pct->chip.ngpio = abx500_get_gpio_num(pct->soc);
914 pct->irq_cluster = pct->soc->gpio_irq_cluster;
915 pct->irq_cluster_size = pct->soc->ngpio_irq_cluster;
916
917 ret = gpiochip_add(&pct->chip);
918 if (ret) {
919 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
920 mutex_destroy(&pct->lock);
921 return ret;
922 }
923 dev_info(&pdev->dev, "added gpiochip\n");
924
925 abx500_pinctrl_desc.pins = pct->soc->pins;
926 abx500_pinctrl_desc.npins = pct->soc->npins;
927 pct->pctldev = pinctrl_register(&abx500_pinctrl_desc, &pdev->dev, pct);
928 if (!pct->pctldev) {
929 dev_err(&pdev->dev,
930 "could not register abx500 pinctrl driver\n");
931 ret = -EINVAL;
932 goto out_rem_chip;
933 }
934 dev_info(&pdev->dev, "registered pin controller\n");
935
936 /* We will handle a range of GPIO pins */
937 for (i = 0; i < pct->soc->gpio_num_ranges; i++) {
938 const struct abx500_pinrange *p = &pct->soc->gpio_ranges[i];
939
940 ret = gpiochip_add_pin_range(&pct->chip,
941 dev_name(&pdev->dev),
942 p->offset - 1, p->offset, p->npins);
943 if (ret < 0)
944 goto out_rem_chip;
945 }
946
947 platform_set_drvdata(pdev, pct);
948 dev_info(&pdev->dev, "initialized abx500 pinctrl driver\n");
949
950 return 0;
951
952 out_rem_chip:
953 err = gpiochip_remove(&pct->chip);
954 if (err)
955 dev_info(&pdev->dev, "failed to remove gpiochip\n");
956
957 mutex_destroy(&pct->lock);
958 return ret;
959 }
960
961 /**
962 * abx500_gpio_remove() - remove Ab8500-gpio driver
963 * @pdev: Platform device registered
964 */
965 static int abx500_gpio_remove(struct platform_device *pdev)
966 {
967 struct abx500_pinctrl *pct = platform_get_drvdata(pdev);
968 int ret;
969
970 ret = gpiochip_remove(&pct->chip);
971 if (ret < 0) {
972 dev_err(pct->dev, "unable to remove gpiochip: %d\n",
973 ret);
974 return ret;
975 }
976
977 mutex_destroy(&pct->lock);
978
979 return 0;
980 }
981
982 static const struct platform_device_id abx500_pinctrl_id[] = {
983 { "pinctrl-ab8500", PINCTRL_AB8500 },
984 { "pinctrl-ab8540", PINCTRL_AB8540 },
985 { "pinctrl-ab9540", PINCTRL_AB9540 },
986 { "pinctrl-ab8505", PINCTRL_AB8505 },
987 { },
988 };
989
990 static struct platform_driver abx500_gpio_driver = {
991 .driver = {
992 .name = "abx500-gpio",
993 .owner = THIS_MODULE,
994 .of_match_table = abx500_gpio_match,
995 },
996 .probe = abx500_gpio_probe,
997 .remove = abx500_gpio_remove,
998 .id_table = abx500_pinctrl_id,
999 };
1000
1001 static int __init abx500_gpio_init(void)
1002 {
1003 return platform_driver_register(&abx500_gpio_driver);
1004 }
1005 core_initcall(abx500_gpio_init);
1006
1007 MODULE_AUTHOR("Patrice Chotard <patrice.chotard@st.com>");
1008 MODULE_DESCRIPTION("Driver allows to use AxB5xx unused pins to be used as GPIO");
1009 MODULE_ALIAS("platform:abx500-gpio");
1010 MODULE_LICENSE("GPL v2");
kernel source for telekom puls (alcatel/mediatek)