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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / zd1211rw / zd_chip.c
1 /* ZD1211 USB-WLAN driver for Linux
2 *
3 * Copyright (C) 2005-2007 Ulrich Kunitz <kune@deine-taler.de>
4 * Copyright (C) 2006-2007 Daniel Drake <dsd@gentoo.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 /* This file implements all the hardware specific functions for the ZD1211
22 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
23 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
24 */
25
26 #include <linux/kernel.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29
30 #include "zd_def.h"
31 #include "zd_chip.h"
32 #include "zd_mac.h"
33 #include "zd_rf.h"
34
35 void zd_chip_init(struct zd_chip *chip,
36 struct ieee80211_hw *hw,
37 struct usb_interface *intf)
38 {
39 memset(chip, 0, sizeof(*chip));
40 mutex_init(&chip->mutex);
41 zd_usb_init(&chip->usb, hw, intf);
42 zd_rf_init(&chip->rf);
43 }
44
45 void zd_chip_clear(struct zd_chip *chip)
46 {
47 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
48 zd_usb_clear(&chip->usb);
49 zd_rf_clear(&chip->rf);
50 mutex_destroy(&chip->mutex);
51 ZD_MEMCLEAR(chip, sizeof(*chip));
52 }
53
54 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
55 {
56 u8 *addr = zd_mac_get_perm_addr(zd_chip_to_mac(chip));
57 return scnprintf(buffer, size, "%02x-%02x-%02x",
58 addr[0], addr[1], addr[2]);
59 }
60
61 /* Prints an identifier line, which will support debugging. */
62 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
63 {
64 int i = 0;
65
66 i = scnprintf(buffer, size, "zd1211%s chip ",
67 zd_chip_is_zd1211b(chip) ? "b" : "");
68 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += scnprint_mac_oui(chip, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " ");
72 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
73 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
74 chip->patch_cck_gain ? 'g' : '-',
75 chip->patch_cr157 ? '7' : '-',
76 chip->patch_6m_band_edge ? '6' : '-',
77 chip->new_phy_layout ? 'N' : '-',
78 chip->al2230s_bit ? 'S' : '-');
79 return i;
80 }
81
82 static void print_id(struct zd_chip *chip)
83 {
84 char buffer[80];
85
86 scnprint_id(chip, buffer, sizeof(buffer));
87 buffer[sizeof(buffer)-1] = 0;
88 dev_info(zd_chip_dev(chip), "%s\n", buffer);
89 }
90
91 static zd_addr_t inc_addr(zd_addr_t addr)
92 {
93 u16 a = (u16)addr;
94 /* Control registers use byte addressing, but everything else uses word
95 * addressing. */
96 if ((a & 0xf000) == CR_START)
97 a += 2;
98 else
99 a += 1;
100 return (zd_addr_t)a;
101 }
102
103 /* Read a variable number of 32-bit values. Parameter count is not allowed to
104 * exceed USB_MAX_IOREAD32_COUNT.
105 */
106 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
107 unsigned int count)
108 {
109 int r;
110 int i;
111 zd_addr_t *a16;
112 u16 *v16;
113 unsigned int count16;
114
115 if (count > USB_MAX_IOREAD32_COUNT)
116 return -EINVAL;
117
118 /* Allocate a single memory block for values and addresses. */
119 count16 = 2*count;
120 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
121 GFP_KERNEL);
122 if (!a16) {
123 dev_dbg_f(zd_chip_dev(chip),
124 "error ENOMEM in allocation of a16\n");
125 r = -ENOMEM;
126 goto out;
127 }
128 v16 = (u16 *)(a16 + count16);
129
130 for (i = 0; i < count; i++) {
131 int j = 2*i;
132 /* We read the high word always first. */
133 a16[j] = inc_addr(addr[i]);
134 a16[j+1] = addr[i];
135 }
136
137 r = zd_ioread16v_locked(chip, v16, a16, count16);
138 if (r) {
139 dev_dbg_f(zd_chip_dev(chip),
140 "error: zd_ioread16v_locked. Error number %d\n", r);
141 goto out;
142 }
143
144 for (i = 0; i < count; i++) {
145 int j = 2*i;
146 values[i] = (v16[j] << 16) | v16[j+1];
147 }
148
149 out:
150 kfree((void *)a16);
151 return r;
152 }
153
154 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
155 unsigned int count)
156 {
157 int i, j, r;
158 struct zd_ioreq16 *ioreqs16;
159 unsigned int count16;
160
161 ZD_ASSERT(mutex_is_locked(&chip->mutex));
162
163 if (count == 0)
164 return 0;
165 if (count > USB_MAX_IOWRITE32_COUNT)
166 return -EINVAL;
167
168 /* Allocate a single memory block for values and addresses. */
169 count16 = 2*count;
170 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
171 if (!ioreqs16) {
172 r = -ENOMEM;
173 dev_dbg_f(zd_chip_dev(chip),
174 "error %d in ioreqs16 allocation\n", r);
175 goto out;
176 }
177
178 for (i = 0; i < count; i++) {
179 j = 2*i;
180 /* We write the high word always first. */
181 ioreqs16[j].value = ioreqs[i].value >> 16;
182 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
183 ioreqs16[j+1].value = ioreqs[i].value;
184 ioreqs16[j+1].addr = ioreqs[i].addr;
185 }
186
187 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
188 #ifdef DEBUG
189 if (r) {
190 dev_dbg_f(zd_chip_dev(chip),
191 "error %d in zd_usb_write16v\n", r);
192 }
193 #endif /* DEBUG */
194 out:
195 kfree(ioreqs16);
196 return r;
197 }
198
199 int zd_iowrite16a_locked(struct zd_chip *chip,
200 const struct zd_ioreq16 *ioreqs, unsigned int count)
201 {
202 int r;
203 unsigned int i, j, t, max;
204
205 ZD_ASSERT(mutex_is_locked(&chip->mutex));
206 for (i = 0; i < count; i += j + t) {
207 t = 0;
208 max = count-i;
209 if (max > USB_MAX_IOWRITE16_COUNT)
210 max = USB_MAX_IOWRITE16_COUNT;
211 for (j = 0; j < max; j++) {
212 if (!ioreqs[i+j].addr) {
213 t = 1;
214 break;
215 }
216 }
217
218 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
219 if (r) {
220 dev_dbg_f(zd_chip_dev(chip),
221 "error zd_usb_iowrite16v. Error number %d\n",
222 r);
223 return r;
224 }
225 }
226
227 return 0;
228 }
229
230 /* Writes a variable number of 32 bit registers. The functions will split
231 * that in several USB requests. A split can be forced by inserting an IO
232 * request with an zero address field.
233 */
234 int zd_iowrite32a_locked(struct zd_chip *chip,
235 const struct zd_ioreq32 *ioreqs, unsigned int count)
236 {
237 int r;
238 unsigned int i, j, t, max;
239
240 for (i = 0; i < count; i += j + t) {
241 t = 0;
242 max = count-i;
243 if (max > USB_MAX_IOWRITE32_COUNT)
244 max = USB_MAX_IOWRITE32_COUNT;
245 for (j = 0; j < max; j++) {
246 if (!ioreqs[i+j].addr) {
247 t = 1;
248 break;
249 }
250 }
251
252 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
253 if (r) {
254 dev_dbg_f(zd_chip_dev(chip),
255 "error _zd_iowrite32v_locked."
256 " Error number %d\n", r);
257 return r;
258 }
259 }
260
261 return 0;
262 }
263
264 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
265 {
266 int r;
267
268 mutex_lock(&chip->mutex);
269 r = zd_ioread16_locked(chip, value, addr);
270 mutex_unlock(&chip->mutex);
271 return r;
272 }
273
274 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
275 {
276 int r;
277
278 mutex_lock(&chip->mutex);
279 r = zd_ioread32_locked(chip, value, addr);
280 mutex_unlock(&chip->mutex);
281 return r;
282 }
283
284 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
285 {
286 int r;
287
288 mutex_lock(&chip->mutex);
289 r = zd_iowrite16_locked(chip, value, addr);
290 mutex_unlock(&chip->mutex);
291 return r;
292 }
293
294 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
295 {
296 int r;
297
298 mutex_lock(&chip->mutex);
299 r = zd_iowrite32_locked(chip, value, addr);
300 mutex_unlock(&chip->mutex);
301 return r;
302 }
303
304 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
305 u32 *values, unsigned int count)
306 {
307 int r;
308
309 mutex_lock(&chip->mutex);
310 r = zd_ioread32v_locked(chip, values, addresses, count);
311 mutex_unlock(&chip->mutex);
312 return r;
313 }
314
315 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
316 unsigned int count)
317 {
318 int r;
319
320 mutex_lock(&chip->mutex);
321 r = zd_iowrite32a_locked(chip, ioreqs, count);
322 mutex_unlock(&chip->mutex);
323 return r;
324 }
325
326 static int read_pod(struct zd_chip *chip, u8 *rf_type)
327 {
328 int r;
329 u32 value;
330
331 ZD_ASSERT(mutex_is_locked(&chip->mutex));
332 r = zd_ioread32_locked(chip, &value, E2P_POD);
333 if (r)
334 goto error;
335 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
336
337 /* FIXME: AL2230 handling (Bit 7 in POD) */
338 *rf_type = value & 0x0f;
339 chip->pa_type = (value >> 16) & 0x0f;
340 chip->patch_cck_gain = (value >> 8) & 0x1;
341 chip->patch_cr157 = (value >> 13) & 0x1;
342 chip->patch_6m_band_edge = (value >> 21) & 0x1;
343 chip->new_phy_layout = (value >> 31) & 0x1;
344 chip->al2230s_bit = (value >> 7) & 0x1;
345 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
346 chip->supports_tx_led = 1;
347 if (value & (1 << 24)) { /* LED scenario */
348 if (value & (1 << 29))
349 chip->supports_tx_led = 0;
350 }
351
352 dev_dbg_f(zd_chip_dev(chip),
353 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
354 "patch 6M %d new PHY %d link LED%d tx led %d\n",
355 zd_rf_name(*rf_type), *rf_type,
356 chip->pa_type, chip->patch_cck_gain,
357 chip->patch_cr157, chip->patch_6m_band_edge,
358 chip->new_phy_layout,
359 chip->link_led == LED1 ? 1 : 2,
360 chip->supports_tx_led);
361 return 0;
362 error:
363 *rf_type = 0;
364 chip->pa_type = 0;
365 chip->patch_cck_gain = 0;
366 chip->patch_cr157 = 0;
367 chip->patch_6m_band_edge = 0;
368 chip->new_phy_layout = 0;
369 return r;
370 }
371
372 /* MAC address: if custom mac addresses are to be used CR_MAC_ADDR_P1 and
373 * CR_MAC_ADDR_P2 must be overwritten
374 */
375 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
376 {
377 int r;
378 struct zd_ioreq32 reqs[2] = {
379 [0] = { .addr = CR_MAC_ADDR_P1 },
380 [1] = { .addr = CR_MAC_ADDR_P2 },
381 };
382
383 if (mac_addr) {
384 reqs[0].value = (mac_addr[3] << 24)
385 | (mac_addr[2] << 16)
386 | (mac_addr[1] << 8)
387 | mac_addr[0];
388 reqs[1].value = (mac_addr[5] << 8)
389 | mac_addr[4];
390 dev_dbg_f(zd_chip_dev(chip), "mac addr %pM\n", mac_addr);
391 } else {
392 dev_dbg_f(zd_chip_dev(chip), "set NULL mac\n");
393 }
394
395 mutex_lock(&chip->mutex);
396 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
397 mutex_unlock(&chip->mutex);
398 return r;
399 }
400
401 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
402 {
403 int r;
404 u32 value;
405
406 mutex_lock(&chip->mutex);
407 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
408 mutex_unlock(&chip->mutex);
409 if (r)
410 return r;
411
412 *regdomain = value >> 16;
413 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
414
415 return 0;
416 }
417
418 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
419 zd_addr_t e2p_addr, u32 guard)
420 {
421 int r;
422 int i;
423 u32 v;
424
425 ZD_ASSERT(mutex_is_locked(&chip->mutex));
426 for (i = 0;;) {
427 r = zd_ioread32_locked(chip, &v,
428 (zd_addr_t)((u16)e2p_addr+i/2));
429 if (r)
430 return r;
431 v -= guard;
432 if (i+4 < count) {
433 values[i++] = v;
434 values[i++] = v >> 8;
435 values[i++] = v >> 16;
436 values[i++] = v >> 24;
437 continue;
438 }
439 for (;i < count; i++)
440 values[i] = v >> (8*(i%3));
441 return 0;
442 }
443 }
444
445 static int read_pwr_cal_values(struct zd_chip *chip)
446 {
447 return read_values(chip, chip->pwr_cal_values,
448 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
449 0);
450 }
451
452 static int read_pwr_int_values(struct zd_chip *chip)
453 {
454 return read_values(chip, chip->pwr_int_values,
455 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
456 E2P_PWR_INT_GUARD);
457 }
458
459 static int read_ofdm_cal_values(struct zd_chip *chip)
460 {
461 int r;
462 int i;
463 static const zd_addr_t addresses[] = {
464 E2P_36M_CAL_VALUE1,
465 E2P_48M_CAL_VALUE1,
466 E2P_54M_CAL_VALUE1,
467 };
468
469 for (i = 0; i < 3; i++) {
470 r = read_values(chip, chip->ofdm_cal_values[i],
471 E2P_CHANNEL_COUNT, addresses[i], 0);
472 if (r)
473 return r;
474 }
475 return 0;
476 }
477
478 static int read_cal_int_tables(struct zd_chip *chip)
479 {
480 int r;
481
482 r = read_pwr_cal_values(chip);
483 if (r)
484 return r;
485 r = read_pwr_int_values(chip);
486 if (r)
487 return r;
488 r = read_ofdm_cal_values(chip);
489 if (r)
490 return r;
491 return 0;
492 }
493
494 /* phy means physical registers */
495 int zd_chip_lock_phy_regs(struct zd_chip *chip)
496 {
497 int r;
498 u32 tmp;
499
500 ZD_ASSERT(mutex_is_locked(&chip->mutex));
501 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
502 if (r) {
503 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
504 return r;
505 }
506
507 tmp &= ~UNLOCK_PHY_REGS;
508
509 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
510 if (r)
511 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
512 return r;
513 }
514
515 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
516 {
517 int r;
518 u32 tmp;
519
520 ZD_ASSERT(mutex_is_locked(&chip->mutex));
521 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
522 if (r) {
523 dev_err(zd_chip_dev(chip),
524 "error ioread32(CR_REG1): %d\n", r);
525 return r;
526 }
527
528 tmp |= UNLOCK_PHY_REGS;
529
530 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
531 if (r)
532 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
533 return r;
534 }
535
536 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
537 static int patch_cr157(struct zd_chip *chip)
538 {
539 int r;
540 u16 value;
541
542 if (!chip->patch_cr157)
543 return 0;
544
545 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
546 if (r)
547 return r;
548
549 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
550 return zd_iowrite32_locked(chip, value >> 8, CR157);
551 }
552
553 /*
554 * 6M band edge can be optionally overwritten for certain RF's
555 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
556 * bit (for AL2230, AL2230S)
557 */
558 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
559 {
560 ZD_ASSERT(mutex_is_locked(&chip->mutex));
561 if (!chip->patch_6m_band_edge)
562 return 0;
563
564 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
565 }
566
567 /* Generic implementation of 6M band edge patching, used by most RFs via
568 * zd_rf_generic_patch_6m() */
569 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
570 {
571 struct zd_ioreq16 ioreqs[] = {
572 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
573 { CR47, 0x1e },
574 };
575
576 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
577 if (channel == 1 || channel == 11)
578 ioreqs[0].value = 0x12;
579
580 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
581 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
582 }
583
584 static int zd1211_hw_reset_phy(struct zd_chip *chip)
585 {
586 static const struct zd_ioreq16 ioreqs[] = {
587 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
588 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
589 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
590 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
591 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
592 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
593 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
594 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
595 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
596 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
597 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
598 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
599 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
600 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
601 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
602 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
603 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
604 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
605 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
606 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
607 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
608 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
609 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
610 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
611 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
612 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
613 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
614 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
615 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
616 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
617 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
618 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
619 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
620 { },
621 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
622 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
623 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
624 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
625 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
626 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
627 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
628 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
629 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
630 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
631 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
632 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
633 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
634 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
635 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
636 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
637 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
638 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
639 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
640 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
641 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
642 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
643 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
644 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
645 { CR170, 0xba }, { CR171, 0xba },
646 /* Note: CR204 must lead the CR203 */
647 { CR204, 0x7d },
648 { },
649 { CR203, 0x30 },
650 };
651
652 int r, t;
653
654 dev_dbg_f(zd_chip_dev(chip), "\n");
655
656 r = zd_chip_lock_phy_regs(chip);
657 if (r)
658 goto out;
659
660 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
661 if (r)
662 goto unlock;
663
664 r = patch_cr157(chip);
665 unlock:
666 t = zd_chip_unlock_phy_regs(chip);
667 if (t && !r)
668 r = t;
669 out:
670 return r;
671 }
672
673 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
674 {
675 static const struct zd_ioreq16 ioreqs[] = {
676 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
677 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
678 { CR10, 0x81 },
679 /* power control { { CR11, 1 << 6 }, */
680 { CR11, 0x00 },
681 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
682 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
683 { CR18, 0x0a }, { CR19, 0x48 },
684 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
685 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
686 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
687 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
688 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
689 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
690 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
691 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
692 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
693 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
694 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
695 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
696 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
697 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
698 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
699 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
700 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
701 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
702 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
703 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
704 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
705 { CR94, 0x01 },
706 { CR95, 0x20 }, /* ZD1211B */
707 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
708 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
709 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
710 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
711 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
712 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
713 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
714 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
715 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
716 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
717 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
718 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
719 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
720 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
721 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
722 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
723 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
724 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
725 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
726 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
727 { CR170, 0xba }, { CR171, 0xba },
728 /* Note: CR204 must lead the CR203 */
729 { CR204, 0x7d },
730 {},
731 { CR203, 0x30 },
732 };
733
734 int r, t;
735
736 dev_dbg_f(zd_chip_dev(chip), "\n");
737
738 r = zd_chip_lock_phy_regs(chip);
739 if (r)
740 goto out;
741
742 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
743 t = zd_chip_unlock_phy_regs(chip);
744 if (t && !r)
745 r = t;
746 out:
747 return r;
748 }
749
750 static int hw_reset_phy(struct zd_chip *chip)
751 {
752 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
753 zd1211_hw_reset_phy(chip);
754 }
755
756 static int zd1211_hw_init_hmac(struct zd_chip *chip)
757 {
758 static const struct zd_ioreq32 ioreqs[] = {
759 { CR_ZD1211_RETRY_MAX, ZD1211_RETRY_COUNT },
760 { CR_RX_THRESHOLD, 0x000c0640 },
761 };
762
763 dev_dbg_f(zd_chip_dev(chip), "\n");
764 ZD_ASSERT(mutex_is_locked(&chip->mutex));
765 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
766 }
767
768 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
769 {
770 static const struct zd_ioreq32 ioreqs[] = {
771 { CR_ZD1211B_RETRY_MAX, ZD1211B_RETRY_COUNT },
772 { CR_ZD1211B_CWIN_MAX_MIN_AC0, 0x007f003f },
773 { CR_ZD1211B_CWIN_MAX_MIN_AC1, 0x007f003f },
774 { CR_ZD1211B_CWIN_MAX_MIN_AC2, 0x003f001f },
775 { CR_ZD1211B_CWIN_MAX_MIN_AC3, 0x001f000f },
776 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
777 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
778 { CR_ZD1211B_TXOP, 0x01800824 },
779 { CR_RX_THRESHOLD, 0x000c0eff, },
780 };
781
782 dev_dbg_f(zd_chip_dev(chip), "\n");
783 ZD_ASSERT(mutex_is_locked(&chip->mutex));
784 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
785 }
786
787 static int hw_init_hmac(struct zd_chip *chip)
788 {
789 int r;
790 static const struct zd_ioreq32 ioreqs[] = {
791 { CR_ACK_TIMEOUT_EXT, 0x20 },
792 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
793 { CR_SNIFFER_ON, 0 },
794 { CR_RX_FILTER, STA_RX_FILTER },
795 { CR_GROUP_HASH_P1, 0x00 },
796 { CR_GROUP_HASH_P2, 0x80000000 },
797 { CR_REG1, 0xa4 },
798 { CR_ADDA_PWR_DWN, 0x7f },
799 { CR_BCN_PLCP_CFG, 0x00f00401 },
800 { CR_PHY_DELAY, 0x00 },
801 { CR_ACK_TIMEOUT_EXT, 0x80 },
802 { CR_ADDA_PWR_DWN, 0x00 },
803 { CR_ACK_TIME_80211, 0x100 },
804 { CR_RX_PE_DELAY, 0x70 },
805 { CR_PS_CTRL, 0x10000000 },
806 { CR_RTS_CTS_RATE, 0x02030203 },
807 { CR_AFTER_PNP, 0x1 },
808 { CR_WEP_PROTECT, 0x114 },
809 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
810 { CR_CAM_MODE, MODE_AP_WDS},
811 };
812
813 ZD_ASSERT(mutex_is_locked(&chip->mutex));
814 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
815 if (r)
816 return r;
817
818 return zd_chip_is_zd1211b(chip) ?
819 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
820 }
821
822 struct aw_pt_bi {
823 u32 atim_wnd_period;
824 u32 pre_tbtt;
825 u32 beacon_interval;
826 };
827
828 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
829 {
830 int r;
831 static const zd_addr_t aw_pt_bi_addr[] =
832 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
833 u32 values[3];
834
835 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
836 ARRAY_SIZE(aw_pt_bi_addr));
837 if (r) {
838 memset(s, 0, sizeof(*s));
839 return r;
840 }
841
842 s->atim_wnd_period = values[0];
843 s->pre_tbtt = values[1];
844 s->beacon_interval = values[2];
845 return 0;
846 }
847
848 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
849 {
850 struct zd_ioreq32 reqs[3];
851
852 if (s->beacon_interval <= 5)
853 s->beacon_interval = 5;
854 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
855 s->pre_tbtt = s->beacon_interval - 1;
856 if (s->atim_wnd_period >= s->pre_tbtt)
857 s->atim_wnd_period = s->pre_tbtt - 1;
858
859 reqs[0].addr = CR_ATIM_WND_PERIOD;
860 reqs[0].value = s->atim_wnd_period;
861 reqs[1].addr = CR_PRE_TBTT;
862 reqs[1].value = s->pre_tbtt;
863 reqs[2].addr = CR_BCN_INTERVAL;
864 reqs[2].value = s->beacon_interval;
865
866 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
867 }
868
869
870 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
871 {
872 int r;
873 struct aw_pt_bi s;
874
875 ZD_ASSERT(mutex_is_locked(&chip->mutex));
876 r = get_aw_pt_bi(chip, &s);
877 if (r)
878 return r;
879 s.beacon_interval = interval;
880 return set_aw_pt_bi(chip, &s);
881 }
882
883 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
884 {
885 int r;
886
887 mutex_lock(&chip->mutex);
888 r = set_beacon_interval(chip, interval);
889 mutex_unlock(&chip->mutex);
890 return r;
891 }
892
893 static int hw_init(struct zd_chip *chip)
894 {
895 int r;
896
897 dev_dbg_f(zd_chip_dev(chip), "\n");
898 ZD_ASSERT(mutex_is_locked(&chip->mutex));
899 r = hw_reset_phy(chip);
900 if (r)
901 return r;
902
903 r = hw_init_hmac(chip);
904 if (r)
905 return r;
906
907 return set_beacon_interval(chip, 100);
908 }
909
910 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
911 {
912 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
913 }
914
915 #ifdef DEBUG
916 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
917 const char *addr_string)
918 {
919 int r;
920 u32 value;
921
922 r = zd_ioread32_locked(chip, &value, addr);
923 if (r) {
924 dev_dbg_f(zd_chip_dev(chip),
925 "error reading %s. Error number %d\n", addr_string, r);
926 return r;
927 }
928
929 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
930 addr_string, (unsigned int)value);
931 return 0;
932 }
933
934 static int test_init(struct zd_chip *chip)
935 {
936 int r;
937
938 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
939 if (r)
940 return r;
941 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
942 if (r)
943 return r;
944 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
945 }
946
947 static void dump_fw_registers(struct zd_chip *chip)
948 {
949 const zd_addr_t addr[4] = {
950 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
951 fw_reg_addr(chip, FW_REG_USB_SPEED),
952 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
953 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
954 };
955
956 int r;
957 u16 values[4];
958
959 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
960 ARRAY_SIZE(addr));
961 if (r) {
962 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
963 r);
964 return;
965 }
966
967 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
968 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
969 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
970 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
971 }
972 #endif /* DEBUG */
973
974 static int print_fw_version(struct zd_chip *chip)
975 {
976 int r;
977 u16 version;
978
979 r = zd_ioread16_locked(chip, &version,
980 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
981 if (r)
982 return r;
983
984 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
985 return 0;
986 }
987
988 static int set_mandatory_rates(struct zd_chip *chip, int gmode)
989 {
990 u32 rates;
991 ZD_ASSERT(mutex_is_locked(&chip->mutex));
992 /* This sets the mandatory rates, which only depend from the standard
993 * that the device is supporting. Until further notice we should try
994 * to support 802.11g also for full speed USB.
995 */
996 if (!gmode)
997 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
998 else
999 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1000 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1001
1002 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1003 }
1004
1005 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1006 int preamble)
1007 {
1008 u32 value = 0;
1009
1010 dev_dbg_f(zd_chip_dev(chip), "preamble=%x\n", preamble);
1011 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1012 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1013
1014 /* We always send 11M RTS/self-CTS messages, like the vendor driver. */
1015 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_RTS_RATE;
1016 value |= ZD_RX_CCK << RTSCTS_SH_RTS_MOD_TYPE;
1017 value |= ZD_PURE_RATE(ZD_CCK_RATE_11M) << RTSCTS_SH_CTS_RATE;
1018 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1019
1020 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1021 }
1022
1023 int zd_chip_enable_hwint(struct zd_chip *chip)
1024 {
1025 int r;
1026
1027 mutex_lock(&chip->mutex);
1028 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1029 mutex_unlock(&chip->mutex);
1030 return r;
1031 }
1032
1033 static int disable_hwint(struct zd_chip *chip)
1034 {
1035 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1036 }
1037
1038 int zd_chip_disable_hwint(struct zd_chip *chip)
1039 {
1040 int r;
1041
1042 mutex_lock(&chip->mutex);
1043 r = disable_hwint(chip);
1044 mutex_unlock(&chip->mutex);
1045 return r;
1046 }
1047
1048 static int read_fw_regs_offset(struct zd_chip *chip)
1049 {
1050 int r;
1051
1052 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1053 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1054 FWRAW_REGS_ADDR);
1055 if (r)
1056 return r;
1057 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1058 (u16)chip->fw_regs_base);
1059
1060 return 0;
1061 }
1062
1063 /* Read mac address using pre-firmware interface */
1064 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1065 {
1066 dev_dbg_f(zd_chip_dev(chip), "\n");
1067 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1068 ETH_ALEN);
1069 }
1070
1071 int zd_chip_init_hw(struct zd_chip *chip)
1072 {
1073 int r;
1074 u8 rf_type;
1075
1076 dev_dbg_f(zd_chip_dev(chip), "\n");
1077
1078 mutex_lock(&chip->mutex);
1079
1080 #ifdef DEBUG
1081 r = test_init(chip);
1082 if (r)
1083 goto out;
1084 #endif
1085 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1086 if (r)
1087 goto out;
1088
1089 r = read_fw_regs_offset(chip);
1090 if (r)
1091 goto out;
1092
1093 /* GPI is always disabled, also in the other driver.
1094 */
1095 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1096 if (r)
1097 goto out;
1098 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1099 if (r)
1100 goto out;
1101 /* Currently we support IEEE 802.11g for full and high speed USB.
1102 * It might be discussed, whether we should suppport pure b mode for
1103 * full speed USB.
1104 */
1105 r = set_mandatory_rates(chip, 1);
1106 if (r)
1107 goto out;
1108 /* Disabling interrupts is certainly a smart thing here.
1109 */
1110 r = disable_hwint(chip);
1111 if (r)
1112 goto out;
1113 r = read_pod(chip, &rf_type);
1114 if (r)
1115 goto out;
1116 r = hw_init(chip);
1117 if (r)
1118 goto out;
1119 r = zd_rf_init_hw(&chip->rf, rf_type);
1120 if (r)
1121 goto out;
1122
1123 r = print_fw_version(chip);
1124 if (r)
1125 goto out;
1126
1127 #ifdef DEBUG
1128 dump_fw_registers(chip);
1129 r = test_init(chip);
1130 if (r)
1131 goto out;
1132 #endif /* DEBUG */
1133
1134 r = read_cal_int_tables(chip);
1135 if (r)
1136 goto out;
1137
1138 print_id(chip);
1139 out:
1140 mutex_unlock(&chip->mutex);
1141 return r;
1142 }
1143
1144 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1145 {
1146 u8 value = chip->pwr_int_values[channel - 1];
1147 return zd_iowrite16_locked(chip, value, CR31);
1148 }
1149
1150 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1151 {
1152 u8 value = chip->pwr_cal_values[channel-1];
1153 return zd_iowrite16_locked(chip, value, CR68);
1154 }
1155
1156 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1157 {
1158 struct zd_ioreq16 ioreqs[3];
1159
1160 ioreqs[0].addr = CR67;
1161 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1162 ioreqs[1].addr = CR66;
1163 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1164 ioreqs[2].addr = CR65;
1165 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1166
1167 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1168 }
1169
1170 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1171 u8 channel)
1172 {
1173 int r;
1174
1175 if (!zd_rf_should_update_pwr_int(&chip->rf))
1176 return 0;
1177
1178 r = update_pwr_int(chip, channel);
1179 if (r)
1180 return r;
1181 if (zd_chip_is_zd1211b(chip)) {
1182 static const struct zd_ioreq16 ioreqs[] = {
1183 { CR69, 0x28 },
1184 {},
1185 { CR69, 0x2a },
1186 };
1187
1188 r = update_ofdm_cal(chip, channel);
1189 if (r)
1190 return r;
1191 r = update_pwr_cal(chip, channel);
1192 if (r)
1193 return r;
1194 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1195 if (r)
1196 return r;
1197 }
1198
1199 return 0;
1200 }
1201
1202 /* The CCK baseband gain can be optionally patched by the EEPROM */
1203 static int patch_cck_gain(struct zd_chip *chip)
1204 {
1205 int r;
1206 u32 value;
1207
1208 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1209 return 0;
1210
1211 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1212 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1213 if (r)
1214 return r;
1215 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1216 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1217 }
1218
1219 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1220 {
1221 int r, t;
1222
1223 mutex_lock(&chip->mutex);
1224 r = zd_chip_lock_phy_regs(chip);
1225 if (r)
1226 goto out;
1227 r = zd_rf_set_channel(&chip->rf, channel);
1228 if (r)
1229 goto unlock;
1230 r = update_channel_integration_and_calibration(chip, channel);
1231 if (r)
1232 goto unlock;
1233 r = patch_cck_gain(chip);
1234 if (r)
1235 goto unlock;
1236 r = patch_6m_band_edge(chip, channel);
1237 if (r)
1238 goto unlock;
1239 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1240 unlock:
1241 t = zd_chip_unlock_phy_regs(chip);
1242 if (t && !r)
1243 r = t;
1244 out:
1245 mutex_unlock(&chip->mutex);
1246 return r;
1247 }
1248
1249 u8 zd_chip_get_channel(struct zd_chip *chip)
1250 {
1251 u8 channel;
1252
1253 mutex_lock(&chip->mutex);
1254 channel = chip->rf.channel;
1255 mutex_unlock(&chip->mutex);
1256 return channel;
1257 }
1258
1259 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1260 {
1261 const zd_addr_t a[] = {
1262 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1263 CR_LED,
1264 };
1265
1266 int r;
1267 u16 v[ARRAY_SIZE(a)];
1268 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1269 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1270 [1] = { CR_LED },
1271 };
1272 u16 other_led;
1273
1274 mutex_lock(&chip->mutex);
1275 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1276 if (r)
1277 goto out;
1278
1279 other_led = chip->link_led == LED1 ? LED2 : LED1;
1280
1281 switch (status) {
1282 case ZD_LED_OFF:
1283 ioreqs[0].value = FW_LINK_OFF;
1284 ioreqs[1].value = v[1] & ~(LED1|LED2);
1285 break;
1286 case ZD_LED_SCANNING:
1287 ioreqs[0].value = FW_LINK_OFF;
1288 ioreqs[1].value = v[1] & ~other_led;
1289 if (get_seconds() % 3 == 0) {
1290 ioreqs[1].value &= ~chip->link_led;
1291 } else {
1292 ioreqs[1].value |= chip->link_led;
1293 }
1294 break;
1295 case ZD_LED_ASSOCIATED:
1296 ioreqs[0].value = FW_LINK_TX;
1297 ioreqs[1].value = v[1] & ~other_led;
1298 ioreqs[1].value |= chip->link_led;
1299 break;
1300 default:
1301 r = -EINVAL;
1302 goto out;
1303 }
1304
1305 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1306 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1307 if (r)
1308 goto out;
1309 }
1310 r = 0;
1311 out:
1312 mutex_unlock(&chip->mutex);
1313 return r;
1314 }
1315
1316 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1317 {
1318 int r;
1319
1320 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1321 return -EINVAL;
1322
1323 mutex_lock(&chip->mutex);
1324 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1325 mutex_unlock(&chip->mutex);
1326 return r;
1327 }
1328
1329 static inline u8 zd_rate_from_ofdm_plcp_header(const void *rx_frame)
1330 {
1331 return ZD_OFDM | zd_ofdm_plcp_header_rate(rx_frame);
1332 }
1333
1334 /**
1335 * zd_rx_rate - report zd-rate
1336 * @rx_frame - received frame
1337 * @rx_status - rx_status as given by the device
1338 *
1339 * This function converts the rate as encoded in the received packet to the
1340 * zd-rate, we are using on other places in the driver.
1341 */
1342 u8 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1343 {
1344 u8 zd_rate;
1345 if (status->frame_status & ZD_RX_OFDM) {
1346 zd_rate = zd_rate_from_ofdm_plcp_header(rx_frame);
1347 } else {
1348 switch (zd_cck_plcp_header_signal(rx_frame)) {
1349 case ZD_CCK_PLCP_SIGNAL_1M:
1350 zd_rate = ZD_CCK_RATE_1M;
1351 break;
1352 case ZD_CCK_PLCP_SIGNAL_2M:
1353 zd_rate = ZD_CCK_RATE_2M;
1354 break;
1355 case ZD_CCK_PLCP_SIGNAL_5M5:
1356 zd_rate = ZD_CCK_RATE_5_5M;
1357 break;
1358 case ZD_CCK_PLCP_SIGNAL_11M:
1359 zd_rate = ZD_CCK_RATE_11M;
1360 break;
1361 default:
1362 zd_rate = 0;
1363 }
1364 }
1365
1366 return zd_rate;
1367 }
1368
1369 int zd_chip_switch_radio_on(struct zd_chip *chip)
1370 {
1371 int r;
1372
1373 mutex_lock(&chip->mutex);
1374 r = zd_switch_radio_on(&chip->rf);
1375 mutex_unlock(&chip->mutex);
1376 return r;
1377 }
1378
1379 int zd_chip_switch_radio_off(struct zd_chip *chip)
1380 {
1381 int r;
1382
1383 mutex_lock(&chip->mutex);
1384 r = zd_switch_radio_off(&chip->rf);
1385 mutex_unlock(&chip->mutex);
1386 return r;
1387 }
1388
1389 int zd_chip_enable_int(struct zd_chip *chip)
1390 {
1391 int r;
1392
1393 mutex_lock(&chip->mutex);
1394 r = zd_usb_enable_int(&chip->usb);
1395 mutex_unlock(&chip->mutex);
1396 return r;
1397 }
1398
1399 void zd_chip_disable_int(struct zd_chip *chip)
1400 {
1401 mutex_lock(&chip->mutex);
1402 zd_usb_disable_int(&chip->usb);
1403 mutex_unlock(&chip->mutex);
1404 }
1405
1406 int zd_chip_enable_rxtx(struct zd_chip *chip)
1407 {
1408 int r;
1409
1410 mutex_lock(&chip->mutex);
1411 zd_usb_enable_tx(&chip->usb);
1412 r = zd_usb_enable_rx(&chip->usb);
1413 mutex_unlock(&chip->mutex);
1414 return r;
1415 }
1416
1417 void zd_chip_disable_rxtx(struct zd_chip *chip)
1418 {
1419 mutex_lock(&chip->mutex);
1420 zd_usb_disable_rx(&chip->usb);
1421 zd_usb_disable_tx(&chip->usb);
1422 mutex_unlock(&chip->mutex);
1423 }
1424
1425 int zd_rfwritev_locked(struct zd_chip *chip,
1426 const u32* values, unsigned int count, u8 bits)
1427 {
1428 int r;
1429 unsigned int i;
1430
1431 for (i = 0; i < count; i++) {
1432 r = zd_rfwrite_locked(chip, values[i], bits);
1433 if (r)
1434 return r;
1435 }
1436
1437 return 0;
1438 }
1439
1440 /*
1441 * We can optionally program the RF directly through CR regs, if supported by
1442 * the hardware. This is much faster than the older method.
1443 */
1444 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1445 {
1446 struct zd_ioreq16 ioreqs[] = {
1447 { CR244, (value >> 16) & 0xff },
1448 { CR243, (value >> 8) & 0xff },
1449 { CR242, value & 0xff },
1450 };
1451 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1452 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1453 }
1454
1455 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1456 const u32 *values, unsigned int count)
1457 {
1458 int r;
1459 unsigned int i;
1460
1461 for (i = 0; i < count; i++) {
1462 r = zd_rfwrite_cr_locked(chip, values[i]);
1463 if (r)
1464 return r;
1465 }
1466
1467 return 0;
1468 }
1469
1470 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1471 struct zd_mc_hash *hash)
1472 {
1473 struct zd_ioreq32 ioreqs[] = {
1474 { CR_GROUP_HASH_P1, hash->low },
1475 { CR_GROUP_HASH_P2, hash->high },
1476 };
1477
1478 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));
1479 }
1480
1481 u64 zd_chip_get_tsf(struct zd_chip *chip)
1482 {
1483 int r;
1484 static const zd_addr_t aw_pt_bi_addr[] =
1485 { CR_TSF_LOW_PART, CR_TSF_HIGH_PART };
1486 u32 values[2];
1487 u64 tsf;
1488
1489 mutex_lock(&chip->mutex);
1490 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
1491 ARRAY_SIZE(aw_pt_bi_addr));
1492 mutex_unlock(&chip->mutex);
1493 if (r)
1494 return 0;
1495
1496 tsf = values[1];
1497 tsf = (tsf << 32) | values[0];
1498
1499 return tsf;
1500 }
kernel source for telekom puls (alcatel/mediatek)