2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/slab.h>
25 #include <linux/wl12xx.h>
26 #include <linux/export.h>
36 static void wl1271_boot_set_ecpu_ctrl(struct wl1271
*wl
, u32 flag
)
40 /* 10.5.0 run the firmware (I) */
41 cpu_ctrl
= wl1271_read32(wl
, ACX_REG_ECPU_CONTROL
);
43 /* 10.5.1 run the firmware (II) */
45 wl1271_write32(wl
, ACX_REG_ECPU_CONTROL
, cpu_ctrl
);
48 static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271
*wl
)
50 unsigned int quirks
= 0;
51 unsigned int *fw_ver
= wl
->chip
.fw_ver
;
53 /* Only new station firmwares support routing fw logs to the host */
54 if ((fw_ver
[FW_VER_IF_TYPE
] == FW_VER_IF_TYPE_STA
) &&
55 (fw_ver
[FW_VER_MINOR
] < FW_VER_MINOR_FWLOG_STA_MIN
))
56 quirks
|= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED
;
58 /* This feature is not yet supported for AP mode */
59 if (fw_ver
[FW_VER_IF_TYPE
] == FW_VER_IF_TYPE_AP
)
60 quirks
|= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED
;
65 static void wl1271_parse_fw_ver(struct wl1271
*wl
)
69 ret
= sscanf(wl
->chip
.fw_ver_str
+ 4, "%u.%u.%u.%u.%u",
70 &wl
->chip
.fw_ver
[0], &wl
->chip
.fw_ver
[1],
71 &wl
->chip
.fw_ver
[2], &wl
->chip
.fw_ver
[3],
75 wl1271_warning("fw version incorrect value");
76 memset(wl
->chip
.fw_ver
, 0, sizeof(wl
->chip
.fw_ver
));
80 /* Check if any quirks are needed with older fw versions */
81 wl
->quirks
|= wl12xx_get_fw_ver_quirks(wl
);
84 static void wl1271_boot_fw_version(struct wl1271
*wl
)
86 struct wl1271_static_data
*static_data
;
88 static_data
= kmalloc(sizeof(*static_data
), GFP_DMA
);
94 wl1271_read(wl
, wl
->cmd_box_addr
, static_data
, sizeof(*static_data
),
97 strncpy(wl
->chip
.fw_ver_str
, static_data
->fw_version
,
98 sizeof(wl
->chip
.fw_ver_str
));
102 /* make sure the string is NULL-terminated */
103 wl
->chip
.fw_ver_str
[sizeof(wl
->chip
.fw_ver_str
) - 1] = '\0';
105 wl1271_parse_fw_ver(wl
);
108 static int wl1271_boot_upload_firmware_chunk(struct wl1271
*wl
, void *buf
,
109 size_t fw_data_len
, u32 dest
)
111 struct wl1271_partition_set partition
;
112 int addr
, chunk_num
, partition_limit
;
115 /* whal_FwCtrl_LoadFwImageSm() */
117 wl1271_debug(DEBUG_BOOT
, "starting firmware upload");
119 wl1271_debug(DEBUG_BOOT
, "fw_data_len %zd chunk_size %d",
120 fw_data_len
, CHUNK_SIZE
);
122 if ((fw_data_len
% 4) != 0) {
123 wl1271_error("firmware length not multiple of four");
127 chunk
= kmalloc(CHUNK_SIZE
, GFP_KERNEL
);
129 wl1271_error("allocation for firmware upload chunk failed");
133 memcpy(&partition
, &wl12xx_part_table
[PART_DOWN
], sizeof(partition
));
134 partition
.mem
.start
= dest
;
135 wl1271_set_partition(wl
, &partition
);
137 /* 10.1 set partition limit and chunk num */
139 partition_limit
= wl12xx_part_table
[PART_DOWN
].mem
.size
;
141 while (chunk_num
< fw_data_len
/ CHUNK_SIZE
) {
142 /* 10.2 update partition, if needed */
143 addr
= dest
+ (chunk_num
+ 2) * CHUNK_SIZE
;
144 if (addr
> partition_limit
) {
145 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
146 partition_limit
= chunk_num
* CHUNK_SIZE
+
147 wl12xx_part_table
[PART_DOWN
].mem
.size
;
148 partition
.mem
.start
= addr
;
149 wl1271_set_partition(wl
, &partition
);
152 /* 10.3 upload the chunk */
153 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
154 p
= buf
+ chunk_num
* CHUNK_SIZE
;
155 memcpy(chunk
, p
, CHUNK_SIZE
);
156 wl1271_debug(DEBUG_BOOT
, "uploading fw chunk 0x%p to 0x%x",
158 wl1271_write(wl
, addr
, chunk
, CHUNK_SIZE
, false);
163 /* 10.4 upload the last chunk */
164 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
165 p
= buf
+ chunk_num
* CHUNK_SIZE
;
166 memcpy(chunk
, p
, fw_data_len
% CHUNK_SIZE
);
167 wl1271_debug(DEBUG_BOOT
, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
168 fw_data_len
% CHUNK_SIZE
, p
, addr
);
169 wl1271_write(wl
, addr
, chunk
, fw_data_len
% CHUNK_SIZE
, false);
175 static int wl1271_boot_upload_firmware(struct wl1271
*wl
)
177 u32 chunks
, addr
, len
;
182 chunks
= be32_to_cpup((__be32
*) fw
);
185 wl1271_debug(DEBUG_BOOT
, "firmware chunks to be uploaded: %u", chunks
);
188 addr
= be32_to_cpup((__be32
*) fw
);
190 len
= be32_to_cpup((__be32
*) fw
);
194 wl1271_info("firmware chunk too long: %u", len
);
197 wl1271_debug(DEBUG_BOOT
, "chunk %d addr 0x%x len %u",
199 ret
= wl1271_boot_upload_firmware_chunk(wl
, fw
, len
, addr
);
208 static int wl1271_boot_upload_nvs(struct wl1271
*wl
)
210 size_t nvs_len
, burst_len
;
213 u8
*nvs_ptr
, *nvs_aligned
;
218 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
219 struct wl128x_nvs_file
*nvs
= (struct wl128x_nvs_file
*)wl
->nvs
;
221 if (wl
->nvs_len
== sizeof(struct wl128x_nvs_file
)) {
222 if (nvs
->general_params
.dual_mode_select
)
223 wl
->enable_11a
= true;
225 wl1271_error("nvs size is not as expected: %zu != %zu",
227 sizeof(struct wl128x_nvs_file
));
234 /* only the first part of the NVS needs to be uploaded */
235 nvs_len
= sizeof(nvs
->nvs
);
236 nvs_ptr
= (u8
*)nvs
->nvs
;
239 struct wl1271_nvs_file
*nvs
=
240 (struct wl1271_nvs_file
*)wl
->nvs
;
242 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
243 * band configurations) can be removed when those NVS files stop
246 if (wl
->nvs_len
== sizeof(struct wl1271_nvs_file
) ||
247 wl
->nvs_len
== WL1271_INI_LEGACY_NVS_FILE_SIZE
) {
248 if (nvs
->general_params
.dual_mode_select
)
249 wl
->enable_11a
= true;
252 if (wl
->nvs_len
!= sizeof(struct wl1271_nvs_file
) &&
253 (wl
->nvs_len
!= WL1271_INI_LEGACY_NVS_FILE_SIZE
||
255 wl1271_error("nvs size is not as expected: %zu != %zu",
256 wl
->nvs_len
, sizeof(struct wl1271_nvs_file
));
263 /* only the first part of the NVS needs to be uploaded */
264 nvs_len
= sizeof(nvs
->nvs
);
265 nvs_ptr
= (u8
*) nvs
->nvs
;
268 /* update current MAC address to NVS */
269 nvs_ptr
[11] = wl
->addresses
[0].addr
[0];
270 nvs_ptr
[10] = wl
->addresses
[0].addr
[1];
271 nvs_ptr
[6] = wl
->addresses
[0].addr
[2];
272 nvs_ptr
[5] = wl
->addresses
[0].addr
[3];
273 nvs_ptr
[4] = wl
->addresses
[0].addr
[4];
274 nvs_ptr
[3] = wl
->addresses
[0].addr
[5];
277 * Layout before the actual NVS tables:
278 * 1 byte : burst length.
279 * 2 bytes: destination address.
280 * n bytes: data to burst copy.
282 * This is ended by a 0 length, then the NVS tables.
285 /* FIXME: Do we need to check here whether the LSB is 1? */
287 burst_len
= nvs_ptr
[0];
288 dest_addr
= (nvs_ptr
[1] & 0xfe) | ((u32
)(nvs_ptr
[2] << 8));
291 * Due to our new wl1271_translate_reg_addr function,
292 * we need to add the REGISTER_BASE to the destination
294 dest_addr
+= REGISTERS_BASE
;
296 /* We move our pointer to the data */
299 for (i
= 0; i
< burst_len
; i
++) {
300 if (nvs_ptr
+ 3 >= (u8
*) wl
->nvs
+ nvs_len
)
303 val
= (nvs_ptr
[0] | (nvs_ptr
[1] << 8)
304 | (nvs_ptr
[2] << 16) | (nvs_ptr
[3] << 24));
306 wl1271_debug(DEBUG_BOOT
,
307 "nvs burst write 0x%x: 0x%x",
309 wl1271_write32(wl
, dest_addr
, val
);
315 if (nvs_ptr
>= (u8
*) wl
->nvs
+ nvs_len
)
320 * We've reached the first zero length, the first NVS table
321 * is located at an aligned offset which is at least 7 bytes further.
322 * NOTE: The wl->nvs->nvs element must be first, in order to
323 * simplify the casting, we assume it is at the beginning of
324 * the wl->nvs structure.
326 nvs_ptr
= (u8
*)wl
->nvs
+
327 ALIGN(nvs_ptr
- (u8
*)wl
->nvs
+ 7, 4);
329 if (nvs_ptr
>= (u8
*) wl
->nvs
+ nvs_len
)
332 nvs_len
-= nvs_ptr
- (u8
*)wl
->nvs
;
334 /* Now we must set the partition correctly */
335 wl1271_set_partition(wl
, &wl12xx_part_table
[PART_WORK
]);
337 /* Copy the NVS tables to a new block to ensure alignment */
338 nvs_aligned
= kmemdup(nvs_ptr
, nvs_len
, GFP_KERNEL
);
342 /* And finally we upload the NVS tables */
343 wl1271_write(wl
, CMD_MBOX_ADDRESS
, nvs_aligned
, nvs_len
, false);
349 wl1271_error("nvs data is malformed");
353 static void wl1271_boot_enable_interrupts(struct wl1271
*wl
)
355 wl1271_enable_interrupts(wl
);
356 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
,
357 WL1271_ACX_INTR_ALL
& ~(WL1271_INTR_MASK
));
358 wl1271_write32(wl
, HI_CFG
, HI_CFG_DEF_VAL
);
361 static int wl1271_boot_soft_reset(struct wl1271
*wl
)
363 unsigned long timeout
;
366 /* perform soft reset */
367 wl1271_write32(wl
, ACX_REG_SLV_SOFT_RESET
, ACX_SLV_SOFT_RESET_BIT
);
369 /* SOFT_RESET is self clearing */
370 timeout
= jiffies
+ usecs_to_jiffies(SOFT_RESET_MAX_TIME
);
372 boot_data
= wl1271_read32(wl
, ACX_REG_SLV_SOFT_RESET
);
373 wl1271_debug(DEBUG_BOOT
, "soft reset bootdata 0x%x", boot_data
);
374 if ((boot_data
& ACX_SLV_SOFT_RESET_BIT
) == 0)
377 if (time_after(jiffies
, timeout
)) {
378 /* 1.2 check pWhalBus->uSelfClearTime if the
379 * timeout was reached */
380 wl1271_error("soft reset timeout");
384 udelay(SOFT_RESET_STALL_TIME
);
388 wl1271_write32(wl
, ENABLE
, 0x0);
390 /* disable auto calibration on start*/
391 wl1271_write32(wl
, SPARE_A2
, 0xffff);
396 static int wl1271_boot_run_firmware(struct wl1271
*wl
)
401 wl1271_boot_set_ecpu_ctrl(wl
, ECPU_CONTROL_HALT
);
403 chip_id
= wl1271_read32(wl
, CHIP_ID_B
);
405 wl1271_debug(DEBUG_BOOT
, "chip id after firmware boot: 0x%x", chip_id
);
407 if (chip_id
!= wl
->chip
.id
) {
408 wl1271_error("chip id doesn't match after firmware boot");
412 /* wait for init to complete */
414 while (loop
++ < INIT_LOOP
) {
415 udelay(INIT_LOOP_DELAY
);
416 intr
= wl1271_read32(wl
, ACX_REG_INTERRUPT_NO_CLEAR
);
418 if (intr
== 0xffffffff) {
419 wl1271_error("error reading hardware complete "
423 /* check that ACX_INTR_INIT_COMPLETE is enabled */
424 else if (intr
& WL1271_ACX_INTR_INIT_COMPLETE
) {
425 wl1271_write32(wl
, ACX_REG_INTERRUPT_ACK
,
426 WL1271_ACX_INTR_INIT_COMPLETE
);
431 if (loop
> INIT_LOOP
) {
432 wl1271_error("timeout waiting for the hardware to "
433 "complete initialization");
437 /* get hardware config command mail box */
438 wl
->cmd_box_addr
= wl1271_read32(wl
, REG_COMMAND_MAILBOX_PTR
);
440 /* get hardware config event mail box */
441 wl
->event_box_addr
= wl1271_read32(wl
, REG_EVENT_MAILBOX_PTR
);
443 /* set the working partition to its "running" mode offset */
444 wl1271_set_partition(wl
, &wl12xx_part_table
[PART_WORK
]);
446 wl1271_debug(DEBUG_MAILBOX
, "cmd_box_addr 0x%x event_box_addr 0x%x",
447 wl
->cmd_box_addr
, wl
->event_box_addr
);
449 wl1271_boot_fw_version(wl
);
452 * in case of full asynchronous mode the firmware event must be
453 * ready to receive event from the command mailbox
456 /* unmask required mbox events */
457 wl
->event_mask
= BSS_LOSE_EVENT_ID
|
458 SCAN_COMPLETE_EVENT_ID
|
459 ROLE_STOP_COMPLETE_EVENT_ID
|
460 RSSI_SNR_TRIGGER_0_EVENT_ID
|
461 PSPOLL_DELIVERY_FAILURE_EVENT_ID
|
462 SOFT_GEMINI_SENSE_EVENT_ID
|
463 PERIODIC_SCAN_REPORT_EVENT_ID
|
464 PERIODIC_SCAN_COMPLETE_EVENT_ID
|
465 DUMMY_PACKET_EVENT_ID
|
466 PEER_REMOVE_COMPLETE_EVENT_ID
|
467 BA_SESSION_RX_CONSTRAINT_EVENT_ID
|
468 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID
|
469 INACTIVE_STA_EVENT_ID
|
470 MAX_TX_RETRY_EVENT_ID
|
471 CHANNEL_SWITCH_COMPLETE_EVENT_ID
;
473 ret
= wl1271_event_unmask(wl
);
475 wl1271_error("EVENT mask setting failed");
479 wl1271_event_mbox_config(wl
);
481 /* firmware startup completed */
485 static int wl1271_boot_write_irq_polarity(struct wl1271
*wl
)
489 polarity
= wl1271_top_reg_read(wl
, OCP_REG_POLARITY
);
491 /* We use HIGH polarity, so unset the LOW bit */
492 polarity
&= ~POLARITY_LOW
;
493 wl1271_top_reg_write(wl
, OCP_REG_POLARITY
, polarity
);
498 static int wl128x_switch_tcxo_to_fref(struct wl1271
*wl
)
502 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
503 spare_reg
= wl1271_top_reg_read(wl
, WL_SPARE_REG
);
504 if (spare_reg
== 0xFFFF)
506 spare_reg
|= (BIT(3) | BIT(5) | BIT(6));
507 wl1271_top_reg_write(wl
, WL_SPARE_REG
, spare_reg
);
509 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
510 wl1271_top_reg_write(wl
, SYS_CLK_CFG_REG
,
511 WL_CLK_REQ_TYPE_PG2
| MCS_PLL_CLK_SEL_FREF
);
513 /* Delay execution for 15msec, to let the HW settle */
519 static bool wl128x_is_tcxo_valid(struct wl1271
*wl
)
523 tcxo_detection
= wl1271_top_reg_read(wl
, TCXO_CLK_DETECT_REG
);
524 if (tcxo_detection
& TCXO_DET_FAILED
)
530 static bool wl128x_is_fref_valid(struct wl1271
*wl
)
534 fref_detection
= wl1271_top_reg_read(wl
, FREF_CLK_DETECT_REG
);
535 if (fref_detection
& FREF_CLK_DETECT_FAIL
)
541 static int wl128x_manually_configure_mcs_pll(struct wl1271
*wl
)
543 wl1271_top_reg_write(wl
, MCS_PLL_M_REG
, MCS_PLL_M_REG_VAL
);
544 wl1271_top_reg_write(wl
, MCS_PLL_N_REG
, MCS_PLL_N_REG_VAL
);
545 wl1271_top_reg_write(wl
, MCS_PLL_CONFIG_REG
, MCS_PLL_CONFIG_REG_VAL
);
550 static int wl128x_configure_mcs_pll(struct wl1271
*wl
, int clk
)
556 /* Mask bits [3:1] in the sys_clk_cfg register */
557 spare_reg
= wl1271_top_reg_read(wl
, WL_SPARE_REG
);
558 if (spare_reg
== 0xFFFF)
561 wl1271_top_reg_write(wl
, WL_SPARE_REG
, spare_reg
);
563 /* Handle special cases of the TCXO clock */
564 if (wl
->tcxo_clock
== WL12XX_TCXOCLOCK_16_8
||
565 wl
->tcxo_clock
== WL12XX_TCXOCLOCK_33_6
)
566 return wl128x_manually_configure_mcs_pll(wl
);
568 /* Set the input frequency according to the selected clock source */
569 input_freq
= (clk
& 1) + 1;
571 pll_config
= wl1271_top_reg_read(wl
, MCS_PLL_CONFIG_REG
);
572 if (pll_config
== 0xFFFF)
574 pll_config
|= (input_freq
<< MCS_SEL_IN_FREQ_SHIFT
);
575 pll_config
|= MCS_PLL_ENABLE_HP
;
576 wl1271_top_reg_write(wl
, MCS_PLL_CONFIG_REG
, pll_config
);
582 * WL128x has two clocks input - TCXO and FREF.
583 * TCXO is the main clock of the device, while FREF is used to sync
584 * between the GPS and the cellular modem.
585 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
586 * as the WLAN/BT main clock.
588 static int wl128x_boot_clk(struct wl1271
*wl
, int *selected_clock
)
592 /* For XTAL-only modes, FREF will be used after switching from TCXO */
593 if (wl
->ref_clock
== WL12XX_REFCLOCK_26_XTAL
||
594 wl
->ref_clock
== WL12XX_REFCLOCK_38_XTAL
) {
595 if (!wl128x_switch_tcxo_to_fref(wl
))
600 /* Query the HW, to determine which clock source we should use */
601 sys_clk_cfg
= wl1271_top_reg_read(wl
, SYS_CLK_CFG_REG
);
602 if (sys_clk_cfg
== 0xFFFF)
604 if (sys_clk_cfg
& PRCM_CM_EN_MUX_WLAN_FREF
)
607 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
608 if (wl
->tcxo_clock
== WL12XX_TCXOCLOCK_16_368
||
609 wl
->tcxo_clock
== WL12XX_TCXOCLOCK_32_736
) {
610 if (!wl128x_switch_tcxo_to_fref(wl
))
615 /* TCXO clock is selected */
616 if (!wl128x_is_tcxo_valid(wl
))
618 *selected_clock
= wl
->tcxo_clock
;
622 /* FREF clock is selected */
623 if (!wl128x_is_fref_valid(wl
))
625 *selected_clock
= wl
->ref_clock
;
628 return wl128x_configure_mcs_pll(wl
, *selected_clock
);
631 static int wl127x_boot_clk(struct wl1271
*wl
)
636 if (WL127X_PG_GET_MAJOR(wl
->hw_pg_ver
) < 3)
637 wl
->quirks
|= WL12XX_QUIRK_END_OF_TRANSACTION
;
639 if (wl
->ref_clock
== CONF_REF_CLK_19_2_E
||
640 wl
->ref_clock
== CONF_REF_CLK_38_4_E
||
641 wl
->ref_clock
== CONF_REF_CLK_38_4_M_XTAL
)
642 /* ref clk: 19.2/38.4/38.4-XTAL */
644 else if (wl
->ref_clock
== CONF_REF_CLK_26_E
||
645 wl
->ref_clock
== CONF_REF_CLK_52_E
)
651 if (wl
->ref_clock
!= CONF_REF_CLK_19_2_E
) {
653 /* Set clock type (open drain) */
654 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_TYPE
);
655 val
&= FREF_CLK_TYPE_BITS
;
656 wl1271_top_reg_write(wl
, OCP_REG_CLK_TYPE
, val
);
658 /* Set clock pull mode (no pull) */
659 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_PULL
);
661 wl1271_top_reg_write(wl
, OCP_REG_CLK_PULL
, val
);
664 /* Set clock polarity */
665 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_POLARITY
);
666 val
&= FREF_CLK_POLARITY_BITS
;
667 val
|= CLK_REQ_OUTN_SEL
;
668 wl1271_top_reg_write(wl
, OCP_REG_CLK_POLARITY
, val
);
671 wl1271_write32(wl
, PLL_PARAMETERS
, clk
);
673 pause
= wl1271_read32(wl
, PLL_PARAMETERS
);
675 wl1271_debug(DEBUG_BOOT
, "pause1 0x%x", pause
);
677 pause
&= ~(WU_COUNTER_PAUSE_VAL
);
678 pause
|= WU_COUNTER_PAUSE_VAL
;
679 wl1271_write32(wl
, WU_COUNTER_PAUSE
, pause
);
684 /* uploads NVS and firmware */
685 int wl1271_load_firmware(struct wl1271
*wl
)
689 int selected_clock
= -1;
691 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
692 ret
= wl128x_boot_clk(wl
, &selected_clock
);
696 ret
= wl127x_boot_clk(wl
);
701 /* Continue the ELP wake up sequence */
702 wl1271_write32(wl
, WELP_ARM_COMMAND
, WELP_ARM_COMMAND_VAL
);
705 wl1271_set_partition(wl
, &wl12xx_part_table
[PART_DRPW
]);
707 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
708 to be used by DRPw FW. The RTRIM value will be added by the FW
709 before taking DRPw out of reset */
711 wl1271_debug(DEBUG_BOOT
, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START
);
712 clk
= wl1271_read32(wl
, DRPW_SCRATCH_START
);
714 wl1271_debug(DEBUG_BOOT
, "clk2 0x%x", clk
);
716 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
717 clk
|= ((selected_clock
& 0x3) << 1) << 4;
719 clk
|= (wl
->ref_clock
<< 1) << 4;
722 wl1271_write32(wl
, DRPW_SCRATCH_START
, clk
);
724 wl1271_set_partition(wl
, &wl12xx_part_table
[PART_WORK
]);
726 /* Disable interrupts */
727 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
, WL1271_ACX_INTR_ALL
);
729 ret
= wl1271_boot_soft_reset(wl
);
733 /* 2. start processing NVS file */
734 ret
= wl1271_boot_upload_nvs(wl
);
738 /* write firmware's last address (ie. it's length) to
739 * ACX_EEPROMLESS_IND_REG */
740 wl1271_debug(DEBUG_BOOT
, "ACX_EEPROMLESS_IND_REG");
742 wl1271_write32(wl
, ACX_EEPROMLESS_IND_REG
, ACX_EEPROMLESS_IND_REG
);
744 tmp
= wl1271_read32(wl
, CHIP_ID_B
);
746 wl1271_debug(DEBUG_BOOT
, "chip id 0x%x", tmp
);
748 /* 6. read the EEPROM parameters */
749 tmp
= wl1271_read32(wl
, SCR_PAD2
);
751 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
754 if (wl
->chip
.id
== CHIP_ID_1283_PG20
)
755 wl1271_top_reg_write(wl
, SDIO_IO_DS
, wl
->conf
.hci_io_ds
);
757 ret
= wl1271_boot_upload_firmware(wl
);
764 EXPORT_SYMBOL_GPL(wl1271_load_firmware
);
766 int wl1271_boot(struct wl1271
*wl
)
770 /* upload NVS and firmware */
771 ret
= wl1271_load_firmware(wl
);
775 /* 10.5 start firmware */
776 ret
= wl1271_boot_run_firmware(wl
);
780 ret
= wl1271_boot_write_irq_polarity(wl
);
784 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
,
785 WL1271_ACX_ALL_EVENTS_VECTOR
);
787 /* Enable firmware interrupts now */
788 wl1271_boot_enable_interrupts(wl
);
790 wl1271_event_mbox_config(wl
);