drivers/net/wireless/ti/wlcore/wlcore.h

   1 /*
   2  * This file is part of wlcore
   3  *
   4  * Copyright (C) 2011 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #ifndef __WLCORE_H__
  23 #define __WLCORE_H__
  24
  25 #include <linux/platform_device.h>
  26
  27 #include "wlcore_i.h"
  28 #include "event.h"
  29 #include "boot.h"
  30
  31 /* The maximum number of Tx descriptors in all chip families */
  32 #define WLCORE_MAX_TX_DESCRIPTORS 32
  33
  34 /*
  35  * We always allocate this number of mac addresses. If we don't
  36  * have enough allocated addresses, the LAA bit is used
  37  */
  38 #define WLCORE_NUM_MAC_ADDRESSES 3
  39
  40 /* forward declaration */
  41 struct wl1271_tx_hw_descr;
  42 enum wl_rx_buf_align;
  43 struct wl1271_rx_descriptor;
  44
  45 struct wlcore_ops {
  46         int (*setup)(struct wl1271 *wl);
  47         int (*identify_chip)(struct wl1271 *wl);
  48         int (*identify_fw)(struct wl1271 *wl);
  49         int (*boot)(struct wl1271 *wl);
  50         int (*plt_init)(struct wl1271 *wl);
  51         int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
  52                            void *buf, size_t len);
  53         int (*ack_event)(struct wl1271 *wl);
  54         int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
  55                               bool *timeout);
  56         int (*process_mailbox_events)(struct wl1271 *wl);
  57         u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
  58         void (*set_tx_desc_blocks)(struct wl1271 *wl,
  59                                    struct wl1271_tx_hw_descr *desc,
  60                                    u32 blks, u32 spare_blks);
  61         void (*set_tx_desc_data_len)(struct wl1271 *wl,
  62                                      struct wl1271_tx_hw_descr *desc,
  63                                      struct sk_buff *skb);
  64         enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
  65                                                  u32 rx_desc);
  66         int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
  67         u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
  68                                  u32 data_len);
  69         int (*tx_delayed_compl)(struct wl1271 *wl);
  70         void (*tx_immediate_compl)(struct wl1271 *wl);
  71         int (*hw_init)(struct wl1271 *wl);
  72         int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
  73         u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
  74                                     struct wl12xx_vif *wlvif);
  75         int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
  76         int (*get_mac)(struct wl1271 *wl);
  77         void (*set_tx_desc_csum)(struct wl1271 *wl,
  78                                  struct wl1271_tx_hw_descr *desc,
  79                                  struct sk_buff *skb);
  80         void (*set_rx_csum)(struct wl1271 *wl,
  81                             struct wl1271_rx_descriptor *desc,
  82                             struct sk_buff *skb);
  83         u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
  84                                           struct wl12xx_vif *wlvif);
  85         int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
  86         int (*handle_static_data)(struct wl1271 *wl,
  87                                   struct wl1271_static_data *static_data);
  88         int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
  89                           struct cfg80211_scan_request *req);
  90         int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
  91         int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
  92                                 struct cfg80211_sched_scan_request *req,
  93                                 struct ieee80211_sched_scan_ies *ies);
  94         void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
  95         int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
  96         int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
  97                        struct ieee80211_vif *vif,
  98                        struct ieee80211_sta *sta,
  99                        struct ieee80211_key_conf *key_conf);
 100         int (*channel_switch)(struct wl1271 *wl,
 101                               struct wl12xx_vif *wlvif,
 102                               struct ieee80211_channel_switch *ch_switch);
 103         u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
 104         void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
 105                               struct ieee80211_sta *sta, u32 changed);
 106 };
 107
 108 enum wlcore_partitions {
 109         PART_DOWN,
 110         PART_WORK,
 111         PART_BOOT,
 112         PART_DRPW,
 113         PART_TOP_PRCM_ELP_SOC,
 114         PART_PHY_INIT,
 115
 116         PART_TABLE_LEN,
 117 };
 118
 119 struct wlcore_partition {
 120         u32 size;
 121         u32 start;
 122 };
 123
 124 struct wlcore_partition_set {
 125         struct wlcore_partition mem;
 126         struct wlcore_partition reg;
 127         struct wlcore_partition mem2;
 128         struct wlcore_partition mem3;
 129 };
 130
 131 enum wlcore_registers {
 132         /* register addresses, used with partition translation */
 133         REG_ECPU_CONTROL,
 134         REG_INTERRUPT_NO_CLEAR,
 135         REG_INTERRUPT_ACK,
 136         REG_COMMAND_MAILBOX_PTR,
 137         REG_EVENT_MAILBOX_PTR,
 138         REG_INTERRUPT_TRIG,
 139         REG_INTERRUPT_MASK,
 140         REG_PC_ON_RECOVERY,
 141         REG_CHIP_ID_B,
 142         REG_CMD_MBOX_ADDRESS,
 143
 144         /* data access memory addresses, used with partition translation */
 145         REG_SLV_MEM_DATA,
 146         REG_SLV_REG_DATA,
 147
 148         /* raw data access memory addresses */
 149         REG_RAW_FW_STATUS_ADDR,
 150
 151         REG_TABLE_LEN,
 152 };
 153
 154 struct wl1271_stats {
 155         void *fw_stats;
 156         unsigned long fw_stats_update;
 157         size_t fw_stats_len;
 158
 159         unsigned int retry_count;
 160         unsigned int excessive_retries;
 161 };
 162
 163 struct wl1271 {
 164         bool initialized;
 165         struct ieee80211_hw *hw;
 166         bool mac80211_registered;
 167
 168         struct device *dev;
 169         struct platform_device *pdev;
 170
 171         void *if_priv;
 172
 173         struct wl1271_if_operations *if_ops;
 174
 175         void (*set_power)(bool enable);
 176         int irq;
 177
 178         spinlock_t wl_lock;
 179
 180         enum wlcore_state state;
 181         enum wl12xx_fw_type fw_type;
 182         bool plt;
 183         enum plt_mode plt_mode;
 184         u8 fem_manuf;
 185         u8 last_vif_count;
 186         struct mutex mutex;
 187
 188         unsigned long flags;
 189
 190         struct wlcore_partition_set curr_part;
 191
 192         struct wl1271_chip chip;
 193
 194         int cmd_box_addr;
 195
 196         u8 *fw;
 197         size_t fw_len;
 198         void *nvs;
 199         size_t nvs_len;
 200
 201         s8 hw_pg_ver;
 202
 203         /* address read from the fuse ROM */
 204         u32 fuse_oui_addr;
 205         u32 fuse_nic_addr;
 206
 207         /* we have up to 2 MAC addresses */
 208         struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
 209         int channel;
 210         u8 system_hlid;
 211
 212         unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
 213         unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
 214         unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
 215         unsigned long rate_policies_map[
 216                         BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
 217         unsigned long klv_templates_map[
 218                         BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
 219
 220         u8 session_ids[WL12XX_MAX_LINKS];
 221
 222         struct list_head wlvif_list;
 223
 224         u8 sta_count;
 225         u8 ap_count;
 226
 227         struct wl1271_acx_mem_map *target_mem_map;
 228
 229         /* Accounting for allocated / available TX blocks on HW */
 230         u32 tx_blocks_freed;
 231         u32 tx_blocks_available;
 232         u32 tx_allocated_blocks;
 233         u32 tx_results_count;
 234
 235         /* Accounting for allocated / available Tx packets in HW */
 236         u32 tx_pkts_freed[NUM_TX_QUEUES];
 237         u32 tx_allocated_pkts[NUM_TX_QUEUES];
 238
 239         /* Transmitted TX packets counter for chipset interface */
 240         u32 tx_packets_count;
 241
 242         /* Time-offset between host and chipset clocks */
 243         s64 time_offset;
 244
 245         /* Frames scheduled for transmission, not handled yet */
 246         int tx_queue_count[NUM_TX_QUEUES];
 247         unsigned long queue_stop_reasons[NUM_TX_QUEUES];
 248
 249         /* Frames received, not handled yet by mac80211 */
 250         struct sk_buff_head deferred_rx_queue;
 251
 252         /* Frames sent, not returned yet to mac80211 */
 253         struct sk_buff_head deferred_tx_queue;
 254
 255         struct work_struct tx_work;
 256         struct workqueue_struct *freezable_wq;
 257
 258         /* Pending TX frames */
 259         unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
 260         struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
 261         int tx_frames_cnt;
 262
 263         /* FW Rx counter */
 264         u32 rx_counter;
 265
 266         /* Intermediate buffer, used for packet aggregation */
 267         u8 *aggr_buf;
 268         u32 aggr_buf_size;
 269
 270         /* Reusable dummy packet template */
 271         struct sk_buff *dummy_packet;
 272
 273         /* Network stack work  */
 274         struct work_struct netstack_work;
 275
 276         /* FW log buffer */
 277         u8 *fwlog;
 278
 279         /* Number of valid bytes in the FW log buffer */
 280         ssize_t fwlog_size;
 281
 282         /* Sysfs FW log entry readers wait queue */
 283         wait_queue_head_t fwlog_waitq;
 284
 285         /* Hardware recovery work */
 286         struct work_struct recovery_work;
 287         bool watchdog_recovery;
 288
 289         /* Reg domain last configuration */
 290         u32 reg_ch_conf_last[2];
 291         /* Reg domain pending configuration */
 292         u32 reg_ch_conf_pending[2];
 293
 294         /* Pointer that holds DMA-friendly block for the mailbox */
 295         void *mbox;
 296
 297         /* The mbox event mask */
 298         u32 event_mask;
 299
 300         /* Mailbox pointers */
 301         u32 mbox_size;
 302         u32 mbox_ptr[2];
 303
 304         /* Are we currently scanning */
 305         struct wl12xx_vif *scan_wlvif;
 306         struct wl1271_scan scan;
 307         struct delayed_work scan_complete_work;
 308
 309         struct ieee80211_vif *roc_vif;
 310         struct delayed_work roc_complete_work;
 311
 312         struct wl12xx_vif *sched_vif;
 313
 314         /* The current band */
 315         enum ieee80211_band band;
 316
 317         struct completion *elp_compl;
 318         struct delayed_work elp_work;
 319
 320         /* in dBm */
 321         int power_level;
 322
 323         struct wl1271_stats stats;
 324
 325         __le32 buffer_32;
 326         u32 buffer_cmd;
 327         u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
 328
 329         struct wl_fw_status_1 *fw_status_1;
 330         struct wl_fw_status_2 *fw_status_2;
 331         struct wl1271_tx_hw_res_if *tx_res_if;
 332
 333         /* Current chipset configuration */
 334         struct wlcore_conf conf;
 335
 336         bool sg_enabled;
 337
 338         bool enable_11a;
 339
 340         int recovery_count;
 341
 342         /* Most recently reported noise in dBm */
 343         s8 noise;
 344
 345         /* bands supported by this instance of wl12xx */
 346         struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
 347
 348         /*
 349          * wowlan trigger was configured during suspend.
 350          * (currently, only "ANY" trigger is supported)
 351          */
 352         bool wow_enabled;
 353         bool irq_wake_enabled;
 354
 355         /*
 356          * AP-mode - links indexed by HLID. The global and broadcast links
 357          * are always active.
 358          */
 359         struct wl1271_link links[WL12XX_MAX_LINKS];
 360
 361         /* AP-mode - a bitmap of links currently in PS mode according to FW */
 362         u32 ap_fw_ps_map;
 363
 364         /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
 365         unsigned long ap_ps_map;
 366
 367         /* Quirks of specific hardware revisions */
 368         unsigned int quirks;
 369
 370         /* Platform limitations */
 371         unsigned int platform_quirks;
 372
 373         /* number of currently active RX BA sessions */
 374         int ba_rx_session_count;
 375
 376         /* AP-mode - number of currently connected stations */
 377         int active_sta_count;
 378
 379         /* last wlvif we transmitted from */
 380         struct wl12xx_vif *last_wlvif;
 381
 382         /* work to fire when Tx is stuck */
 383         struct delayed_work tx_watchdog_work;
 384
 385         struct wlcore_ops *ops;
 386         /* pointer to the lower driver partition table */
 387         const struct wlcore_partition_set *ptable;
 388         /* pointer to the lower driver register table */
 389         const int *rtable;
 390         /* name of the firmwares to load - for PLT, single role, multi-role */
 391         const char *plt_fw_name;
 392         const char *sr_fw_name;
 393         const char *mr_fw_name;
 394
 395         u8 scan_templ_id_2_4;
 396         u8 scan_templ_id_5;
 397         u8 sched_scan_templ_id_2_4;
 398         u8 sched_scan_templ_id_5;
 399         u8 max_channels_5;
 400
 401         /* per-chip-family private structure */
 402         void *priv;
 403
 404         /* number of TX descriptors the HW supports. */
 405         u32 num_tx_desc;
 406         /* number of RX descriptors the HW supports. */
 407         u32 num_rx_desc;
 408
 409         /* translate HW Tx rates to standard rate-indices */
 410         const u8 **band_rate_to_idx;
 411
 412         /* size of table for HW rates that can be received from chip */
 413         u8 hw_tx_rate_tbl_size;
 414
 415         /* this HW rate and below are considered HT rates for this chip */
 416         u8 hw_min_ht_rate;
 417
 418         /* HW HT (11n) capabilities */
 419         struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
 420
 421         /* size of the private FW status data */
 422         size_t fw_status_priv_len;
 423
 424         /* RX Data filter rule state - enabled/disabled */
 425         bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
 426
 427         /* size of the private static data */
 428         size_t static_data_priv_len;
 429
 430         /* the current channel type */
 431         enum nl80211_channel_type channel_type;
 432
 433         /* mutex for protecting the tx_flush function */
 434         struct mutex flush_mutex;
 435
 436         /* sleep auth value currently configured to FW */
 437         int sleep_auth;
 438
 439         /* the number of allocated MAC addresses in this chip */
 440         int num_mac_addr;
 441
 442         /* the minimum FW version required for the driver to work */
 443         unsigned int min_fw_ver[NUM_FW_VER];
 444
 445         struct completion nvs_loading_complete;
 446
 447         /* number of concurrent channels the HW supports */
 448         u32 num_channels;
 449 };
 450
 451 int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
 452 int __devexit wlcore_remove(struct platform_device *pdev);
 453 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
 454                                      u32 mbox_size);
 455 int wlcore_free_hw(struct wl1271 *wl);
 456 int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
 457                    struct ieee80211_vif *vif,
 458                    struct ieee80211_sta *sta,
 459                    struct ieee80211_key_conf *key_conf);
 460 void wlcore_regdomain_config(struct wl1271 *wl);
 461
 462 static inline void
 463 wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
 464                   struct ieee80211_sta_ht_cap *ht_cap)
 465 {
 466         memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
 467 }
 468
 469 /* Tell wlcore not to care about this element when checking the version */
 470 #define WLCORE_FW_VER_IGNORE    -1
 471
 472 static inline void
 473 wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
 474                       unsigned int iftype, unsigned int major,
 475                       unsigned int subtype, unsigned int minor)
 476 {
 477         wl->min_fw_ver[FW_VER_CHIP] = chip;
 478         wl->min_fw_ver[FW_VER_IF_TYPE] = iftype;
 479         wl->min_fw_ver[FW_VER_MAJOR] = major;
 480         wl->min_fw_ver[FW_VER_SUBTYPE] = subtype;
 481         wl->min_fw_ver[FW_VER_MINOR] = minor;
 482 }
 483
 484 /* Firmware image load chunk size */
 485 #define CHUNK_SIZE      16384
 486
 487 /* Quirks */
 488
 489 /* Each RX/TX transaction requires an end-of-transaction transfer */
 490 #define WLCORE_QUIRK_END_OF_TRANSACTION         BIT(0)
 491
 492 /* the first start_role(sta) sometimes doesn't work on wl12xx */
 493 #define WLCORE_QUIRK_START_STA_FAILS            BIT(1)
 494
 495 /* wl127x and SPI don't support SDIO block size alignment */
 496 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN         BIT(2)
 497
 498 /* means aggregated Rx packets are aligned to a SDIO block */
 499 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN         BIT(3)
 500
 501 /* Older firmwares did not implement the FW logger over bus feature */
 502 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED      BIT(4)
 503
 504 /* Older firmwares use an old NVS format */
 505 #define WLCORE_QUIRK_LEGACY_NVS                 BIT(5)
 506
 507 /* Some firmwares may not support ELP */
 508 #define WLCORE_QUIRK_NO_ELP                     BIT(6)
 509
 510 /* pad only the last frame in the aggregate buffer */
 511 #define WLCORE_QUIRK_TX_PAD_LAST_FRAME          BIT(7)
 512
 513 /* extra header space is required for TKIP */
 514 #define WLCORE_QUIRK_TKIP_HEADER_SPACE          BIT(8)
 515
 516 /* Some firmwares not support sched scans while connected */
 517 #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN   BIT(9)
 518
 519 /* separate probe response templates for one-shot and sched scans */
 520 #define WLCORE_QUIRK_DUAL_PROBE_TMPL            BIT(10)
 521
 522 /* Firmware requires reg domain configuration for active calibration */
 523 #define WLCORE_QUIRK_REGDOMAIN_CONF             BIT(11)
 524
 525
 526 /* TODO: move all these common registers and values elsewhere */
 527 #define HW_ACCESS_ELP_CTRL_REG          0x1FFFC
 528
 529 /* ELP register commands */
 530 #define ELPCTRL_WAKE_UP             0x1
 531 #define ELPCTRL_WAKE_UP_WLAN_READY  0x5
 532 #define ELPCTRL_SLEEP               0x0
 533 /* ELP WLAN_READY bit */
 534 #define ELPCTRL_WLAN_READY          0x2
 535
 536 /*************************************************************************
 537
 538     Interrupt Trigger Register (Host -> WiLink)
 539
 540 **************************************************************************/
 541
 542 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
 543
 544 /*
 545  * The host sets this bit to inform the Wlan
 546  * FW that a TX packet is in the XFER
 547  * Buffer #0.
 548  */
 549 #define INTR_TRIG_TX_PROC0 BIT(2)
 550
 551 /*
 552  * The host sets this bit to inform the FW
 553  * that it read a packet from RX XFER
 554  * Buffer #0.
 555  */
 556 #define INTR_TRIG_RX_PROC0 BIT(3)
 557
 558 #define INTR_TRIG_DEBUG_ACK BIT(4)
 559
 560 #define INTR_TRIG_STATE_CHANGED BIT(5)
 561
 562 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
 563
 564 /*
 565  * The host sets this bit to inform the FW
 566  * that it read a packet from RX XFER
 567  * Buffer #1.
 568  */
 569 #define INTR_TRIG_RX_PROC1 BIT(17)
 570
 571 /*
 572  * The host sets this bit to inform the Wlan
 573  * hardware that a TX packet is in the XFER
 574  * Buffer #1.
 575  */
 576 #define INTR_TRIG_TX_PROC1 BIT(18)
 577
 578 #define ACX_SLV_SOFT_RESET_BIT  BIT(1)
 579 #define SOFT_RESET_MAX_TIME     1000000
 580 #define SOFT_RESET_STALL_TIME   1000
 581
 582 #define ECPU_CONTROL_HALT       0x00000101
 583
 584 #define WELP_ARM_COMMAND_VAL    0x4
 585
 586 #endif /* __WLCORE_H__ */